FAN7530 Critical Conduction Mode PFC Controller Features Description Low Total Harmonic Distortion (THD) The FAN7530 is an active power factor correction (PFC) controller for the boost PFC applications that operates in critical conduction mode (CRM). It uses the voltage mode PWM that compares an internal ramp signal with the error amplifier output to generate MOSFET turn-off signal. Because the voltage mode CRM PFC controller does not need the rectified AC line voltage information, it can save the power loss of the input voltage sensing network necessary for the current mode CRM PFC controller. Precise Adjustable Output Over-Voltage Protection Open-Feedback Protection and Disable Function Zero Current Detector 150µs Internal Start-up Timer MOSFET Over-Current Protection Under-Voltage Lockout with 3.5V Hysteresis Low Start-up (40µA) and Operating Current (1.5mA) Totem Pole Output with High State Clamp +500/-800mA Peak Gate Drive Current FAN7530 provides many protection functions such as over voltage protection, open-feedback protection, overcurrent protection, and under-voltage lockout protection. The FAN7530 can be disabled if the INV pin voltage is lower than 0.45V and the operating current decreases to 65µA. Using a new variable on-time control method, THD is lower than the conventional CRM boost PFC ICs. 8-pin DIP or 8-pin SOP Applications Adapter Ballast LCD TV, CRT TV SMPS Related Application Notes AN-6027 - Design of Power Factor Correction Circuit Using FAN7530 Ordering Information Part Number Operating Temp. Range Pb-Free Package Packing Method Marking Code FAN7530N -40°C to +125°C Yes 8-DIP Rail FAN7530 FAN7530M -40°C to +125°C Yes 8-SOP Rail FAN7530 FAN7530MX -40°C to +125°C Yes 8-SOP Tape & Reel FAN7530 © 2006 Fairchild Semiconductor Corporation FAN7530 Rev. 1.0.2 www.fairchildsemi.com FAN7530 Critical Conduction Mode PFC Controller April 2007 FAN7530 Critical Conduction Mode PFC Controller Typical Application Diagrams L D VO AC IN VAUX I2 NAUX RZCD R2 ZCD CO VCC FAN7530 INV MOT CS I1 COMP R1 GND FAN7530 Rev. 00 Figure 1. Typical Boost PFC Application Internal Block Diagram 2.5V Ref VCC 8 UVLO Vref1 VCC Internal Bias 12V 8.5V Drive Output Disable 150ms Timer ZCD 5 S 6.7V Q 1.4V 1.5V R Zero Current Detector CS OVP 4 Disable 40k 8pF 0.8V MOT 2 7 OUT 13V Ramp Signal Saw Tooth Generator 2.675V 2.5V 0.45V 0.35V Current Protection Comparator Vref1 1V Offset Error Amplifier Gm 1V~5V Range 1 INV 3 6 GND COMP FAN7530 Rev. 00 Figure 2. Functional Block Diagram of FAN7530 © 2006 Fairchild Semiconductor Corporation FAN7530 Rev. 1.0.2 www.fairchildsemi.com 2 VCC OUT GND ZCD 8 7 6 5 YWW FAN7530 1 2 3 4 INV MOT COMP CS FAN7530 Rev. 00 Figure 3. Pin Configuration (Top View) Pin Definitions Pin # Name Description 1 INV This pin is the inverting input of the error amplifier. The output voltage of the boost PFC converter should be resistively divided to 2.5V. 2 MOT This pin is used to set the slope of the internal ramp. The voltage of this pin is maintained at 3V. If a resistor is connected between this pin and GND, current flows out of the pin and the slope of the internal ramp is proportional to this current. 3 COMP This pin is the output of the transconductance error amplifier. Components for the output voltage compensation should be connected between this pin and GND. 4 CS This pin is the input of the over-current protection comparator. The MOSFET current is sensed using a sensing resistor and the resulting voltage is applied to this pin. An internal RC filter is included to filter switching noise. 5 ZCD This pin is the input of the zero current detection block. If the voltage of this pin goes higher than 1.5V, then goes lower than 1.4V, the MOSFET is turned on. 6 GND This pin is used for the ground potential of all the pins. For proper operation, the signal ground and the power ground should be separated. 7 OUT This pin is the gate drive output. The peak sourcing and sinking current levels are +500mA and -800mA respectively. For proper operation, the stray inductance in the gate driving path must be minimized. 8 VCC This pin is the IC supply pin. IC current and MOSFET drive current are supplied using this pin. © 2006 Fairchild Semiconductor Corporation FAN7530 Rev. 1.0.2 www.fairchildsemi.com 3 FAN7530 Critical Conduction Mode PFC Controller Pin Assignments Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA = 25°C unless otherwise specified. Symbol VCC IOH, IOL Iclamp Parameter Supply Voltage Peak Drive Output Current Driver Output Clamping Diodes VO>VCC or VO<-0.3V Idet Detector Clamping Diodes VIN Error Amplifier, MOT, CS Input Voltages Value Unit VZ V +500/-800 mA ±10 mA ±10 mA -0.3 to 6 V 150 °C °C Tj Operating Junction Temperature TA Operating Temperature Range -40 to 125 Tstg Storage Temperature Range -65 to 150 °C VESD_HBM ESD Capability, Human Body Model 2.0 kV VESD_MM ESD Capability, Machine Model 300 V VESD_CDM ESD Capability, Charged Device Model 500 V Value Unit 8-DIP 110 °C/W 8-SOP 150 °C/W Thermal Impedance(1) Symbol Rθja Parameter Thermal Resistance, Junction-to-Ambient Note: 1. Regarding the test environment and PCB type, please refer to JESD51-2 and JESD51-10. © 2006 Fairchild Semiconductor Corporation FAN7530 Rev. 1.0.2 www.fairchildsemi.com 4 FAN7530 Critical Conduction Mode PFC Controller Absolute Maximum Ratings VCC = 14V, TA = -40°C~125°C, unless otherwise specified. Symbol Parameter Condition Min. Typ. Max. Unit 11 12 13 V UNDER-VOLTAGE LOCKOUT SECTION Vth(start) Start Threshold Voltage VCC increasing Vth(stop) Stop Threshold Voltage VCC decreasing HY(uvlo) UVLO Hysteresis VZ Zener Voltage ICC = 20mA 7.5 8.5 9.5 V 3.0 3.5 4.0 V 20 22 24 V SUPPLY CURRENT SECTION Ist Start-up Supply Current VCC = Vth(start) - 0.2V 40 70 µA ICC Operating Supply Current Output no switching 1.5 3.0 mA Idcc Dynamic Operating Supply Current 50kHz, Cl=1nF 2.5 4.0 mA Operating Current at Disable Vinv = 0V 20 65 95 µA Voltage Feedback Input Threshold1 TA = 25°C 2.465 2.500 2.535 V Line Regulation VCC = 14V ~ 20V 0.1 10.0 mV ICC(dis) ERROR AMPLIFIER SECTION Vref1 ΔVref1 ΔVref2 Temperature Stability of Ib(ea) Input Bias Current Vinv = 1V ~ 4V Isource Output Source Current Vinv = Vref1 - 0.1V -12 µA Output Sink Current Vinv = Vref1 + 0.1V 12 µA Veao(H) Output Upper Clamp Voltage Vinv = Vref1 - 0.1V Veao(Z) Zero Duty Cycle Output Voltage 0.9 1.0 1.1 V Transconductance(2) 90 115 140 µmho 2.784 2.900 3.016 V 19 24 29 µs 0.7 0.8 0.9 V -1.0 -0.1 1.0 µA 350 500 ns Isink gm Vref1(2) 20 -0.5 5.4 mV 0.5 6.0 6.6 µA V MAXIMUM ON-TIME SECTION Vmot Ton(max) Maximum On-time Voltage Rmot = 40.5kΩ Maximum On-time Programming Rmot = 40.5kΩ, TA = 25°C CURRENT SENSE SECTION VCS(limit) Ib(cs) td(cs) Current Sense Input Threshold Voltage Limit Input Bias Current Current Sense Delay to VCS = 0V ~ 1V Output(2) dV/dt = 1V/100ns, From 0V to 5V Note: 2. These parameters, although guaranteed by design, are not tested in mass production. © 2006 Fairchild Semiconductor Corporation FAN7530 Rev. 1.0.2 www.fairchildsemi.com 5 FAN7530 Critical Conduction Mode PFC Controller Electrical Characteristics VCC = 14V, TA = -40°C~125°C, unless otherwise specified. Symbol Parameter Condition Min. Typ. Max. Unit 1.35 1.50 1.65 V ZERO CURRENT DETECT SECTION Vth(ZCD) Input Voltage Threshold(3) (3) HY(ZCD) Detect Hysteresis 0.05 0.10 0.15 V Vclamp(H) Input High Clamp Voltage Idet = 3mA 6.0 6.7 7.4 V Vclamp(L) Input Low Clamp Voltage Idet = -3mA 0 0.65 1.00 V -1.0 -0.1 1.0 µA Ib(ZCD) Input Bias Current VZCD = 1V ~ 5V (3) Isource(zcd) Source Current Capability TA = 25°C -10 mA Isink(zcd) Sink Current Capability(3) TA = 25°C 10 mA 200 ns 11.0 12.8 V tdead Maximum Delay from ZCD to Output dV/dt = -1V/100ns, Turn-on(3) From 5V to 0V 100 OUTPUT SECTION VOH Output Voltage High IO = -100mA, TA = 25°C VOL Output Voltage Low IO = 200mA, TA = 25°C 1.0 2.5 V tr Rising Time(3) Cl = 1nF 50 100 ns Falling Time(3) Cl = 1nF 50 100 ns 13.0 14.5 V 1 V tf VO(max) VO(UVLO) Maximum Output Voltage VCC = 20V, IO = 100μA Output Voltage with UVLO Activated VCC = 5V, IO = 100μA 9.2 11.5 RESTART TIMER SECTION td(rst) Restart Timer Delay 50 150 300 µs OVER-VOLTAGE PROTECTION SECTION Vovp HY(ovp) OVP Threshold Voltage TA = 25°C 2.620 2.675 2.730 V OVP Hysteresis TA = 25°C 0.120 0.175 0.230 V ENABLE SECTION Vth(en) Enable Threshold Voltage 0.40 0.45 0.50 V HY(en) Enable Hysteresis 0.05 0.10 0.15 V Note: 3. These parameters, although guaranteed by design, are not tested in mass production. © 2006 Fairchild Semiconductor Corporation FAN7530 Rev. 1.0.2 www.fairchildsemi.com 6 FAN7530 Critical Conduction Mode PFC Controller Electrical Characteristics (Continued) 9.5 12.5 9.0 Vth(stop) [V] Vth(start) [V] 13.0 12.0 8.5 8.0 11.5 7.5 11.0 -60 -40 -20 0 20 40 60 80 -60 -40 -20 100 120 140 0 40 60 80 100 120 140 Figure 5. Stop Threshold Voltage vs. Temp. 4.00 23.0 3.75 22.5 VZ [V] HY(UVLO) [V] Figure 4. Start Threshold Voltage vs. Temp. 3.50 22.0 21.5 3.25 21.0 3.00 -60 -40 -20 0 20 40 60 80 -60 -40 -20 100 120 140 0 20 40 60 80 100 120 140 Temperature [°C] Temperature [°C] Figure 6. UVLO Hysteresis vs. Temp. Figure 7. Zener Voltage vs. Temp. 60 2.4 ICC [mA] 45 Ist [μA] 20 Temperature [°C] Temperature [°C] 30 1.6 0.8 15 0.0 -60 -40 -20 0 20 40 60 80 -60 -40 -20 100 120 140 Figure 8. Start-up Supply Current vs. Temp. 20 40 60 80 100 120 140 Figure 9. Operating Supply Current vs. Temp. © 2006 Fairchild Semiconductor Corporation FAN7530 Rev. 1.0.2 0 Temperature [°C] Temperature [°C] www.fairchildsemi.com 7 FAN7530 Critical Conduction Mode PFC Controller Typical Characteristics 90 3 72 ICC(dis) [μA] Idcc [mA] 4 2 1 54 36 0 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 Temperature [°C] 20 40 60 80 100 120 140 Temperature [°C] Figure 10. Dynamic Operating Supply Current vs. Temp. Figure 11. Operating Current at Disable vs. Temp. 10.0 7.5 ΔVref1 [mV] Vref1 [V] 2.52 2.50 5.0 2.5 2.48 0.0 -60 -40 -20 0 20 40 60 80 -60 -40 -20 100 120 140 0 20 40 60 80 100 120 140 Temperature [°C] Temperature [°C] Figure 13. ΔVref1 vs. Temp. Figure 12. Vref1 vs. Temp. 0.50 -9 Isource [μA] Ib(ea) [μA] 0.25 0.00 -12 -15 -0.25 -0.50 -18 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 Temperature [°C] 20 40 60 80 100 120 140 Temperature [°C] Figure 14. Input Bias Current vs. Temp. Figure 15. Output Source Current vs. Temp. © 2006 Fairchild Semiconductor Corporation FAN7530 Rev. 1.0.2 0 www.fairchildsemi.com 8 FAN7530 Critical Conduction Mode PFC Controller Typical Characteristics (Continued) 6.6 15 6.3 Veao(H) [V] Isink [μA] 18 12 9 6.0 5.7 6 5.4 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 Temperature [°C] 20 40 60 80 100 120 140 Temperature [°C] Figure 16. Output Sink Current vs. Temp. Figure 17. Output Upper Clamp Voltage vs. Temp. 1.10 3.00 2.95 Vmot [V] Veao(Z) [V] 1.05 1.00 2.90 2.85 0.95 2.80 0.90 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 Temperature [°C] 20 40 60 80 100 120 140 Temperature [°C] Figure 18. Zero Duty Cycle Output Voltage vs. Temp. Figure 19. Maximum On-Time Voltage vs. Temp. 0.90 0.85 Vcs(limit) [V] Ton(max) [μs] 27 24 0.80 0.75 21 0.70 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 Temperature [°C] 20 40 60 80 100 120 140 Temperature [°C] Figure 20. Maximum On-Time vs. Temp. Figure 21. Current Sense Input Threshold Voltage vs. Temp. © 2006 Fairchild Semiconductor Corporation FAN7530 Rev. 1.0.2 0 www.fairchildsemi.com 9 FAN7530 Critical Conduction Mode PFC Controller Typical Characteristics (Continued) 1.0 7.2 6.8 Vclamp(H) [V] Ib(cs) [μA] 0.5 0.0 6.4 -0.5 6.0 -1.0 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 Temperature [°C] Figure 22. Input Bias Current vs. Temp. 40 60 80 100 120 140 Figure 23. Input High Clamp Voltage vs. Temp. 1.00 1.0 0.75 0.5 Ib(zcd) [μA] Vclamp(L) [V] 20 Temperature [°C] 0.50 0.25 0.0 -0.5 0.00 -1.0 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 Temperature [°C] 20 40 60 80 100 120 140 Temperature [°C] Figure 24. Input Low Clamp Voltage vs. Temp. Figure 25. Input Bias Current vs. Temp. 0.9 14 VO(uvlo) [V] VO(max) [V] 0.6 13 12 0.3 0.0 -0.3 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 Temperature [°C] 20 40 60 80 100 120 140 Temperature [°C] Figure 26. Maximum Output Voltage vs. Temp. Figure 27. Output Voltage with UVLO Activated vs. Temp. © 2006 Fairchild Semiconductor Corporation FAN7530 Rev. 1.0.2 0 www.fairchildsemi.com 10 FAN7530 Critical Conduction Mode PFC Controller Typical Characteristics (Continued) 2.73 300 250 200 Vovp [V] td(rst) [μs] 2.70 150 100 2.67 2.64 50 -60 -40 -20 0 20 40 60 80 -60 -40 -20 100 120 140 0 20 40 60 80 100 120 140 Temperature [°C] Temperature [°C] Figure 28. Restart Delay Time vs. Temp. Figure 29. OVP Threshold Voltage vs. Temp. 0.500 0.21 Vth(en) [V] HY(OVP) [V] 0.475 0.18 0.450 0.15 0.425 0.400 0.12 -60 -40 -20 0 20 40 60 80 -60 -40 -20 100 120 140 0 20 40 60 80 100 120 140 Temperature [°C] Temperature [°C] Figure 30. OVP Hysteresis vs. Temp. Figure 31. Enable Threshold voltage vs. Temp. 0.150 HY(en) [V] 0.125 0.100 0.075 0.050 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature [°C] Figure 32. Enable Hysteresis vs. Temp. © 2006 Fairchild Semiconductor Corporation FAN7530 Rev. 1.0.2 www.fairchildsemi.com 11 FAN7530 Critical Conduction Mode PFC Controller Typical Characteristics (Continued) 1. Error Amplifier Block rent detector turns on the MOSFET. The ZCD pin is protected internally by two clamps, 6.7V-high clamp and 0.65V-low clamp. The 150µs timer generates a MOSFET turn-on signal if the drive output has been low for more than 150µs from the falling edge of the drive output. The error amplifier block consists of a transconductance amplifier, output OVP comparator, and disable comparator. For the output voltage control, a transconductance amplifier is used instead of the conventional voltage amplifier. The transconductance amplifier (voltage controlled current source) aids the implementation of OVP and disable function. The output current of the amplifier changes according to the voltage difference of the inverting and non-inverting input of the amplifier. The output voltage of the amplifier is compared with the internal ramp signal to generate the switch turn-off signal. The OVP comparator shuts down the output drive block when the voltage of the INV pin is higher than 2.675V and there is 0.175V hysteresis. The disable comparator disables the operation of the FAN7530 when the voltage of the inverting input is lower than 0.45V and there is 100mV hysteresis. An external small signal MOSFET can be used to disable the IC, as shown in Figure 33. The IC operating current decreases below 65µA to reduce power consumption if the IC is disabled. 150μs Timer Vin Turn-on Signal ZCD 5 S RZCD 6.7V Q 1.4V 1.5V Zero Current Detector R FAN7529 Rev. 00 Figure 34. Zero Current Detector Block 3. Sawtooth Generator Block 2.675V The output of the error amplifier and the output of the sawtooth generator are compared to determine the MOSFET turn-off instance. The slope of the sawtooth is determined by an external resistor connected to the MOT pin. The voltage of the MOT pin is 2.9V and the slope is proportional to the current flowing out of the MOT pin. The internal ramp signal has a 1V offset; therefore, the drive output is shut down if the voltage of the COMP pin is lower than 1V. The MOSFET on-time is maximum when the COMP pin voltage is 5V. According to the slope of the internal ramp, the maximum on-time can be programmed. The necessary maximum on-time depends on the boost inductor, lowest AC line voltage, and maximum output power. The resistor value should be designed properly. 2.5V OVP Disable 0.45V 0.35V Vout Vref1 (2.5V) Error Amp Gm INV 1 Disable Signal 3 COMP Off Signal FAN7530 Rev. 00 1V Offset MOT Sawtooth Generator 3 Figure 33. Error Amplifier Block 2.9V 2. Zero Current Detection Block Error Amp Output The zero current detector (ZCD) generates the turn-on signal of the MOSFET when the boost inductor current reaches zero using an auxiliary winding coupled with the inductor. If the voltage of the ZCD pin goes higher than 1.5V, the ZCD comparator waits until the voltage goes below 1.4V. If the voltage goes below 1.4V, the zero cur- FAN7529 Rev. 00 Figure 35. Sawtooth Generator Block © 2006 Fairchild Semiconductor Corporation FAN7530 Rev. 1.0.2 www.fairchildsemi.com 12 FAN7530 Critical Conduction Mode PFC Controller Applications Information 5. Switch Drive Block The MOSFET current is sensed using an external sensing resistor for the over-current protection. If the CS pin voltage is higher than 0.8V, the over-current protection comparator generates a protection signal. An internal RC filter is included to filter switching noise. The FAN7530 contains a single totem-pole output stage designed for a direct drive of the power MOSFET. The drive output is capable of up to +500/-800mA peak current with a typical rise and fall time of 50ns with 1nF load. The output voltage is clamped to 13V to protect the MOSFET gate even if the VCC voltage is higher than 13V. OCP Signal 40k CS 4 6. Under-Voltage Lockout Block 8pF 0.8V If the VCC voltage reaches 12V, the IC’s internal blocks are enabled and start operation. If the VCC voltage drops below 8.5V, most of the internal blocks are disabled to reduce the operating current. VCC voltage should be higher than 8.5V under normal conditions. Over-Current Protection Comparator FAN7529 Rev. 00 Figure 36. Over-Current Protection Block © 2006 Fairchild Semiconductor Corporation FAN7530 Rev. 1.0.2 www.fairchildsemi.com 13 FAN7530 Critical Conduction Mode PFC Controller 4. Over-Current Protection Block Application Output Power Input Voltage Output Voltage Ballast 100W Universal input (85~265Vac) 400V Features High efficiency (>90% at 85Vac input) Low THD (total harmonic distortion) (<10% at 265Vac input, 25W load) Key Design Notes R1, R2, R5, C11 should be optimized for best THD characteristic. 1. Schematic T1 PFC OUTPUT VAUX BD D2 C5 R4 R3 R5 R10 D3 C10 Q1 NTC ZD1 R6 C11 D1 C3 C9 C4 8 7 VCC 6 5 OUT GND ZCD C2 R9 LF1 FAN7530 R2 C1 V1 INV MOT COMP CS 1 2 R1 F1 3 R11 4 R8 R7 C7 C6 C8 FAN7530 Rev. 00 AC INPUT Figure 37. Schematic © 2006 Fairchild Semiconductor Corporation FAN7530 Rev. 1.0.2 www.fairchildsemi.com 14 FAN7530 Critical Conduction Mode PFC Controller Typical application circuit FAN7530 Critical Conduction Mode PFC Controller 2. Inductor Schematic Diagram 4 NVcc 2 3 Np 5 FAN7529 Rev. 00 Figure 38. Inductor Schematic Diagram 3. Winding Specification No Pin (s→f) 5→3 Np Wire 0.1φ × 30 Turns Winding Method 58 Solenoid Winding 8 Solenoid Winding Insulation: Polyester Tape t = 0.050mm, 4 Layers 2→4 NVcc 0.2φ × 10 Outer Insulation: Polyester Tape t = 0.050mm, 4 Layers Air Gap: 0.6mm for each leg 4. Electrical Characteristics Inductance Pin Specification Remarks 3-5 600µH ± 10% 100kHz, 1V 5. Core & Bobbin Core: EI 3026 Bobbin: EI3026 Ae(mm2): 111 © 2006 Fairchild Semiconductor Corporation FAN7530 Rev. 1.0.2 www.fairchildsemi.com 15 Part Value Note Part Value Fuse F1 3A/250V NTC 10D-9 Note Inductor T1 600µH EI3026 NTC MOSFET Resistor Q1 FQPF13N50C Fairchild R1 56kΩ 1/4W R2 820kΩ 1/4W R3 330kΩ 1/2W D1 1N4148 Fairchild R4 150Ω 1/2W D2 BYV26C 600V, 1A R5 20kΩ 1/4W D3 SB140 Fairchild R6 10Ω 1/4W ZD1 1N4746 18V R7 0.2Ω 1/2W R8 10kΩ 1/4W R9 10kΩ 1/4W R10 2MΩ 1/4W R11 12.9kΩ 1/4W Diode Bridge Diode BD KBL06 600V/4A Line Filter Capacitor LF1 C1 150nF/275VAC Box Capacitor C2 470nF/275VAC Box Capacitor C3 2.2nF/3kV Ceramic Capacitor C4 2.2nF/3kV Ceramic Capacitor C6 47µF/25V Electrolytic Capacitor C7 47nF/50V Ceramic Capacitor 220nF/50V Multilayer Ceramic Capacitor C9 100µF/450V Electrolytic Capacitor C10 12nF/100V Film Capacitor C11 56pF/50V Ceramic Capacitor 40mH IC IC1 FAN7530 V1 471 C5 C8 Fairchild TNR © 2006 Fairchild Semiconductor Corporation FAN7530 Rev. 1.0.2 Wire 0.4mm 470V www.fairchildsemi.com 16 FAN7530 Critical Conduction Mode PFC Controller 6. Demo Circuit Part List FAN7530 Critical Conduction Mode PFC Controller 7. Layout Power Ground Signal Ground Separate the power ground and the signal ground Place the output voltage sensing resistors close to IC Figure 39. PCB Layout Considerations for FAN7530 8. Performance Data POUT 100W 75W 50W 25W 85Vac 115Vac 230Vac 265Vac PF 0.998 0.998 0.991 0.984 THD 5.1% 3.6% 5.2% 6.2% Efficiency 90.9% 93.7% 95.6% 96% PF 0.999 0.998 0.986 0.975 THD 4.1% 3.6% 5.0% 5.7% Efficiency 91.6% 93.3% 94.6% 95.3% PF 0.998 0.997 0.974 0.956 THD 4.4% 5.0% 5.7% 6.2% Efficiency 91.3% 91.9% 92.7% 93.4% PF 0.995 0.991 0.923 0.876 THD 7.9% 8.6% 8.3% 8.7% Efficiency 86.4% 87.1% 87.3% 88.1% © 2006 Fairchild Semiconductor Corporation FAN7530 Rev. 1.0.2 www.fairchildsemi.com 17 8-DIP #5 1.524 ±0.10 0.060 ±0.004 #4 0.018 ±0.004 #8 2.54 0.100 9.60 MAX 0.378 #1 9.20 ±0.20 0.362 ±0.008 ( 6.40 ±0.20 0.252 ±0.008 0.46 ±0.10 0.79 ) 0.031 Dimensions are in millimeters (inches) unless otherwise noted.. 7.62 0.300 3.30 ±0.30 0.130 ±0.012 5.08 MAX 0.200 3.40 ±0.20 0.134 ±0.008 0.33 MIN 0.013 +0.10 0.25 –0.05 +0.004 0~15° 0.010 –0.002 September 1999, Rev B 8dip_dim.pdf Figure 40. 8-Lead Dual In-Line Package (DIP) © 2006 Fairchild Semiconductor Corporation FAN7530 Rev. 1.0.2 www.fairchildsemi.com 18 FAN7530 Critical Conduction Mode PFC Controller Mechanical Dimensions 8-SOP Dimensions are in millimeters (inches) unless otherwise noted. MIN #5 6.00 ±0.30 0.236 ±0.012 0.41 ±0.10 0.016 ±0.004 #4 1.27 0.050 #8 5.13 MAX 0.202 #1 4.92 ±0.20 0.194 ±0.008 ( 0.56 ) 0.022 1.55 ±0.20 0.061 ±0.008 0.1~0.25 0.004~0.001 MAX0.10 MAX0.004 +0.10 0.15 -0.05 +0.004 0.006 -0.002 1.80 MAX 0.071 3.95 ±0.20 0.156 ±0.008 0~ 8° 5.72 0.225 0.50 ±0.20 0.020 ±0.008 September 2001, Rev B1 sop8_dim.pdf Figure 41. 8-Lead Small Outline Package (SOP) © 2006 Fairchild Semiconductor Corporation FAN7530 Rev. 1.0.2 www.fairchildsemi.com 19 FAN7530 Critical Conduction Mode PFC Controller Mechanical Dimensions (Continued) ® ACEx Across the board. Around the world.¥ ActiveArray¥ Bottomless¥ Build it Now¥ CoolFET¥ CROSSVOLT¥ CTL™ Current Transfer Logic™ DOME¥ 2 E CMOS¥ ® EcoSPARK EnSigna¥ FACT Quiet Series™ ® FACT ® FAST FASTr¥ FPS¥ ® FRFET GlobalOptoisolator¥ GTO¥ HiSeC¥ i-Lo¥ ImpliedDisconnect¥ IntelliMAX¥ ISOPLANAR¥ MICROCOUPLER¥ MicroPak¥ MICROWIRE¥ Motion-SPM™ MSX¥ MSXPro¥ OCX¥ OCXPro¥ ® OPTOLOGIC ® OPTOPLANAR PACMAN¥ PDP-SPM™ POP¥ ® Power220 ® Power247 PowerEdge¥ PowerSaver¥ Power-SPM¥ ® PowerTrench Programmable Active Droop¥ ® QFET QS¥ QT Optoelectronics¥ Quiet Series¥ RapidConfigure¥ RapidConnect¥ ScalarPump¥ SMART START¥ ® SPM STEALTH™ SuperFET¥ SuperSOT¥-3 SuperSOT¥-6 SuperSOT¥-8 SyncFET™ TCM¥ ® The Power Franchise TinyBoost¥ TinyBuck¥ ® TinyLogic TINYOPTO¥ TinyPower¥ TinyWire¥ TruTranslation¥ PSerDes¥ ® UHC UniFET¥ VCX¥ Wire¥ ™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I26 © 2006 Fairchild Semiconductor Corporation FAN7530 Rev. 1.0.2 www.fairchildsemi.com 20 FAN7530 Critical Conduction Mode PFC Controller TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.