Cypress CY7C1380D 18-mbit (512 k x 36/1 m x 18) pipelined sram Datasheet

CY7C1380D
CY7C1380F
CY7C1382D
18-Mbit (512 K × 36/1 M × 18)
Pipelined SRAM
18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM
Features
Functional Description
■
Supports bus operation up to 250 MHz
■
Available speed grades are 250, 200, and 167 MHz
■
Registered inputs and outputs for pipelined operation
■
3.3 V core power supply
■
2.5 V or 3.3 V I/O power supply
■
Fast clock-to-output times
❐ 2.6 ns (for 250 MHz device)
■
Provides high performance 3-1-1-1 access rate
■
User selectable burst counter supporting Intel® Pentium®
interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self-timed write
■
Asynchronous output enable
■
Single cycle chip deselect
■
CY7C1380D/CY7C1382D is available in JEDEC-standard
Pb-free 100-pin TQFP package; CY7C1380F is available in
non Pb-free 165-ball FBGA package
■
IEEE 1149.1 JTAG-Compatible Boundary Scan
■
ZZ sleep mode option
The CY7C1380D/CY7C1380F/CY7C1382D SRAM integrates
524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. All synchronous inputs are gated by
registers controlled by a positive edge triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE1), depth-expansion
chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP,
and ADV), write enables (BWX, and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when address strobe processor (ADSP) or address strobe
controller (ADSC) are active. Subsequent burst addresses can
be internally generated as they are controlled by the advance pin
(ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle. This part supports byte write
operations (see Pin Definitions on page 6 and Truth Table on
page 9 for further details). Write cycles can be one to two or four
bytes wide as controlled by the byte write control inputs. GW
when active LOW causes all bytes to be written.
The CY7C1380D/CY7C1380F/CY7C1382D operates from a
+3.3 V core power supply while all outputs operate with a +2.5
or +3.3 V power supply. All inputs and outputs are
JEDEC-standard and JESD8-5-compatible.
Selection Guide
Description
250 MHz
200 MHz
167 MHz
Unit
Maximum Access Time
2.6
3.0
3.4
ns
Maximum Operating Current
350
300
275
mA
Maximum CMOS Standby Current
70
70
70
mA
Cypress Semiconductor Corporation
Document Number: 38-05543 Rev. *N
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 23, 2013
CY7C1380D
CY7C1380F
CY7C1382D
Logic Block Diagram – CY7C1380D/CY7C1380F
A0, A1, A
ADDRESS
REGISTER
2
A [1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER
CLR AND
LOGIC
ADSC
Q0
ADSP
BW D
DQ D , DQP D
BYTE
WRITE REGISTER
DQ D ,DQP D
BYTE
WRITE DRIVER
BW C
DQ C , DQP C
BYTE
WRITE REGISTER
DQ C , DQP C
BYTE
WRITE DRIVER
DQ B , DQP B
BYTE
WRITE REGISTER
DQ B , DQP B
BYTE
WRITE DRIVER
BW B
BW A
BWE
ZZ
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQP A
DQP B
DQP C
DQP D
DQ A , DQP A
BYTE
WRITE DRIVER
DQ A , DQP A
BYTE
WRITE REGISTER
GW
CE 1
CE 2
CE 3
OE
MEMORY
ARRAY
ENABLE
REGISTER
INPUT
REGISTERS
PIPELINED
ENABLE
SLEEP
CONTROL
Logic Block Diagram – CY7C1382D
A0, A1, A
ADDRESS
REGISTER
2
BURST Q1
COUNTER AND
LOGIC
ADV
CLK
ADSC
BW B
DQ B, DQP B
WRITE DRIVER
DQ B, DQP B
WRITE REGISTER
MEMORY
ARRAY
BW A
SENSE
OUTPUT
OUTPUT
BUFFERS
DQs
DQP A
DQP B
DQ A, DQP A
WRITE DRIVER
DQ A, DQP A
WRITE REGISTER
BWE
GW
CE 1
CE2
CE3
INPUT
ENABLE
REGISTER
PIPELINED
ENABLE
OE
ZZ
SLEEP
CONTROL
Document Number: 38-05543 Rev. *N
Page 2 of 37
CY7C1380D
CY7C1380F
CY7C1382D
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 7
Single Read Accesses ................................................ 7
Single Write Accesses Initiated by ADSP ................... 7
Single Write Accesses Initiated by ADSC ................... 8
Burst Sequences ......................................................... 8
Sleep Mode ................................................................. 8
Interleaved Burst Address Table ................................. 8
Linear Burst Address Table ......................................... 8
ZZ Mode Electrical Characteristics .............................. 8
Truth Table ........................................................................ 9
Truth Table for Read/Write ............................................ 10
Truth Table for Read/Write ............................................ 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ...................................... 11
Test Access Port (TAP) ............................................. 11
PERFORMING A TAP RESET .................................. 11
TAP REGISTERS ...................................................... 11
TAP Instruction Set ................................................... 11
Reserved ................................................................... 12
TAP Controller State Diagram ....................................... 13
TAP Controller Block Diagram ...................................... 14
TAP Timing ...................................................................... 15
TAP AC Switching Characteristics ............................... 15
3.3 V TAP AC Test Conditions ....................................... 16
3.3 V TAP AC Output Load Equivalent ......................... 16
2.5 V TAP AC Test Conditions ....................................... 16
2.5 V TAP AC Output Load Equivalent ......................... 16
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 16
Document Number: 38-05543 Rev. *N
Identification Register Definitions ................................ 17
Scan Register Sizes ....................................................... 17
Identification Codes ....................................................... 17
Boundary Scan Order .................................................... 18
Maximum Ratings ........................................................... 19
Operating Range ............................................................. 19
Electrical Characteristics ............................................... 19
Capacitance .................................................................... 20
Thermal Resistance ........................................................ 20
AC Test Loads and Waveforms ..................................... 21
Switching Characteristics .............................................. 22
Switching Waveforms .................................................... 23
Ordering Information ...................................................... 27
Ordering Code Definitions ......................................... 27
Package Diagrams .......................................................... 28
Acronyms ........................................................................ 30
Document Conventions ................................................. 30
Units of Measure ....................................................... 30
Appendix: Silicon Errata Document for
RAM9 (90-nm), 18-Mb (CY7C138*D)
Synchronous & NoBL™ SRAMs ................................... 31
Part Numbers Affected .............................................. 31
Product Status ........................................................... 31
Ram9 Sync/NoBL ZZ Pin,
JTAG & Chip Enable Issues Errata Summary .................. 31
Document History Page ................................................. 34
Sales, Solutions, and Legal Information ...................... 37
Worldwide Sales and Design Support ....................... 37
Products .................................................................... 37
PSoC Solutions ......................................................... 37
Page 3 of 37
CY7C1380D
CY7C1380F
CY7C1382D
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (3-Chip Enable)
CY7C1380D (512 K × 36)
Document Number: 38-05543 Rev. *N
CY7C1382D (1 M × 18)
Page 4 of 37
CY7C1380D
CY7C1380F
CY7C1382D
Pin Configurations (continued)
Figure 2. 165-ball FBGA (13 × 15 × 1.4 mm) pinout (3-Chip Enable)
CY7C1380F (512 K × 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
R
2
3
4
5
6
7
8
9
10
11
CE1
BWC
BWB
CE3
NC
BWE
ADSC
ADV
A
NC/144M
A
CE2
BWD
BWA
CLK
GW
OE
ADSP
A
NC/576M
DQPC
DQC
NC
DQC
VDDQ
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
VDDQ
NC/1G
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
NC
DQD
DQC
NC
DQD
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
DQB
NC
DQA
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC
NC/72M
A
A
TDI
A1
TDO
A
A
A
A
MODE
NC/36M
A
A
TMS
TCK
A
A
A
A
A
Document Number: 38-05543 Rev. *N
VSS
A0
Page 5 of 37
CY7C1380D
CY7C1380F
CY7C1382D
Pin Definitions
Name
A0, A1, A
I/O
Description
InputAddress inputs used to select one of the address locations. Sampled at the rising edge of the CLK
Synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1:A0 are fed to the two-bit
counter.
InputByte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled
BWA, BWB,
BWC, BWD Synchronous on the rising edge of CLK.
GW
InputGlobal write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write
Synchronous is conducted (all bytes are written, regardless of the values on BWX and BWE).
BWE
InputByte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted
Synchronous LOW to conduct a byte write.
CLK
InputClock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE1
InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a
new external address is loaded.
CE2
InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded.
CE3
InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded.
OE
InputOutput enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
Asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
InputAdvance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
Synchronous automatically increments the address in a burst cycle.
ADSP
InputAddress strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
ADSC
InputAddress strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ
InputZZ sleep input. This active HIGH input places the device in a non-time critical sleep condition with data
Asynchronous integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal
pull down.
DQs, DQPX
I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled
by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed
in a tri-state condition.
VDD
Power Supply Power supply inputs to the core of the device
VSS
Ground
Ground for the core of the device.
VSSQ
I/O Ground Ground for the I/O circuitry.
VDDQ
I/O Power
Supply
MODE
Input-Static Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and must remain static during device operation.
Mode pin has an internal pull up.
Power supply for the I/O circuitry.
Document Number: 38-05543 Rev. *N
Page 6 of 37
CY7C1380D
CY7C1380F
CY7C1382D
Pin Definitions (continued)
Name
I/O
Description
TDO
JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is
not being utilized, this pin must be disconnected. This pin is not available on TQFP packages.
output
Synchronous
TDI
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being
input
utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
Synchronous
TMS
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being
input
utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
Synchronous
TCK
JTAGClock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected
to VSS. This pin is not available on TQFP packages.
NC
–
No Connects. 36M, 72M, 144M, 288M, 576M, and 1G are address expansion pins and are not internally
connected to the die.
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (tCO) is 2.6 ns (250 MHz device).
CY7C1380D/CY7C1380F/CY7C1382D supports secondary
cache in systems using a linear or interleaved burst sequence.
The interleaved burst order supports Pentium and i486
processors. The linear burst sequence suits processors that use
a linear burst sequence. The burst order is user selectable, and
is determined by sampling the MODE input. Accesses can be
initiated with either the processor address strobe (ADSP) or the
controller address strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BWX) inputs. A global write enable
(GW) overrides all byte write inputs and writes data to all four
bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous chip selects (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1 is
HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) CE1, CE2, CE3 are all asserted active, and (3) the write
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE1 is HIGH. The address presented to the address inputs (A)
is stored into the address advancement logic and the address
register while being presented to the memory array. The
corresponding data is enabled to propagate to the input of the
Document Number: 38-05543 Rev. *N
output registers. At the rising edge of the next clock, the data is
enabled to propagate through the output register and onto the
data bus within 2.6 ns (250 MHz device) if OE is active LOW. The
only exception occurs when the SRAM is emerging from a
deselected state to a selected state; its outputs are always
tri-stated during the first cycle of the access. After the first cycle
of the access, the outputs are controlled by the OE signal.
Consecutive single read cycles are supported. Once the SRAM
is deselected at clock rise by the chip select and either ADSP or
ADSC signals, its output tri-states immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW and (2) CE1,
CE2, and CE3 are all asserted active. The address presented to
A is loaded into the address register and the address
advancement logic while being delivered to the memory array.
The write signals (GW, BWE, and BWX) and ADV inputs are
ignored during this first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the
corresponding address location in the memory array. If GW is
HIGH, then the write operation is controlled by BWE and BWX
signals.
CY7C1380D/CY7C1380F/CY7C1382D provides byte write
capability that is described in the write cycle descriptions table.
Asserting the byte write enable input (BWE) with the selected
byte write (BWX) input, selectively writes to only the desired
bytes. Bytes not selected during a byte write operation remain
unaltered. A synchronous self-timed write mechanism has been
provided to simplify the write operations.
CY7C1380D/CY7C1380F/CY7C1382D is a common I/O device,
the output enable (OE) must be deserted HIGH before
presenting data to the DQs inputs. Doing so tri-states the output
drivers. As a safety precaution, DQs are automatically tri-stated
whenever a write cycle is detected, regardless of the state of OE.
Page 7 of 37
CY7C1380D
CY7C1380F
CY7C1382D
Single Write Accesses Initiated by ADSC
Sleep Mode
ADSC write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deserted
HIGH, (3) CE1, CE2, and CE3 are all asserted active, and (4) the
appropriate combination of the write inputs (GW, BWE, and
BWX) are asserted active to conduct a write to the desired
byte(s). ADSC-triggered Write accesses require a single clock
cycle to complete. The address presented to A is loaded into the
address register and the address advancement logic while being
delivered to the memory array. The ADV input is ignored during
this cycle. If a global write is conducted, the data presented to
the DQs is written into the corresponding address location in the
memory core. If a byte write is conducted, only the selected bytes
are written. Bytes not selected during a byte write operation
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. While in
this mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
deselected prior to entering the sleep mode. CE1, CE2, CE3,
ADSP, and ADSC must remain inactive for the duration of tZZREC
after the ZZ input returns LOW.
CY7C1380D/CY7C1380F/CY7C1382D is a common I/O device,
the output enable (OE) must be deserted HIGH before
presenting data to the DQs inputs. Doing so tri-states the output
drivers. As a safety precaution, DQs are automatically tri-stated
whenever a write cycle is detected, regardless of the state of OE.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1:A0
00
01
10
11
Second
Address
A1:A0
01
00
11
10
Third
Address
A1:A0
10
11
00
01
Fourth
Address
A1:A0
11
10
01
00
Third
Address
A1:A0
10
11
00
01
Fourth
Address
A1:A0
11
00
01
10
Burst Sequences
CY7C1380D/CY7C1380F/CY7C1382D provides a two-bit
wraparound counter, fed by A1:A0, that implements an
interleaved or a linear burst sequence. The interleaved burst
sequence is designed specifically to support Intel Pentium
applications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input.
Asserting ADV LOW at clock rise automatically increments the
burst counter to the next address in the burst sequence. Both
read and write burst operations are supported.
Linear Burst Address Table
(MODE = GND)
First
Address
A1:A0
00
01
10
11
Second
Address
A1:A0
01
10
11
00
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to sleep current
ZZ Inactive to exit sleep current
Document Number: 38-05543 Rev. *N
Test Conditions
ZZ > VDD– 0.2 V
ZZ > VDD – 0.2 V
ZZ < 0.2 V
This parameter is sampled
This parameter is sampled
Min
–
–
2tCYC
–
0
Max
80
2tCYC
–
2tCYC
–
Unit
mA
ns
ns
ns
ns
Page 8 of 37
CY7C1380D
CY7C1380F
CY7C1382D
Truth Table
The Truth Table for CY7C1380D/CY7C1380F/CY7C1382D follows. [1, 2, 3, 4, 5]
Operation
Add. Used
CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Deselect Cycle, Power Down
None
H
X
X
L
X
L
X
X
X
L–H Tri-state
Deselect Cycle, Power Down
None
L
L
X
L
L
X
X
X
X
L–H Tri-state
Deselect Cycle, Power Down
None
L
X
H
L
L
X
X
X
X
L–H Tri-state
Deselect Cycle, Power Down
None
L
L
X
L
H
L
X
X
X
L–H Tri-state
L–H Tri-state
Deselect Cycle, Power Down
None
L
X
H
L
H
L
X
X
X
Sleep Mode, Power Down
None
X
X
X
H
X
X
X
X
X
X
Tri-state
READ Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
L
L–H
Q
READ Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
H
L–H Tri-state
WRITE Cycle, Begin Burst
External
L
H
L
L
H
L
X
L
X
L–H
D
READ Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L–H
Q
READ Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L–H Tri-state
Next
X
X
X
L
H
H
L
H
L
L–H
READ Cycle, Continue Burst
Q
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L–H Tri-state
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L–H
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L–H Tri-state
WRITE Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L–H
WRITE Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L–H
D
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L–H
Q
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L–H Tri-state
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L–H
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L–H Tri-state
WRITE Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L–H
D
WRITE Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L–H
D
Q
D
Q
Notes
1. X = Don't Care, H = Logic HIGH, L = Logic LOW.
2. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care
for the remainder of the write cycle.
5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 38-05543 Rev. *N
Page 9 of 37
CY7C1380D
CY7C1380F
CY7C1382D
Truth Table for Read/Write
The Truth Table for Read/Write for CY7C1380D/CY7C1380F follows. [6, 7]
Function (CY7C1380D/CY7C1380F)
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte A – (DQA and DQPA)
H
L
H
H
H
L
Write Byte B – (DQB and DQPB)
H
L
H
H
L
H
Write Bytes B, A
H
L
H
H
L
L
Write Byte C – (DQC and DQPC)
H
L
H
L
H
H
Write Bytes C, A
H
L
H
L
H
L
Write Bytes C, B
H
L
H
L
L
H
Write Bytes C, B, A
H
L
H
L
L
L
Write Byte D – (DQD and DQPD)
H
L
L
H
H
H
Write Bytes D, A
H
L
L
H
H
L
Write Bytes D, B
H
L
L
H
L
H
Write Bytes D, B, A
H
L
L
H
L
L
Write Bytes D, C
H
L
L
L
H
H
Write Bytes D, C, A
H
L
L
L
H
L
Write Bytes D, C, B
H
L
L
L
L
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
GW
BWE
BWB
BWA
Read
H
H
X
X
Read
H
L
H
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
H
L
H
L
H
L
L
H
Write Bytes B, A
H
L
L
L
Write All Bytes
H
L
L
L
Write All Bytes
L
X
X
X
Truth Table for Read/Write
The Truth Table for Read/Write for CY7C1382D follows. [6, 7]
Function (CY7C1382D)
Notes
6. X = Don't Care, H = Logic HIGH, L = Logic LOW.
7. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is done based on which byte write is active.
Document Number: 38-05543 Rev. *N
Page 10 of 37
CY7C1380D
CY7C1380F
CY7C1382D
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1380F incorporates a serial boundary scan test
access port (TAP).This part is fully compliant with 1149.1. The
TAP operates using JEDEC-standard 3.3 V or 2.5 V I/O logic
levels.
CY7C1380F contains a TAP controller, instruction register,
boundary scan register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull up resistor. TDO
must be left unconnected. Upon power up, the device comes up
in a reset state which does not interfere with the operation of the
device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see TAP Controller State
Diagram on page 13. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine (see Identification Codes on page 17).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 14. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to enable fault
isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This enables data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
balls when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
The Boundary Scan Order on page 18 show the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions on
page 17.
TAP Instruction Set
Performing a TAP Reset
Overview
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in Identification
Codes on page 17. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in detail in this section.
At power up, the TAP is reset internally to ensure that TDO
comes up in a high Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
enable data to be scanned in and out of the SRAM test circuitry.
Only one register can be selected at a time through the
Document Number: 38-05543 Rev. *N
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
Page 11 of 37
CY7C1380D
CY7C1380F
CY7C1382D
the instruction once it is shifted in, the TAP controller must be
moved into the Update-IR state.
still possible to capture all other signals and simply ignore the
value of the CK and CK# captured in the boundary scan register.
EXTEST
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the Shift-DR controller state.
IDCODE
The IDCODE instruction causes a vendor-specific 32-bit code to
be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and enables
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. The SAMPLE Z command places
all SRAM outputs into a high Z state.
PRELOAD enables an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required; that is, while data captured is
shifted out, the preloaded data is shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
The boundary scan register has a special bit located at Bit #89
(for 165-ball FBGA package). When this scan cell, called the
“extest output bus tri-state,” is latched into the preload register
during the Update-DR state in the TAP controller, it directly
controls the state of the output (Q-bus) pins, when the EXTEST
is entered as the current instruction. When HIGH, it enables the
output buffers to drive the output bus. When LOW, this bit places
the output bus into a high Z condition.
The TAP controller clock can only operate at a frequency up to
20 MHz, while the SRAM clock operates more than an order of
magnitude faster. As there is a large difference in the clock
frequencies, it is possible that during the Capture-DR state, an
input or output undergoes a transition. The TAP may then try to
capture a signal while in transition (metastable state). This does
not harm the device, but there is no guarantee as to the value
that is captured. Repeatable results may not be possible.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
Reserved
SAMPLE/PRELOAD
Document Number: 38-05543 Rev. *N
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 12 of 37
CY7C1380D
CY7C1380F
CY7C1382D
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-IR
0
1
0
PAUSE-DR
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
UPDATE-IR
1
0
1
EXIT1-DR
0
1
0
1
0
The 0 or 1 next to each state represents the value of TMS at the rising edge of TCK.
Document Number: 38-05543 Rev. *N
Page 13 of 37
CY7C1380D
CY7C1380F
CY7C1382D
TAP Controller Block Diagram
0
Bypass Register
2 1 0
TDI
Selection
Circuitry
Instruction Register
31 30 29 . . . 2 1 0
S election
TDO
Circuitr y
Identification Register
x . . . . . 2 1 0
Boundary Scan Register
TCK
TMS
Document Number: 38-05543 Rev. *N
TAP CONTROLLER
Page 14 of 37
CY7C1380D
CY7C1380F
CY7C1382D
TAP Timing
Figure 3. TAP Timing
Test Clock
(TCK)
t
t TH
t TMSS
t TMSH
t TDIS
t TDIH
TL
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range
Parameter [8, 9]
Description
Min
Max
Unit
50
–
ns
Clock
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
–
20
MHz
tTH
TCK Clock HIGH time
20
–
ns
tTL
TCK Clock LOW time
20
–
ns
tTDOV
TCK Clock LOW to TDO Valid
–
10
ns
tTDOX
TCK Clock LOW to TDO Invalid
0
–
ns
tTMSS
TMS Setup to TCK Clock Rise
5
–
ns
tTDIS
TDI Setup to TCK Clock Rise
5
–
ns
tCS
Capture Setup to TCK Rise
5
–
ns
tTMSH
TMS Hold after TCK Clock Rise
5
–
ns
tTDIH
TDI Hold after Clock Rise
5
–
ns
tCH
Capture Hold after Clock Rise
5
–
ns
Output Times
Setup Times
Hold Times
Notes
8. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
9. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document Number: 38-05543 Rev. *N
Page 15 of 37
CY7C1380D
CY7C1380F
CY7C1382D
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input pulse levels ............................................... VSS to 2.5 V
Input rise and fall times ...................................................1 ns
Input rise and fall time ....................................................1 ns
Input timing reference levels ......................................... 1.5 V
Input timing reference levels ....................................... 1.25 V
Output reference levels ................................................ 1.5 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage ............................ 1.5 V
Test load termination supply voltage .......................... 1.25 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
Z O= 50 Ω
Z O= 50 Ω
20pF
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted)
Parameter [10]
Description
Min
Max
Unit
IOH = –4.0 mA, VDDQ = 3.3 V
Test Conditions
2.4
–
V
IOH = –1.0 mA, VDDQ = 2.5 V
2.0
–
V
IOH = –100 µA
VDDQ = 3.3 V
2.9
–
V
VDDQ = 2.5 V
2.1
–
V
VDDQ = 3.3 V
–
0.4
V
VDDQ = 2.5 V
–
0.4
V
VDDQ = 3.3 V
–
0.2
V
–
0.2
V
2.0
VDD + 0.3
V
1.7
VDD + 0.3
V
–0.3
0.8
V
VOH1
Output HIGH Voltage
VOH2
Output HIGH Voltage
VOL1
Output LOW Voltage
IOL = 8.0 mA
VOL2
Output LOW Voltage
IOL = 100 µA
VDDQ = 2.5 V
VIH
Input HIGH Voltage
VDDQ = 3.3 V
VDDQ = 2.5 V
VIL
Input LOW Voltage
VDDQ = 3.3 V
VDDQ = 2.5 V
–0.3
0.7
V
IX
Input Load Current
–5
5
µA
GND < VIN < VDDQ
Note
10. All voltages referenced to VSS (GND).
Document Number: 38-05543 Rev. *N
Page 16 of 37
CY7C1380D
CY7C1380F
CY7C1382D
Identification Register Definitions
Instruction Field
CY7C1380F (512 K × 36)
Revision Number (31:29)
000
Device Depth (28:24) [11]
01011
Description
Describes the version number.
Reserved for internal use.
Device Width (23:18) 165-ball FBGA
000000
Defines the memory type and architecture.
Cypress Device ID (17:12)
100101
Defines the width and density.
Cypress JEDEC ID Code (11:1)
00000110100
ID Register Presence Indicator (0)
1
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (× 36)
Instruction
3
Bypass
1
ID
32
Boundary Scan Order (165-ball FBGA package)
89
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to high Z state.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a high Z state.
RESERVED
011
Do Not Use. This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
101
Do Not Use. This instruction is reserved for future use.
RESERVED
110
Do Not Use. This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note
11. Bit #24 is 1 in the register definitions for both 2.5 V and 3.3 V versions of this device.
Document Number: 38-05543 Rev. *N
Page 17 of 37
CY7C1380D
CY7C1380F
CY7C1382D
Boundary Scan Order
165-ball BGA [12, 13]
Bit #
Ball ID
Bit #
Ball ID
Bit #
Ball ID
1
N6
31
D10
61
G1
2
N7
32
C11
62
D2
3
N10
33
A11
63
E2
4
P11
34
B11
64
F2
5
P8
35
A10
65
G2
6
R8
36
B10
66
H1
7
R9
37
A9
67
H3
8
P9
38
B9
68
J1
9
P10
39
C10
69
K1
10
R10
40
A8
70
L1
11
R11
41
B8
71
M1
12
H11
42
A7
72
J2
13
N11
43
B7
73
K2
14
M11
44
B6
74
L2
15
L11
45
A6
75
M2
16
K11
46
B5
76
N1
17
J11
47
A5
77
N2
18
M10
48
A4
78
P1
19
L10
49
B4
79
R1
20
K10
50
B3
80
R2
21
J10
51
A3
81
P3
22
H9
52
A2
82
R3
23
H10
53
B2
83
P2
24
G11
54
C2
84
R4
25
F11
55
B1
85
P4
26
E11
56
A1
86
N5
27
D11
57
C1
87
P6
28
G10
58
D1
88
R6
89
Internal
29
F10
59
E1
30
E10
60
F1
Note
12. Balls which are NC (No Connect) are pre-set LOW.
13. Bit# 89 is pre-set HIGH.
Document Number: 38-05543 Rev. *N
Page 18 of 37
CY7C1380D
CY7C1380F
CY7C1382D
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. For user guidelines, not tested.
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Supply Voltage on VDD Relative to GND .....–0.3 V to +4.6 V
Supply Voltage on VDDQ Relative to GND .... –0.3 V to +VDD
DC Voltage Applied to Outputs
in tri-state ..........................................–0.5 V to VDDQ + 0.5 V
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .......................... > 2001 V
Latch-up Current .................................................... > 200 mA
Operating Range
Ambient
Temperature
Commercial
0 °C to +70 °C
Industrial
–40 °C to +85 °C
Range
VDD
VDDQ
3.3 V– 5% / 2.5 V – 5% to
+ 10%
VDD
Electrical Characteristics
Over the Operating Range
Parameter [14, 15]
Description
Power Supply Voltage
VDD
VDDQ
I/O Supply Voltage
VOH
VOL
VIH
VIL
IX
IOZ
IDD
ISB1
Test Conditions
for 3.3 V I/O
for 2.5 V I/O
Output HIGH Voltage
for 3.3 V I/O, IOH = –4.0 mA
for 2.5 V I/O, IOH = –1.0 mA
Output LOW Voltage
for 3.3 V I/O, IOL = 8.0 mA
for 2.5 V I/O, IOL = 1.0 mA
Input HIGH Voltage [14]
for 3.3 V I/O
for 2.5 V I/O
Input LOW Voltage [14]
for 3.3 V I/O
for 2.5 V I/O
Input Leakage Current except ZZ GND  VI  VDDQ
and MODE
Input Current of MODE
Input = VSS
Input = VDD
Input Current of ZZ
Input = VSS
Input = VDD
Output Leakage Current
GND  VI  VDDQ, Output Disabled
VDD Operating Supply Current
VDD = Max., IOUT = 0 mA,
4.0-ns cycle,
f = fMAX = 1/tCYC
250 MHz
5.0-ns cycle,
200 MHz
6.0-ns cycle,
167 MHz
Automatic CE Power Down
VDD = Max, Device Deselected, 4.0-ns cycle,
Current – TTL Inputs
VIN  VIH or VIN  VIL,
250 MHz
f = fMAX = 1/tCYC
5.0-ns cycle,
200 MHz
6.0-ns cycle,
167 MHz
Min
3.135
3.135
2.375
2.4
2.0
–
–
2.0
1.7
–0.3
–0.3
–5
Max
Unit
3.6
V
VDD
V
2.625
V
–
V
–
V
0.4
V
0.4
V
VDD + 0.3 V
V
V
VDD + 0.3 V
0.8
V
0.7
V
5
A
–5
–
–
5
–
30
5
350
A
A
A
A
A
mA
–
300
mA
–
275
mA
–
160
mA
–
150
mA
–
140
mA
–30
–5
Notes
14. Overshoot: VIH(AC) < VDD + 1.5 V (pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2).
15. TPower up: Assumes a linear ramp from 0 V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 38-05543 Rev. *N
Page 19 of 37
CY7C1380D
CY7C1380F
CY7C1382D
Electrical Characteristics (continued)
Over the Operating Range
Parameter [14, 15]
Description
Automatic CE Power Down
ISB2
Current – CMOS Inputs
ISB3
Automatic CE Power Down
Current – CMOS Inputs
ISB4
Automatic CE Power Down
Current – TTL Inputs
Test Conditions
VDD = Max, Device Deselected,
VIN  0.3 V or VIN > VDDQ – 0.3 V,
f=0
VDD = Max, Device Deselected,
VIN  0.3 V or VIN > VDDQ – 0.3 V,
f = fMAX = 1/tCYC
All speeds
4.0-ns cycle,
250 MHz
5.0-ns cycle,
200 MHz
6.0-ns cycle,
167 MHz
VDD = Max, Device Deselected, All speeds
VIN  VIH or VIN  VIL, f = 0
Min
–
Max
70
Unit
mA
–
135
mA
–
130
mA
–
125
mA
–
80
mA
Capacitance
Parameter [16]
Description
CIN
Input capacitance
CCLK
Clock input capacitance
CIO
Input/Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
100-pin TQFP 165-ball FBGA Unit
Package
Package
5
9
pF
5
9
pF
5
9
pF
Thermal Resistance
Parameter [16]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, in accordance with
EIA/JESD51.
100-pin TQFP 165-ball FBGA Unit
Package
Package
28.66
20.7
°C/W
4.08
4.0
°C/W
Note
16. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05543 Rev. *N
Page 20 of 37
CY7C1380D
CY7C1380F
CY7C1382D
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317 
3.3 V
OUTPUT
OUTPUT
RL = 50 
Z0 = 50 
GND
5 pF
R = 351 
VT = 1.5 V
INCLUDING
JIG AND
SCOPE
(a)
2.5 V I/O Test Load
OUTPUT
RL = 50 
Z0 = 50 
VT = 1.25 V
(a)
Document Number: 38-05543 Rev. *N
10%
(c)
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
 1 ns
(b)
GND
5 pF
R = 1538 
(b)
90%
10%
90%
 1 ns
R = 1667 
2.5 V
OUTPUT
ALL INPUT PULSES
VDDQ
10%
90%
10%
90%
 1 ns
 1 ns
(c)
Page 21 of 37
CY7C1380D
CY7C1380F
CY7C1382D
Switching Characteristics
Over the Operating Range
Parameter [17, 18]
tPOWER
250 MHz
Description
VDD(typical) to the first Access [19]
200 MHz
167 MHz
Unit
Min
Max
Min
Max
Min
Max
1
–
1
–
1
–
ms
Clock
tCYC
Clock Cycle Time
4.0
–
5
–
6
–
ns
tCH
Clock HIGH
1.7
–
2.0
–
2.2
–
ns
tCL
Clock LOW
1.7
–
2.0
–
2.2
–
ns
Output Times
tCO
Data Output Valid After CLK Rise
–
2.6
–
3.0
–
3.4
ns
tDOH
Data Output Hold After CLK Rise
1.0
–
1.3
–
1.3
–
ns
tCLZ
Clock to Low-Z [20, 21, 22]
1.0
–
1.3
–
1.3
–
ns
tCHZ
Clock to High-Z
[20, 21, 22]
–
2.6
–
3.0
–
3.4
ns
tOEV
OE LOW to Output Valid
–
2.6
–
3.0
–
3.4
ns
0
–
0
–
0
–
ns
–
2.6
–
3.0
–
3.4
ns
[20, 21, 22]
tOELZ
OE LOW to Output Low-Z
tOEHZ
OE HIGH to Output High-Z [20, 21, 22]
Setup Times
tAS
Address Setup Before CLK Rise
1.2
–
1.4
–
1.5
–
ns
tADS
ADSC, ADSP Setup Before CLK Rise
1.2
–
1.4
–
1.5
–
ns
tADVS
ADV Setup Before CLK Rise
1.2
–
1.4
–
1.5
–
ns
tWES
GW, BWE, BWX Setup Before CLK
Rise
1.2
–
1.4
–
1.5
–
ns
tDS
Data Input Setup Before CLK Rise
1.2
–
1.4
–
1.5
–
ns
tCES
Chip Enable SetUp Before CLK Rise
1.2
–
1.4
–
1.5
–
ns
tAH
Address Hold After CLK Rise
0.3
–
0.4
–
0.5
–
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.3
–
0.4
–
0.5
–
ns
tADVH
ADV Hold After CLK Rise
0.3
–
0.4
–
0.5
–
ns
tWEH
GW, BWE, BWX Hold After CLK Rise
0.3
–
0.4
–
0.5
–
ns
tDH
Data Input Hold After CLK Rise
0.3
–
0.4
–
0.5
–
ns
tCEH
Chip Enable Hold After CLK Rise
0.3
–
0.4
–
0.5
–
ns
Hold Times
Notes
17. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
18. Test conditions shown in (a) of Figure 4 on page 21 unless otherwise noted.
19. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can
be initiated.
20. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 4 on page 21. Transition is measured ±200 mV from steady-state voltage.
21. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system conditions.
22. This parameter is sampled and not 100% tested.
Document Number: 38-05543 Rev. *N
Page 22 of 37
CY7C1380D
CY7C1380F
CY7C1382D
Switching Waveforms
Figure 5. Read Cycle Timing [23]
t CYC
CLK
t
t
ADS
CH
t
CL
t
ADH
ADSP
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
t WES
A3
Burst continued with
new base address
tWEH
GW, BWE,
BWx
t CES
Deselect
cycle
tCEH
CE
t ADVS
tADVH
ADV
ADV
suspends
burst.
OE
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t OEV
t CO
t OELZ
t DOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
t CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note
23. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document Number: 38-05543 Rev. *N
Page 23 of 37
CY7C1380D
CY7C1380F
CY7C1382D
Switching Waveforms (continued)
Figure 6. Write Cycle Timing [24, 25]
t CYC
CLK
tCH
t ADS
tCL
tADH
ADSP
t ADS
ADSC extends burst
tADH
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t WES tWEH
BWE,
BW X
t WES tWEH
GW
t CES
tCEH
CE
t
t
ADVS ADVH
ADV
ADV suspends burst
OE
t DS
Data In (D)
High-Z
t
OEHZ
tDH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
ata Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Notes
24. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
25. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
Document Number: 38-05543 Rev. *N
Page 24 of 37
CY7C1380D
CY7C1380F
CY7C1382D
Switching Waveforms (continued)
Figure 7. Read/Write Cycle Timing [26, 27, 28]
tCYC
CLK
tCL
tCH
t ADS
tADH
t AS
tAH
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
t WES tWEH
BWE,
BW X
t CES
tCEH
CE
ADV
OE
t DS
tCO
tDH
t OELZ
Data In (D)
High-Z
tOEHZ
tCLZ
Data Out (Q)
High-Z
Q(A1)
D(A5)
D(A3)
Q(A2)
Back-to-Back READs
Q(A4)
Single WRITE
Q(A4+1)
BURST READ
DON’T CARE
Q(A4+2)
D(A6)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes
26. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
27. The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
28. GW is HIGH.
Document Number: 38-05543 Rev. *N
Page 25 of 37
CY7C1380D
CY7C1380F
CY7C1382D
Switching Waveforms (continued)
Figure 8. ZZ Mode Timing [29, 30]
CLK
t
ZZ
I
t
t
ZZ
ZZREC
ZZI
SUPPLY
I
t RZZI
DDZZ
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
29. Device must be deselected when entering ZZ mode. See Truth Table on page 9 for all possible signal conditions to deselect the device.
30. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 38-05543 Rev. *N
Page 26 of 37
CY7C1380D
CY7C1380F
CY7C1382D
Ordering Information
The below table lists the key package features and ordering codes. The table contains only the parts that are currently available. If
you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at
www.cypress.com and refer to the product summary page at http://www.cypress.com/products.
Speed
(MHz)
Package
Diagram
Ordering Code
Part and Package Type
Operating
Range
250
CY7C1380D-250AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
200
CY7C1380D-200AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
CY7C1380D-167AXI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Industrial
CY7C1380F-167BZI
51-85180 165-ball FBGA (13 × 15 × 1.4 mm)
CY7C1382D-200AXC
167
CY7C1380D-167AXC
CY7C1382D-167AXC
Ordering Code Definitions
CY 7
C 138X X -
XXX
XX X
X
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type: XX = A or BZ
A = 100-pin TQFP
BZ = 165-ball FPBGA
Frequency Range: XXX = 250 MHz or 200 MHz or 167 MHz
Die Revision: X = D or F
D  90 nm
F  90nm errata fix PCN084636
Part Identifier: 138X = 1380 or 1382
1380 = SCD, 512 K × 36 (18 Mb)
1382 = SCD, 1 Mb × 18 (18 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05543 Rev. *N
Page 27 of 37
CY7C1380D
CY7C1380F
CY7C1382D
Package Diagrams
Figure 9. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *D
Document Number: 38-05543 Rev. *N
Page 28 of 37
CY7C1380D
CY7C1380F
CY7C1382D
Package Diagrams (continued)
Figure 10. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180
51-85180 *F
Document Number: 38-05543 Rev. *N
Page 29 of 37
CY7C1380D
CY7C1380F
CY7C1382D
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
FBGA
Fine-Pitch Ball Grid Array
°C
degree Celsius
I/O
Input/Output
MHz
megahertz
JTAG
Joint Test Action Group
µA
microampere
LSB
Least Significant Bit
mA
milliampere
MSB
Most Significant Bit
mm
millimeter
Symbol
Unit of Measure
OE
Output Enable
ms
millisecond
SRAM
Static Random Access Memory
ns
nanosecond
TCK
Test Clock

ohm
TMS
Test Mode Select
%
percent
TDI
Test Data-In
pF
picofarad
TDO
Test Data-Out
V
volt
TQFP
Thin Quad Flat Pack
W
watt
TTL
Transistor-Transistor Logic
Document Number: 38-05543 Rev. *N
Page 30 of 37
CY7C1380D
CY7C1380F
CY7C1382D
Appendix: Silicon Errata Document for RAM9 (90-nm), 18-Mb (CY7C138*D) Synchronous &
NoBL™ SRAMs
This section describes the Ram9 Sync/NOBL ZZ pin, JTAG and Chip Enable issues. Details include trigger conditions, the devices
affected, proposed workaround and silicon revision applicability. Please contact your local Cypress sales representative if you have
further questions.
Part Numbers Affected
Density & Revision
Package Type
Operating Range
18Mb-Ram9 Synchronous SRAMs: CY7C138*D
All packages
Commercial/
Industrial
Product Status
All of the devices in the Ram9 4Mb/18Mb/72Mb Sync/NoBL family are qualified and available in production quantities.
Ram9 Sync/NoBL ZZ Pin, JTAG & Chip Enable Issues Errata Summary
The following table defines the errata applicable to available Ram9 18Mb Sync/NoBL family devices.
Item
Description
Device
1.
ZZ Pin
Issues
When asserted HIGH, the ZZ pin places
device in a “sleep” condition with data integrity
preserved.The ZZ pin currently does not have
an internal pull-down resistor and hence
cannot be left floating externally by the user
during normal mode of operation.
18M-Ram9 (90nm)
For the 18M Ram9 (90 nm)
devices, there is no plan to fix
this issue.
2.
JTAG
Functionality
During JTAG test mode, the Boundary scan
circuitry does not perform as described in the
datasheet.However, it is possible to perform
the JTAG test with these devices in “BYPASS
mode”.
18M-Ram9 (90nm)
This issue will be fixed in the
new revision, which use the
65 nm technology. Please
contact your local sales rep for
availability.
3.
Chip Enable
The internal Chip Enable CE3# pad is floating 18M-Ram9 Synchronous
instead of being tied to Ground. This floating SRAMs 119-ball BGA
input may cause unstable behavior of the
package option only
device during normal mode of operation.
(90nm)
Document Number: 38-05543 Rev. *N
Fix Status
This issue was fixed in the new
revision of the device by a
substrate change. Please
contact your local sales rep for
availability.
Page 31 of 37
CY7C1380D
CY7C1380F
CY7C1382D
1. ZZ Pin Issue
■
PROBLEM DEFINITION
The problem occurs only when the device is operated in the normal mode with ZZ pin left floating. The ZZ pin on the SRAM
device does not have an internal pull-down resistor. Switching noise in the system may cause the SRAM to recognize a HIGH
on the ZZ input, which may cause the SRAM to enter sleep mode. This could result in incorrect or undesirable operation of the
SRAM.
■
TRIGGER CONDITIONS
Device operated with ZZ pin left floating.
■
SCOPE OF IMPACT
When the ZZ pin is left floating, the device delivers incorrect data.
■
WORKAROUND
Tie the ZZ pin externally to ground.
■
FIX STATUS
Fix was done for the 72Mb RAM9 Synchronous SRAMs and 72M RAM9 NoBL SRAMs devices. Fixed devices have a new
revision. The following table lists the devices affected and the new revision after the fix.
2. JTAG Functionality
■
PROBLEM DEFINITION
The problem occurs only when the device is operated in the JTAG test mode.During this mode, the JTAG circuitry can perform
incorrectly by delivering the incorrect data or the incorrect scan chain length.
■
TRIGGER CONDITIONS
Several conditions can trigger this failure mode.
1. The device can deliver an incorrect length scan chain when operating in JTAG mode.
2. Some Byte Write inputs only recognize a logic HIGH level when in JTAG mode.
3. Incorrect JTAG data can be read from the device when the ZZ input is tied HIGH during JTAG operation.
■
SCOPE OF IMPACT
The device fails for JTAG test. This does not impact the normal functionality of the device.
■
WORKAROUND
1.Perform JTAG testing with these devices in “BYPASS mode”.
2.Do not use JTAG test.
Document Number: 38-05543 Rev. *N
Page 32 of 37
CY7C1380D
CY7C1380F
CY7C1382D
3. Chip Enable Issue
■
PROBLEM DEFINITION
The die used for CY7C138*D has three Chip Enables, CE1#, CE2 and CE3#. The devices having part numbers CY7C138*D
(with 119-ball BGA package option only) utilize a single Chip Enable (CE1#) signal. CE2 and CE3# signals which are unused
should be internally connected to Vcc and Ground respectively to keep them in “enabled” state, thus allowing CE1# to have
full control of the chip. The internal Chip Enable CE3# pad is floating instead of being tied to Ground. This state of CE3# signal
can result in incorrect or undesirable operation of the SRAM.
■
TRIGGER CONDITIONS
There are no specific trigger conditions. The issue can occur at any time during the normal operation of the device.
■
SCOPE OF IMPACT
This issue affects the normal functionality, and can cause unstable operation of the device.
■
WORKAROUND
Use the fixed revision of the device.
■
FIX STATUS
Fix was done for all the devices having this issue and was involved re-design of the substrate in order to have CE2 and CE3#
pads bonded to Vcc and Ground lines respectively in the substrate. Fixed devices have a new revision. The following table lists
the devices affected and the new revision after the fix.
Table 1. List of Affected Devices and the new revision
Revision after the Fix
New Revision after the Fix
CY7C138*D (119-ball BGA package)
CY7C138*F (119-ball BGA package)
Document Number: 38-05543 Rev. *N
Page 33 of 37
CY7C1380D
CY7C1380F
CY7C1382D
Document History Page
Document Title: CY7C1380D/CY7C1380F/CY7C1382D, 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM
Document Number: 38-05543
Rev.
ECN No.
Submission
Date
Orig. of
Change
**
254515
See ECN
RKF
New data sheet.
*A
288531
See ECN
SYT
Updated Selection Guide (Removed 225 MHz and 133 MHz frequencies
related information).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Edited description for
non-compliance with 1149.1).
Updated Electrical Characteristics (Removed 225 MHz and 133 MHz
frequencies related information).
Updated Switching Characteristics (Removed 225 MHz and 133 MHz
frequencies related information).
Updated Ordering Information (Added Pb-free information for 100-pin TQFP,
119-ball BGA and 165-ball FBGA packages) and added comment for ‘Pb-free
BG packages availability’ below the Ordering Information.
*B
326078
See ECN
PCI
Updated Pin Configurations (Address expansion pins/balls in the pinouts for
all packages are modified as per JEDEC standard).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Updated TAP Instruction
Set (Updated OVERVIEW (description), updated EXTEST (description),
added EXTEST Output Bus Tri-State)).
Updated Identification Register Definitions (Splitted Device Width (23:18) into
two rows (one for 119-ball BGA and another for 165-ball FBGA), retained the
same values of 165-ball FBGA and changed the values from 000000 to 101000
for 119-ball BGA)
Updated Electrical Characteristics (Modified Test Conditions for VOL, VOH
parameters).
Updated Thermal Resistance (Changed JA and JC for 100-pin TQFP
Package from 31 and 6 C/W to 28.66 and 4.08 C/W respectively, changed
JA and JC for 119-ball BGA Package from 45 and 7 C/W to 23.8 and
6.2 C/W respectively, changed JA and JC for 165-ball FBGA Package from
46 and 3 C/W to 20.7 and 4.0 C/W respectively).
Updated Ordering Information (Updated part numbers) and removed comment
of ‘Pb-free BG packages availability’ below the Ordering Information.
*C
416321
See ECN
NXR
Changed status from Preliminary to Final.
Changed address of Cypress Semiconductor Corporation from “3901 North
First Street” to “198 Champion Court”.
Updated Electrical Characteristics (Changed the description of IX parameter
from Input Load Current to Input Leakage Current, changed the minimum and
maximum values of IX parameter (corresponding to Input Current of MODE)
from –5 A and 30 A to –30 A and 5 A, changed the minimum and maximum
values of IX parameter (corresponding to Input current of ZZ) from –30 A and
5 A to –5 A and 30 A, updated Note 15).
Updated Ordering Information (Updated part numbers) and replaced Package
Name column with Package Diagram in the Ordering Information table.
*D
475009
See ECN
VKN
Updated TAP AC Switching Characteristics (Changed minimum values of tTH,
and tTL parameters from 25 ns to 20 ns, and maximum value of tTDOV
parameter from 5 ns to 10 ns).
Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage
on VDDQ Relative to GND).
Updated Ordering Information (Updated part numbers).
Document Number: 38-05543 Rev. *N
Description of Change
Page 34 of 37
CY7C1380D
CY7C1380F
CY7C1382D
Document History Page (continued)
Document Title: CY7C1380D/CY7C1380F/CY7C1382D, 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM
Document Number: 38-05543
Rev.
ECN No.
Submission
Date
Orig. of
Change
Description of Change
*E
776456
See ECN
VKN
Updated Features (Included CY7C1380F/CY7C1382F related information).
Updated Functional Description (Included CY7C1380F/CY7C1382F related
information).
Updated Logic Block Diagram – CY7C1380D/CY7C1380F (Included
CY7C1380F related information, added the Note “CY7C1380F and
CY7C1382F in 119-ball BGA package have only 1 chip enable (CE1).” and
referred the same note in the title).
Updated Logic Block Diagram – CY7C1382D/CY7C1382F (Included
CY7C1382F related information, added the Note “CY7C1380F and
CY7C1382F in 119-ball BGA package have only 1 chip enable (CE1).” and
referred the same note in the title).
Updated Pin Configurations (Included CY7C1380F/CY7C1382F related
information).
Updated Functional Overview (Included CY7C1380F/CY7C1382F related
information).
Updated Truth Table (Included CY7C1380F/CY7C1382F related information).
Updated Truth Table for Read/Write (Included CY7C1380F related
information).
Updated Truth Table for Read/Write (Included CY7C1382F related
information).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Included
CY7C1380F/CY7C1382F related information).
Updated Identification Register Definitions (Included
CY7C1380F/CY7C1382F related information).
Updated Ordering Information (Updated part numbers).
*F
2648065
01/27/09
VKN /
PYRS
Updated Ordering Information (To include CY7C1380F/CY7C1382F in 100-pin
TSOP package and 165-ball FBGA package) and modified text on top of the
Ordering information table.
*G
2897120
03/22/2010
NJY
Updated Ordering Information (Removed inactive parts).
Updated Package Diagrams.
*H
3067398
10/20/10
NJY
Updated Ordering Information (The part CY7C1380F-167BGC is found to be
in “EOL-Prune” state in Oracle PLM and therefore, it has been removed) and
added Ordering Code Definitions.
*I
3159479
02/01/2011
NJY
Added Acronyms and Units of Measure.
Minor edits and updated in new template.
Updated Package Diagrams.
*J
3192403
03/10/2011
NJY
Updated in new template.
*K
3210400
03/30/11
NJY
Updated Ordering Information (Removed pruned part CY7C1380D-167BZC
from the ordering information table).
Document Number: 38-05543 Rev. *N
Page 35 of 37
CY7C1380D
CY7C1380F
CY7C1382D
Document History Page (continued)
Document Title: CY7C1380D/CY7C1380F/CY7C1382D, 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM
Document Number: 38-05543
Rev.
ECN No.
Submission
Date
*L
3575733
04/09/2012
*M
3945784
03/27/2013
PRIT
Updated Package Diagrams:
spec 51-85180 – Changed revision from *E to *F.
*N
3977530
04/23/2013
PRIT
Added Appendix: Silicon Errata Document for RAM9 (90-nm), 18-Mb
(CY7C138*D) Synchronous & NoBL™ SRAMs.
Document Number: 38-05543 Rev. *N
Orig. of
Change
Description of Change
NJY / PRIT Updated Features (Removed CY7C1382F related information, removed
165-ball FBGA package related information for CY7C1382D, removed 100-pin
TQFP package related information for CY7C1380F, removed 119-ball BGA
package related information).
Updated Functional Description (Removed the Note “For best practices or
recommendations, please refer to the Cypress application note AN1064,
SRAM System Design Guidelines on www.cypress.com.” and its reference,
removed the Note “CE3, CE2 are for 100-pin TQFP and 165-ball FBGA
packages only. 119-ball BGA is offered only in 1 chip enable.” and its
reference).
Updated Logic Block Diagram – CY7C1380D/CY7C1380F (Removed the Note
“CY7C1380F and CY7C1382F in 119-ball BGA package have only 1 chip
enable (CE1).” and its reference).
Updated Logic Block Diagram – CY7C1382D (Removed CY7C1382F related
information, removed the Note “CY7C1380F and CY7C1382F in 119-ball BGA
package have only 1 chip enable (CE1).” and its reference).
Updated Pin Configurations (Removed CY7C1382F related information,
removed 119-ball BGA package related information, removed 100-pin TQFP
package related information for CY7C1380F, removed 165-ball FBGA
package related information for CY7C1382D, removed the Note “CE3, CE2 are
for 100-pin TQFP and 165-ball FBGA packages only. 119-ball BGA is offered
only in 1 chip enable.” and its reference).
Updated Functional Overview (Removed CY7C1382F related information).
Updated Truth Table (Removed CY7C1382F related information).
Updated Truth Table for Read/Write (Removed CY7C1382F related
information).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Removed CY7C1380D,
CY7C1382D, and CY7C1382F related information).
Updated Identification Register Definitions (Removed CY7C1380D,
CY7C1382D, and CY7C1382F related information, removed 119-ball BGA
package related information).
Updated Scan Register Sizes (Removed 119-ball BGA package related
information).
Removed Boundary Scan Order (Corresponding to 119-ball BGA).
Updated Capacitance (Removed 119-ball BGA package related information).
Updated Thermal Resistance (Removed 119-ball BGA package related
information).
Updated Package Diagrams (Removed 119-ball BGA package related
information).
Page 36 of 37
CY7C1380D
CY7C1380F
CY7C1382D
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
Automotive
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Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
cypress.com/go/memory
cypress.com/go/image
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05543 Rev. *N
Revised April 23, 2013
Page 37 of 37
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may be the trademarks of their respective holders.