MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
DESCRIPTION
FEATURES
The M32000D4AFP is a new generation microcomputer with a 32-bit
CPU and built-in high capacity DRAM. Using this device it is possible
to implement the complex applications of the multimedia age with
high performance and low power consumption.
The M32000D4AFP contains 2M bytes of DRAM and 4K bytes of
cache memory. The CPU is implemented with a RISC architecture
and has a high performance figure of 52.4 MIPS (at an internal clock
rate of 66.6 MHz ). Memory for main storage is provided internally to
the device eliminating external memory and associated control circuits thus reducing overall system noise and power consumption.
The CPU, internal DRAM and cache memory are connected by a
128-bit, 15 ns/cycle internal bus which virtually eliminates transfer
bottlenecks in between the CPU and the memory. The M32000D4AFP
internally multiplies the frequency of the input clock signals by four.
For an internal operating frequency of 66.6 MHz the input clock frequency is 16.65MHz.
A 16-bit data and 24-bit address bus are the M32000D4AFP's external bus and the interface to external peripheral controllers. When the
hold state is set, the internal DRAM can be accessed from an external device.
A 3-chip basic system configuration using the M32000D4AFP is the
device itself plus an ASIC as a peripheral controller and a program
ROM. Execution starts from the reset vector entry on the external
ROM after power on, a program requiring high speed execution is
then transferred to internal DRAM and this is then executed. The
M32000D4AFP also has a slave mode additional to its master mode.
When set to slave mode the M32000D4AFP can be used as a
coprocessor. In this mode it does not access its external bus
immediatly after reset, but waits for the master to start its operation.
• CPU .......................................................... M32R family CPU core
• Pipeline .............................................................................. 5 steps
• Basic bus cycle ................................. 15 ns (at internal 66.6 MHz)
• Logical address space ............................................ 4G-byte linear
• External bus ........................................................ data bus: 16 bits
•
•
•
•
•
•
•
•
•
•
•
•
•
address bus: 24 bits
Internal DRAM ............................................... 16M bits (2M bytes)
Cache .......................................................... 4K bytes (direct map)
Register configuration ...... general-purpose registers: 32 bits x 16
control registers: 32 bits x 5
Instruction set ....................... 83 instructions/6 addressing modes
Instruction format .................................................... 16 bits/32 bits
Multiply-accumulate operation unit (DSP function instruction)
Internal memory controller
Programmable I/O ports
Power management function .................................. standby mode
/CPU sleep mode
PLL clock generating circuit ................. four-time clock PLL circuit
Operation mode .............................................. master/slave
mode
___
___
Interrupt input ............................................................ INT and SBI
Power source .......................................................... 3.3 V (±10 %)
APPLICATIONS
Portable equipment, Still camera, Navigation system,
Digital instrument, Printer, Scanner, FA equipment
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2
A21
A20
VCC
53
52
51
VSS
56
A23
A24
57
A22
A25
58
54
M/S
59
55
*1
RST
*1
62
60
*1
63
61
VSS
VCC
66
65
VCC
VSS
67
64
R/W
*1
68
VCC
70
69
BCL
73
SID
A26
BCH
74
72
VSS
75
71
A28
A27
A29
76
A30
78
77
VCC
80
79
PIN CONFIGURATION (TOP VIEW)
VSS
81
50
VSS
D15
82
49
D7
D14
83
48
D6
D13
84
47
D5
D12
85
46
D4
VCC
86
45
VCC
BURST
87
44
VCC
ST
88
43
VSS
VCC
89
42
VSS
VSS
90
41
VCC
VCC
91
40
VSS
92
39
HREQ
HACK
VCC
93
38
SBI
WKUP
VCC
94
37
INT
95
36
*1
D11
96
35
D3
D10
97
34
D2
D9
98
33
D1
D8
99
32
D0
VSS
100
31
VSS
M32000D4AFP
24
25
26
27
28
29
30
A12
VSS
A11
A10
A9
A8
VCC
21
PP0
23
20
PP1
22
19
*2
CS
18
CLKIN
A13
16
15
PLLVSS
17
14
PLLVCC
VSS
13
BS
PLLCAP
12
8
A14
11
7
A15
DC
6
VSS
STBY
5
A16
9
4
A17
10
3
A18
*1
2
A19
VCC
1
VCC
100-pin QFP/0.65 mm pitch
Note: Connect *1 pins to VCC.
Connect *2 pins to VSS.
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
BLOCK DIAGRAM
128
128
M32000D4AFP
instruction queue
(128 bits x 2 stages)
cache memory
(4K bytes)
32 bits
M32R CPU core
RST
instruction decoder
multiplyaccumulate
unit
register
32 bits
x
16
PC
ALU
load/
store
shift
32 x 16 bits
MUL
+
56-bit -ACC
DRAM
(2M bytes)
INT
SBI
WKUP
STBY
32 bits
128
programmable
I/O port
memory
controller
data selector
32 bits⇔128 bits
128
PLL clock
generating
circuit
external bus interface unit
128 bits⇔16 bits
PP1
CLKIN
PLLCAP
PLLVCC
PLLVSS
HACK
DC
HREQ
BURST
ST
R/W
BS
BCL
SID
BCH
D0 - D15
16
A8 - A30
23
PP0
CS
128
128-bit internal bus
M/S
3
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
FUNCTIONS
4
function block
characteristics
CPU core
• bus specification
basic bus cycle: 15 ns (internal operation at 66.6 MHz)
logical address space: linear 4G bytes
____ ____
external address bus: 24 bits (external output pin: A8 to A30, BCH, BCL)
external data bus: 16 bits
• implementation: 5-stage pipeline
• core internal: 32 bits
• register configuration
general-purpose registers: 32 bits ✕ 16
control registers: 32 bits ✕ 5
• instruction set
16-bit/32-bit instruction format
83 instructions/6 addressing modes
• multiply-accumulate operation built in
internal DRAM
• 16M bits (2M bytes)
cache memory
memory controller
•
•
•
•
programmable I/O port
• two programmable I/O ports
4K bytes (internal instruction/data cache mode, instruction cache mode, cache-off mode)
cache control
internal DRAM control, refresh control
power management function (standby mode, CPU sleep mode selection control)
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
PIN FUNCTION DIAGRAM
clock
CLKIN
SID
PLLCAP
BCL
PLLVCC
BCH
PLLVSS
BS
ST
R/W
RST
M32000D4AFP
system control
M/S
WKUP
STBY
address bus
A8 - A30
bus control
BURST
DC
HREQ
HACK
CS
23
INT
data bus
D0 - D15
SBI
16
PP0
PP1
16
interrupt input
programmable I/O port
15
VCC VSS
5
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION (1/3)
type
pin name
name
I/O
function
power
source
VCC
VSS
power source
ground
–
–
All power source pins should be connected to VCC.
All ground pins should be connected to VSS.
clock
CLKIN
clock input
input
PLLCAP
C connection
for PLL
power source
for PLL
ground
for PLL
reset
–
Clock input pin. The M32000D4AFP has an internal PLL multiplier
circuit, and an input clock which is 1/4 of the internal operating
frequency (when the internal operating frequency is 66.6 MHz,
the CLKIN input is 16.65 MHz).
Connects a capacitor for the internal PLL.
–
Power source for the internal PLL.
–
Ground for the internal PLL.
input
master/slave
input
Internally resets the M32000D4AFP. It is also used to return
from standby mode and CPU sleep mode.
Sets the M32000D4AFP default operation to either system bus
master (M/S = "H") or bus slave (M/S = "L").
When the M32000D4AFP is set to bus slave, it does not carry
out a reset vector_ entry fetch after a reset.
The setting of M/S cannot be changed during operation.
Keep at either an "H" or an "L" level.
wakeup
input
Input pin to request return from
standby mode.
_____
This is only accepted when STBY is "L" level.
It generates the wakeup interrupt.
STBY
standby
output
address
bus
A8 to A30
address bus
I/O
(Hi-z)*
data bus
D0 to D15
data bus
I/O
(Hi-z)*
Indicates that the M32000D4AFP has switched to standby
mode. An "L" level is output while the device is in standby
mode.
The M32000D4AFP has a 24-bit address (A8 to A31) bus for
a 16 MB address space. A31 is not output. During the write
cycle,
the valid
____
____byte positions on the 16-bit data bus are output
as BCH or BCL. During the read cycle, the 16-bit data bus is
read, however,only data in the valid byte positions is transferred
to the M32000D4AFP.
Address bus pins are bidirectional. When accessing the internal
DRAM from an external bus master while the M32000D4AFP is
in the hold state, input the address from the system bus side.
16-bit data bus for connecting to external devices.
PLLVCC
PLLVSS
____
system
control
RST
_
M/S
______
WKUP
_____
* (Hi-z): This pin goes to high-impedance in the hold state.
6
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION (2/3)
type
pin name
name
I/O
function
bus
control
SID
space
identifier
output
(Hi-z)*
byte control
I/O
(Hi-z)*
BS
bus start
output
(Hi-z)*
ST
bus status
output
(Hi-z)*
read/write
I/O
(Hi-z)*
burst
output
(Hi-z)*
Space identifier between user space and I/O space.
SID = "L": user space
SID = "H": I/O space
SID = undefined: when idle
Indicates
the valid byte positions of transferred____
data.
____
BCH corresponds to the MSB side (D0 to D7), and BCL corresponds
____
to the
LSB side (D8 to D15). During a read bus cycle, both BCH
____
and BCL are an "L" level.
____
____
During a write bus cycle, either BCH and/or BCL is an "L" level
depending on the byte(s) to be written.
When accessing the internal DRAM from an external bus master,
the byte control signal is input from the system bus side.
__
When the M32000D4AFP drives an external bus cycle, BS goes
to an "L" level at __
the start of the bus cycle.
In burst transfer, BS goes to the "L" level for each transfer
cycle. When accessing internal__resources such as an internal
DRAM or internal I/O register, BS is not output.
Indicates whether the bus cycle that the M32000D4AFP drives is
an instruction fetch access cycle or an operand access cycle.
ST = "L": for instruction fetch access
ST = "H": for operand access
ST __
= undefined: when idle
Outputs R/W to identify whether the external bus cycle a read or
a write cycle. When
accessing the internal DRAM from an external
__
bus master, R/W is input from the external bus.
The M32000D4AFP drives two consecutive bus cycles to access
32-bit data allocated on the 32-bit word boundary.
For instruction fetches, it drives 8 (max.) consecutive cycles
(8 cycles in instruction cache mode) to data
on the 128-bit boundary.
______
During these consecutive bus cycles, BURST goes to "L" level.
When accessing 32-bit data, an "L" level followed by an "H" level
is output from address A30, because the MSB-side 16 bits are
accessed prior to the LSB-side 16 bits.
When accessing 128-bit data, the addresses are output from an
arbitrary 16-bit aligned address and wraparound within a 128-bit
aligned boundary.
____
____
BCH, BCL
__
__
R/W
______
BURST
* (Hi-z): This pin goes to high-impedance in the hold state.
7
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION (3/3)
type
pin name
bus
control
(cont.)
DC*
name
I/O
function
data complete
I/O
(Hi-z)
hold
input
hold
acknowledge
chip
select
output
system
break
interrupt
external
interrupt
input
When the M32000D4AFP drives an __
external bus cycle, it
automatically inserts wait cycles until DC is input by the slave
device in the system bus.
When the M32000D4AFP is in the hold state and the internal
DRAM is __
accessed from an external bus master, the M32000D4AFP
outputs DC to notify to the external bus master that the bus
cycle to the internal DRAM has been completed. ______
Bus right request input pin of the system bus. When HREQ is an
"L" level, the M32000D4AFP switches to the hold state.
Indicates that the M32000D4AFP has switched to the hold state
and releases the bus right of the system bus to the requestor.
Signal input to the M32000D4AFP when it is in the hold state to
request access to the internal DRAM
from an external bus master.
__
When an "L"level is input to CS, the M32000D4AFP access
accesses the internal DRAMat the address input via the address
pins.
System break interrupt input pin. The SBI is not masked by the
IE bit in the PSW register. It is also used to return from CPU
sleep mode and to request the start of operation in slave mode.
External interrupt request input pin. It is also used to return from
CPU sleep mode and to request the start of operation the slave
mode.
Two programmable I/O ports.
__
______
HREQ
_____
HACK
__
CS
input
___
interrupt
controller
SBI
___
INT
programmable I/O port
__
PP0, PP1
input
port
I/O
__
* The DC pin becomes an output pin when the CS signal is input to the M32000D4AFP.
8
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
CPU
Control registers
The M32R CPU has 16 general-purpose registers, 5 control registers, an accumulator and a program counter. The accumulator is of
64-bit width. The registers and program counter are of 32-bit width.
There are 5 control registers which are the processor status word
register (PSW), the condition bit register (CBR), the interrupt stack
pointer (SPI), the user stack pointer (SPU) and the backup PC (BPC).
The MVTC and MVFC instructions are used for writing and reading
these control registers.
General-purpose registers
The 16 general-purpose registers (R0 - R15) are of 32-bit width and
are used to retain data and base addresses. R14 is used as the link
register and R15 as the stack pointer (SPI or SPU). The link register
is used to store the return address when executing a subroutine call
instruction. The interrupt stack pointer (SPI) and the user stack pointer
(SPU) are alternatively represented by R15 depending on the value
of the stack mode bit (SM) in the processor status word register (PSW).
0
31
0
31
R0
R8
R1
R9
R2
R10
R3
R11
R4
R12
R5
R13
R6
R14 (link register)
R7
R15 (stack pointer) (see note)
(see notes)
CRn
CR0
0
31
PSW
processor status word register
CBR
condition bit register
CR2
SPI
interrupt stack pointer
CR3
SPU
user stack pointer
CR6
BPC
backup PC
CR1
Notes 1: CRn (n = 0 - 3, 6) denotes the control register number.
2: The MVTC and MVFC instructions are used for writing
and reading these control registers.
Fig. 2 Control registers
Note: The interrupt stack pointer (SPI) and the user stack pointer (SPU) are
alternatively represented by R15 depending on the value of the stack
mode bit (SM) in the PSW.
Fig. 1 General-purpose registers
9
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Processor status word register: PSW (CR0)
The PSW field is made up of the stack mode bit (SM), the interrupt
enable bit (IE) and the condition bit (C). The BPSW field is made up
of the backup stack mode bit (BSM), the backup interrupt enable bit
(BIE) and the backup condition bit (BC).
The processor status word register (PSW) shows the M32R CPU
status. It consists of the current PSW field, and the BPSW field where
a copy of the PSW field is saved when EIT occurs.
BPSW field
0
PSW
7
8
15 16 17
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BSM
23 24 25
0 0 0 0 0
BIE
BC
31
0 0 0 0 0
SM
IE
C
D
bit name
function
16
BSM (backup SM)
saves value of SM bit when EIT occurs
undefined
17
BIE (backup IE)
saves value of IE bit when EIT occurs
undefined
23
BC (backup C)
saves value of C bit when EIT occurs
undefined
24
SM (stack mode)
0: uses R15 as the interrupt stack pointer
1: uses R15 as the user stack pointer
0
25
IE (interrupt enable)
0: does not accept interrupt
1: accepts interrupt
0
31
C (condition bit)
indicates carry, borrow and overflow resulting
from operations (instruction dependent)
0
Note: "init." ...initial state immediately after reset
"R" .... : read enabled
"W" .... : write enabled
Fig. 3 Processor status word register
10
PSW field
init.
R
W
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Condition bit register
Backup PC
The condition bit register (CBR) is a separate read-only register which
contains a copy of the current value of the condition bit (C) in the
PSW. An attempt to write to the CBR with the MVTC instruction is
ignored.
The backup PC (BPC) is the register where a copy of the PC value is
saved when EIT occurs. Bit 31 is fixed at "0". When EIT occurs, the
PC value immediately before EIT occurrence or that of the next instruction is set. The value of the BPC is reloaded to the PC when the
RTE instruction is executed. However, the values of the lower 2 bits
of the PC become "00" on returning (It always returns to the word
boundary).
Interrupt stack pointer, User stack pointer
The interrupt stack pointer (SPI) and the user stack pointer (SPU)
retain the current stack address. The SPI and SPU can be accessed
as the general-purpose register R15. R15 switches between representing the SPI and SPU depending on the value of the stack mode
bit (SM) in the PSW.
0
CBR
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C
0
SPI
31
SPI
0
SPU
31
SPU
0
BPC
31
BPC
0
Fig. 4 Condition bit register, interrupt stack pointer, user stack pointer and backup PC
11
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Accumulator
Program counter
The accumulator (ACC) is a 64-bit register used for DSP type functions. Use the MVTACHI and MVTACLO instructions for writing to
the accumulator. The high-order 32 bits (bit 0 - bit 31) can be set with
the MVTACHI instruction and the low-order 32 bits (bit 32 - bit 63)
can be set with the MVTACLO instruction. Use the MVFACHI,
MVFACLO and MVFACMI instructions for reading from the accumulator. The high-order 32 bits (bit 0 - bit 31) are read with the MVFACHI
instruction, the low order 32 bits (bit 32 - bit 63) with the MVFACLO
instruction and the middle 32 bits (bit 16 - bit 47) with the MVFACMI
instruction.
The program counter (PC) is a 32-bit counter that retains the address of the instruction being executed. Since the M32R CPU instruction starts with even-numbered addresses, the LSB (bit 31) is
always "0".
read range with MVFACMI instruction
(see note)
0
78
15
16
31
32
47
48
63
ACC
read/write range with
MVTACHI or MVFACHI instruction
read/write range with
MVTACLO or MVFACLO instruction
Note: Bits 0 - 7 are always read as the sign-extended value of bit 8.
An attempt to write to this area is ignored.
Fig. 5 Accumulator
0
PC
Fig. 6 Program counter
12
31
PC
0
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Data types
Data formats
Signed and unsigned integers of byte (8 bits), halfword (16 bits), and
word (32 bits) types are supported as data in the M32R CPU instruction set. A signed integer is represented in a 2's complement format.
Data size of a register of the M32R CPU is always a word (32 bits).
Byte (8 bits) and halfword (16 bits) data in memory are sign-extended
(the LDB and LDH instructions) or zero-extended (the LDUB and
LDUH instructions) to 32 bits, and loaded into the register.
Word (32 bits) data in a register is stored to memory by the ST instruction. Halfword (16 bits) data in the LSB side of a register is stored
to memory by the STH instruction. Byte (8 bits) data in the LSB side
of a register is stored to memory by the STB instruction.
Data stored in memory can be one of these types: byte (8 bits),
halfword (16 bits) or word (32 bits).
Although the byte data can be located at any address, the halfword
data and the word data can only be located on the halfword boundary and the word boundary, respectively. If an attempt is made to
access data in memory which is not located on the correct boundary,
an address exception occurs.
7
0
signed byte
(8-bit) integer
S
7
0
unsigned byte
(8-bit) integer
15
0
signed halfword
(16-bit) integer
S
15
0
unsigned halfword
(16-bit) integer
31
0
signed word
(32-bit) integer
S
31
0
unsigned word
(32-bit) integer
S: sign bit
Fig. 7 Data type
<data format in a register>
< load >
0
<data format in memory>
address
from memory
(LDB, LDUB instruction)
sign-extention (LDB instruction) or
zero-extention (LDUB instruction)
+0
+2
+3
31
24
0
byte
Rn
+1
7 8
15 16
23 24
31
byte
sign-extention (LDH instruction) or
zero-extention (LDUH instruction)
0
from memory (LDH, LDUH instruction)
16
31
byte
byte
byte
halfword
Rn
byte
from memory (LD instruction)
0
31
halfword
word
Rn
halfword
halfword
< store >
word
0
24
word
31
byte
Rn
to memory (STB instruction)
0
16
31
halfword
Rn
to memory (STH instruction)
0
Rn
31
word
to memory (ST instruction)
Fig. 8 Data format
13
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Address space
The M32000D4AFP logical address is 32-bit wide and offers 4 GB
linear space. The M32000D4AFP has address spaces allocated as
shown below.
The user space is specified by SID = 0 (H'0000 0000 to H'7FFF FFFF).
The area available to the user is 16 MB from address H'0000 0000
to address H'00FF FFFF.
The I/O space is specified by SID = 1 (H'8000 0000 to H'FFFF FFFF).
The area available to the user is 16 MB from address H’FF00 0000
to address H'FFFF FFFF. The I/O space cannot be cached.
These areas below are allocated in each space.
• User space
internal DRAM area
external area
• I/O space
user I/O area
system area
internal I/O area
< logical space >
< physical space >
EIT vector entry
(except for reset interrupt)
SID
logical address
physical address
(24 bits)
logical address
H'0000 0000
H'0000 0000
0 : H'00 0000
internal DRAM
area (2M bytes)
(16M bytes)
H'001F FFFF
H'0020 0000
0 : H'1F FFFF
0 : H'20 0000
external area
(14M bytes)
user space
(SID = 0)
H'00FF FFFF
0 : H'FF FFFF
EIT vector entry
(reset interrupt)
H'7FFF FFFF
H'8000 0000
SID
physical address
(24 bits)
logical address
H'FF00 0000
1 : H'00 0000
user I/O area
(8M bytes)
I/O space
(SID = 1)
H'FF7F FFFF
H'FF80 0000
H'FFBF FFFF
H'FFC0 0000
(16M bytes)
H'FFFF FFFF
Fig. 9 Address space
14
H'FFFF FFFF
system area
(4M bytes)
internal I/O area
(4M bytes)
1 : H'7F FFFF
1 : H'80 0000
1 : H'BF FFFF
1 : H'C0 0000
1 : H'FF FFFF
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
The internal DRAM (2 MB) is allocated from address H'0000 0000 to
address H'001F FFFF. The EIT vector entry (other than the reset
interrupt) is allocated in the address H'0000 0000 to address H'0000
008F of this area.
The internal DRAM is connected to the M32R CPU via a 4 KB cache
memory with a 128-bit bus. When the M32000D4AFP is in the hold
state, the internal DRAM can be accessed from an external bus master
by inputting control signals.
The external area consists of 14 MB from address H'0020 0000 to
address H'00FF FFFF. When this space is accessed, the control signals to access external devices are output. The bottom 16 bytes in
this area (H'00FF FFF0 to H'00FF FFFF) are the reset interrupt EIT
vector entry.
+0 address
logical address
+1 address
The user I/O area is 8 MB from address H'FF00 0000 to address
H'FF7F FFFF. When this space is accessed, the control signals to
access external devices are output. The system area is 4 MB from
address H'FF80 0000 to address H'FFBF FFFF. This area is reserved
for development tools such as in-circuit emulators or debug monitors. The user cannot use this area.
The internal I/O area is 4 MB from address H'FFC0 0000 to address
H'FFFF FFFF. The memory controller and programmable I/O port
registers are allocated in this area.
+2 address
+3 address
0
31
H'FFC0 0000
(reserved)
H'FFFF FFE0
PPCR0
H'FFFF FFE4
PPCR1
H'FFFF FFE8
PPDR0
H'FFFF FFEC
PPDR1
programmable I/O port
(reserved)
H'FFFF FFF4
MLCR
H'FFFF FFF8
MPMR
H'FFFF FFFC
MCCR
memory controller
PPCR0: programmable I/O port direction control register 0
MLCR: lock control register
PPCR1: programmable I/O port direction control register 1
MPMR: power management control register
PPDR0: programmable port data register 0
MCCR: cache control register
PPDR1: programmable port data register 1
Fig. 10 Internal I/O space memory map
15
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
EIT
While the CPU is executing a program, sometimes it is necessary to
suspend execution, because a certain event occurs, and execute
another program. These kinds of events are referred to as EIT (Exception, Interrupt, Trap).
• Exception
The event is related to the context being executed. It is generated by
errors or violations that occur during instruction execution. With the
M32000D4AFP, the address exception (AE) and reserved instruction exception (RIE) are of this type.
• Interrupt
The event is not related to the context being executed. It is generated by an external hardware signal. With the M32000D4AFP, the
external interrupt (EI), system break interrupt (SBI), wakeup interrupt (WI) and reset interrupt (RI) are of this type.
• Trap
This is a software interrupt which is generated by executing the TRAP
instruction. It is intentionally added to the program by the programmer, as a system call.
EIT
Exception
Reserved Instruction
Exception (RIE)
Address Exception (AE)
Interrupt
Reset Interrupt (RI)
Wakeup Interrupt (WI)
System Break Interrupt (SBI)
External Interrupt (EI)
Trap
Fig. 11 EIT events
16
Trap (TRAP)
EIT events are shown below.
• Reserved instruction exception (RIE)
The reserved instruction exception (RIE) occurs when execution of a
reserved instruction (unimplemented instruction) is detected.
• Address exception (AE)
The address exception (AE) occurs if an attempt is made to access
an unaligned address with either a load instruction or a store instruction.
• Reset interrupt (RI)
___
The reset interrupt (RI) is always accepted when the RST signal is
input. It has the highest priority.
• Wakeup interrupt (WI)
______
The wakeup interrupt (WI) is accepted when the WKUP signal is
input while the M32000D4AFP is in standby mode. It is only used to
return from standby mode.
• System break interrupt (SBI)
___
The system break interrupt (SBI) is an interrupt request from the SBI
pin. It is used when a break in power source or an error from an
external watchdog timer is detected. It is also used to return from
CPU sleep mode and to start an M32000D4AFP set to slave mode.
• External interrupt (EI)
___
The external interrupt (EI) is an interrupt request from the INT pin. It
is used by an interrupt from the external peripheral I/O and can be
masked by the IE bit in the PSW register. It is also used to return
from CPU sleep mode and to start an M32000D4AFP set to slave
mode.
• Trap
The trap (TRAP) is a software interrupt which is generated by executing the TRAP instruction. A total of 16 EIT vector entries are
available for operands 0 to 15 of the TRAP instruction.
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Internal memory system
The memory system built into the M32000D4AFP has the following
characteristics.
• internal 16M-bit (2M-byte) DRAM
• internal 4K-byte cache memory
• CPU, cache and internal DRAM are connected by a 128-bit bus
• selectable cache memory operation mode
– internal instruction/data cache mode
– instruction cache mode
– cache-off mode
cache control register (MCCR) < address: H'FFFF FFFF>
D24
D25
D26
D27
D28
D29
CP
D
24
25 - 29
30, 31
bit name
CP
(cache purge)
Not assigned.
CM0, CM1
(cache mode)
function
0: no purge
1: purge
D30
D31
CM0
CM1
<at reset: H'01>
R W
0
0
00: cache mode
is not changed
01: cache-off mode
10: internal
instruction/data
cache mode
11: instruction cache
mode
R = 0 ... "0" when reading
W = ... write enabled
Fig. 12 Cache control register
When the internal instruction/data cache mode is selected, the cache
memory functions as a cache for both instruction and data from the
internal DRAM, and caches all bus access to the DRAM. This mode
is for a system which uses the internal DRAM as main memory. Transfer between the M32R CPU, cache memory and internal DRAM is
always carried out in blocks of 128 bits. Caching is carried out by the
direct map method. Writing is by the copy back method.
When the M32000D4AFP access destination is an external space,
data transfer between the M32R CPU and the external device is carried out via the bus interface unit (BIU). The BIU has a 128-bit data
buffer which converts the bus width between the 128-bit bus in the
M32000D4AFP and the external bus. Caching is not applicable in
this case of data transfer.
When accessing the internal DRAM from an external bus master,
and a cache hit occurs (the accessed data is inside the cache), data
transfer between the cache memory and the external bus via the BIU
is carried out. When a cache miss occurs, (the accessed data is not
inside the cache) data transfer is carried out between the internal
DRAM and the external bus via the BIU without cache replacement.
✕
M32000D4AFP
DRAM
128
instruction/
data cache
R = ... read enabled
W = ✕ : write disabled
128
CPU
external bus
interface
128
16
BIU
external bus
(16 bits)
Fig. 13 Internal instruction/data cache mode
17
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
When the instruction cache mode is selected, the cache functions as
an instruction cache for the internal DRAM or the external memory,
and caching is carried out for instruction fetch access. This mode is
designed for use when an external ROM is used as program memory
and the internal DRAM is used as data memory, or when instructions
are located in the internal DRAM. Caching is carried out by the direct
map method. When instruction codes in the user space are overwritten by the external bus master or another source, instruction code
coherency in the cache memory is not guaranteed. Furthermore,
caching is not applied when accessing the internal DRAM from the
external bus master.
When the cache-off mode is selected, the M32000D4AFP internal
memory system is configured as follows. In this mode, caching is not
applied, and all bus cycles are directly to the internal DRAM or external bus.
M32000D4AFP
DRAM
external bus
interface
M32000D4AFP
128
DRAM
CPU
external bus
interface
128
CPU
128
instruction
cache
16
BIU
external bus
(16 bits)
Fig. 15 Cache-off mode
Fig. 14 Instruction cache mode
18
128
16
BIU
external bus
(16 bits)
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Bus interface unit (BIU)
The M32000D4AFP has the following signals related to the external
bus.
• Address (A8 to A30)
The M32000D4AFP has a 24-bit address bus (A8 to A31) corresponding to a 16 MB address space. Of these, A31 (the LSB) is not output
externally. In write cycles, the validity
of the ___
two bytes output on the
___
16-bit data bus is indicated by BCH and/or BCL. In read cycles, the
16-bit data bus is always read, however, only data in the valid byte
position in the M32000D4AFP is transferred. The address pins are
bidirectional. If the M32000D4AFP is in the hold state and the internal DRAM is accessed from an external bus master, the address
signal is input from the system bus side.
• Space identifier (SID)
The space identifier is used to specify user space and I/O space.
user space: SID = "L"
I/O space: SID = "H"
hold: SID = high-impedance
idle: SID
= undefined
___ ___
• Byte control (BCH, BCL)
Byte control signals indicate the___
byte position of valid data transferred of the external
bus
cycle.
BCH
corresponds to the MSB side
________
(D0 to D7), and BCL corresponds
to
the
LSB side (D8 to D15). Dur___
___
ing the bus read cycle,
both
BCH
and
BCL
are an "L" level. During
___
___
the bus write cycle, BCH and/or BCL go to an "L" level depending on
the bytes to be written. If the M32000D4AFP is in the hold state and
the internal DRAM is accessed from an external bus master, the byte
control signal is input from the system bus side.
• Data bus (D0 to D15)
The M32000D4AFP has a 16-bit data bus to access external devices. If the M32000D4AFP is in the hold state and the internal DRAM
is accessed from an external bus master, the data bus is used as a
data I/O bus__
from the system bus side.
• Bus start (BS)
When the M32000D4AFP
drives the bus cycle to the system bus, an
__
"L" level is output
to BS at the start of the bus cycle. Also, for __
a burst
__
transfer, the BS signal is output for each transfer cycle. The BS signal is not output when accessing internal resources such as the internal DRAM or internal I/O registers.
• Bus status (ST)
The ST signal identifies whether the bus cycle the M32000D4AFP is
driving is an instruction fetch cycle or an operand access cycle.
instruction fetch access: ST = "L"
operand access: ST = "H"
hold: ST = high-impedance
idle: ST__
= undefined
• Read/write (R/W)
__
The M32000D4AFP outputs a R/W signal to identify whether the external bus cycle is a read or write operation. When
accessing the
__
internal DRAM from an external bus master, a R/W signal is input
from the system bus side. __
read bus cycle: R/W
= "H"
__
write
bus cycle: R/W = "L"
______
• Burst (BURST)
The M32000D4AFP drives two consecutive bus cycles to access 32bit data located on the 32-bit boundary. In instruction fetching, it drives
a maximum of 8 (fixed to 8 cycles in instruction cache mode) consecutive read cycles to access data located on the 128-bit boundary.
While driving these
consecutive bus cycles, the M32000D4AFP out______
puts "L" level to BURST. When accessing 32-bit data, the address of
the MSB-side 16 bits are output before the address of the LSB side
16 bits. When accessing 128-bit data, the addresses are output for
every access cycle from the arbitrary 16-bit aligned addresses to
wraparound within__
the 128-bit boundary.
• Data complete (DC)
When starting an external bus cycle,
the M32000D4AFP automati__
cally inserts wait cycles
until
the
DC
signal is input from external.
__
Wait control using the DC signal is effective also for bus cycles during burst
transfer. When the M32000D4AFP is in the hold__
state and if
__
the CS signal is input, the M32000D4AFP outputs the DC signal to
notify the external bus master that internal DRAM access is complete.
_____ _____
• Hold control (HREQ, HACK)
The hold state is the state when the external bus access stops and
all pins go to a high-impedance state. However, the internal DRAM
can be accessed while the external bus is in the hold state._____
To put
the M32000D4AFP into the hold state, input an "L" level to HREQ.
When the hold request is accepted and the
M32000D4AFP enters
_____
the hold state, an "L" level is output from HACK.
19
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
__
• Internal DRAM access control (CS)
__
The internal DRAM can be accessed when CS is driven
to an "L"
____
level after the M32000D4AFP enters the hold state (HACK = "L").
To access the internal DRAM from external, the following signals
from the system bus side should be controlled.
• A8 to A30
Input
internal DRAM addresses to be read or written.
___ ___
• BCH, BCL
Specify the byte position of data to be written into the internal
___
___
DRAM. BCH corresponds to the MSB side (D0 to D7), and BCL
corresponds to the LSB side (D8 to D15).
Read and write operations of the M32000D4AFP
are carried_____
out us___ _______ _______
ing the address bus, data bus,
and
the
R/W,
BCH,
BCL
and
DC
sig___
nals.
When
reading,
the
R/W
signal
goes
to
an
"H"
level,
and
the
_______
_______
BCH and BCL signals go to an "L" level. The CPU reads the data in
the
valid_______
byte positions.
When writing, an "L" level is output from R/
___
_______
W, and BCH and BCL are output according to the valid byte positions, so as to specify the byte positions for writing into an external
device.
idle
__
• R/W
___
Specify read
or write operation. When reading, R/W = "H". When
__
writing, R/W = "L".
• D0 to D15
16-bit
data I/O bus.
_____
• DC
This signal notifies to an external bus master that the internal
DRAM access is_____
complete. When access is complete, an "L"
level is output to DC.
read
read
idle
CLKIN
BS
A8 - A30
SID, ST
R/W
"H"
BCH, BCL
Table 1 Pin condition in hold state
pin name
pin condition or operation
A8 - A30,
____SID,
BCH, BCL
__ ___ ______
ST, R/W, BS, BURST
D0 - D15
high-impedance
____
__
DC
_____
HACK
other pins
BURST
D0 - D15
"H"
"Hi-z"
"Hi-z"
DC
output when internal DRAM__
is read
by__
an external bus master (CS = "L",
R/W = "H"), otherwise high-impedance
output when internal DRAM is
accessed
by an external bus master
__
(CS = "L"), otherwise high-impedance
output "L"
normal operation
idle
write
write
idle
CLKIN
BS
A8 - A30
SID, ST
R/W
BCH, BCL
BURST
D0 - D15
"H"
"Hi-z"
"Hi-z"
DC
Note: "Hi-z" means high-impedance, and
indicates sampling timing.
Fig. 16 Read/write timing (two no-wait accesses)
20
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
__
When an "L" level is input to DC, the next bus cycle is processed and
wait cycles are inserted until this point. When a write cycle comes
immediately after a read cycle, the M32000D4AFP inserts an idle
cycle to prevent a collision with data on the system bus. The same
applies to write cycles (burst write access) immediately after a burst
read cycle.
idle
read
idle
write
idle
CLKIN
BS
A8 - A30
idle
read
read
idle
SID, ST
R/W
CLKIN
BCH, BCL
BS
A8 - A30
BURST
"H"
SID, ST
R/W
D0 - D15
"H"
BCH, BCL
BURST
D0 - D15
"Hi-z"
"Hi-z"
"Hi-z"
DC
"H"
"Hi-z"
"Hi-z"
Note: "Hi-z" means high-impedance, and
"Hi-z"
indicates sampling timing.
DC
Fig. 18 Automatic idle cycle insertion between consecutive read
and write cycles
idle
write
write
idle
CLKIN
BS
A8 - A30
SID, ST
R/W
BCH, BCL
BURST
D0 - D15
"H"
"Hi-z"
"Hi-z"
DC
Note: "Hi-z" means high-impedance, and
indicates sampling timing.
Keep DC signal at the "H" level when waits are inserted.
Fig. 17 Read/write timing (two one-wait accesses)
21
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
______
The M32000D4AFP outputs the BURST signal and carries out a burst
transfer when reading "the word-size data aligned on the 32-bit boundary" or "a maximum 4 words of instructions aligned on the 128-bit
______
boundary". The BURST signal is synchronized with the CLKIN falling
edge of the first bus access cycle and output "L" level. It returns to an
"H" level synchronized with the first CLKIN falling edge of the last
bus access cycle. Addresses A8 to A30 are output for each cycle.
When burst reading 32-bit data, the MSB-side 16-bit read bus cycle
is carried out first followed by the LSB-side 16-bit read bus cycle.
When the cache memory operation mode is the instruction cache
mode, and burst reading of the instructions within the 128-bit boundary for cache replacement occurs, the bus cycle is driven a fixed 8
times from an arbitrary 32-bit boundary address and to wraparound
within the 128-bit boundary. When other than the instruction cache
mode is selected and burst reading a set of instructions of less than
128 bits, consecutive bus cycles are driven from an arbitrary 32-bit
boundary address as the top to the 128-bit line (A28 to A30 = "111").
idle
burst read (1 word)
idle
CLKIN
BS
A8 - A30
SID, ST
R/W
"H"
BCH, BCL
BURST
D0 - D15
"Hi-z"
"Hi-z"
DC
Note: "Hi-z" means high-impedance, and
indicates sampling timing.
Wait cycles can be inserted even when burst transferring by setting
DC = "H".
Fig. 19 1-word (32-bit) burst read timing (1-0 wait)
idle
burst read ( 4 words)
CLKIN
BS
A8 - A30
SID, ST
R/W
"H"
BCH, BCL
BURST
D0 - D15
"Hi-z"
DC
Note: "Hi-z" means high-impedance, and
indicates sampling timing.
Wait cycles can be inserted even when burst transferring by setting DC = "H".
Fig. 20 4-word (128-bit) burst read timing (1-0-0-0-0-0-0-0 wait)
22
idle
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
_____
When writing word-size data aligned on the 32-bit boundary,
the
______
M32000D4AFP carries out a burst-transfer by outputting the BURST
signal. When burst-writing 32-bit data, the MSB-side 16-bit write bus
cycle______
is driven first, followed by the LSB-side 16-bit write bus cycle.
The BURST signal is synchronized with the CLKIN falling edge of
the first bus access cycle, and "L" level is output. It returns to "H"
level in synchronization with the CLKIN falling edge of the last bus
access cycle. Addresses A8 to A30 are output for each cycle.
When an "L" level is input to HREQ, the M32000D4AFP
switches to
_____
the hold state and outputs an "L" level to HACK. While the
M32000D4AFP is in the hold state, bus related pins go to a high
impedance state, and data transfer is carried out on the system
bus.
_____
To return to normal operation mode from the hold state, the HREQ
signal should be changed to an "H" level.
(see note 1)
write
idle
burst write (1 word)
idle
idle
(see note 1)
hold shift
hold
return
idle
CLKIN
(see note 2)
HREQ
CLKIN
HACK
BS
(see note 2)
BS
"Hi-z"
A8 - A30
SID,ST
A8 - A30
SID, ST
R/W
R/W
BCH, BCL
BCH, BCL
"Hi-z"
"Hi-z"
"Hi-z"
BURST
"Hi-z"
BURST
D0 - D15
"Hi-z"
"Hi-z"
D0 - D15
"Hi-z"
(see note 3)
DC
"Hi-z"
DC
Note: "Hi-z" means high-impedance, and
indicates sampling timing.
Wait cycles can be inserted even when burst transferring by
setting DC = "H".
Fig. 21 1-word (32-bit) burst write timing (1-0 wait)
Notes 1: Before switching to the hold state, an idle cycle of 1 CLKIN clock period is always
inserted.
After returning from the hold state, an idle cycle of 1 to 5 CLKIN clock periods is
always inserted.
2: "Hi-z" means high impedance, and
indicates sampling timing.
3: While the M32000D4AFP is in the hold state, the DC signal is driven and output
when the CS signal is input.
Fig. 22 Bus arbitration timing
23
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
When the M32000D4AFP is in the hold state and an "L" level is input
__
to CS, the M32000D4AFP interprets it as a bus access request to
__
the internal DRAM. In this case, when the R/W signal is an "H" level,
the memory controller drives a read cycle to the internal DRAM. In
the read cycle, the 16-bit data for the address specified with A8 to
____
___
A30, is output from D0 to D15 regardless of the BCH and BCL set__
tings. Also the DC signal is output.
The M32000D4AFP reads 128 bits of data from the block on the
128-bit boundary including the requested address into the 128-bit
buffer of the bus interface unit. 3 to 7 CLKIN clock periods are necessary for the first bus access, however, when reading consecutive
address within the 128-bit boundary, the subsequent read bus cycles
are completed in 1 CLKIN clock period because a read from the internal DRAM does not take place.
Once the external bus master read cycle has been driven, it cannot
__
be aborted. When an "L" level is input to CS and an access has
started, the values of this and other control signals should be held
__
__
during the wait cycles (that is while DC = "H"). After DC outputs an
__
"L" level (access complete), return CS to the "H" level between the
CLKIN falling edge corresponding to the last read cycle and the fol______
lowing CLKIN falling edge. Return HREQ to the "H" level to return
the M32000D4AFP to the normal operation mode from the hold state
__
either at the same time as or after CS is returned to the "H" level.
hold shift
return
hold
read
read
read
HREQ
HACK
CS
A8 - A30
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
R/W
BCH, BCL
"Hi-z"
D0 - D15
"Hi-z"
"Hi-z"
"Hi-z"
DC
("L" output)
✽
Note: "Hi-z" means high impedance, and
indicates sampling timing.
The value of the R/W signal that controls the data direction of the bus interface
cannot be changed during CS="L". Hold this value while CS="L".
Also, where marked above with ✽, 3 to 7 CLKIN clock periods are necessary for
the first read operation (also when reading crosses an 128-bit boundary) when
reading from the internal DRAM. Hold the input value of the address or other control
signals during these wait cycle periods (DC = "H"). Consecutive read operations
within an 128-bit boundary are completed in 1 CLKIN clock period.
During these wait cycle period, CS cannot be returned to an "H" level (the access
cannot be aborted). CS can only be returned to an "H" level after DC is driven to "L".
Fig. 23 Read bus cycle to internal DRAM
24
read
CLKIN
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
When
the M32000D4AFP is in the hold state and an "L" level is input
__
to CS, the M32000D4AFP interprets it as a bus
access request to
__
the internal DRAM. In this case, when the R/W signal is at an "L"
level, the memory controller drives a write cycle to the internal DRAM.
____
___
Byte data control is specified by the BCH and BCL signals.
Only
data
____
___
in the byte positions for which an "L" level is input__
to BCH or BCL are
written. When writing is complete, an "L" level DC signal is output.
The M32000D4AFP stores the requested data in the 128-bit data
buffer of the BIU, before writing to the internal DRAM. This reduces
the number of accesses to the internal DRAM when a request to
writing to consecutive addresses is made, and improves bus cycle
throughput. Consecutive write cycles within an 128-bit boundary are
completed in 1 CLKIN clock period. 3 to 7 CLKIN clock periods are
necessary for a write access crossing an 128-bit boundary when
writing to the internal DRAM. Once the external bus master write
cycle has been driven, it cannot be aborted. When an "L" level is
__
input to CS and an access has started, the values of this and other
__
control signals
should be held during the wait cycles (that is while
DC
__
__
= "H"). After DC outputs an "L" level (access complete), return CS to
the "H" level between the CLKIN falling edge corresponding to the
______
last write cycle and the following CLKIN falling edge. Return HREQ
to the "H" level to return the M32000D4AFP to the normal operation
__
mode from the hold state either at the same time as or after CS is
returned to the "H" level.
When
the external bus master makes an access, the value of the
__
R/W signal that controls
the data direction of the bus interface can__
not be changed during CS="L".
Therefore, read cycles and write cycles
__
cannot be mixed while CS = "L". When starting a write cycle following after a__
read cycle and starting a read cycle following a write cycle,
keep the CS signal at an "H" level for at least 1 CLKIN.
hold shift
hold
read
return
CS = "H"
write
CLKIN
HREQ
HACK
CS
A8 - A30
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
R/W
"Hi-z"
"Hi-z"
BCH, BCL
"Hi-z"
D0 - D15
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
DC
("L" output)
hold shift
hold
write
write
("L" output)
return
write
✽
write
Note: "Hi-z" means high-impedance, and
indicates sampling timing.
Also, where marked above with ✽, keep CS signal to "H" at least 1 CLKIN when
starting a write bus cycle after a read bus cycle or a read bus cycle after a write
bus cycle.
CLKIN
HREQ
HACK
Fig. 25 Read/write bus cycle
CS
A8 - A30
R/W
BCH, BCL
D0 - D15
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
DC
("L" output)
("L" output)
✽
Note: "Hi-z" means high impedance, and
indicates sampling timing.
The value of the R/W signal that controls the data direction of the bus interface
cannot be changed during CS="L". Hold this value while CS="L".
Also, where marked above with ✽, 3 to 7 CLKIN clock periods are necessary for writing
operation to internal DRAM crossing an 128-bit boundary. Hold the input value of the
address or other control signals during these wait cycle periods (DC = "H"). Consecutive
writing operations within an 128-bit boundary are completed in 1 CLKIN clock period.
During these wait cycle period, CS cannot be returned to "H" level (the access
cannot be aborted). CS can only be returned to a "H" level after DC is driven to "L".
Fig. 24 Write bus cycle to internal DRAM
25
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Master/slave mode
_
The M32000D4AFP has an M/S (master/slave) pin for multiprocessor configuration use.
_
• master mode (M/S = "H")
_
This is normal operation mode. Set the M/S pin to an "H" level. It is
used when the M32000D4AFP is used as the main CPU in a system.
_
• slave mode (M/S = "L")
This operation mode is for when the M32000D4AFP is used as a
_
coprocessor. Set the M/S pin to an "L" level. When set to slave mode,
the M32000D4AFP does not start operation even after a reset, until
an interrupt request or the SBI is input. Processing is carried out by
communicating with the master M32000D4AFP, using the two programmable I/O ports and the external interrupt signal.
• Coprocessor only configuration example
The slave M32000D4AFP
accesses
only the internal DRAM and never
_
_____
the external bus. M/S and HREQ are fixed at the "L" level. The slave
M32000D4AFP executes the instructions that the master
M32000D4AFP downloads to the internal DRAM. The data transfer
request (processing complete) from the slave M32000D4AFP is notified to the master M32000D4AFP by inputting the interrupt request
via the programmable I/O port. The data transaction is carried out
when the master M32000D4AFP accesses the internal DRAM in the
slave M32000D4AFP.
• Common bus coprocessor configuration example
In this configuration, the slave M32000D4AFP can also access the
external bus. Communications between the master and slave CPUs
is carried out using the programmable I/O ports and the interrupt
request input.
lock control register (MLCR) < address: H'FFFF FFF7>
D24
D25
D26
D27
D28
D29
D30
D31
<coprocessor only configuration>
LM
no access to
external bus
M/S
<at reset: H'00>
R
W
0
✕
D
24 - 30
bit name
Not
assigned.
function
31
LM
(lock mode)
0: HREQ
exclusive
lock mode
___
1: CS exclusive
lock mode
______
R = 0 ... "0" when reading
W=
... write enabled
M/S
M32000D4AFP
(master)
HREQ
M32000D4AFP
(slave)
INT
INT
PP0
ROM
ASIC
R = ... read enabled
W = ✕ : write disabled
<common bus coprocessor configuration>
Fig. 26 Lock control register
M/S
M/S
HREQ
HACK
HREQ
HACK
M32000D4AFP
(master)
M32000D4AFP
(slave)
INT
INT
PP0
ROM
ASIC
bus
arbiter
Fig. 27 Master/slave system configuration example
26
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Power management function
In standby mode, all clock supply stops and only the contents of the
internal DRAM are retained. The power requirement is only that which
the internal DRAM needs for refreshing itself. When set to standby
mode, the M32000D4AFP waits for the current bus operation to be
completed. It then purges the cache memory and switches the internal DRAM to self-refresh mode. After that, the PLL and all clock sup_____
plies stop and the STBY signal goes to an "L" level to indicate
the
_____
completion
of
the
switch
to
standby
mode.
Input
an
"L"
level
to
WKUP
___
or RST to return from standby mode to normal operation mode. The
contents of the internal DRAM are retained upon return using the
_____
WKUP signal.
In CPU sleep mode, clock supply to the M32R CPU stops. In this
mode, the internal DRAM, cache memory, memory controller and
external bus interface continue to operate and the internal DRAM
___ ___
can___
be accessed from the external bus. Input an "L" level to INT, SBI
or RST to return to normal operation mode from CPU sleep mode.
The contents of the cache memory, internal DRAM, general-purpose
registers and programmable I/O control register are retained upon
___
___
return using the INT or SBI signals.
The M32000D4AFP has the following two low-power consumption
modes.
• standby mode
• CPU sleep mode
power management (MPMR) < address: H'FFFF FFFB>
D24
D
24 - 29
30, 31
D25
D26
D27
bit name
Not assigned.
PM0, PM1
(low power
consumption
mode)
R = 0 ... "0" when reading
W=
... write enabled
D28
D29
function
D30
D31
PM0
PM1
<at reset: H'00>
R
W
0
✕
00: normal
operation
mode
01: (reserved)
10: CPU sleep
mode
11: standby mode
R = ... read enabled
W = ✕ : write disabled
Fig. 28 Power management control register
reset
normal
operation mode
set to standby mode
(H'03 is written to
MPMR register)
set to CPU sleep mode
(H'02 is written to
MPMR register)
WKUP, RST
input
standby mode
INT, SBI, RST
input
CPU sleep
mode
Fig. 29 State transition for low power consumption mode
27
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Programmable I/O port
Reset
The M32000D4AFP has two programmable I/O ports (PP0, PP1).
Each port can be set as input or output.
When an "L" level is input to RST, the M32000D4AFP switches to
the reset state. The reset state is released when an "H" level is input
____
to RST, and the program is executed from the EIT vector entry of the
reset interrupt. All internal resources including the internal PLL (4x
clock generator) are initialized. In order to stabilize PLL oscillation,
____
the "L" input to RST should last a minimum of 2 ms after the clock
input to CLKIN stabilizes and VCC stabilizes to the specified voltage
level.
programmable I/O port direction control register 0 (PPCR0)
< address: H'FFFF FFE3>
D24
D25
D26
D27
D28
D29
D30
____
D31
PP0C
Table 2 Internal state after reset
internal resources
DRAM
cache memory
programmable I/O port direction control register 1 (PPCR1)
< address: H'FFFF FFE7>
D24
D25
D26
D27
D28
D29
D30
D31
PP1C
D
24 - 30
31
bit name
Not assigned.
PP0C, PP1C
(port I/O direction)
R = 0 ... "0" when reading
W=
... write enabled
general purpose
registers
(R0 - R15)
control registers PSW (CR0)
CBR (CR1)
SPI (CR2)
SPU (CR3)
BPC (CR6)
<at reset: H'00>
R
W
0
0: input port
1: output port
function
PC
R = ... read enabled
W = : write disabled
Fig. 30 Programmable I/O port direction control register
programmable I/O port data register 0 (PPDR0)
< address: H'FFFF FFEB>
D24
D25
D26
D27
D28
D29
D30
D31
PP0D
programmable I/O port data register 1 (PPDR1)
< address: H'FFFF FFEF>
D24
D25
D26
D27
D28
D29
D30
D31
PP1D
D
24 - 30
31
bit name
Not assigned.
PP0D, PP1D
(port data)
R = 0 ... "0" when reading
W=
... write enabled
<at reset: B'0000 000?>
function
R
W
0
0: data = "0"
1: data = "1"
R = ... read enabled
W = : write disabled
Fig. 31 Programmable I/O port data register
28
I/O registers
state
undefined
invalid
(purged all)
undefined
B'0000 0000 0000 0000 ??00 000? 0000 0000
(BSM, BIE, and BC are undefined)
H'0000 0000
undefined
undefined
undefined
master mode:
execute from address H'7FFF FFF0
slave mode:
wait for interrupt input at address
H'7FFF FFF0
• execute from___
address H'0000 0010
by inputting SBI signal
• execute from___
address H'0000 0080
by inputting INT signal
ACC
(accumulator) undefined
PPCR0, PPCR1 H'00 (input)
PPDR0, PPDR1 B'0000 000? (depends on input
pin state)
_____
MLCR
H'00 (HREQ exclusive lock mode)
MPMR
H'00 (normal operation)
MCCR
H'01 (cache-off mode)
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Clock generating circuit
ADDRESSING MODE
The M32000D4AFP has a clock multiplier circuit and operates at
four times the input frequency. The internal operation frequency becomes 66.6 MHz when a 16.65 MHz clock is input to CLKIN. A capacitor (C) should be connected to the PLLCAP pin, and the clock is
input to the CLKIN pin. The PLLVCC and PLLVSS pins should be
connected to the power source or the ground, respectively.
M32R family supports the following addressing modes.
< register direct >
The general-purpose register or the control register to be processed
is specified.
< register indirect >
The contents of the register specify the address in memory to be
accessed. This mode can be used by all load/store instructions.
< register relative indirect >
(The contents of the register) + (16-bit immediate value which is signextended to 32 bits) specify the address in memory to be accessed.
< register indirect and register update >
• 4 is added to the register contents
(the contents of the register before update specify
the address in memory to be accessed) [LD instruction]
• 4 is added to the register contents
(the contents of the register after update specify
the address in memory to be accessed) [ST instruction]
• 4 is subtracted from the register contents
(the contents of the register after update specify
the address in memory to be accessed) [ST instruction]
< immediate >
The 4-, 5-, 8-, 16- or 24-bit immediate value.
< PC relative >
(The contents of PC) + (8, 16, or 24-bit displacement which is signextended to 32 bits and 2 bits left-shifted) specify the address in
memory to be accessed.
M32000D4AFP
VCC
14 (PLLVCC)
18 (CLKIN)
clock input
PLL clock
generating
circuit
16 (PLLCAP)
15 (PLLVSS)
recommended values in circuit
C: 1000 pF
C
Fig. 32 Oscillation circuit
29
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
INSTRUCTION FORMAT
INSTRUCTION SET
There are two major instruction formats: two 16-bit instructions packed
together within a word boundary, and a single 32-bit instruction.
A total of 83 instructions are implemented.
< 16-bit instruction >
op2
R2
R1 = R1 op R 2
op1
R1
op1
R1
c
R1 = R1 op c
op1
cond
c
Branch (Short Displacement)
< 32-bit instruction >
op1
R1
op2
R2
c
R1 = R2 op c
op1
R1
op2
R2
c
Compare and Branch
op1
R1
c
R1 = R1 op c
op1
cond
c
Branch
Fig. 33 Instruction format
<Load/store instructions>
The load/store instructions carry out data transfers between a register and a memory.
LD
Load
LDB
Load byte
LDUB
Load unsigned byte
LDH
Load halfword
LDUH
Load unsigned halfword
LOCK
Load locked
ST
Store
STB
Store byte
STH
Store halfword
UNLOCK
Store unlocked
<Transfer instructions>
The transfer instructions carry out data transfers between registers
or a register and an immediate value.
LD24
Load 24-bit immediate
LDI
Load immediate
MV
Move register
MVFC
Move from control register
MVTC
Move to control register
SETH
Set high-order 16-bit
<Operation instructions>
Compare, arithmetic/logic operation, multiply and divide, and shift
are carried out between registers.
• compare instructions
CMP
Compare
CMPI
Compare immediate
CMPU
Compare unsigned
CMPUI
Compare unsigned immediate
• arithmetic operation instructions
ADD
Add
ADD3
Add 3-operand
ADDI
Add immediate
ADDV
Add with overflow checking
ADDV3
Add 3-operand
ADDX
Add with carry
NEG
Negate
SUB
Subtract
SUBV
Subtract with overflow checking
SUBX
Subtract with borrow
30
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
• logic operation instructions
AND
AND
AND3
AND 3-operand
NOT
Logical NOT
OR
OR
OR3
OR 3-operand
XOR
Exclusive OR
XOR3
Exclusive OR 3-operand
• multiply/divide instructions
DIV
Divide
DIVU
Divide unsigned
MUL
Multiply
REM
Remainder
REMU
Remainder unsigned
• shift instructions
SLL
Shift left logical
SLL3
Shift left logical 3-operand
SLLI
Shift left logical immediate
SRA
Shift right arithmetic
SRA3
Shift right arithmetic 3-operand
SRAI
Shift right arithmetic immediate
SRL
Shift right logical
SRL3
Shift right logical 3-operand
SRLI
Shift right logical immediate
<Branch instructions>
The branch instructions are used to change the program flow.
BC
Branch on C-bit
BEQ
Branch on equal
BEQZ
Branch on equal zero
BGEZ
Branch on greater than or equal zero
BGTZ
Branch on greater than zero
BL
Branch and link
BLEZ
Branch on less than or equal zero
BLTZ
Branch on less than zero
BNC
Branch on not C-bit
BNE
Branch on not equal
BNEZ
Branch on not equal zero
BRA
Branch
JL
Jump and link
JMP
Jump
NOP
No operation
<EIT-related instructions>
The EIT-related instructions carry out the EIT events (Exception, Interrupt and Trap). Trap initiation and return from EIT are EIT-related
instructions.
TRAP
Trap
RTE
Return from EIT
<DSP function instructions>
The DSP function instructions carry out multiplication of 32 bits ✕ 16
bits and 16 bits ✕ 16 bits or multiply and add operation; there are
also instructions to round off data in the accumulator and carry out
transfer of data between the accumulator and a general-purpose register.
MACHI
Multiply-accumulate high-order halfwords
MACLO
Multiply-accumulate low-order halfwords
MACWHI
Multiply-accumulate word and high-order halfword
MACWLO Multiply-accumulate word and low-order halfword
MULHI
Multiply high-order halfwords
MULLO
Multiply low-order halfwords
MULWHI
Multiply word and high-order halfword
MULWLO
Multiply word and low-order halfword
MVFACHI Move from accumulator high-order word
MVFACLO Move from accumulator low-order word
MVFACMI Move from accumulator middle-order word
MVTACHI Move to accumulator high-order word
MVTACLO Move to accumulator low-order word
RAC
Round accumulator
RACH
Round accumulator halfword
31
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Ratings
Parameter
Symbol
Conditions
Min.
Max.
Unit
VCC
Power source voltage
–0.5
4.6
V
VI
Input voltage
–0.5
4.6
V
–0.5
4.6
V
1000
mW
0
70
°C
–65
150
°C
VO
Output voltage
PD
Power consumption
TOPR
Operating temperature
TSTG
Storage temperature
TOPR = 25 °C
RECOMMENDED OPERATING CONDITIONS (VCC = 3.3 V ± 0.3 V, TOPR = 0 to 70 °C unless otherwise noted)
Symbol
Parameter
Ratings
Min.
Typ.
Max.
Unit
3.0
3.6
V
2.0
VCC+0.3
V
0.8VCC
–0.3
VCC+0.3
V
0.8
V
–0.3
0.2VCC
V
IOH (see note) “H” output current
2
mA
IOL (see note) “L” output current
2
mA
50
pF
VCC
Power source voltage
VIH
“H” input voltage
All inputs except following
____
RST pin
VIL
“L” input voltage
All inputs except following
____
RST pin
CL
output load capacity
Note: IOH and IOL represent the maximum values of DC current load. Intermittent current that is generated during output need not to be
considered as long as the output load capacity is within the specified range.
32
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
DC CHARACTERISTICS
ELECTRICAL CHARACTERISTICS (VCC = 3.3 V ± 0.3 V, TOPR = 0 to 70 °C unless otherwise noted)
Symbol
Parameter
Test conditions
VOH
“H” output voltage
IOH = –2 mA
VOL
“L” output voltage
IOL = 2 mA
IOZ
Output current in off state
VO = 0 to VCC
IIH
“H” input current
VIH = 0 to VCC +0.3 V
IIL
“L” input current
ICC
Power source current
C
Pin capacitance
VIH = 0 to VCC +0.3 V
Average in normal operation
mode VCC = 3.3 V
Average in CPU sleep mode
VCC = 3.3 V
Average in standby mode
VCC = 3.3 V
All pins
Ratings
Min.
Typ.
Max.
2.4
Unit
V
–10.0
0.4
V
10.0
µA
10.0
µA
–10.0
µA
140
220
mA
100
170
mA
2000
µA
15
pF
33
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
AC CHARACTERISTICS
TIMING REQUIREMENTS (VCC = 3.3 ± 0.3 V, CL = 50 pF, TOPR = 0 to 70 °C unless otherwise noted)
(1) Input transition time
Symbol
tr(INPUT)
Parameter
Input rise transition time
Test conditions
Limits
Max.
Min.
Unit
5
ns
RST pin
2
ms
CMOS input
5
ns
2
ms
CMOS input
____
tf(INPUT)
Input fall transition time
____
RST pin
Reference
number
1
2
(2) Clock, reset and wakeup timing
Symbol
Parameter
Test conditions
Limits
Min.
Max.
60
100
Unit
Reference
number
ns
5
ns
6
tc(CLKIN)
Clock input cycle time
tw(CLKINH)
External clock input “H” pulse width
1/4CLKIN
tw(CLKINL)
External clock input “L” pulse width
1/4CLKIN
ns
7
tr(CLKIN)
External clock input rising time
5
ns
8
tf(CLKIN)
External clock input falling time
5
ns
9
tw(RST)
Reset input “L” pulse width
2
ms
10
tw(WKUP)
Wakeup input “L” pulse width
2
ms
11
Unit
Reference
number
5.5
ns
30
2
ns
31
10
ns
36
2
ns
37
10
ns
38
2
ns
39
(3) Read and write timing
Symbol
Parameter
tsu(D-CLKIN)
Data input set-up time before CLKIN
th(CLKIN-D)
Data input hold time after CLKIN
Limits
Test conditions
Min.
Max.
__
tsu(DCH-CLKIN) DC input “H” set-up time before CLKIN
__
th(CLKIN-DCH)
DC input “H” hold time after CLKIN
tsu(DCL-CLKIN)
DC input “L” set-up time before CLKIN
__
__
th(CLKIN-DCL)
34
DC input “L” hold time after CLKIN
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
(4) Arbitration and external bus master read/write timing
Symbol
Parameter
Test conditions
Limits
Unit
Reference
number
5
ns
40
2
ns
41
Max.
Min.
_____
tsu(HREQ-CLKIN) HREQ input set-up time before CLKIN
_____
th(CLKIN-HREQ)
HREQ input hold time after CLKIN
__
tsu(CS-CLKIN)
CS input set-up time before CLKIN
7
ns
48
th(CLKIN-CS)
CS input hold time after CLKIN
2
ns
49
tsu(A-CLKIN)
Address input set-up time before CLKIN
5
ns
50
th(CLKIN-A)
Address input hold time after CLKIN
3
ns
51
tsu(D-CLKINL)
Data input set-up time before CLKIN
5
ns
52
Data input hold time after CLKIN
3
ns
53
Unit
Reference
number
tc(CLKIN)
ns
63
tc(CLKIN)
ns
64
Unit
Reference
number
__
th(CLKINL-D)
(5) Interrupt control unit timing
Symbol
Parameter
Test conditions
Limits
Max.
Min.
___
tw(INT)
INT input pulse width (see note)
___
tw(SBI)
___
SBI input pulse width (see note)
___
Note: Both INT and SBI are level-sense inputs. Keep them at an "L" level until the interrupt is accepted.
(6) I/O port timing
Symbol
Parameter
Test conditions
Limits
Min.
Max.
tw(PORTINL)
Port input “L” pulse width
30
ns
69
tw(PORTINH)
Port input “H” pulse width
30
ns
70
35
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
SWITCHING CHARACTERISTICS (VCC = 3.3 ± 0.3 V, CL = 50 pF, TOPR = 0 to 70 °C unless otherwise noted)
(1) Output transition time
Symbol
Parameter
Limits
Test conditions
Min.
Typ.
Max.
Unit
Reference
number
tr(OUTPUT)
Output rising transition time
8
ns
tf(OUTPUT)
Output falling transition time
8
ns
3
4
Unit
Reference
number
ns
12
ns
13
ns
14
15
(2) Read and write timing
Test
Symbol
Parameter
conditions
Limits
Min.
Max.
__
td(CLKIN-BSHX)
td(CLKIN-BSL)
BS = “H” effective time after CLKIN
0
__
12
BS = “L” delay time after CLKIN
__
td(CLKIN-BSLX)
BS = “L” effective time after CLKIN
tc(CLKIN)/4
__
td(CLKIN-BSH)
BS = “H” delay time after CLKIN
tc(CLKIN)/4+8
ns
td(CLKIN-AV)
Address delay time after CLKIN
16
ns
16
td(CLKIN-AX)
Address effective time after CLKIN
ns
17
ns
18
ns
19
ns
20
ns
21
ns
22
ns
23
ns
24
0
ns
25
0
ns
26
ns
27
ns
28
ns
29
ns
32
ns
33
ns
34
ns
35
td(CLKIN-BCV)
____
td(CLKIN-SIDV)
___
16
BCH, BCL delay time after CLKIN
____
td(CLKIN-BCX)
0
___
BCH, BCL effective time after CLKIN
0
16
SID delay time after CLKIN
td(CLKIN-SIDX)
SID effective time after CLKIN
td(CLKIN-STV)
ST delay time after CLKIN
td(CLKIN-STX)
ST effective time after CLKIN
0
16
0
__
td(CLKIN-RWV)
td(CLKIN-RWX)
16
R/W delay time after CLKIN
__
R/W effective time after CLKIN
______
td(CLKIN-BURSTHX) BURST = “H” effective time after CLKIN
______
td(CLKIN-BURSTL)
BURST = “L” delay time after CLKIN
12
______
td(CLKIN-BURSTLX)
BURST = “L” effective time after CLKIN
td(CLKIN-BURSTH)
BURST = “H” delay time after CLKIN
0
______
td(CLKIN-DZX)
td(CLKIN-DV)
Data output enable time after CLKIN
0
18
Data output delay time after CLKIN
td(CLKIN-DVX)
Data output effective time after CLKIN
td(CLKIN-DXZ)
Data output disable time after CLKIN
36
12
0
16
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
(3) Arbitration and external bus master read/write timing
Symbol
Limits
Test conditions
Parameter
_____
td(CLKIN-HACKHX)
HACK = “H” effective time after CLKIN
_____
td(CLKIN-HACKL)
Unit
Reference
number
ns
42
ns
43
ns
44
12
ns
45
16
ns
46
47
Max.
Min.
0
12
HACK = “L” delay time after CLKIN
_____
td(CLKIN-HACKLX)
0
HACK = “L” effective time after CLKIN
_____
td(CLKIN-HACKH)
HACK = “H” delay time after CLKIN
td(CLKIN-AZ)
Address output disable time after CLKIN
td(CLKIN-AZX)
Address output enable time after CLKIN
0
ns
td(CLKIN-DZX)
Data output enable time after CLKIN
0
ns
54
td(CLKIN-DV)
Data output delay time after CLKIN
18
ns
55
td(CLKIN-DXZ)
Data output disable time after CLKIN
16
ns
56
0
ns
57
0
ns
58
td(CLKIN-DVX)
Data output effective time after CLKIN
__
td(CS-DCZX)
__
DC output enable time after CS
__
td(CLKIN-DCHX)
DC = “H” effective time after CLKIN
td(CLKIN-DCL)
DC = “L” delay time after CLKIN
td(CLKIN-DCXZ)
DC output disable time after CLKIN
ns
59
16
ns
60
16
ns
61
ns
62
0
__
__
__
td(CLKIN-DCLX)
0
DC = “L” effective time after CLKIN
(4) Standby timing
Symbol
Parameter
Test conditions
Limits
Min.
Max.
_____
td(CLKIN-STBYHX)
0
STBY = “H” effective time after CLKIN
_____
td(CLKIN-STBYL)
tc(CLKIN)n/4+15
STBY = “L” delay time after CLKIN (see note)
_____
td(CLKIN-STBYLX)
STBY = “L” effective time after CLKIN
0
_____
td(CLKIN-STBYH)
tc(CLKIN)n/4+15
STBY = “H” delay time after CLKIN (see note)
Unit
Reference
number
ns
65
ns
66
ns
67
ns
68
_____
Note: The STBY signal is synchronized with the internal clock, therefore its timing changes at 0, 90, 180 and 270 (n=0, 1, 2, 3) degree phase
of CLKIN.
(5) I/O port timing
Symbol
Parameter
Test conditions
Limits
Min.
Max.
Unit
Reference
number
tw(PORTOUTL)
Port output “L” pulse width (see note)
12
ns
71
tw(PORTOUTH)
Port output “H” pulse width (see note)
12
ns
72
Note: The minimum pulse width value is that where the output is changed within 1 clock of the internal clock. Software processing time to write
to the port data register is not included.
37
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
0.5VCC
1.0 kΩ
measured pin
measured pin
CL = 50 pF
CMOS output
CL = 50 pF
CMOS output
(during floating delay time measurement)
Fig. 34 Output switching characteristic measurement circuit
timing reference point
(when not specified)
CMOS input
schmitt trigger input
CLKIN input
"H" input level
0.9VCC
"L" input level
0.1VCC
"H" input level
VCC
"L" input level
0.0 V
"H" input level
VCC
"L" input level
0.0 V
0.8VCC
0.2VCC
0.9VCC
0.1VCC
Fig. 35 Input waveform and timing reference point during characteristic measurement
timing reference point
CMOS output (when not specified)
0.8VCC
0.2VCC
"H" → "Z"
CMOS output
(during floating delay time measurement)
0.6VCC
0.4VCC
0.1VCC
"L" → "Z"
Fig. 36 Output timing measurement point during characteristic measurement
38
"Z" → "H"
0.9VCC
"Z" → "L"
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
1 tr(INPUT)
2 tf(INPUT)
0.8VCC
0.2VCC
CMOS input
(except for schmitt trigger input and CLKIN input)
1 tr(INPUT)
2 tf(INPUT)
schmitt trigger input
(RST)
0.9VCC
0.1VCC
Fig. 37 Input transition time
3 tr(OUTPUT) 4 tf(OUTPUT)
0.8VCC
0.2VCC
output pin
Fig. 38 Output transition time
5 tc(CLKIN)
6
7
tw(CLKINH) tw(CLKINL)
CLKIN
8 tr(CLKIN)
9 tf(CLKIN)
(input)
0.8VCC
0.5VCC
0.2VCC
*1
10 tw(RST)
RST
(input)
*1
11 tw(WKUP)
WKUP
(input)
*1 The WKUP and RST signals can be input asynchronously.
When returning from standby mode, the same timing applies.
Fig. 39 Clock reset and wakeup timing
39
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
0.5 VCC
0.5 VCC
(input)
CLKIN
14 td(CLKIN-BSLX)
12 td(CLKIN-BSHX)
13 td(CLKIN-BSL)
*2
15 td(CLKIN-BSH)
*2
(output)
BS
16 td(CLKIN-AV)
17 td(CLKIN-AX)
A8 to A30 (output)
18 td(CLKIN-BCV)
19 td(CLKIN-BCX)
BCH, BCL (output)
SID, ST
20 td(CLKIN-SIDV)
22 td(CLKIN-STV)
21 td(CLKIN-SIDX)
23 td(CLKIN-STX)
24 td(CLKIN-RWV)
25 td(CLKIN-RWX)
(output)
(output)
R/W
*2
26 td(CLKIN-BURSTHX)
27 td(CLKIN-BURSTL)
28 td(CLKIN-BURSTLX)*2
29 td(CLKIN-BURSTH) *2
*2
BURST
(output)
30 tsu(D-CLKIN)
31 th(CLKIN-D)
D0 to D15 (input)
32 td(CLKIN-DZX)
33 td(CLKIN-DV)
34 td(CLKIN-DVX)
35 td(CLKIN-DXZ)
D0 to D15 (output)
*1
36 tsu(DCH-CLKIN)
DC
*1
37 th(CLKIN-DCH)
38 tsu(DCL-CLKIN)
39 th(CLKIN-DCL)
(input)
*1 The set up/hold of DC = "H" may vary depending on the wait cycle insertion.
*2 All switching characteristics and timing requirements based on the falling edge of CLKIN are calculated according to
the internal CLKIN (duty ratio is 50%) . When designing external peripheral circuits, the correction for the duty cycle of
the actual CLKIN is necessary.
[example]
BS signal transition ("L" –> "H") when inputting 16.65 MHz clock whose duty ratio is 45 - 55% (± 5%) to CLKIN:
• minimum value of td(CLKIN-BSLX) = (value in table) – (correction value) = 15 – (60 x 5/100) = 12 [ns]
• maximum value of td(CLKIN-BSH) = (value in table) + (correction value) = (60/4 + 8) + (60 x 5/100) = 26 [ns]
Fig. 40 Read/write timing
40
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
0.5VCC
CLKIN
0.5VCC
(input)
*1
40 tsu(HREQ-CLKIN)
HREQ
*1
41 th(CLKIN-HREQ)
(input)
*2
42 td(CLKIN-HACKHX)
43 td(CLKIN-HACKL)*2
HACK
*2
44 td(CLKIN-HACKLX)
*2
45 td(CLKIN-HACKH)
(output)
46 td(CLKIN-AZ)
47 td(CLKIN-AZX)
A8 to A30, SID, ST,
BS, BCH, BCL, (output)
R/W, BURST
*1 The HREQ signal can be input asynchronously.
*2 All switching characteristics and timing requirements based on the falling edge of CLKIN are calculated according to
the internal CLKIN (duty ratio is 50%) . When designing external peripheral circuits, the correction for the duty cycle of
the actual CLKIN is necessary.
[example]
HACK signal transition ("H" –> "L") when inputting 16.65 MHz clock whose duty ratio is 45 - 55% (± 5%) to CLKIN:
• minimum value of td(CLKIN-HACKHX) = (value in table) – (correction value) = 0 – (60 x 5/100) = –3 [ns]
• maximum value of td(CLKIN-HACKL) = (value in table) + (correction value) = 12 + (60 x 5/100) = 15 [ns]
Fig. 41 Bus arbitration timing
41
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
0.5 VCC
CLKIN
(input)
40 tsu(HREQ-CLKIN)
*1
41 th(CLKIN-HREQ) *1
HREQ
(input)
*1
*1
42 td(CLKIN-HACKHX)
43 td(CLKIN-HACKL) *1
44 td(CLKIN-HACKLX)
45 td(CLKIN-HACKH)
*1
HACK
(output)
*1
*1
49 th(CLKIN-CS)
48 tsu(CS-CLKIN)
CS
(input)
*1
50 tsu(A-CLKIN)
48
48
49
51 th(CLKIN-A)
50
51
51
50
51
*1
49
R/W
(input)
50
A8 to A30
BCH, BCL
(input)
*1 53 th(CLKINL-D)
*1
52 tsu(D-CLKINL)
D0 to D15
(input)
*1
54 td(CLKIN-DZX)
55 td(CLKIN-DV)*1
D0 to D15
(output)
*1
59 td(CLKIN-DCHX)
60 td(CLKIN-DCL)*1
58 td(CS-DCZX)
56 td(CLKIN-DXZ) *1
57 td(CLKIN-DVX)*1
58
59
60
61 td(CLKIN-DCXZ)*1
62 td(CLKIN-DCLX)*1
*1
DC
(output)
*1 All switching characteristics and timing requirements based on the falling edge of CLKIN are calculated according to
the internal CLKIN (duty ratio is 50%) . When designing external peripheral circuits, the correction for the duty cycle of
the actual CLKIN is necessary.
[example]
CS signal transition ("L" –> "H") when inputting 16.65 MHz clock whose duty ratio is 45 - 55% (± 5%) to CLKIN:
• minimum value of tsu(CS-CLKIN) = (value in table) + (correction value) = 10 + (60 x 5/100) = 13 [ns]
• minimum value of th(CLKIN-CS) = (value in table) + (correction value) = 2 + (60 x 5/100) = 5 [ns]
Fig. 42 External bus master read/write timing
42
61
62
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
63 tw(INT) *1
(input)
INT
64 tw(SBI) *1
SBI
(input)
*1 The INT and SBI signals can be input asynchronously.
When returning from CPU sleep mode, the same timing applies.
This timing value is "a value necessary for sampling the input to pins", however, not "a value
that guarantees the interrupt acceptance".
The interrupt request is a level-sensed input , and should be kept "L" until it is accepted.
Fig. 43 Interrupt input timing
CLKIN
(input)
internal clock
(66.6 MHz)
STBY
65 td(CLKIN-STBYHX)
67 td(CLKIN-STBYLX)
66 td(CLKIN-STBYL) *1 *2
68 td(CLKIN-STBYH) *1 *3
(output)
*1 The STBY signal is synchronized with the internal clock therefore, its timing changes at 0, 90, 180 and 270
degree phase of CLKIN.
*2 The STBY goes to an "L" level when switched to the standby mode.
*3 When returning from standby mode, the STBY signal goes to an "H" level 1 CLKIN after
sampling that WKUP has returned from "L" to "H", or 3 CLKINs after sampling that RST = "L".
Fig. 44 Standby timing
[for input]
69 tw(PORTINL)
70 tw(PORTINH)
71 tw(PORTOUTL)
72 tw(PORTOUTH)
PX
[for output]
PX
Fig. 45 I/O port timing
43
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
•
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intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
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product distributor for the latest product information before purchasing a product listed herein.
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Notes regarding these materials
•
•
•
•
•
•
© 1998 MITSUBISHI ELECTRIC CORP.
Revised edition, effective May. 1998
Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev.
No.
1.0
M32000D4AFP DATA SHEET
Revision Description
First Edition
Rev.
date
970901
__
1.1
• "After DC outputs an ~ CLKIN falling edge." revised (line 18, page 24).
980501
• Notes in Figure 23 revised (page 24).
__
• "After DC outputs an ~ CLKIN falling edge." revised (line 19, page 25).
• Notes in Figure 24 revised (page 25).
• Table 2 revised (page 28).
• (3) Arbitration and external bus master read/write timing
Symbol
Parameter
~
~
~
__
__
td(CS-DCZX) DC output enable time after CS
corrected (page 37).
•" 58 td(CS-DCZX) *1 " in Fig. 42 corrected (page 42).
• Notes in Figure 44 revised (page 43).
1.2
• Figure 23 revised (page 24).
980911
(1/1)