AD ADAU1978 Quad analog-to-digital converter (adc) Datasheet

Quad Analog-to-Digital Converter (ADC)
ADAU1978
Data Sheet
FEATURES
GENERAL DESCRIPTION
Four 2 V rms differential inputs
On-chip phase-locked loop (PLL) for master clock
Low electromagnetic interference (EMI) design
106 dB analog-to-digital converter (ADC) dynamic range
Total harmonic distortion + noise (THD + N): −95 dB
Selectable digital high-pass filter
24-bit stereo ADC with 8 kHz to 192 kHz sample rates
Digital volume control with autoramp function
I2C/SPI controllable for flexibility
Software-controllable clickless mute
Software power-down
Right justified, left justified, I2S, and TDM modes
Master and slave operation modes
40-lead LFCSP package
Qualified for automotive applications
The ADAU1978 incorporates four high performance, analog-todigital converters (ADCs) with 2 V rms capable ac-coupled inputs.
The ADCs use a multibit sigma-delta (Σ-Δ) architecture with
continuous time front end for low EMI. An I2C/serial peripheral
interface (SPI) control port is included that allows a microcontroller
to adjust volume and many other parameters. The ADAU1978
uses only a single 3.3 V supply. The part internally generates the
required digital DVDD supply. The low power architecture
reduces the power consumption. The ADAU1978 is available in
a 40-lead LFCSP package. The on-chip PLL can derive the master
clock from an external clock input or frame clock (sample rate
clock). When fed with the frame clock, it eliminates the need
for a separate high frequency master clock in the system.
Note that throughout this data sheet, multifunction pins, such
as SCL/CCLK, are referred to either by the entire pin name or
by a single function of the pin, for example, CCLK, when only
that function is relevant.
APPLICATIONS
Automotive audio systems
Active noise cancellation systems
AVDD2
AVDD1
AVDD3
ADC
ADC
ADC
ADC
SERIAL AUDIO PORT
AIN1P
AIN1N
AIN2P
AIN2N
AIN3P
AIN3N
AIN4P
AIN4N
3.3V TO 1.8V
REGULATOR
PROGRAMMABLE GAIN
DECIMATOR/HPF
DC CALIBRATION
ADAU1978
AGND3
AGND1
IOVDD
LRCLK
BCLK
SDATAOUT1
SDATAOUT2
SCL/CCLK
SDA/COUT
ADDR1/CIN
ADDR0/CLATCH
PD/RST
PLL_FILT
AGND2
I2C/SPI
CONTROL
SA_MODE
AGND2
MCLKIN
PLL
VREF
BG
REF
DGND
AGND6
AGND5
AGND4
AGND3
AGND2
AGND1
AVDD2
DVDD
11292-001
AVDD3
AVDD1
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
Rev. 0
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ADAU1978
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
SPI Mode ..................................................................................... 25
Applications ....................................................................................... 1
Register Summary .......................................................................... 27
General Description ......................................................................... 1
Register Details ............................................................................... 28
Functional Block Diagram .............................................................. 1
Master Power and Soft Reset Register ..................................... 28
Revision History ............................................................................... 2
PLL Control Register ................................................................. 29
Specifications..................................................................................... 3
Block Power Control and Serial Port Control Register ......... 30
Analog Performance Specifications ........................................... 3
Serial Port Control Register 1 ................................................... 31
Digital Input/Output Specifications........................................... 3
Serial Port Control Register 2 ................................................... 32
Power Supply Specifications........................................................ 4
Channel 1 and Channel 2 Mapping for Output Serial Ports
Register ........................................................................................ 33
Digital Filter Specifications ......................................................... 4
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 12
Overview...................................................................................... 12
Channel 3 and Channel 4 Mapping for Output Serial Ports
Register ........................................................................................ 35
Serial Output Drive and Overtemperature Protection Control
Register ........................................................................................ 36
Post ADC Gain Channel 1 Control Register .......................... 37
Post ADC Gain Channel 2 Control Register .......................... 38
Post ADC Gain Channel 3 Control Register .......................... 38
Post ADC Gain Channel 4 Control Register .......................... 39
Power Supply and Voltage Reference ....................................... 12
High-Pass Filter and DC Offset Control Register and Master
Mute Register .............................................................................. 40
Power-On Reset Sequence ........................................................ 12
ADC Clipping Status Register .................................................. 41
PLL and Clock............................................................................. 13
Digital DC High-Pass Filter and Calibration Register .......... 42
Analog Inputs .............................................................................. 14
Typical Application Circuit ........................................................... 43
ADC ............................................................................................. 16
Outline Dimensions ....................................................................... 44
ADC Summing Modes .............................................................. 16
Ordering Guide .......................................................................... 44
Serial Audio Data Output Ports, Data Format ....................... 17
Automotive Products ................................................................. 44
Control Ports ................................................................................... 21
I2C Mode ...................................................................................... 22
REVISION HISTORY
5/13—Revision 0: Initial Version
Rev. 0 | Page 2 of 44
Data Sheet
ADAU1978
SPECIFICATIONS
Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.
AVDDx/IOVDD = 3.3 V; DVDD (internally generated) = 1.8 V; TA = −40°C to +105°C, unless otherwise noted. Master clock = 12.288 MHz
(48 kHz fS, 256 × fS mode); input sample rate = 48 kHz; measurement bandwidth = 20 Hz to 20 kHz; word width = 24 bits; load capacitance
(digital output) = 20 pF; load current (digital output) = ±1 mA; digital input voltage high = 2.0 V; and digital input voltage low = 0.8 V.
ANALOG PERFORMANCE SPECIFICATIONS
Table 1.
Parameter
LINE INPUT
Full-Scale AC Differential Input Voltage
Full-Scale Single-Ended Input Voltage
Input Common-Mode Voltage
ANALOG-TO-DIGITAL CONVERTERS
Differential Input Resistance
Single-Ended Input Resistance
ADC Resolution
Dynamic Range (A-Weighted) Line Input 1
Total Harmonic Distortion + Noise (THD + N)
Digital Gain Post ADC
Gain Error
Interchannel Gain Mismatch
Gain Drift
Common-Mode Rejection Ratio (CMRR)
Power Supply Rejection Ratio (PSRR)
Interchannel Isolation
Interchannel Phase Deviation
REFERENCE
Internal Reference Voltage
Output Impedance
ADC SERIAL PORT
Output Sample Rate
1
Test Conditions/Comments
Min
VIN, cm at AINxP/AINxN pins
Between AINxP and AINxN
Between AINxP and AINxN
Input = 1 kHz, −60 dBFS (0 dBFS = 2 V rms input)
Input = 1 kHz, −1 dBFS ( 0 dBFS = 2 V rms input)
103
Typ
50
VREF pin
1.47
Unit
2
1
1.5
V rms
V rms
V dc
28.6
14.3
24
106
−95
kΩ
kΩ
Bits
dB
dB
dB
%
dB
ppm/°C
dB
dB
dB
dB
Degrees
0
−10
−0.25
200 mV rms, 1 kHz
200 mV rms, 20 kHz
100 mV rms, 1 kHz on AVDD = 3.3 V
Max
−88
60
+10
+0.25
100
65
56
70
100
0
1.50
20
8
1.54
V
kΩ
192
kHz
This is for a sampling frequency, fS, ranging from 44.1 kHz to 192 kHz.
DIGITAL INPUT/OUTPUT SPECIFICATIONS
Table 2.
Parameter
INPUT
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
Input Leakage Current
Input Capacitance
OUTPUT
High Level Output Voltage (VOH)
Low Level Output Voltage (VOL)
Test Conditions/Comments
Min
Typ
Max
Unit
0.3 × IOVDD
+10
5
V
V
µA
pF
0.4
V
V
0.7 × IOVDD
−10
IOH = 1 mA
IOL = 1 mA
IOVDD − 0.60
Rev. 0 | Page 3 of 44
ADAU1978
Data Sheet
POWER SUPPLY SPECIFICATIONS
AVDD = 3.3 V, DVDD = 1.8 V, IOVDD = 3.3 V, and fS = 48 kHz (master mode), unless otherwise noted.
Table 3.
Parameter
SUPPLY
DVDD
AVDDx
IOVDD
IOVDD CURRENT
Normal Operation
Power-Down
AVDDx CURRENT
Normal Operation
Power-Down
DVDD CURRENT
Normal Operation
Power-Down
POWER DISSIPATION
Normal Operation
Analog Supply
Digital Supply
Digital I/O Supply
Power-Down, All Supplies
Test Conditions/Comments
Min
Typ
Max
Unit
On-chip low dropout (LDO) regulator
AVDD
IOVDD
Master clock = 256 × fS
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
fS = 48 kHz to 192 kHz
1.62
3.0
1.62
1.8
3.3
3.3
1.98
3.6
3.6
V
V
V
450
880
1.75
20
µA
µA
mA
µA
4-channel ADC, DVDD internal
4-channel ADC, DVDD external
14
9.5
270
mA
mA
µA
DVDD external
4.5
65
mA
µA
46.2
31
8.1
1.49
960
mW
mW
mW
mW
µW
Master clock = 256 fS, 48 kHz
DVDD internal
DVDD external
DVDD external
IOVDD = 3.3 V
DIGITAL FILTER SPECIFICATIONS
Table 4.
Parameter
ADC DECIMATION FILTER
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
HIGH-PASS FILTER
Cutoff Frequency
Phase Deviation
Settling Time
ADC DIGITAL GAIN
Gain Step Size
Mode
All modes, typical at fS = 48 kHz
Factor
Min
0.4375 × fS
Typ
Max
21
±0.015
24
27
0.5 × fS
0.5625 × fS
kHz
dB
kHz
kHz
dB
µs
µs
79
fS = 8 kHz to 96 kHz
fS = 192 kHz
All modes, typical at 48 kHz
At −3 dB point
At 20 Hz
All modes
22.9844/fS
479
35
0.9375
10
1
0
60
0.375
Rev. 0 | Page 4 of 44
Unit
Hz
Degrees
sec
dB
dB
Data Sheet
ADAU1978
TIMING SPECIFICATIONS
Table 5.
Parameter
INPUT MASTER CLOCK (MCLK)
Duty Cycle
fMCLKIN
RESET
Reset Pulse
PLL
Lock Time
I2C PORT
fSCL
tSCLH
tSCLL
tSCS
tSCH
tDS
tDH
tSCR
tSCF
tSDR
tSDF
tBFT
tSUSTO
SPI PORT
fCCLK
tCCPH
tCCPL
tCDS
tCDH
tCLS
tCLH
tCLPH
tCOE
tCOD
tCOTS
ADC SERIAL PORT
tABH
tABL
tALS
tALH
tABDD
Limit at
Min
Max
Unit
Description
40
60
See Table 9
%
MHz
MCLKIN duty cycle; MCLKIN at 256 × fS, 384 × fS, 512 × fS, and 768 × fS
MCLKIN frequency, PLL in MCLK mode
15
ns
RST low
10
ms
400
kHz
µs
µs
µs
µs
ns
300
300
300
300
ns
ns
ns
ns
µs
µs
10
30
30
30
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
See Figure 4
SCL frequency
SCL high
SCL low
Setup time; relevant for repeated start condition
Hold time; after this period of time, the first clock pulse is generated
Data setup time
Data hold time
SCL rise time
SCL fall time
SDA rise time
SDA fall time
Bus-free time; time between stop and start
Setup time for stop condition
see Figure 3
CCLK frequency
CCLK high
CCLK low
CIN setup to CCLK rising
CIN hold from CCLK rising
CLATCH setup to CCLK rising
CLATCH hold from CCLK rising
CLATCH high
COUT enable from CLATCH falling
COUT delay from CCLK falling
COUT tristate from CLATCH rising
18
ns
ns
ns
ns
ns
see Figure 2
BCLK high, slave mode
BCLK low, slave mode
LRCLK setup to BCLK rising, slave mode
LRCLK hold from BCLK rising, slave mode
SDATAOUTx delay from BCLK falling
0.6
1.3
0.6
0.6
100
0
1.3
0.6
35
35
10
10
10
40
10
10
10
10
5
Rev. 0 | Page 5 of 44
ADAU1978
Data Sheet
Timing Digrams
tALS
LRCLK
tALH
tABH
BCLK
tABL
SDATAOUTx
LEFT JUSTIFIED
MODE
tABDD
MSB
MSB – 1
tABDD
SDATAOUTx
I2S MODE
MSB
tABDD
SDATAOUTx
RIGHT JUSTIFIED
MODE
MSB
LSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
11292-002
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 2. Serial Output Port Timing
tCOE
tCLH
tCLS
tCCPH
CLATCH
tCLPH
tCCPL
CCLK
CIN
tCDH
tCDS
tCOTS
11292-003
COUT
tCOD
Figure 3. SPI Port Timing
tSCH
tDS
tSDR
STOP
tSCH
START
SDA
tSDF
tSCLH
tBFT
tSCR
tSCLL
tDH
tSCF
tSCS
Figure 4. I2C Port Timing
Rev. 0 | Page 6 of 44
tSUSTO
11292-004
SCL
Data Sheet
ADAU1978
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 6.
Parameter
Analog (AVDDx) Supply
Digital Supply
DVDD
IOVDD
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Operating Temperature Range (Ambient)
Junction Temperature Range
Storage Temperature Range
θJA represents junction-to-ambient thermal resistance, and
θJC represents the junction-to-case thermal resistance. All
characteristics are for a standard JEDEC board per JESD51.
Rating
−0.3 V to +3.6 V
−0.3 V to +1.98 V
−0.3 V to +3.63 V
±20 mA
–0.3 V to +3.6 V
−0.3 V to +3.6 V
−40°C to +105°C
−40°C to +125°C
−65°C to +150°C
Table 7. Thermal Resistance
Package Type
40-Lead LFCSP
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 7 of 44
θJA
32.8
θJC
1.93
Unit
°C/W
ADAU1978
Data Sheet
40
39
38
37
36
35
34
33
32
31
AVDD1
AIN4P
AIN4N
AIN3P
AIN3N
AIN2P
AIN2N
AIN1P
AIN1N
AVDD3
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
ADAU1978
TOP VIEW
(Not to Scale)
30
29
28
27
26
25
24
23
22
21
NC
AGND6
AGND5
NC
NC
NC
NC
NC
AGND4
AGND3
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD MUST BE CONNECTED TO THE
GROUND PLANE ON THE PRINTED CIRCUIT BOARD (PCB).
11292-005
DGND
IOVDD
SDATAOUT1
SDATAOUT2
LRCLK
BCLK
SDA/COUT
SCL/CCLK
ADDR0/CLATCH
ADDR1/CIN
11
12
13
14
15
16
17
18
19
20
AGND1
VREF
PLL_FILT
AVDD2
AGND2
PD/RST
MCLKIN
NC
SA_MODE
DVDD
Figure 5. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
1
2
Mnemonic
AGND1
VREF
Type1
P
O
3
4
5
6
7
8, 23 to 27, 30
9
PLL_FILT
AVDD2
AGND2
PD/RST
MCLKIN
NC
SA_MODE
O
P
P
I
I
10
11
12
13
14
15
16
17
18
19
DVDD
DGND
IOVDD
SDATAOUT1
SDATAOUT2
LRCLK
BCLK
SDA/COUT
SCL/CCLK
ADDR0/
CLATCH
ADDR1/CIN
AGND3
AGND4
AGND5
AGND6
AVDD3
O
P
P
O
O
I/O
I/O
I/O
I
I
Description
Analog Ground.
Voltage Reference. Decouple VREF to AGND with a 10 μF capacitor in parallel with a 100 nF
capacitor.
PLL Loop Filter. Return PLL_FILT to AVDD using recommended loop filter components.
Analog Power Supply. Connect AVDD2 to an analog 3.3 V supply.
Analog Ground.
Power-Down/Reset (Active Low).
Master Clock Input.
No Connect. Do not connect to these pins. Leave the NC pins open.
Standalone Mode. Connect SA_MODE to IOVDD using 10 kΩ pull-up resistor for standalone
mode.
1.8 V Digital Power Supply Output. Decouple to DGND with 100 nF and 10 μF capacitors.
Digital Ground.
Digital I/O Power Supply. Connect IOVDD to a supply from 1.8 V to 3.3 V.
ADC Serial Data Output Pair 1 (ADC L1 and ADC R1).
ADC Serial Data Output Pair 2 (ADC L2 and ADC R2).
Frame Clock for ADC Serial Port.
Bit Clock for ADC Serial Port.
Serial Data Out (I2C)/Control Data Output (SPI).
Serial Clock Input (I2C)/Control Clock Input (SPI).
Chip Address Bit 0 Setting (I2C)/Chip Select Input for Control Data (SPI).
I
P
P
P
P
P
Chip Address Bit 1 Setting (I2C)/Control Data Input (SPI).
Analog Ground.
Analog Ground.
Analog Ground.
Analog Ground.
Analog Power Supply. Connect AVDD3 to an analog 3.3 V supply.
20
21
22
28
29
31
I
Rev. 0 | Page 8 of 44
Data Sheet
Pin No.
32
33
34
35
36
37
38
39
40
1
Mnemonic
AIN1N
AIN1P
AIN2N
AIN2P
AIN3N
AIN3P
AIN4N
AIN4P
AVDD1
EP
ADAU1978
Type1
I
I
I
I
I
I
I
I
P
Description
Analog Input Channel 1 Inverting Input.
Analog Input Channel 1 Noninverting Input.
Analog Input Channel 2 Inverting Input.
Analog Input Channel 2 Noninverting Input.
Analog Input Channel 3 Inverting Input.
Analog Input Channel 3 Noninverting Input.
Analog Input Channel 4 Inverting Input.
Analog Input Channel 4 Noninverting Input.
Analog Power Supply. Connect AVDD1 to an analog 3.3 V supply.
Exposed Pad. The exposed pad must be connected to the ground plane on the printed circuit
board (PCB).
P = power, O = output, I = input, I/O = input/output.
Rev. 0 | Page 9 of 44
ADAU1978
Data Sheet
0
–10
–20
–30
–50
–70
–80
–90
–100
–110
–120
–130
–140
–160
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (kHz)
11292-006
–150
0
0
–10
–10
–20
–20
–30
–30
–40
–40
–50
–50
–60
–70
–80
–90
–100
–110
–60
–70
–80
–90
–100
–110
–120
–120
–130
–130
–140
–140
–150
–150
0.1
1
–160
11292-007
–160
10
FREQUENCY (kHz)
100
1
FREQUENCY (kHz)
Figure 9. CMRR Differential Input, Referenced to 200 mV Differential Input
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
Figure 6. Fast Fourier Transform, 2 mV Differential Input at fS = 48 kHz
0.1
0
2
4
6
8
10
12
14
16
18
FREQUENCY (kHz)
Figure 7. Fast Fourier Transform, −1 dBFS Differential Input
20
11292-010
–60
CMRR (dB)
AMPLITUDE (dBFS)
–40
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
11292-009
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 10. Fast Fourier Transform, No Input
0
0.10
–10
0.08
–20
–30
0.06
–40
MAGNITUDE (dB)
0.04
–60
–70
–80
–90
–100
–110
0.02
0
–0.02
–0.04
–120
–130
–0.06
–140
–160
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
INPUT AMPLITUDE (V rms)
1.8
2.0
Figure 8. THD + N vs. Input Amplitude
–0.10
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
FREQUENCY (Hz)
Figure 11. ADC Pass-Band Ripple at fS = 48 kHz
Rev. 0 | Page 10 of 44
11292-011
–0.08
–150
11292-008
THD + N (dBFS)
–50
Data Sheet
ADAU1978
0
–10
–20
–40
–50
–60
–70
–80
–90
–100
0
5000 10000 15000 20000 25000 30000 35000 40000
FREQUENCY (Hz)
11292-012
MAGNITUDE (dB)
–30
Figure 12. ADC Filter Stop-Band Response at fS = 48 kHz
Rev. 0 | Page 11 of 44
ADAU1978
Data Sheet
THEORY OF OPERATION
The ADAU1978 incorporates four high performance ADCs and
a phase-locked loop circuit for generating the necessary on-chip
clock signals.
POWER SUPPLY AND VOLTAGE REFERENCE
The ADAU1978 requires a single 3.3 V power supply. Separate
power supply input pins are provided for the analog and boost
converter. Decouple these pins to AGND with 100 nF ceramic
chip capacitors placed as close as possible to the pins to minimize
noise pickup. A bulk aluminum electrolytic capacitor of at least
10 μF must be provided on the same PCB as the ADC. It is
important that the analog supply be as clean as possible for
best performance.
The supply voltage for the digital core (DVDD) is generated
using an internal low dropout regulator. The typical DVDD
output is 1.8 V and must be decoupled using a 100 nF ceramic
capacitor and a 10 μF capacitor. Place the 100 nF ceramic
capacitor as close as possible to the DVDD pin.
The voltage reference for the analog blocks is generated
internally and output at the VREF pin (Pin 2). The typical
voltage at the pin is 1.5 V with an AVDDx of 3.3 V.
All digital inputs are compatible with TTL and CMOS levels.
All outputs are driven from the IOVDD supply. The IOVDD
can be in the 1.8 V to 3.3 V range. The IOVDD pin must be
decoupled with a 100 nF capacitor placed as close to the
IOVDD pin as possible.
The ADC internal voltage reference is output from the VREF pin
and must be decoupled using a 100 nF ceramic capacitor in
parallel with a 10 μF capacitor. The VREF pin has limited current
capability. The voltage reference is used as a reference to the
ADC; therefore, it is recommended not to draw current from
this pin for external circuits. When using this reference, use a
noninverting amplifier buffer to provide a reference to other
circuits in the application.
In reset mode, the VREF pin is disabled to save power and is
enabled only when the RST pin is pulled high.
POWER-ON RESET SEQUENCE
The ADAU1978 requires that a single 3.3 V power supply be
provided externally at the AVDDx pin. The part internally
generates DVDD (1.8 V), which is used for the digital core of
the ADC. The DVDD supply output pin (Pin 10) is provided
to connect the decoupling capacitors to DGND. The typical
recommended values for the decoupling capacitors are 100 nF
in parallel with 10 μF. During a reset, the DVDD regulator is
disabled to reduce power consumption. After the PD/RST pin
(Pin 6) is pulled high, the part enables the DVDD regulator.
However, the internal ADC and digital core reset is controlled by
the internal POR signal (power-on reset) circuit, which monitors
the DVDD level. Therefore, the device does not come out of a
reset until DVDD reaches 1.2 V and the POR signal is released.
The DVDD settling time depends on the charge-up time for the
external capacitors and on the AVDDx ramp-up time.
The internal power-on reset circuit is provided with hysteresis to
ensure that a reset of the part is not initiated by an instantaneous
glitch on DVDD. The typical trip points are 1.2 V with PD/RST
high and 0.6 V (±20%) with PD/RST low. This ensures that
the core is not reset until the DVDD level falls below the 0.6 V
trip point.
As soon as the PD/RST pin is pulled high, the internal regulator
starts charging up CEXT on the DVDD pin. The DVDD charge-up
time is based on the output resistance of the regulator and the
external decoupling capacitor. The time constant can be calculated as
tC = ROUT × CEXT
where ROUT = 20 Ω typical.
For example, if CEXT is 10 μF, tC is 200 μs and is the time that it
takes to reach the DVDD voltage, within 63.6%.
The power-on reset circuit releases an internal reset of the core
when DVDD reaches 1.2 V (see Figure 13). Therefore, it is
recommended to wait for at least the tC period to elapse before
sending I2C or SPI control signals.
AVDDx
tRESET
PD/RST
tC
DVDD (1.8V)
1.2V
tD
0.48V
11292-013
OVERVIEW
POR
Figure 13. Power-On Reset Timing
When applying a hardware reset to the part by pulling the
PD/RST pin (Pin 6) low and then high, there are certain time
restrictions. During the PD/RST low pulse period, the DVDD
starts discharging. The discharge time constant is decided on by
the internal resistance of the regulator and CEXT. The time
required for DVDD to fall from 1.8 V to 0.48 V (0.6 V − 20%)
can be estimated using the following equation:
tD = 1.32 × RINT × CEXT
where RINT = 64 kΩ typical. (RINT can vary due to process by ±20%.)
For example, if CEXT is 10 μF, tD is 0.845 sec.
Depending on CEXT, tD may vary and, in turn, affect the minimum hold period for the PD/RST pulse. The PD/RST pulse
Rev. 0 | Page 12 of 44
Data Sheet
ADAU1978
The PLL_LOCK bit (Bit 7) of Register 0x01 indicates the lock
status of the PLL. It is recommended that after initial power-up
the PLL lock status be read to ensure that the PLL outputs the
correct frequency before unmuting the audio outputs.
must be held low for the tD time period to initialize the core
properly.
The required PD/RST low pulse period can be reduced by
adding a resistor across CEXT. The new tD value can then be
calculated as
Table 9. Required Input Master Clock Frequency for
Common Sample Rates
tD = 1.32 × REQ × CEXT
where REQ = 64 kΩ || REXT.
The resistor ensures that DVDD not only discharges quickly during
a reset or an AVDDx power loss but also resets the internal blocks
correctly. Note that some power loss in this resistor is to be
expected because the resistor constantly draws current from
DVDD. The typical value for CEXT is 10 µF and for REXT is 3 kΩ.
This results in a time constant of
tD = 1.32 × REQ × CEXT = 37.8 ms
where REQ = 2.866 kΩ (64 kΩ || 3 kΩ).
Using this equation at a set CEXT value, the REXT can be calculated
for a desired PD/RST pulse period.
There is also a software reset bit (S_RST, Bit 7 of Register 0x00)
available that can be used to reset the part, but note that during an
AVDDx power loss, the software reset may not ensure proper
initialization because DVDD may not be stable.
+3.3V
AVDD1
AVDD3
AVDD2
3.3V TO 1.8V
REGULATOR
TO INTERNAL
BLOCKS
DVDD
C
0.1µF
CEXT
10µF
MLCC X7R
REXT
3kΩ
+1.8V OR +3.3V
MCS
(Bits[2:0])
000
001
010
011
100
000
001
010
011
100
000
001
010
011
100
000
001
010
011
100
000
001
010
011
100
fS (kHz)
32
32
32
32
32
44.1
44.1
44.1
44.1
44.1
48
48
48
48
48
96
96
96
96
96
192
192
192
192
192
Frequency
Multiplication Ratio
128 × fS
256 × fS
384 × fS
512 × fS
768 × fS
128 × fS
256 × fS
384 × fS
512 × fS
768 × fS
128 × fS
256 × fS
384 × fS
512 × fS
768 × fS
64 × fS
128 × fS
192 × fS
256 × fS
384 × fS
32 × fS
64 × fS
96 × fS
128 × fS
192 × fS
MCLKIN
Frequency (MHz)
4.096
8.192
12.288
16.384
24.576
5.6448
11.2896
16.9344
22.5792
33.8688
6.144
12.288
18.432
24.576
36.864
6.144
12.288
18.432
24.576
36.864
6.144
12.288
18.432
24.576
36.864
IOVDD
Figure 14. DVDD Regulator Output Connections
PLL AND CLOCK
The ADAU1978 has a built-in analog PLL to provide a jitter-free
master clock to the internal ADC. The PLL must be programmed
for the appropriate input clock frequency. The PLL_CONTROL
Register 0x01 is used for setting the PLL.
The CLK_S bit (Bit 4) of Register 0x01 is used for setting the
clock source for the PLL. The clock source can be either the
MCLKIN pin or the LRCLK pin (slave mode). In LRCLK mode,
the PLL can support sample rates between 32 kHz and 192 kHz.
The PLL can accept the audio frame clock (sample rate clock)
as the input, but the serial port must be configured as a slave,
and the frame clock must be fed to the part from the master.
It is strongly recommended that the PLL be disabled, reprogrammed with the new setting, and then reenabled. A lock bit
is provided that can be polled via the I2C to check whether the
PLL has acquired lock.
The PLL requires an external filter, which is connected at the
PLL_FILT pin (Pin 3). The recommended PLL filter circuit for
MCLK or LRCLK mode is shown in Figure 15. Using NPO
capacitors is recommended for temperature stability. Place the
filter components close to the device for best performance.
In MCLK input mode, the MCS bits (Bits[2:0] of Register 0x01)
must be set to the desired input clock frequency for the MCLKIN
pin. Table 9 shows the input master clock frequency required
for the most common sample rates and the MCS bit settings.
Rev. 0 | Page 13 of 44
AVDDx
AVDDx
39nF
4.87kΩ
PLL_FILT
5.6nF
2.2nF
1kΩ
PLL_FILT
LRCLK MODE
MCLK MODE
Figure 15. PLL Filter
390pF
11292-014
C
0.1µF
11292-114
ADAU1978
ADAU1978
Data Sheet
ANALOG INPUTS
R
The block diagram shown in Figure 16 represents the typical
input circuit.
In most audio applications, the dc content of the signal is removed
by using a coupling capacitor. However, the ADAU1978 consists
of a unique input structure that allows ac coupling of the input
signals. The typical input resistance is approximately 14 kΩ
from each input to AGND.
The high-pass filter has a 1.4 Hz, 6 dB per octave cutoff at a
48 kHz sample rate. The cutoff frequency scales directly with
the sample frequency. However, care is required in dc-coupled
applications to ensure that the common-mode dc voltage does
not exceed the specified limit. The input required for the fullscale ADC output (0 dBFS) is typically 2 V rms differential.
Rev. 0 | Page 14 of 44
AINxP
VREF
AINxN
R
R
VID = V INPUT DIFFERENTIAL
VICM+ = VCM AT AINxP
VICM– = VCM AT AINxN
Figure 16. Analog Input Block
11292-015
The ADAU1978 has four differential analog inputs. The ADCs
can accommodate both dc- and ac-coupled input signals.
R
Data Sheet
ADAU1978
Line Inputs
The C1 and C2 values can be found for the required low
frequency cutoff using the following equation:
This section describes some of the possible ways to connect the
line level inputs of the ADAU1978.
C1 or C2 = 1/(2 × π × fC × Input Resistance)
Line Input Balanced or Differential Input DC-Coupled Case
where the Input Resistance of the ADAU1978 is 14.3 kΩ typical.
For example, for an input signal of 2 V rms differential with
approximately 1.5 V common-mode dc, the signal at each input
pin has a 1 V rms or 2.8 V p-p signal swing. With common-mode
dc of 1.5 V, the signal can swing between (1.5 V + 1.414 V) =
2.914 V to (1.5 V − 1.414 V) = 0.086 V at each input. Therefore,
this is approximately 5.6 V p-p differential across AINxP and
AINxN and measures close to 0 dBFS (ac only with a dc highpass filter) at the ADC output (see Figure 17).
Refer to Figure 18 for information about connecting the line
level inputs to the ADAU1978.
Line Input Unbalanced or Single-Ended, Pseudo Differential
AC-Coupled Case
For a single-ended application, reduce the signal swing by half
because only one input is used for the signal with the other connected to 0 V. Doing this reduces the input signal capability to
1 V rms in the single-ended application and measures approximately −6.16 dBFS (ac only with a dc high-pass filter) at the
ADC output.
Line Input Balanced or Differential Input AC-Coupled Case
For connecting the ADAU1978 to a head unit amplifier output,
ac coupling is recommended. In this case, the AINxP/AINxN
pins are at a common-mode level of 1.5 V. The attenuator can
be used to reduce the input level if it is more than 2 V rms.
See Figure 19 for additional information. The value of the C1/C2 is
similar to the balanced ac-coupled case previously mentioned in
the Line Input Balanced or Differential Input AC-Coupled Case
section.
TYPICAL AUDIO POWER
AMPLIFIER OUTPUT
AINxP
VDIFF = 2V rms AC
VCM = 1.5V DC
11292-016
AINxN
OPTION A: DIFFERENTIAL DC-COUPLED
Figure 17. Connecting the Line Level Inputs—Differential DC-Coupled Case
TYPICAL AUDIO POWER
AMPLIFIER OUTPUT
C1
AINxP
ATTENUATOR
AINxN
VDIFF = 2V rms
OPTION B: DIFFERENTIAL AC-COUPLED
Figure 18. Connecting the Line Level Inputs—Differential AC-Coupled Case
TYPICAL AUDIO POWER
AMPLIFIER OUTPUT
C2
AINxP
AINxN
VIN = 1V rms AC
OPTION C: PSEUDO DIFFERENTIAL AC-COUPLED
Figure 19. Connecting the Line Level Inputs—Pseudo Differential AC-Coupled Case
Rev. 0 | Page 15 of 44
11292-018
C1
11292-017
C2
ADAU1978
Data Sheet
ADC
TYPICAL STEREO
OUTPUT
The ADAU1978 contains four sigma-delta (Σ-Δ) ADC channels
configured as two stereo pairs with configurable differential/
single-ended inputs. The ADC can operate at a nominal sample
rate of 32 kHz up to 192 kHz. The ADCs include on-board
digital antialiasing filters with 79 dB stop-band attenuation and
linear phase response. Digital outputs are supplied through two
serial data output pins (one for each stereo pair) and a common
frame clock (LRCLK) and bit clock (BCLK). Alternatively, one
of the TDM modes can be used to support up to 16 channels on
a single TDM data line.
C1
ADC SUMMING MODES
The four ADCs can be grouped into either a single stereo ADC
or a single mono ADC to increase the SNR for the application.
Two options are available: one option for summing two channels
of the ADC and another option for summing all four channels
of the ADC. Summing is performed in the digital block.
2-Channel Summing Mode
AIN1P
AIN1N
C2
Σ
AIN2P
AIN2N
C3
AIN3P
AIN3N
With smaller amplitude input signals, a 10-bit programmable
digital gain compensation for an individual channel is provided
to scale up the output word to full scale. Take care to avoid
overcompensation (large gain compensation), which leads to
clipping and THD degradation in the ADC.
C4
Σ
AIN4P
AIN4N
11292-019
The ADCs also have a dc offset calibration algorithm to null the
systematic dc offset of the ADC. This feature is useful for dc
measurement applications.
OPTION B: DIFFERENTIAL AC-COUPLED
VDIFF = 2V rms
Figure 20. 2-Channel Summing Mode Connection Diagram
4-Channel Summing Mode
When the SUM_MODE Bits (Bits[7:6] of Register 0x0E) are set
to 10, the Channel 1 through Channel 4 ADC data are combined
and output from the SDATAOUT1 pin. As a result, the SNR
improves by 6 dB. For this mode, all four channels must be
connected to the same input signal source.
TYPICAL STEREO
OUTPUT
When the SUM_MODE bits (Bits[7:6] of Register 0x0E) are set
to 01, the Channel 1 and Channel 2 ADC data are combined
and output from the SDATAOUT1 pin. Similarly, the Channel 3
and Channel 4 ADC data are combined and output from the
SDATAOUT2 pin. As a result, the SNR improves by 3 dB. For this
mode, both Channel 1 and Channel 2 must be connected to the
same input signal source. Similarly, Channel 3 and Channel 4
must be connected to the same input signal source.
OPTION B: DIFFERENTIAL AC-COUPLED
VDIFF = 2V rms
C1
AIN1P
AIN1N
C2
AIN2P
AIN2N
Σ
AIN3P
AIN3N
AIN4P
11292-020
AIN4N
Figure 21. 4-Channel Summing Mode Connection Diagram
Rev. 0 | Page 16 of 44
Data Sheet
ADAU1978
Stereo Mode
SERIAL AUDIO DATA OUTPUT PORTS, DATA
FORMAT
The serial audio port comprises four pins: BCLK, LRCLK,
SDATAOUT1, and SDATAOUT2. The ADAU1978 ADC outputs
are available on the SDATAOUT1 and SDATAOUT2 pins in
serial format. The BCLK and LRCLK pins serve as the bit clock
and frame clock, respectively. The port can be operated as master
or slave and can be set either in stereo mode (2-channel mode)
or in TDM multichannel mode. The supported popular audio
formats are I2S, left justified (LJ), and right justified (RJ).
In 2-channel or stereo mode, the SDATAOUT1 outputs ADC
data for Channel 1 and Channel 2, and the SDATOUT2 outputs
ADC data for Channel 3 and Channel 4. Figure 22 through
Figure 24 show the supported audio formats.
BCLK
LRCLK
SDATAOUT1
(I2S MODE)
CHANNEL 1
CHANNEL 2
8 TO 32 BCLKs
8 TO 32 BCLKs
CHANNEL 3
CHANNEL 4
11292-024
SDATAOUT2
(I2S MODE)
NOTES
1. SAI = 0.
2. SDATA_FMT = 00 (I2S).
Figure 22. I2S Audio Format
BCLK
LRCLK
SDATAOUT2
(LJ MODE)
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
11292-025
SDATAOUT1
(LJ MODE)
NOTES
1. SDATA_FMT = 01 (LJ).
Figure 23. Left Justified Audio Format
BCLK
LRCLK
CHANNEL 1
SDATAOUT2
(RJ MODE)
CHANNEL 3
CHANNEL 2
CHANNEL 4
11292-026
SDATAOUT1
(RJ MODE)
NOTES
1. SDATA_FMT = 10 (RJ, 24-BIT).
Figure 24. Right Justified Audio Format
Rev. 0 | Page 17 of 44
ADAU1978
Data Sheet
TDM Mode
(Figure 27 shows the TDM mode slot assignments). During the
unused slots, the output pin becomes high-Z so that the same
data line can be shared with other devices on the TDM bus.
Register 0x05 through Register 0x08 provide programmability
for the TDM mode. The TDM slot width, data width, and
channel assignment, as well as the pin used to output the data,
are programmable.
The TDM port can be operated as either a master or a slave.
In master mode, the BCLK and LRCLK are output from the
ADAU1978, whereas in slave mode, the BCLK and LRCLK pins
are set to receive the clock from the master in the system.
By default, serial data is output on the SDATAOUT1 pin;
however, the SDATA_SEL bit (Bit 7 of Register 0x06) can be
used to change the setting so that serial data is output from the
SDATAOUT2 pin.
Both the nonpulse and pulse modes are supported. In nonpulse
mode, the LRCLK signal is typically 50% of the duty cycle, whereas
in pulse mode, the LRCLK signal must be at least one BCLK wide
(see Figure 25 and Figure 26).
The TDM mode supports two, four, eight, or 16 channels. The
ADAU1978 outputs four channels of data in the assigned slots
BCLK
32/24/16 BCLKs
32/24/16 BCLKs
32/24/16 BCLKs
LRCLK
CHANNEL 1
SDATA I 2S
CHANNEL 2
8 TO 32 BCLKs
SDATA LJ
8 TO 32 BCLKs
CHANNEL 2
CHANNEL 1
8 TO 32 BCLKs
8 TO 32 BCLKs
CHANNEL N
8 TO 32 BCLKs
CHANNEL 1
SDATA I 2S
CHANNEL N
8 TO 32 BCLKs
CHANNEL 2
24 OR 16 BCLKs
CHANNEL N
24 OR 16 BCLKs
24 OR 16 BCLKs
11292-027
NOTES
1. SAI = 001 (2 CHANNELS), 010 (4 CHANNELS), 011 (8 CHANNELS), 100 (16 CHANNELS).
2. SDATA_FMT = 00 (I2S), 01 (LJ), 10 (RJ, 24-BIT), 11 (RJ, 16-BIT).
3. BCLKEDGE = 0.
4. LR_MODE = 0.
5. SLOT_WIDTH = 00 (32 BCLKs), 01 (24 BCLKs), 10 (16 BCLKs).
Figure 25. TDM Nonpulse Mode Audio Format
BCLK
32/24/16 BCLKs
32/24/16 BCLKs
32/24/16 BCLKs
LRCLK
CHANNEL 1
SDATA I 2S
SDATA LJ
8 TO 32 BCLKs
SDATA I 2S
8 TO 32 BCLKs
CHANNEL 2
CHANNEL 1
CHANNEL N
CHANNEL 2
8 TO 32 BCLKs
CHANNEL N
8 TO 32 BCLKs
CHANNEL 1
8 TO 32 BCLKs
CHANNEL 2
24 OR 16 BCLKs
8 TO 32 BCLKs
24 OR 16 BCLKs
24 OR 16 BCLKs
11292-028
NOTES
1. SAI = 001 (2 CHANNELS), 010 (4 CHANNELS), 011 (8 CHANNELS), 100 (16 CHANNELS)
2. SDATA_FMT = 00 (I2S), 01 (LJ), 10 (RJ, 24-BIT), 11 (RJ, 16-BIT)
3. BCLKEDGE = 0
4. LR_MODE = 1
5. SLOT_WIDTH = 00 (32 BCLKs), 01 (24 BCLKs), 10 (16 BCLKs)
CHANNEL N
Figure 26. TDM Pulse Mode Audio Format
Rev. 0 | Page 18 of 44
Data Sheet
ADAU1978
LRCLK
NUMBER OF BCLK CYCLES = (NUMBER OF BCLKs/SLOT) × NUMBER OF SLOTS
BCLK
SDATAOUTx—TDM2
SLOT1
SDATAOUTx—TDM4
SLOT1
SLOT2
SLOT1
SLOT1
HIGH-Z
SLOT2
DATA WIDTH
16/24 BITS
SLOT2
SLOT3
SLOT4
SLOT3
SLOT3
SLOT5
SLOT4
SLOT6
SLOT7
SLOT5
SLOT8
SLOT9
SLOT10
SLOT4
SLOT6
SLOT11
SLOT12
SLOT7
SLOT13
SLOT8
SLOT14
SLOT15
SLOT16
HIGH-Z
11292-029
SDATAOUTx—TDM8
SDATAOUTx—TDM16
SLOT2
SLOT WIDTH
16/24/32 BITS
Figure 27. TDM Mode Slot Assignment
Table 10. Bit Clock Frequency TDM Mode
Mode
TDM2
TDM4
TDM8
TDM16
BCLK Frequency
24-Bit Clocks Per Slot
48 × fS
96 × fS
192 × fS
384 × fS
16-Bit Clocks Per Slot
32 × fS
64 × fS
128 × fS
256 × fS
The bit clock frequency depends on the sample rate, the slot
width, and the number of bit clocks per slot. Table 10 can be
used to calculate the BCLK frequency.
The sample rate (fS) can range from 8 kHz up to 192 kHz.
However, in master mode, the maximum bit clock frequency
(BCLK) is 24.576 MHz. For example, for a sample rate of
192 kHz, 128 × fS is the maximum possible BCLK frequency.
Therefore, only 128-bit clock cycles are available per TDM
32-Bit Clocks Per Slot
64 × fS
128 × fS
256 × fS
512 × fS
frame. There are two options in this case: either operate with a
32-bit data width in TDM4 or operate with a 16-bit data width
in TDM8. In slave mode, this limitation does not exist because
the bit clock and frame clock are fed to the ADAU1978. Various
combinations of BCLK frequencies and modes are available, but
take care to choose the combination that is most suitable for the
application.
Rev. 0 | Page 19 of 44
ADAU1978
Data Sheet
Connection Options
Figure 28 through Figure 32 show the available options for
connecting the serial audio port in I2S or TDM mode. In
TDM mode, it is recommended to include the pull-down
resistor on the data signal to prevent the line from floating
when the SDATAOUTx pin of the ADAU1978 becomes high-Z
during an inactive period. The resistor value should be such
that no more than 2 mA is drawn from the SDATAOUTx pin.
Although the resistor value is typically in the 10 kΩ to 47 kΩ
range, the appropriate resistor value depends on the devices
on the data bus.
SLAVE
ADAU1978
DSP
SLAVE
DSP
BCLK
LRCLK
SDATAOUTx
MASTER
ADAU1978
OR
SIMILIAR ADC
BCLK
LRCLK
SDATAOUTx
BCLK
11292-034
MASTER
SLAVE
ADAU1978
Figure 31. Serial Port Connection Option 4—TDM Mode, Second ADC Master
LRCLK
11292-030
SDATAOUT1
Figure 28. Serial Port Connection Option 1—I2S/Left Justified/Right Justified
Modes, ADAU1978 Master
SLAVE
MASTER
ADAU1978
DSP
SLAVE
MASTER
ADAU1978
DSP
BCLK
LRCLK
SDATAOUTx
SLAVE
ADAU1978
SDATAOUT1
OR
SIMILIAR ADC
11292-033
BCLK
LRCLK
SDATAOUT2
BCLK
LRCLK
Figure 29. Serial Port Connection Option 2—I2S/Left Justified/Right Justified
Modes, ADAU1978 Slave
MASTER
SLAVE
ADAU1978
DSP
SDATAOUTx
Figure 32. Serial Port Connection Option 5—TDM Mode, DSP Master
BCLK
LRCLK
SDATAOUTx
SLAVE
ADAU1978
OR
SIMILIAR ADC
BCLK
11292-031
LRCLK
SDATAOUTx
11292-032
SDATAOUT2
Figure 30. Serial Port Connection Option 3—TDM Mode, ADAU1978 Master
Rev. 0 | Page 20 of 44
Data Sheet
ADAU1978
CONTROL PORTS
The ADAU1978 control port allows two modes of operation,
either 2-wire I2C mode or 4-wire SPI mode, that are used for
setting the internal registers of the part. Both the I2C and SPI
modes allow read and write capability of the registers. All the
registers are eight bits wide. The registers start at Address 0x00
and end at Address 0x1A.
The control port in both I2C and SPI modes is slave only and,
therefore, requires the master in the system to operate. The
registers can be accessed with or without the master clock to
the part. However, to operate the PLL, serial audio ports, and
boost converter, the master clock is necessary.
By default, the ADAU1978 operates in I2C mode, but the part can
be put into SPI mode by pulling the CLATCH pin low three times.
The control port pins are multifunctional, depending on the
mode in which the part is operating. Table 11 describes the
control port pin functions in both modes.
Table 11. Control Port Pin Functions
I2C Mode
Pin No.
17
18
19
20
Mnemonic
SDA/COUT
SCL/CCLK
ADDR0/CLATCH
ADDR1/CIN
Pin Function
SDA data
SCL clock
I2C Device Address Bit 0
I2C Device Address Bit 1
Rev. 0 | Page 21 of 44
Pin Type
I/O
I
I
I
SPI Mode
Pin Function
COUT output data
CCLK input clock
CLATCH input
CIN input data
Pin Type
O
I
I
I
ADAU1978
Data Sheet
I2C MODE
The ADAU1978 supports a 2-wire serial (I2C-compatible) bus
protocol. Two pins, serial data (SDA) and serial clock (SCL), are
used to communicate with the system I2C master controller. In
I2C mode, the ADAU1978 is always a slave on the bus, meaning
that it cannot initiate a data transfer. Each slave device on the
I2C bus is recognized by a unique device address. The device
address and R/W byte for the ADAU1978 are shown in Table 12.
The address resides in the first seven bits of the I2C write. Bit 7
and Bit 6 of the I2C address for the ADAU1978 are set by the
levels on the ADDR1 and ADDR0 pins. The LSB of the first I2C
byte (the R/W bit) from the master identifies whether it is a read
or write operation. Logic Level 1 in the LSB (Bit 0) corresponds
to a read operation, and Logic Level 0 corresponds to a write
operation.
Table 12. I2C First Byte Format
Bit 7
ADDR1
Bit 6
ADDR0
Bit 5
1
Bit 4
0
The SDA pin can sink 2 mA of current; therefore, the minimum
value of RPULL UP for an IOVDD of 3.3 V is 1.5 kΩ.
Depending on the capacitance of the board, the speed of the bus
can be restricted to meet the rise time and fall time specifications.
For fast mode with a bit rate time of around 1 Mbps, the rise
time must be less than 550 ns. Use the following equation to
determine whether the rise time specification can be met:
t = 0.8473 × RPULL UP × CBOARD
where CBOARD must be less than 236 pF to meet the 300 ns rise
time requirement.
For the SCL pin, the calculations depend on the current sink
capability of the I2C master used in the system.
Addressing
Bit 3
0
Bit 2
0
Bit 1
1
Bit 0
R/W
The first seven bits of the I2C chip address for the ADAU1978
are xx10001. Bit 7 and Bit 6 of the address byte can be set using
the ADDR1 and ADDR0 pins to set the chip address to the
desired value.
The 7-bit I2C device address can be set to one of four of the
following possible options using the ADDR1 and ADDR0 pins:
•
•
•
•
per the I2C specifications).
ISINK is the current sink capability of the I/O pin.
I2C Device Address 0010001 (0x11)
I2C Device Address 0110001 (0x31)
I2C Device Address 1010001 (0x51)
I2C Device Address 1110001 (0x71)
In I2C mode, both the SDA and SCL pins require that an
appropriate pull-up resistor be connected to IOVDD. Ensure
that the voltage on these signal lines does not exceed the voltage
on the IOVDD pin. Figure 44 shows a typical connection
diagram for the I2C mode.
The value of the pull-up resistor for the SDA or SCL pin can be
calculated as follows.
Minimum RPULL UP = (IOVDD − VIL)/ISINK
where:
IOVDD is the I/O supply voltage, typically ranging from 1.8 V
up to 3.3 V.
VIL is the maximum voltage at Logic Level 0 (that is, 0.4 V, as
Initially, each device on the I2C bus is in an idle state and monitors
the SDA and SCL lines for a start condition and the proper address.
The I2C master initiates a data transfer by establishing a start
condition, defined by a high-to-low transition on SDA while
SCL remains high. This indicates that an address/data stream
follows. All devices on the bus respond to the start condition
and acquire the next eight bits from the master (the 7-bit address
plus the R/W bit) MSB first. The master sends the 7-bit device
address with the R/W bit to all the slaves on the bus. The device
with the matching address responds by pulling the data line
(SDA) low during the ninth clock pulse. This ninth bit is known
as an acknowledge bit. All other devices withdraw from the bus
at this point and return to the idle condition.
The R/W bit determines the direction of the data. A Logic 0 on the
LSB of the first byte means that the master is to write information
to the slave, whereas a Logic 1 means that the master is to read
information from the slave after writing the address and repeating
the start address. A data transfer takes place until a master initiates
a stop condition. A stop condition occurs when SDA transitions
from low to high while SCL is held high.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence
during normal read and write operations, the ADAU1978
immediately jumps to the idle condition.
Figure 33 and Figure 34 use the following abbreviations:
ACK = acknowledge
No ACK = no acknowledge
Rev. 0 | Page 22 of 44
Data Sheet
0
1
ADAU1978
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
SCL
0
0
0
SECOND BYTE (REGISTER ADDRESS)
1
THIRD BYTE (DATA)
R/W
ACK
ADAU1978
START
STOP
ACK
ADAU1978
Figure 33. I2C Write to ADAU1978, Single Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SCL
FIRST BYTE (DEVICE ADDRESS)
ADDR1 ADDR0
SDA
1
0
0
0
SECOND BYTE (REGISTER ADDRESS)
1
R/W
ACK
ADAU1978
START
19
20
21
22
23
24
25
26
27
28
ACK
ADAU1978
29
30
31
32
33
34
35
36
37
38
SCL
THIRD BYTE (DEVICE ADDRESS)
SDA
ADDR1 ADDR0
REPEAT START
1
0
0
0
1
DATA BYTE FROM ADAU1978
R/W
NO ACK
ACK
ADAU1978
Figure 34. I2C Read from ADAU1978, Single Byte
Rev. 0 | Page 23 of 44
STOP
11292-036
SDA
1
11292-035
FIRST BYTE (DEVICE ADDRESS)
ADDR1 ADDR0
ADAU1978
Data Sheet
I2C Read and Write Operations
followed by the chip address byte with the R/W bit set to 1
(read). This causes the ADAU1978 SDA to reverse and begin
driving data back to the master. The master then responds every
ninth pulse with an acknowledge pulse to the ADAU1978.
Figure 35 shows the format of a single-word I2C write
operation. Every ninth clock pulse, the ADAU1978 issues an
acknowledge by pulling SDA low.
Figure 38 shows the format of a burst mode read sequence. This
figure shows an example of a read from sequential single-byte
registers. The ADAU1978 increments its address registers after
every byte because the ADAU1978 uses an 8-bit register address.
Figure 36 shows the format of a burst mode write sequence. This
figure shows an example of a write to sequential single-byte
registers. The ADAU1978 increments its address register after
every byte because the requested address corresponds to a
register or memory area with a 1-byte word length.
Figure 35 to Figure 38 use the following abbreviations:
S = start bit
P = stop bit
AM = acknowledge by master
AS = acknowledge by slave
S
CHIP ADDRESS,
R/W = 0
AS
REGISTER ADDRESS
8 BITS
AS
DATA BYTE
P
11292-037
Figure 37 shows the format of a single-word I C read operation.
Note that the first R/W bit is 0, indicating a write operation.
This is because the address still needs to be written to set up the
internal address. After the ADAU1978 acknowledges the receipt
of the address, the master must issue a repeated start command
2
CHIP
ADDRESS,
R/W = 0
CHIP
AS REGISTER
ADDRESS ADDRESS,
R/W = 0
8 BITS
AS
DATA AS
BYTE 1
DATA AS DATA
BYTE 2
BYTE 3
AS
AS
DATA
BYTE 4
...
S
CHIP
ADDRESS,
R/W = 0
AS
REGISTER
ADDRESS
8 BITS
AS
S
AS
CHIP
ADDRESS,
R/W = 1
DATA
BYTE 1
P
AM
...
11292-039
Figure 36. Burst Mode I2C Write Format
Figure 37. Single-Word I2C Read Format
S
CHIP
ADDRESS,
R/W = 0
AS
REGISTER
ADDRESS
8 BITS
AS
S
CHIP
ADDRESS,
R/W = 1
AS
DATA
BYTE 1
Figure 38. Burst Mode I2C Read Format
Rev. 0 | Page 24 of 44
AM
DATA
BYTE 2
P
11292-040
S
P
11292-038
Figure 35. Single-Word I2C Write Format
Data Sheet
ADAU1978
SPI MODE
Register Address
By default, the ADAU1978 is in I2C mode. To invoke SPI control
mode, pull CLATCH low three times. This can be done by performing three dummy writes to the SPI port (the ADAU1978 does not
acknowledge these three writes, see Figure 39). Beginning with the
fourth SPI write, data can be written to or read from the device.
The ADAU1978 can be taken out of SPI mode only by a full
reset initiated by power cycling the device.
The 8-bit address word is decoded to a location in one of the
registers. This address is the location of the appropriate register.
The SPI port uses a 4-wire interface, consisting of the CLATCH,
CCLK, CIN, and COUT signals, and it is always a slave port.
The CLATCH signal goes low at the beginning of a transaction
and high at the end of a transaction. The CCLK signal latches
COUT on a low-to-high transition. COUT data is shifted out of
the ADAU1978 on the falling edge of CCLK and is clocked into
a receiving device, such as a microcontroller, on the CCLK
rising edge. The CIN signal carries the serial input data, and the
COUT signal carries the serial output data. The COUT signal
remains tristated until a read operation is requested. This allows
direct connection to other SPI-compatible peripheral COUT ports
for sharing the same system controller port. All SPI transactions
have the same basic generic control word format, as shown in
Table 15. A timing diagram is shown in Figure 3. Write all data
MSB first.
Data Bytes
The number of data bytes varies according to the register being
accessed. During a burst mode write, an initial register address is
written followed by a continuous sequence of data for consecutive
register locations.
A sample timing diagram for a single-word SPI write operation
to a register is shown in Figure 40. A sample timing diagram of
a single-word SPI read operation is shown in Figure 41. The
COUT pin goes from being high-Z to being driven at the
beginning of Byte 3. In this example, Byte 0 to Byte 1 contain
the device address, the R/W bit, and the register address to be
read. Subsequent bytes carry the data from the device.
Standalone Mode
The ADAU1978 can also operate in standalone mode. However,
in standalone mode, the boost converter, microphone bias, and
diagnostics blocks are powered down. To set the part in standalone
mode, pull the SA_MODE pin to IOVDD. In this mode, some
pins change functionality to provide more flexibility (see Table 14
for more information).
Chip Address R/W
Table 14. Pin Functionality in Standalone Mode
The LSB of the first byte of an SPI transaction is a R/W bit. This bit
determines whether the communication is a read (Logic Level 1)
or a write (Logic Level 0). This format is shown in Table 13.
Pin Function1
ADDR0
Setting
0
1
Table 13. SPI Address and R/W Byte Format
ADDR1
0
1
0
1
0
1
0
1
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
R/W
SDA
SCL
SDATAOUT2
1
Description
I2S SAI format
TDM modes, determined by the
SDATAOUT2 pin
Master mode SAI
Slave mode SAI
MCLK = 256 × fS, PLL on
MCLK = 384 × fS, PLL on
48 kHz sample rate
96 kHz sample rate
TDM4—LRCLK pulse
TDM8—LRCLK pulse
Pin functionality, not full pin names, is listed. See Table 11 for additional
information.
Table 15. Generic Control Word Format
Byte 0
Device Address[6:0], R/W
1
Byte 1
Register Address[7:0]
Byte 2
Data[7:0]
Continues to end of data.
Rev. 0 | Page 25 of 44
Byte 3 1
Data[7:0]
ADAU1978
0
1
Data Sheet
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
16
17
18
19
20
21
22
23
24
25
27
CLATCH
11292-041
CCLK
CIN
Figure 39. SPI Mode Initial Sequence
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
CLATCH
DEVICE ADDRESS (7 BITS)
R/W
REGISTER ADDRESS BYTE
CIN
11292-042
CCLK
DATA BYTE
Figure 40. SPI Write to ADAU1978 Clocking (Single-Word Write Mode)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CCLK
CLATCH
REGISTER ADDRESS BYTE
DATA BYTE
R/W
DATA BYTE FROM ADAU1978
COUT
11292-043
DEVICE ADDRESS (7 BITS)
CIN
Figure 41. SPI Read from ADAU1978 Clocking (Single-Word Read Mode)
CLATCH
CCLK
DEVICE
ADDRESS
BYTE
REGISTER
ADDRESS
BYTE
DATA BYTE1
DATA BYTE2
DATA BYTE n – 1
DATA BYTE n
DATA BYTE n – 1
DATA BYTE n
11292-044
CIN
Figure 42. SPI Write to ADAU1978 (Multiple Bytes)
CLATCH
CCLK
CIN
REGISTER
ADDRESS
BYTE
COUT
DATA BYTE1
DATA BYTE2
DATA BYTE3
Figure 43. SPI Read from ADAU1978 (Multiple Bytes)
Rev. 0 | Page 26 of 44
11292-045
DEVICE
ADDRESS
BYTE
Data Sheet
ADAU1978
REGISTER SUMMARY
Table 16. REGMAP_ADAU1978 Register Summary
Reg
Name
0x00 M_POWER
0x01 PLL_CONTROL
Bits Bit 7
Bit 6
[7:0] S_RST
[7:0] PLL_LOCK
PLL_MUTE
0x02 RESERVED
[7:0]
0x03 RESERVED
[7:0]
0x04 BLOCK_POWER_SAI [7:0] LR_POL
BCLKEDGE
Bit 5
Bit 4
RESERVED
RESERVED
CLK_S
RESERVED
LDO_EN
RESERVED
RESERVED
VREF_EN
ADC_EN4
SDATA_FMT
Bit 3
0x05 SAI_CTRL0
[7:0]
0x06 SAI_CTRL1
[7:0] SDATA_SEL
0x07
0x08
0x09
0x0A
0x0B
0x0C
SAI_CMAP12
SAI_CMAP34
SAI_OVERTEMP
POSTADC_GAIN1
POSTADC_GAIN2
POSTADC_GAIN3
[7:0]
CMAP_C2
[7:0]
CMAP_C4
[7:0] SAI_DRV_C4 SAI_DRV_C3
SAI_DRV_C2 SAI_DRV_C1 DRV_HIZ
[7:0]
PADC_GAIN1
[7:0]
PADC_GAIN2
[7:0]
PADC_GAIN3
0x0D
0x0E
0x0F
0x10
POSTADC_GAIN4
MISC_CONTROL
RESERVED
RESERVED
[7:0]
[7:0]
[7:0]
[7:0]
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
ASDC_CLIP
DC_HPF_CAL
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Bit 0
Reset
RW
PWUP
0x00
0x41
RW
RW
ADC_EN3
ADC_EN2
ADC_EN1
FS
DATA_WIDTH LR_MODE
SAI_MSB
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
ADC_CLIP4
ADC_CLIP3
DC_HPF_C4
DC_HPF_C3
Rev. 0 | Page 27 of 44
Reserved Reserved
Reserved Reserved
0x3F
RW
0x02
RW
0x00
RW
0x10
0x32
0xF0
0xA0
0xA0
0xA0
RW
RW
RW
RW
RW
RW
DC_CAL
RESERVED
RESERVED RESERVED
0xA0
0x02
0xFF
0x0F
RW
RW
RW
RW
RESERVED RESERVED
RESERVED RESERVED
RESERVED RESERVED
RESERVED RESERVED
RESERVED RESERVED
RESERVED RESERVED
RESERVED
RESERVED RESERVED
ADC_CLIP2 ADC_CLIP1
DC_HPF_C2 DC_HPF_C1
0x00
0x00
0x00
0x00
0x20
0x00
Reserved
Reserved
0x00
0x00
RW
RW
RW
RW
RW
RW
Reserved
Reserved
RW
RW
BCLKRATE
CMAP_C1
CMAP_C3
RESERVED RESERVED
PADC_GAIN4
RESERVED
MMUTE
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
DC_SUB_C4 DC_SUB_C3
DC_SUB_C2 DC_SUB_C1
Bit 1
MCS
SAI
SLOT_WIDTH
SUM_MODE
RESERVED
Bit 2
SAI_MS
OT
ADAU1978
Data Sheet
REGISTER DETAILS
MASTER POWER AND SOFT RESET REGISTER
Address: 0x00, Reset: 0x00, Name: M_POWER
The power management control register is used for enabling the boost regulator, microphone bias, PLL, band gap reference, ADC, and
LDO regulator.
Table 17. Bit Descriptions for M_POWER
Bits
7
Bit Name
S_RST
Settings
0
1
[6:1]
0
RESERVED
PWUP
0
1
Description
Software Reset. The software reset resets all internal circuitry and all control registers to
their respective default states. It is not necessary to reset the ADAU1978 during a powerup or power-down cycle.
Normal Operation.
Software Reset.
Reserved.
Master Power-Up Control. The master power-up control fully powers up or powers down
the ADAU1978. This must be set to 1 to power up the ADAU1978. Individual blocks can
be powered down via their respective power control registers.
Full Power-Down.
Master Power-Up.
Rev. 0 | Page 28 of 44
Reset
0x0
Access
RW
0x00
0x0
RW
RW
Data Sheet
ADAU1978
PLL CONTROL REGISTER
Address: 0x01, Reset: 0x41, Name: PLL_CONTROL
Table 18. Bit Descriptions for PLL_CONTROL
Bits
7
Bit Name
PLL_LOCK
Settings
0
1
6
PLL_MUTE
0
1
5
4
RESERVED
CLK_S
0
1
3
[2:0]
RESERVED
MCS
001
010
011
100
000
101
110
111
Description
PLL Lock Status. PLL lock status bit. When set to 1, the PLL is locked.
PLL Not Locked.
PLL Locked.
PLL Unlock Automute. When set to 1, it mutes the ADC output if PLL becomes unlocked.
No Automatic Mute on PLL Unlock.
Automatic Mute with PLL Unlock.
Reserved.
PLL Clock Source Select. Selecting input clock source for PLL.
MCLK Used for PLL Input.
LRCLK Used for PLL Input; Only Supported for Sample Rates in the range of 32 kHz to 192 kHz.
Reserved.
Master Clock Select. MCS bits determine the frequency multiplication ratio of the PLL. It
must be set based on the input MCLK frequency and sample rate.
256 × fS MCLK for 32 kHz up to 48 kHz (see the PLL and Clock section for other sample rates).
384 × fS MCLK for 32 kHz up to 48 kHz (see the PLL and Clock section for other sample rates).
512 × fS MCLK for 32 kHz up to 48 kHz (see the PLL and Clock section for other sample rates).
768 × fS MCLK for 32 kHz up to 48 kHz (see the PLL and Clock section for other sample rates).
128 × fS MCLK for 32 kHz up to 48 kHz (see the PLL and Clock section for other sample rates).
Reserved.
Reserved.
Reserved.
Rev. 0 | Page 29 of 44
Reset
0x0
Access
R
0x1
RW
0x0
0x0
RW
RW
0x0
0x1
RW
RW
ADAU1978
Data Sheet
BLOCK POWER CONTROL AND SERIAL PORT CONTROL REGISTER
Address: 0x04, Reset: 0x3F, Name: BLOCK_POWER_SAI
Table 19. Bit Descriptions for BLOCK_POWER_SAI
Bits
7
Bit Name
LR_POL
Settings
0
1
6
BCLKEDGE
0
1
5
LDO_EN
0
1
4
VREF_EN
0
1
3
ADC_EN4
0
1
2
ADC_EN3
0
1
1
ADC_EN2
0
1
0
ADC_EN1
0
1
Description
Sets LRCLK Polarity
LRCLK Low then High
LRCLK High then Low
Sets the Bit Clock Edge on Which Data Changes
Data Changes on Falling Edge
Data Changes on Rising Edge
LDO Regulator Enable
LDO Powered Down
LDO Enabled
Voltage Reference Enable
Voltage Reference Powered Down
Voltage Reference Enabled
ADC Channel 4 Enable
ADC Channel Powered Down
ADC Channel Enabled
ADC Channel 3 Enable
ADC Channel Powered Down
ADC Channel Enabled
ADC Channel 2 Enable
ADC Channel Powered Down
ADC Channel Enabled
ADC Channel 1 Enable
ADC Channel Powered Down
ADC Channel Enabled
Rev. 0 | Page 30 of 44
Reset
0x0
Access
RW
0x0
RW
0x1
RW
0x1
RW
0x1
RW
0x1
RW
0x1
RW
0x1
RW
Data Sheet
ADAU1978
SERIAL PORT CONTROL REGISTER 1
Address: 0x05, Reset: 0x02, Name: SAI_CTRL0
Table 20. Bit Descriptions for SAI_CTRL0
Bits
[7:6]
Bit Name
SDATA_FMT
Settings
00
01
10
11
[5:3]
SAI
000
001
010
011
100
[2:0]
FS
000
001
010
011
100
Description
Serial Data Format
I2S Data Delayed from Edge of LRCLK by 1 BCLK
Left Justified
Right Justified, 24-Bit Data
Right Justified, 16-Bit Data
Serial Port Mode
Stereo (I2S, LJ, RJ)
TDM2
TDM4
TDM8
TDM16
Sampling Rate
8 kHz to 12 kHz
16 kHz to 24 kHz
32 kHz to 48 kHz
64 kHz to 96 kHz
128 kHz to 192 kHz
Rev. 0 | Page 31 of 44
Reset
0x0
Access
RW
0x0
RW
0x2
RW
ADAU1978
Data Sheet
SERIAL PORT CONTROL REGISTER 2
Address: 0x06, Reset: 0x00, Name: SAI_CTRL1
Table 21. Bit Descriptions for SAI_CTRL1
Bits
7
Bit Name
SDATA_SEL
Settings
0
1
[6:5]
SLOT_WIDTH
00
01
10
11
4
DATA_WIDTH
0
1
3
LR_MODE
0
1
2
SAI_MSB
0
1
1
BCLKRATE
0
1
0
SAI_MS
0
1
Description
SDATAOUTx Pin Selection in TDM4 or Greater Modes
SDATAOUT1 used for output
SDATAOUT2 used for output
Number of BCLKs per Slot in TDM Mode
32 BCLKs per TDM slot
24 BCLKs per TDM slot
16 BCLKs per TDM slot
Reserved
Output Data Bit Width
24-bit data
16-bit data
Sets LRCLK Mode
50% duty cycle clock
Pulse—LRCLK is a single BCLK cycle wide pulse
Sets Data to be Input/Output Either MSB or LSB First
MSB first data
LSB first data
Sets the Number of Bit Clock Cycles per Data Channel Generated When in
Master Mode
32 BCLKs/channel
16 BCLKs/channel
Sets the Serial Port into Master or Slave Mode
LRCLK/BCLK slave
LRCLK/BCLK master
Rev. 0 | Page 32 of 44
Reset
0x0
Access
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
Data Sheet
ADAU1978
CHANNEL 1 AND CHANNEL 2 MAPPING FOR OUTPUT SERIAL PORTS REGISTER
Address: 0x07, Reset: 0x10, Name: SAI_CMAP12
Table 22. Bit Descriptions for SAI_CMAP12
Bits
[7:4]
Bit Name
CMAP_C2
Settings
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description
ADC Channel 2 Output Mapping
Slot 1 for Channel
Slot 2 for Channel
Slot 3 for Channel (on SDATAOUT2 in stereo modes)
Slot 4 for Channel (on SDATAOUT2 in stereo modes)
Slot 5 for Channel (TDM8+ only)
Slot 6 for Channel (TDM8+ only)
Slot 7 for Channel (TDM8+ only)
Slot 8 for Channel (TDM8+ only)
Slot 9 for Channel (TDM16 only)
Slot 10 for Channel (TDM16 only)
Slot 11 for Channel (TDM16 only)
Slot 12 for Channel (TDM16 only)
Slot 13 for Channel (TDM16 only)
Slot 14 for Channel (TDM16 only)
Slot 15 for Channel (TDM16 only)
Slot 16 for Channel (TDM16 only)
Rev. 0 | Page 33 of 44
Reset
0x1
Access
RW
ADAU1978
Bits
[3:0]
Bit Name
CMAP_C1
Data Sheet
Settings
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description
ADC Channel 1 Output Mapping. If CMAP is set to a slot that does not
exist for a given serial mode, that channel is not driven. For example, if
CMAP is set to Slot 9 and the serial format is I2S, that channel is not driven.
If more than one channel is set to the same slot, only the lowest channel
number is driven; other channels are not driven.
Slot 1 for Channel
Slot 2 for Channel
Slot 3 for Channel (on SDATAOUT2 in stereo modes)
Slot 4 for Channel (on SDATAOUT2 in stereo modes)
Slot 5 for Channel (TDM8+ only)
Slot 6 for Channel (TDM8+ only)
Slot 7 for Channel (TDM8+ only)
Slot 8 for Channel (TDM8+ only)
Slot 9 for Channel (TDM16 only)
Slot 10 for Channel (TDM16 only)
Slot 11 for Channel (TDM16 only)
Slot 12 for Channel (TDM16 only)
Slot 13 for Channel (TDM16 only)
Slot 14 for Channel (TDM16 only)
Slot 15 for Channel (TDM16 only)
Slot 16 for Channel (TDM16 only)
Rev. 0 | Page 34 of 44
Reset
0x0
Access
RW
Data Sheet
ADAU1978
CHANNEL 3 AND CHANNEL 4 MAPPING FOR OUTPUT SERIAL PORTS REGISTER
Address: 0x08, Reset: 0x32, Name: SAI_CMAP34
Table 23. Bit Descriptions for SAI_CMAP34
Bits
[7:4]
Bit Name
CMAP_C4
Settings
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description
ADC Channel 4 Output Mapping
Slot 1 for Channel
Slot 2 for Channel
Slot 3 for Channel (on SDATAOUT2 in stereo modes)
Slot 4 for Channel (on SDATAOUT2 in stereo modes)
Slot 5 for Channel (TDM8+ only)
Slot 6 for Channel (TDM8+ only)
Slot 7 for Channel (TDM8+ only)
Slot 8 for Channel (TDM8+ only)
Slot 9 for Channel (TDM16 only)
Slot 10 for Channel (TDM16 only)
Slot 11 for Channel (TDM16 only)
Slot 12 for Channel (TDM16 only)
Slot 13 for Channel (TDM16 only)
Slot 14 for Channel (TDM16 only)
Slot 15 for Channel (TDM16 only)
Slot 16 for Channel (TDM16 only)
Rev. 0 | Page 35 of 44
Reset
0x3
Access
RW
ADAU1978
Bits
[3:0]
Bit Name
CMAP_C3
Data Sheet
Settings
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description
ADC Channel 3 Output Mapping
Slot 1 for Channel
Slot 2 for Channel
Slot 3 for Channel (on SDATAOUT2 in stereo modes)
Slot 4 for Channel (on SDATAOUT2 in stereo modes)
Slot 5 for Channel (TDM8+ only)
Slot 6 for Channel (TDM8+ only)
Slot 7 for Channel (TDM8+ only)
Slot 8 for Channel (TDM8+ only)
Slot 9 for Channel (TDM16 only)
Slot 10 for Channel (TDM16 only)
Slot 11 for Channel (TDM16 only)
Slot 12 for Channel (TDM16 only)
Slot 13 for Channel (TDM16 only)
Slot 14 for Channel (TDM16 only)
Slot 15 for Channel (TDM16 only)
Slot 16 for Channel (TDM16 only)
Reset
0x2
Access
RW
SERIAL OUTPUT DRIVE CONTROL AND OVERTEMPERATURE PROTECTION STATUS REGISTER
Address: 0x09, Reset: 0xF0, Name: SAI_OVERTEMP
Table 24. Bit Descriptions for SAI_OVERTEMP
Bits
7
Bit Name
SAI_DRV_C4
Settings
0
1
Description
Channel 4 Serial Output Drive Enable.
Channel Not Driven on Serial Output Port.
Channel Driven on Serial Output Port. Slot determined by CMAP_4.
Rev. 0 | Page 36 of 44
Reset
0x1
Access
RW
Data Sheet
Bits
6
Bit Name
SAI_DRV_C3
ADAU1978
Settings
0
1
5
SAI_DRV_C2
0
1
4
SAI_DRV_C1
0
1
3
DRV_HIZ
0
1
[2:1]
0
RESERVED
OT
0
1
Description
Channel 3 Serial Output Drive Enable.
Channel Not Driven on Serial Output Port.
Channel Driven on Serial Output Port. Slot determined by CMAP_3.
Channel 2 Serial Output Drive Enable.
Channel Not Driven on Serial Output Port.
Channel Driven on Serial Output Port. Slot determined by CMAP_2.
Channel 1 Serial Output Drive Enable.
Channel Not Driven on Serial Output Port.
Channel Driven on Serial Output Port. Slot determined by CMAP_1.
Select whether to tristate unused SAI channels or actively drive these data slots.
Unused outputs driven low.
Unused outputs High-Z.
Reserved
Overtemperature Status.
Normal Operation.
Overtemperature Fault.
Reset
0x1
Access
RW
0x1
RW
0x1
RW
0x0
RW
0x0
0x0
R
R
POST ADC GAIN CHANNEL 1 CONTROL REGISTER
Address: 0x0A, Reset: 0xA0, Name: POSTADC_GAIN1
Table 25. Bit Descriptions for POSTADC_GAIN1
Bits
[7:0]
Bit Name
PADC_GAIN1
Settings
00000000
00000001
00000010
...
10011111
10100000
10100001
...
11111110
11111111
Description
Channel 1 Post ADC Gain
+60 dB Gain
+59.625 dB Gain
+59.25 dB Gain
...
+0.375 dB Gain
0 dB Gain
−0.375 dB Gain
...
−35.625 dB Gain
Mute
Rev. 0 | Page 37 of 44
Reset
0xA0
Access
RW
ADAU1978
Data Sheet
POST ADC GAIN CHANNEL 2 CONTROL REGISTER
Address: 0x0B, Reset: 0xA0, Name: POSTADC_GAIN2
Table 26. Bit Descriptions for POSTADC_GAIN2
Bits
[7:0]
Bit Name
PADC_GAIN2
Settings
00000000
00000001
00000010
...
10011111
10100000
10100001
...
11111110
11111111
Description
Channel 2 Post ADC Gain
+60 dB Gain
+59.625 dB Gain
+59.25 dB Gain
...
+0.375 dB Gain
0 dB Gain
−0.375 dB Gain
...
−35.625 dB Gain
Mute
Reset
0xA0
Access
RW
Reset
0xA0
Access
RW
POST ADC GAIN CHANNEL 3 CONTROL REGISTER
Address: 0x0C, Reset: 0xA0, Name: POSTADC_GAIN3
Table 27. Bit Descriptions for POSTADC_GAIN3
Bits
[7:0]
Bit Name
PADC_GAIN3
Settings
00000000
00000001
00000010
...
10011111
10100000
10100001
...
11111110
11111111
Description
Channel 3 Post ADC Gain
+60 dB Gain
+59.625 dB Gain
+59.25 dB Gain
...
+0.375 dB Gain
0 dB Gain
−0.375 dB Gain
...
−35.625 dB Gain
Mute
Rev. 0 | Page 38 of 44
Data Sheet
ADAU1978
POST ADC GAIN CHANNEL 4 CONTROL REGISTER
Address: 0x0D, Reset: 0xA0, Name: POSTADC_GAIN4
Table 28. Bit Descriptions for POSTADC_GAIN4
Bits
[7:0]
Bit Name
PADC_GAIN4
Settings
00000000
00000001
00000010
...
10011111
10100000
10100001
...
11111110
11111111
Description
Channel 4 Post ADC Gain
+60 dB Gain
+59.625 dB Gain
+59.25 dB Gain
...
+0.375 dB Gain
0 dB Gain
−0.375 dB Gain
...
−35.625 dB Gain
Mute
Rev. 0 | Page 39 of 44
Reset
0xA0
Access
RW
ADAU1978
Data Sheet
HIGH-PASS FILTER AND DC OFFSET CONTROL REGISTER AND MASTER MUTE REGISTER
Address: 0x0E, Reset: 0x02, Name: MISC_CONTROL
Table 29. Bit Descriptions for MISC_CONTROL
Bits
[7:6]
Bit Name
SUM_MODE
Settings
00
01
10
11
5
4
RESERVED
MMUTE
0
1
[3:1]
0
RESERVED
DC_CAL
0
1
Description
Channel Summing Mode Control for Higher SNR
Normal 4-Channel Operation
2-Channel Summing Operation (See the ADC Summing Modes Section)
1-Channel Summing Operation (See the ADC Summing Modes Section)
Reserved
Reserved
Master Mute
Normal Operation
All Channels Muted
Reserved
DC Calibration Enable
Normal Operation
Perform DC Calibration
Rev. 0 | Page 40 of 44
Reset
0x0
Access
RW
0x0
0x0
RW
RW
0x0
0x0
RW
RW
Data Sheet
ADAU1978
ADC CLIPPING STATUS REGISTER
Address: 0x19, Reset: 0x00, Name: ASDC_CLIP
Table 30. Bit Descriptions for ASDC_CLIP
Bits
[7:4]
3
Bit Name
RESERVED
ADC_CLIP4
Settings
0
1
2
ADC_CLIP3
0
1
1
ADC_CLIP2
0
1
0
ADC_CLIP1
0
1
Description
Reserved
ADC Channel 4 Clip Status
Normal Operation
ADC Channel Clipping
ADC Channel 3 Clip Status
Normal Operation
ADC Channel Clipping
ADC Channel 2 Clip Status
Normal Operation
ADC Channel Clipping
ADC Channel 1 Clip Status
Normal Operation
ADC Channel Clipping
Rev. 0 | Page 41 of 44
Reset
0x0
0x0
Access
RW
R
0x0
R
0x0
R
0x0
R
ADAU1978
Data Sheet
DIGITAL DC HIGH-PASS FILTER AND CALIBRATION REGISTER
Address: 0x1A, Reset: 0x00, Name: DC_HPF_CAL
Table 31. Bit Descriptions for DC_HPF_CAL
Bits
7
Bit Name
DC_SUB_C4
Settings
0
1
6
DC_SUB_C3
0
1
5
DC_SUB_C2
0
1
4
DC_SUB_C1
0
1
3
DC_HPF_C4
0
1
2
DC_HPF_C3
0
1
1
DC_HPF_C2
0
1
0
DC_HPF_C1
0
1
Description
Channel 4 DC Subtraction from Calibration
No DC Subtraction
DC Value from DC Calibration Is Subtracted
Channel 3 DC Subtraction from Calibration
No DC Subtraction
DC Value from DC Calibration Is Subtracted
Channel 2 DC Subtraction from Calibration
No DC Subtraction
DC Value from DC Calibration Is Subtracted
Channel 1 DC Subtraction from Calibration
No DC Subtraction
DC Value from DC Calibration Is Subtracted
Channel 4 DC High-Pass Filter Enable
HPF Off
HPF On
Channel 3 DC High-Pass Filter Enable
HPF Off
HPF On
Channel 2 DC High-Pass Filter Enable
HPF Off
HPF On
Channel 1 DC High-Pass Filter Enable
HPF Off
HPF On
Rev. 0 | Page 42 of 44
Reset
0x0
Access
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
Data Sheet
ADAU1978
TYPICAL APPLICATION CIRCUIT
+3.3V
10µF
MLCC X7R
C12
0.1µF
C13
0.1µF
AVDD1
AVDD3
AVDD2
C14
0.1µF
* FOR MORE INFORMATION ABOUT CALCULATING THE VALUE
FOR REXT , SEE THE POWER-ON RESET SEQUENCE SECTION.
3.3V TO 1.8V
REGULATOR
DVDD
AVDD1
AVDD3
IOVDD
C7
0.1µF
LRCLK
BCLK
SDATAOUT1
SDATAOUT2
AVDD2
I2C/SPI
CONTROL
PLL
AGND2
AGND2
R16
R12
R11
R9
IOVDD
AGND3
BG
REF
TO DSP
R10
ADC
AGND1
SERIAL AUDIO PORT
PROGRAMMABLE GAIN
DECIMATOR/HPF
DC CALIBRATION
ADC
SCL/CCLK
SDA/COUT
ADDR1/CIN
MICROCONTROLLER
ADDR0/CLATCH
C18
10µF
C19
0.1µF
SA_MODE
PD/RST
PLL_FILT
R13
R14
NOTES
1. R9, R10 = TYPICAL 2kΩ FOR IOVDD = 3.3V, 1kΩ FOR IOVDD = 1.8V.
2. R11 THROUGH R14 USED FOR SETTING THE DEVICE IN I 2C MODE.
3. R16 = TYPICAL 47kΩ FOR IOVDD = 3.3V, 22kΩ FOR IOVDD = 1.8V.
4. PLL LOOP FILTER:
C21
C20
PLL INPUT OPTION
R17
+3.3V (AVDD2)
R17
C20
C21
LRCLK
MCLK
4.87kΩ
2200pF
39nF
1kΩ
390pF
5600pF
Figure 44. Typical Application Circuit, Four Inputs, I2C and I2S Mode
Rev. 0 | Page 43 of 44
11292-046
LINE4
ADC
MCLKIN
LINE3
VREF
LINE2
REXT *
+1.8V OR +3.3V
ADC
DGND
LINE1
AIN1P
AIN1N
AIN2P
AIN2N
AIN3P
AIN3N
AIN4P
AIN4N
AGND1
AGND2
AGND3
AGND4
AGND5
AGND6
MAX INPUT 2V rms
DIFFERENTIAL
C16
10µF
MLCC X7R
C15
0.1µF
ADAU1978
ADAU1978
Data Sheet
OUTLINE DIMENSIONS
0.30
0.25
0.18
31
0.50
BSC
1
TOP VIEW
0.80
0.75
0.70
10
11
20
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
4.05
3.90 SQ
3.75
EXPOSED
PAD
21
0.45
0.40
0.35
PIN 1
INDICATOR
40
30
BOTTOM VIEW
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.
05-06-2011-A
PIN 1
INDICATOR
6.10
6.00 SQ
5.90
Figure 45. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
6 mm × 6 mm Body, Very Very Thin Quad
(CP-40-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
ADAU1978WBCPZ
ADAU1978WBCPZ-RL
EVAL-ADAU1978Z
1
2
Temperature Range
–40°C to +105°C
–40°C to +105°C
Package Description
40-Lead LFCSP_WQ
40-Lead LFCSP, 13” Tape and Reel
Evaluation Board
Package Option
CP-40-14
CP-40-14
Z = RoHS Compliant Part.
W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The ADAU1978WBCPZ models are available with controlled manufacturing to support the quality and reliability requirements of
automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore,
designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for
use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and
to obtain the specific Automotive Reliability reports for these models.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11292-0-5/13(0)
Rev. 0 | Page 44 of 44
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