Buck PWM Controller with Internal Compensation and External Reference Tracking ISL95873 Features The ISL95873 is a Single-Phase Synchronous-Buck PWM controller featuring Intersil’s proprietary R4™ Technology. The R4™ modulator has integrated compensation, fast transient performance, accurate switching frequency control, and excellent light-load efficiency. These technology advances, together with integrated MOSFET drivers and a Schottky bootstrap diode, allow for a high performance regulator that is highly compact and needs few external components. Differential remote sensing of the output voltage is an additional feature. For maximum efficiency, the converter automatically enters diode-emulation mode (DEM) during light-load conditions, such as system standby. • External reference tracking • Intersil’s R4™ modulator technology - Internal compensation - Fast, optimal transient response The ISL95873 accepts a wide 3.3V to 25V input voltage range, making it ideal for systems that run on battery or AC-adapter power sources. It also is a low-cost solution for applications requiring tracking of an external reference voltage during soft-start. When the external reference level meets the internal reference voltage, the ISL95873 switches from the external reference to the internal reference. The external reference is only used during soft-start. • Input voltage range: 3.3V to 25V • Output voltage range: 0.5V to 3.3V • Precision voltage regulation - ±0.5% System accuracy over -10°C to +100°C • Output voltage remote sense • Fixed 300kHz PWM frequency in continuous conduction - Proprietary frequency control loop • Automatic diode emulation mode for highest efficiency • Power-good monitor for soft-start and fault detection Applications • Compact buck regulators requiring external tracking RVCC +5V CVCC VCC REFIN PGOOD QHS 12 11 LO 10 CBOOT VO ROFS VOUT 0.5V TO 3.3V QLS 9 8 5 CSOFT EXTERNAL REFERENCE VOLTAGE CIN ROCSET PHASE VIN 3.3V TO 25V RPGOOD 13 14 PVCC LGATE EN SREF 4 UGATE OCSET GPIO RTN 7 3 BOOT FB 2 GND 6 1 RFB1 ROFS1 RTN1 PGND 16 15 CPVCC CO CSEN RTN1 RO RFB 0 FIGURE 1. ISL95873 APPLICATION SCHEMATIC WITH DCR CURRENT SENSE December 10, 2012 FN8390.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved. R3 , R4 Modulator Technologies and Intersil (and design) are trademarks owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL95873 Application Schematics RVCC +5V CVCC CPVCC FB VOUT 0.5V TO 3.3V LO PHASE QLS PGOOD CO ROCSET 9 SREF RPGOOD VCC 13 PVCC 10 4 UGATE CBOOT CSEN RTN1 RO RFB CSOFT EXTERNAL REFERENCE VOLTAGE 14 3 5 ROFS1 REFIN 11 QHS BOOT 8 GPIO 2 CIN VO EN 12 7 RTN 1 6 GND RFB1 OCSET RTN1 15 16 PGND LGATE VIN 3.3V TO 25V 0 ROFS FIGURE 2. ISL95873 APPLICATION SCHEMATIC WITH ONE OUTPUT VOLTAGE SETPOINT AND DCR CURRENT SENSE RVCC +5V CVCC CPVCC RPGOOD VCC 13 VOUT 0.5V TO 3.3V QLS PGOOD CBOOT CO CSEN RTN1 RO RFB ROFS R2 RSEN ROCSET 9 LO PHASE 8 4 QHS UGATE CSOFT R1 14 10 SREF EXTERNAL REFERENCE VOLTAGE PVCC 3 5 ROFS1 REFIN 11 CIN BOOT VO GPIO 2 7 EN 12 6 RTN 1 FB RFB1 OCSET GND RTN1 15 16 PGND LGATE VIN 3.3V TO 25V 0 FIGURE 3. ISL95873 APPLICATION SCHEMATIC WITH ONE OUTPUT VOLTAGE SETPOINT AND RESISTOR CURRENT SENSE 2 FN8390.0 December 10, 2012 Block Diagram VCC POR SOFT-START CIRCUITRY BOOT EN 3 DRIVER PGOOD CIRCUITRY PGOOD UGATE PHASE DEAD-TIME GENERATION FB PVCC UNDERVOLTAGE MONITOR SREF DRIVER + LGATE PGND R4 TM MODULATOR VO REFIN REFERENCE VOLTAGE CIRCUITRY REMOTE SENSE CIRCUITRY OVERCURRENT OCSET GND FN8390.0 December 10, 2012 RTN FIGURE 4. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL95873 ISL95873 INTERNAL COMPENSATION AMPLIFIER ISL95873 Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING ISL95873HRUZ-T 873 TEMP RANGE (°C) PACKAGE (Pb-Free) -10 to +100 16 Ld 2.6x1.8 UTQFN PKG. DWG. # L16.2.6x1.8A NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL95873. For more information on MSL, please see tech brief TB363 Functional Pin Descriptions (Continued) Pin Configuration 13 VCC 14 PVCC 15 LGATE 16 PGND ISL95873 (16 LD 2.6X1.8 UTQFN) TOP VIEW EN 3 10 PHASE REFIN 4 9 PGOOD VO 8 11 UGATE OCSET 7 RTN 2 FB 6 12 BOOT SREF 5 GND 1 Functional Pin Descriptions PIN NUMBER SYMBOL PIN NUMBER SYMBOL 7 OCSET Input for the overcurrent detection circuit. The overcurrent setpoint programming resistor ROCSET connects from this pin to the sense node. 8 VO Output voltage sense input for the R4TM modulator. The VO pin also serves as the reference input for the overcurrent detection circuit. 9 PGOOD Power-good open-drain indicator output. This pin changes to high impedance when the converter is able to supply regulated voltage. 10 PHASE Return current path for the UGATE high-side MOSFET driver, VIN sense input for the R4TM modulator, and inductor current polarity detector input. 11 UGATE High-side MOSFET gate driver output. Connect to the gate terminal of the high-side MOSFET of the converter. 12 BOOT Positive input supply for the UGATE high-side MOSFET gate driver. The BOOT pin is internally connected to the cathode of the Schottky boot-strap diode. Connect an MLCC between the BOOT pin and the PHASE pin. 13 VCC Input for the IC bias voltage. Connect +5V to the VCC pin and decouple with at least a MLCC to the GND pin. 14 PVCC Input for the LGATE and UGATE MOSFET driver circuits. The PVCC pin is internally connected to the anode of the Schottky boot-strap diode. Connect +5V to the PVCC pin and decouple with a MLCC to the PGND pin. DESCRIPTION 1 GND IC ground for bias supply and signal reference. 2 RTN Negative remote sense input of VOUT. If resistor divider consisting of RFB and ROFS is used at FB pin, the same resistor divider should be used at RTN pin, i.e. keep RFB1 = RFB, and ROFS1 = ROFS. DESCRIPTION 3 EN Enable input for the IC. Pulling EN above the rising threshold voltage initializes the soft-start sequence. 4 REFIN Input for supplying the external reference voltage followed by the controller during soft-start. 15 LGATE 5 SREF Soft-start and voltage slew-rate programming capacitor input. Connects internally to the inverting input of the VSET voltage setpoint amplifier. Low-side MOSFET gate driver output. Connect to the gate terminal of the low-side MOSFET of the converter. 16 PGND Return current path for the LGATE MOSFET driver. Connect to the source of the low-side MOSFET. 6 FB Voltage feedback sense input. Connects internally to the inverting input of the control-loop error amplifier. The converter is in regulation when the voltage at the FB pin equals the voltage on the SREF pin. 4 FN8390.0 December 10, 2012 ISL95873 Table of Contents Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Enabling the Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 External Reference Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Output Voltage Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 R4TM Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Diode Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Overvoltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Over-Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PGOOD Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Integrated MOSFET Gate-Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Adaptive Shoot-Through Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 General Application Design Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Selecting the LC Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selecting the Input Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selecting the Bootstrap Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driver Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOSFET Selection and Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13 13 13 14 14 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package Outline Drawing L16.2.6x1.8A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 FN8390.0 December 10, 2012 ISL95873 Absolute Maximum Ratings Thermal Information VCC, PVCC, PGOOD, FSEL to GND . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V VCC, PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V GND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V EN, VO, REFIN, FB, RTN, OCSET, SREF . . . . . . . . . -0.3V to GND, VCC + 0.3V BOOT Voltage (VBOOT-GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 33V BOOT To PHASE Voltage (VBOOT-PHASE). . . . . . . . . . . . . . . . -0.3V to 7V (DC) -0.3V to 9V (<10ns) PHASE Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 28V GND -8V (<20ns Pulse Width, 10µJ) UGATE Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . VPHASE - 0.3V (DC) to VBOOT VPHASE - 5V (<20ns Pulse Width, 10µJ) to VBOOT LGATE Voltage . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V (DC) to VCC + 0.3V . . . . . . . . . . . . . . . . . . GND - 2.5V (<20ns Pulse Width, 5µJ) to VCC + 0.3V Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 16 Ld UTQFN (Notes 4, 5) . . . . . . . . . . . . . . 90 60 Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -55°C to +150°C Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C Converter Input Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . 3.3V to 25V VCC, PVCC to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5% CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. For θJC, the “case temp” location is taken at the package top center. Electrical Specifications All typical specifications TA = +25°C, VCC = 5V. Boldface limits apply over the operating temperature range, -10°C to +100°C, unless otherwise stated. PARAMETER MIN (Note 7) TYP MAX (Note 7) UNIT EN = 5V, VCC = 5V, FB = 0.55V, SREF < FB - 1.2 1.9 mA SYMBOL TEST CONDITIONS VCC and PVCC VCC Input Bias Current IVCC VCC Shutdown Current IVCCoff EN = GND, VCC = 5V - 0 1.0 µA PVCC Shutdown Current IPVCCoff EN = GND, PVCC = 5V - 0 1.0 µA VCC POR THRESHOLD Rising VCC POR Threshold Voltage VVCC_THR 4.40 4.52 4.60 V Falling VCC POR Threshold Voltage V 4.10 4.22 4.35 V -0.5 - +0.5 % - 0.5 - V 0.461 0.482 0.4975 V 255 300 345 kHz VCC_THF REGULATION System Accuracy PWM Mode = CCM Internal Reference Voltage Feedback Voltage Reference Transfer Voltage PWM Switching Frequency Accuracy FSW PWM Mode = CCM RVO EN = 5V - 600 - kΩ VO VO Input Impedance VO Reference Offset Current IVOSS VENTHR < EN, SREF = Soft-Start Mode - 8.5 - µA VO Input Leakage Current IVOoff EN = GND, VO = 3.6V - 0 - µA IFB EN = 5V, FB = 0.50V -30 - +50 nA ISS SREF = Soft-Start Mode ±51 85 ±119 µA RPG PGOOD = 5mA Sink - 50 150 Ω ERROR AMPLIFIER FB Input Bias Current SREF Maximum Soft-Start Current POWER GOOD PGOOD Pull-down Impedance 6 FN8390.0 December 10, 2012 ISL95873 Electrical Specifications All typical specifications TA = +25°C, VCC = 5V. Boldface limits apply over the operating temperature range, -10°C to +100°C, unless otherwise stated. (Continued) PARAMETER MIN (Note 7) TYP MAX (Note 7) UNIT PGOOD = 5V - 0.1 1.0 µA SYMBOL PGOOD Leakage Current IPG TEST CONDITIONS GATE DRIVER UGATE Pull-Up Resistance (Note 6) RUGPU 200mA Source Current - 1.1 1.7 Ω UGATE Source Current (Note 6) IUGSRC UGATE - PHASE = 2.5V - 1.8 - A UGATE Sink Resistance (Note 6) RUGPD 250mA Sink Current - 1.1 1.7 Ω UGATE Sink Current (Note 6) IUGSNK UGATE - PHASE = 2.5V - 1.8 - A LGATE Pull-Up Resistance (Note 6) RLGPU 250mA Source Current - 1.1 1.7 Ω LGATE Source Current (Note 6) ILGSRC LGATE - GND = 2.5V - 1.8 - A LGATE Sink Resistance (Note 6) RLGPD 250mA Sink Current - 0.55 1.0 Ω LGATE Sink Current (Note 6) ILGSNK LGATE - PGND = 2.5V - 3.6 - A UGATE to LGATE Deadtime tUGFLGR UGATE falling to LGATE rising, no load - 21 - ns LGATE to UGATE Deadtime tLGFUGR LGATE falling to UGATE rising, no load - 21 - ns - 33 - kΩ PHASE PHASE Input Impedance RPHASE BOOTSTRAP DIODE Forward Voltage VF PVCC = 5V, IF = 2mA - 0.58 - V Reverse Leakage IR VR = 25V - 0 - µA CONTROL INPUTS EN High Threshold Voltage VENTHR 2.0 - - V EN Low Threshold Voltage VENTHF - - 1.0 V 0.85 1.7 2.55 µA - 0 1.0 µA VOCSET - VO -1.15 - 1.15 mV EN Input Bias Current IEN EN Leakage Current IENoff EN = 5V EN = GND PROTECTION OCP Threshold Voltage VOCPTH OCP Reference Current IOCP EN = 5.0V 7.905 8.5 8.925 µA OCSET Input Resistance ROCSET EN = 5.0V - 600 - kΩ OCSET Leakage Current IOCSET EN = GND - 0 - µA UVP Threshold Voltage VUVTH VFB = %VSREF 81 84 87 % OVP Rising Threshold Voltage VOVRTH VFB = %VSREF 113 116 120 % OVP Falling Threshold Voltage VOVFTH VFB = %VSREF 100 102 106 % OTP Rising Threshold Temperature (Note 6) TOTRTH - 150 - °C OTP Hysteresis (Note 6) TOTHYS - 25 - °C NOTES: 6. Limits established by characterization and are not production tested. 7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 7 FN8390.0 December 10, 2012 ISL95873 Theory of Operation The following sections will provide a detailed description of the inner workings of the ISL95873. Power-On Reset The IC is disabled until the voltage at the VCC pin has increased above the rising power-on reset (POR) threshold voltage VVCC_THR. The controller will become disabled when the voltage at the VCC pin decreases below the falling POR threshold voltage VVCC_THF. The POR detector has a noise filter of approximately 1µs. Enabling the Controller Once VCC has ramped above VVCC_THR, the controller can be enabled by pulling the EN pin voltage above the input-high threshold VENTHR. Once EN exceeds this threshold, the soft-start sequence is initiated. External Reference Setup The REFIN input of the ISL95873 requires an external reference voltage to be connected to this pin. Typically, this will be another system rail, which requires the output of the ISL95873 to follow it up during boot-up of the two regulators. A resistor divider is required between the external reference voltage and the REFIN pin to scale the external voltage down to the internal reference voltage, see Figure 5. VOUT to 85µA and is sourced out of the SREF pin and begins charging the CSOFT capacitor on the SREF pin until it equals VREFIN. The soft-start current will adjust to match the external reference ramp rate as seen through the resistor divider on the REFIN pin. The regulator controls the PWM, such that the voltage on the SREF pin tracks the rising voltage on the REFIN pin. The maximum dv/dt that the external voltage (VEXT) can achieve is outlined in Equation 2. R1 + R2 dV EXT I SS - ⋅ -------------------------------------- = -----------------R2 dt C SOFT (EQ. 2) The elapsed time from when the EN pin is asserted to when VSREF has charged CSOFT to VREF IN will depend on the dv/dt of the external reference voltage used to generate the signal at REFIN. CSOFT will not impact the dv/dt unless it is over sized or the dv/dt (outlined in Equation 2), is exceeded by the external reference. The minimum CSOFT capacitance is 10nF. Once the feedback voltage, FB, exceeds the 0.482V threshold on an internal comparator, the ISL95873 switches from the external reference (VEXT) to the internal reference, VREF, see Figure 6. The end of soft-start is detected by ISS tapering off when capacitor CSOFT charges to VREFIN. The pull-down on PGOOD is released to indicate that the controller is regulating properly. VEXT SLOPE DETERMINED BY LOAD CURRENT RFB FB VCOMP - ROFS EA VREF + VREF VREFIN + VSET - CSOFT SREF + VEXT REFIN R1 VREFIN 0.482V FB R2 FIGURE 5. REFIN CONNECTION TO SYSTEM RAIL The relation between the voltage at the REFIN pin, VREFIN, and the external reference voltage, VEXT, is given in Equation 1: R2 V REFIN = V REF = V EXT ⋅ --------------------R +R 1 (EQ. 1) 2 From this expression the resistor divider values can be calculated. The voltage on the REFIN pin must equal to the internal reference of the ISL95873. Soft-Start Once the POR threshold on VCC has been met and ENABLE is applied, the SREF pin releases its discharge clamp, and enables the reference amplifier VSET. The soft-start current ISS is limited 8 FIGURE 6. SOFT-START TRACKING OF EXTERNAL REFERENCE During soft-start, the regulator always operates in CCM until the soft-start sequence is complete. Once soft-start is complete, diode emulation mode (DEM) is enabled. If REFIN is pre-charged, the ISL95873 will begin switching and charging the output voltage of the regulator to the pre-charged REFIN level once enabled. Then the controller waits for REFIN to begin to move and starts charging the SREF capacitor and ramping as described previously. Output Voltage Programming The ISL95873 has a fixed 0.5V internal reference voltage (VSREF). Figure 7 shows that the output voltage is the reference voltage if RFB is shorted and ROFS is open. A resistor divider consisting of ROFS and RFB allows the user to scale the output voltage between 0.5V and 3.3V. The relation between the output voltage and the reference voltage is given in Equation 3: R FB + R OFS V OUT = V REF ⋅ ---------------------------------R (EQ. 3) OFS FN8390.0 December 10, 2012 ISL95873 VOUT COMPENSATION TO COUNTER RFB FB - VCOMP INTEGRATOR POLE VREF VOUT INTEGRATOR FOR HIGH DC GAIN ROFS EA + + VCOMP VSET VDAC FIGURE 8. INTEGRATOR ERROR-AMPLIFIER CONFIGURATION CSOFT SREF R3TM LOOP GAIN (dB) INTEGRATOR POLE p1 L/C DOUBLE-POLE FIGURE 7. ISL95873 VOLTAGE PROGRAMMING CIRCUIT R4TM Modulator p2 -2 /d B 0d ec c 9 / de Classic control theory requires a single-pole transition through unity gain to ensure a stable system. Current-mode architectures (includes peak, peak-valley, current-mode hysteretic, R3™ and R4™) generate a zero at or near the L/C resonant point, effectively canceling one of the system’s poles. The system still contains two poles, one of which must be canceled with a zero before unity gain crossover to achieve stability. Compensation components are added to introduce the necessary zero. ec The removal of compensation derives from the R4™ modulator’s lack of need for high DC gain. In traditional architectures, high DC gain is achieved with an integrator in the voltage loop. The integrator introduces a pole in the open-loop transfer function at low frequencies. Thus, combined with the double-pole from the output L/C filter, creates a three pole system that must be compensated to maintain stability. COMPENSATOR TO ADD z2 IS NEEDED CURRENT-MODE ZERO z1 dB -40 Stability -20dB CROSSOVER REQUIRED FOR STABILITY p3 -60dB/d The R4™ modulator is an evolutionary step in R3™ technology. Like R3™, the R4™ modulator allows variable frequency in response to load transients and maintains the benefits of current-mode hysteretic controllers. However, in addition, the R4™ modulator reduces regulator output impedance and uses accurate referencing to eliminate the need for a high-gain voltage amplifier in the compensation loop. The result is a topology that can be tuned to voltage-mode hysteretic transient speed while maintaining a linear control model and removes the need for any compensation. This greatly simplifies the regulator design for customers and reduces external component cost. f (Hz) FIGURE 9. UNCOMPENSATED INTEGRATOR OPEN-LOOP RESPONSE Figure 8 illustrates the classic integrator configuration for a voltage loop error-amplifier. While the integrator provides the high DC gain required for accurate regulation in traditional technologies, it also introduces a low-frequency pole into the control loop. Figure 9 shows the open-loop response that results from the addition of an integrating capacitor in the voltage loop. The compensation components found in Figure 8 are necessary to achieve stability. Because R4™ does not require a high-gain voltage loop, the integrator can be removed, reducing the number of inherent poles in the loop to two. The current-mode zero continues to cancel one of the poles, ensuring a single-pole crossover for a wide range of output filter choices. The result is a stable system with no need for compensation components or complex equations to properly tune the stability. Figure 10 shows the R4™ error-amplifier that does not require an integrator for high DC gain to achieve accurate regulation. The result to the open loop response can be seen in Figure 11. FN8390.0 December 10, 2012 ISL95873 R2 VOUT VCOMP R1 The dotted red and blue lines in Figure 12 represent the time delayed behavior of VOUT and VCOMP in response to a load transient when an integrator is used. The solid red and blue lines illustrate the increased response of R4™ in the absence of the integrator capacitor. Diode Emulation VDAC FIGURE 10. NON-INTEGRATED R4TM ERROR-AMPLIFIER CONFIGURATION R4TM LOOP GAIN (dB) L/C DOUBLE-POLE p1 SYSTEM HAS 2 POLES AND 1 ZERO p2 NO COMPENSATOR IS NEEDED ec /d B 0d ec -2 /d B c 0d de B/ -2 CURRENT-MODE ZERO z1 d -40 f (Hz) FIGURE 11. UNCOMPENSATED R4TM OPEN-LOOP RESPONSE Transient Response In addition to requiring a compensation zero, the integrator in traditional architectures also slows system response to transient conditions. The change in COMP voltage is slow in response to a rapid change in output voltage. If the integrating capacitor is removed, COMP moves as quickly as VOUT, and the modulator immediately increases or decreases switching frequency to recover the output voltage. IOUT t R4TM R3TM The polarity of the output inductor current is defined as positive when conducting away from the phase node, and defined as negative when conducting towards the phase node. The DC component of the inductor current is positive, but the AC component known as the ripple current, can be either positive or negative. Should the sum of the AC and DC components of the inductor current remain positive for the entire switching period, the converter is in continuous-conduction-mode (CCM). However, if the inductor current becomes negative or zero, the converter is in discontinuous-conduction-mode (DCM). Unlike the standard DC/DC buck regulator, the synchronous rectifier can sink current from the output filter inductor during DCM, reducing the light-load efficiency with unnecessary conduction loss as the low-side MOSFET sinks the inductor current. The ISL95873 controller avoids the DCM conduction loss by making the low-side MOSFET emulate the current-blocking behavior of a diode. This smart-diode operation called diode-emulation-mode (DEM) is triggered when the negative inductor current produces a positive voltage drop across the rDS(ON) of the low-side MOSFET for eight consecutive PWM cycles while the LGATE pin is high. The converter will exit DEM on the next PWM pulse after detecting a negative voltage across the rDS(ON) of the low-side MOSFET. It is characteristic of the R4™ architecture for the PWM switching frequency to decrease while in DCM, increasing efficiency by reducing unnecessary gate-driver switching losses. The extent of the frequency reduction is proportional to the reduction of load current. Upon entering DEM, the PWM frequency is forced to fall approximately 30% by forcing a similar increase of the window voltage V W. This measure is taken to prevent oscillating between modes at the boundary between CCM and DCM. The 30% increase of VW is removed upon exit of DEM, forcing the PWM switching frequency to jump back to the nominal CCM value. Overcurrent VCOMP t VOUT t The overcurrent protection (OCP) setpoint is programmed with resistor ROCSET, which is connected across the OCSET and PHASE pins. Resistor RO is connected between the VO pin and the actual output voltage of the converter. During normal operation, the VO pin is a high impedance path, therefore there is no voltage drop across RO. The value of resistor RO should always match the value of resistor ROCSET. FIGURE 12. R3TM vs R4TM IDEALIZED TRANSIENT RESPONSE 10 FN8390.0 December 10, 2012 ISL95873 L C SEN = -----------------------------------------R OCSET ⋅ DCR L DCR IL PHASE + ROCSET 8.5µA OCSET + VROCSET VDCR CSEN VO _ CO _ RO VO Figure 13 shows the overcurrent set circuit. The inductor consists of inductance L and the DC resistance DCR. The inductor DC current IL creates a voltage drop across DCR, which is given by Equation 4: (EQ. 4) The IOCSET current source sinks 8.5µA into the OCSET pin, creating a DC voltage drop across the resistor ROCSET, which is given by Equation 5: V ROCSET = 8.5μA ⋅ R OCSET For example, if L is 1.5µH, DCR is 4.5mΩ, and ROCSET is 9kΩ, the choice of CSEN = 1.5µH/(9kΩ x 4.5mΩ) = 0.037µF. When an OCP fault is declared, the converter will be latched off and the PGOOD pin will be asserted low. The fault will remain latched until the EN pin has been pulled below the falling EN threshold voltage VENTHF or if VCC has decayed below the falling POR threshold voltage VVCC_THF. Overvoltage FIGURE 13. OVERCURRENT PROGRAMMING CIRCUIT V DCR = I L ⋅ DCR (EQ. 8) (EQ. 5) The DC voltage difference between the OCSET pin and the VO pin, given by Equation 6: The overvoltage (OV) detection circuit triggers after the FB pin voltage is above the rising overvoltage threshold VOVRTH for more than 2µs. For example, if the converter is programmed to regulate 1.0V at the FB pin, that voltage would have to rise above the typical VOVRTH threshold of 116% for more than 2µs to trigger an OV. In numerical terms, that would be 116% x 1.0V = 1.16V. When an OV is detected, the converter will take PGOOD low and continue to switching. The converter is not latched off. When the converter output voltage drops below the falling overvoltage threshold, VOVFTH, for more than 2µs then PGOOD is taken high again and the OV detection is considered cleared. 116% VOUT 102% V OCSET – V VO = V DCR – V ROCSET = I L ⋅ DCR – I OCSET ⋅ R OCSET PGOOD (EQ. 6) The IC monitors the voltage of the OCSET pin and the VO pin. When the voltage of the OCSET pin is higher than the voltage of the VO pin for more than 10µs, an OCP fault latches the converter off. MOSFET CCM/DCM OPERATION ENABLE The value of ROCSET is calculated with Equation 7, which is written as: I OC ⋅ DCR R OCSET = ---------------------------I OCSET (EQ. 7) Where: - ROCSET (Ω) is the resistor used to program the overcurrent setpoint - IOC is the output DC load current that will activate the OCP fault detection circuit - DCR is the inductor DC resistance For example, if IOC is 20A and DCR is 4.5mΩ, the choice of ROCSET is equal to 20A x 4.5mΩ/8.5µA = 10.5kΩ. Resistor ROCSET and capacitor CSEN form an R-C network to sense the inductor current. To sense the inductor current correctly not only in DC operation, but also during dynamic operation, the R-C network time constant ROCSET CSEN needs to match the inductor time constant L/DCR. The value of CSEN is then written as Equation 8: 11 FIGURE 14. OVERVOLTAGE OPERATION The falling overvoltage threshold VOVFTH is typically 102%. That means if the FB pin voltage falls below 102% x 1.0V = 1.02V for more than 2µs, the controller will return PGOOD high. Figure 14 shows a simple illustration of PGOOD operation during an OV detection event. The cross hatch portion of the PGOOD waveform shown represents the 2µs recognition time prior to the PGOOD transition. Undervoltage The UVP fault detection circuit triggers after the FB pin voltage is below the undervoltage threshold VUVTH for more than 2µs. For example, if the converter is programmed to regulate 1.0V at the FB pin, that voltage would have to fall below the typical VUVTH threshold of 84% for more than 2µs in order to trip the UVP fault latch. In numerical terms, that would be 84% x 1.0V = 0.84V. When a UVP fault is declared, the converter will be latched off and the PGOOD pin will be asserted low. The fault will remain latched until the EN pin has been pulled below the falling EN threshold voltage VENTHF or if VCC has decayed below the falling POR threshold voltage VVCC_THF. FN8390.0 December 10, 2012 ISL95873 Over-Temperature When the temperature of the IC increases above the rising threshold temperature TOTRTH, it will enter the OTP state that suspends the PWM, forcing the LGATE and UGATE gate-driver outputs low. The status of the PGOOD pin does not change nor does the converter latch-off. The PWM remains suspended until the IC temperature falls below the hysteresis temperature TOTHYS at which time normal PWM operation resumes. The OTP state can be reset if the EN pin is pulled below the falling EN threshold voltage VENTHF or if VCC has decayed below the falling POR threshold voltage VVCC_THF. All other protection circuits remain functional while the IC is in the OTP state. It is likely that the IC will detect an UVP fault because in the absence of PWM, the output voltage decays below the undervoltage threshold VUVTH. UGATE 1V 1V 1V 1V PGOOD Monitor LGATE The PGOOD pin indicates when the converter is capable of supplying regulated voltage. The PGOOD pin is an undefined impedance if the VCC pin has not reached the rising POR threshold VVCC_THR, or if the VCC pin is below the falling POR threshold VVCC_THF. If there is a fault condition of output overcurrent or undervoltage, PGOOD is asserted low. The PGOOD pull-down impedance is 50Ω. The PGOOD pin will transition low when an OV condition is detected, but will return high when the OV condition is removed. Integrated MOSFET Gate-Drivers The LGATE pin and UGATE pins are MOSFET driver outputs. The LGATE pin drives the low-side MOSFET of the converter while the UGATE pin drives the high-side MOSFET of the converter. The LGATE driver is optimized for low duty-cycle applications where the low-side MOSFET experiences long conduction times. In this environment, the low-side MOSFETs require exceptionally low rDS(ON) and tend to have large parasitic charges that conduct transient currents within the devices in response to high dv/dt switching present at the phase node. The drain-gate charge in particular can conduct sufficient current through the driver pull-down resistance that the VGS(th) of the device can be exceeded and turned on. For this reason, the LGATE driver has been designed with low pull-down resistance and high sink current capability to ensure clamping the MOSFETs gate voltage below VGS(th). Adaptive Shoot-Through Protection Adaptive shoot-through protection prevents a gate-driver output from turning on until the opposite gate-driver output has fallen below approximately 1V. The dead-time shown in Figure 15 is extended by the additional period that the falling gate voltage remains above the 1V threshold. The high-side gate-driver output voltage is measured across the UGATE and PHASE pins while the low-side gate-driver output voltage is measured across the LGATE and PGND pins. The power for the LGATE gate-driver is sourced directly from the PVCC pin. The power for the UGATE gate-driver is supplied by a boot-strap capacitor connected across the BOOT and PHASE pins. The capacitor is charged each time the phase node voltage falls a diode drop below PVCC such as when the low-side MOSFET is turned on. 12 FIGURE 15. GATE DRIVE ADAPTIVE SHOOT-THROUGH PROTECTION General Application Design Guide This design guide is intended to provide a high-level explanation of the steps necessary to design a single-phase buck converter. It is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following. In addition to this guide, Intersil provides complete reference designs that include schematics, bill of materials, and example board layouts. Selecting the LC Output Filter The duty cycle of an ideal buck converter is a function of the input and the output voltage. This relationship is expressed in Equation 9: VO D = --------V IN (EQ. 9) The output inductor peak-to-peak ripple current is expressed in Equation 10: VO ⋅ ( 1 – D ) I P-P = ------------------------------F SW ⋅ L (EQ. 10) A typical step-down DC/DC converter will have an IP-P of 20% to 40% of the maximum DC output load current. The value of IP-P is selected based upon several criteria, such as MOSFET switching loss, inductor core loss, and the resistive loss of the inductor winding. The DC copper loss of the inductor can be estimated using Equation 11: 2 P COPPER = I LOAD ⋅ DCR (EQ. 11) Where, ILOAD is the converter output DC current. The copper loss can be significant so close attention needs to be given to the DCR of the inductor. Another factor to consider when choosing the inductor is its saturation characteristics at elevated temperature. A saturated inductor could cause destruction of circuit components, as well as nuisance OCP faults. FN8390.0 December 10, 2012 ISL95873 A DC/DC buck regulator must have output capacitance CO into which ripple current IP-P can flow. Current IP-P develops a corresponding ripple voltage VP-P across CO, which is the sum of the voltage drop across the capacitor ESR and of the voltage change stemming from charge moved in and out of the capacitor. These two voltages are expressed in Equations 12 and 13: (EQ. 12) ΔV ESR = I P-P ⋅ E SR I P-P ΔV C = --------------------------------8 ⋅ CO ⋅ F (EQ. 13) SW If the output of the converter has to support a load with high pulsating current, several capacitors will need to be paralleled to reduce the total ESR until the required VP-P is achieved. The inductance of the capacitor can significantly impact the output voltage ripple and cause a brief voltage spike if the load transient has an extremely high slew rate. Low inductance capacitors should be considered. A capacitor dissipates heat as a function of RMS current and frequency. Be sure that IP-P is shared by a sufficient quantity of paralleled capacitors so that they operate below the maximum rated RMS current at FSW. Take into account that the rated value of a capacitor can fade as much as 50% as the DC voltage across it increases. Selecting the Input Capacitor Where: - IMAX is the maximum continuous ILOAD of the converter - x is a multiplier (0 to 1) corresponding to the inductor peak-to-peak ripple amplitude expressed as a percentage of IMAX (0% to 100%) - D is the duty cycle that is adjusted to take into account the efficiency of the converter Duty cycle is written as Equation 15: VO D = -------------------------V IN ⋅ EFF In addition to the bulk capacitors, some low ESL ceramic capacitors are recommended to decouple between the drain of the high-side MOSFET and the source of the low-side MOSFET. Selecting the Bootstrap Capacitor The integrated driver features an internal bootstrap Schottky diode. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. The bootstrap capacitor voltage rating is selected to be at least 10V. Although the theoretical maximum voltage of the capacitor is PVCC-VDIODE (voltage drop across the boot diode), large excursions below ground by the phase node requires at least a 10V rating for the bootstrap capacitor. The bootstrap capacitor can be chosen from Equation 16: Q GATE C BOOT ≥ -----------------------ΔV BOOT 0.6 (EQ. 15) (EQ. 16) NORMALIZED INPUT RMS RIPPLE CURRENT 0.5 Where: x=0 0.4 - QGATE is the amount of gate charge required to fully charge the gate of the upper MOSFET - ΔVBOOT is the maximum decay across the BOOT capacitor x = 0.5 0.3 0.2 x=1 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 DUTY CYCLE FIGURE 16. NORMALIZED INPUT RMS CURRENT FOR EFF = 1 The important parameters for the bulk input capacitors are the voltage rating and the RMS current rating. For reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and capable of supplying the RMS current required by the switching circuit. Their voltage rating should be at least 1.25x greater than the maximum input voltage, while a voltage rating of 1.5x is a preferred rating. Figure 16 is a graph of the input RMS ripple current, normalized relative to output load current, as a function of duty cycle that is adjusted for converter efficiency. The ripple current calculation is written as Equation 14: 2 2 D 2 2 ( I MAX ⋅ ( D – D ) ) + ⎛ x ⋅ I MAX ⋅ ------ ⎞ ⎝ 12 ⎠ I IN_RMS = -------------------------------------------------------------------------------------------------------I MAX 13 (EQ. 14) As an example, suppose the high-side MOSFET has a total gate charge Qg, of 25nC at VGS = 5V, and a ΔVBOOT of 200mV. The calculated bootstrap capacitance is 0.125µF; for a comfortable margin, select a capacitor that is double the calculated capacitance. In this example, 0.22µF will suffice. Use a low temperature-coefficient ceramic capacitor. Driver Power Dissipation Switching power dissipation in the driver is mainly a function of the switching frequency and total gate charge of the selected MOSFETs. Calculating the power dissipation in the driver for a desired application is critical to ensuring safe operation. Exceeding the maximum allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of +125°C. When designing the application, it is recommended that the following calculation be performed to ensure safe operation at the desired frequency for the selected MOSFETs. The power dissipated by the drivers is approximated as Equation 17: P = F sw ( 1.5V U Q + V L Q ) + P L + P U U L (EQ. 17) FN8390.0 December 10, 2012 ISL95873 Where: Fsw is the switching frequency of the PWM signal VU is the upper gate driver bias supply voltage VL is the lower gate driver bias supply voltage QU is the charge to be delivered by the upper driver into the gate of the MOSFET and discrete capacitors - QL is the charge to be delivered by the lower driver into the gate of the MOSFET and discrete capacitors - PL is the quiescent power consumption of the lower driver - PU is the quiescent power consumption of the upper driver - 1000 QU =100nC QL =200nC 900 QU =50nC QL =100nC QU =50nC QL=50nC 800 POWER (mW) V IN ⋅ I VALLEY ⋅ t ON ⋅ F V IN ⋅ I PEAK ⋅ t OFF ⋅ F SW SW P SW_HS = ---------------------------------------------------------------------- + -----------------------------------------------------------------2 2 (EQ. 20) Where: - IVALLEY is the difference of the DC component of the inductor current minus 1/2 of the inductor ripple current - IPEAK is the sum of the DC component of the inductor current plus 1/2 of the inductor ripple current - tON is the time required to drive the device into saturation - tOFF is the time required to drive the device into cut-off Layout Considerations 700 600 As a general rule, power layers should be close together, either on the top or bottom of the board, with the weak analog or logic signal layers on the opposite side of the board. The ground-plane layer should be adjacent to the signal layer to provide shielding. The ground plane layer should have an island located under the IC, the components connected to analog or logic signals. The island should be connected to the rest of the ground plane layer at one quiet point. QU =20nC QL=50nC 500 400 300 200 100 0 For the high-side MOSFET, its switching loss is written as Equation 20: 0 200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k FREQUENCY (Hz) FIGURE 17. POWER DISSIPATION vs FREQUENCY MOSFET Selection and Considerations The choice of MOSFETs depends on the current each MOSFET will be required to conduct, the switching frequency, the capability of the MOSFETs to dissipate heat, and the availability and nature of heat sinking and air flow. Typically, a MOSFET cannot tolerate even brief excursions beyond their maximum drain-to-source voltage rating. The MOSFETs used in the power stage of the converter should have a maximum VDS rating that exceeds the sum of the upper voltage tolerance of the input power source and the voltage spike that occurs when the MOSFETs switch. There are several power MOSFETs readily available that are optimized for DC/DC converter applications. The preferred high-side MOSFET emphasizes low gate charge so that the device spends the least amount of time dissipating power in the linear region. The preferred low-side MOSFET emphasizes low r DS(ON) when fully saturated to minimize conduction loss. For the low-side MOSFET, (LS), the power loss can be assumed to be conductive only and is written as Equation 18: 2 P CON_LS ≈ I LOAD ⋅ r DS ( ON )_LS ⋅ ( 1 – D ) (EQ. 18) For the high-side MOSFET, (HS), its conduction loss is written as Equation 19: 2 P CON_HS = I LOAD ⋅ r DS ( ON )_HS ⋅ D 14 (EQ. 19) There are two sets of components in a DC/DC converter; the power components and the small signal components. The power components are the most critical because they switch large amount of energy. The small signal components connect to sensitive nodes or supply critical bypassing current and signal coupling. The power components should be placed first and these include MOSFETs, input and output capacitors, and the inductor. Keeping the distance between the power train and the control IC short helps keep the gate drive traces short. These drive signals include the LGATE, UGATE, PGND, PHASE and BOOT. When placing MOSFETs, try to keep the source of the upper MOSFETs and the drain of the lower MOSFETs as close as thermally possible (see Figure 18). Input high frequency capacitors should be placed close to the drain of the upper MOSFETs and the source of the lower MOSFETs. Place the output inductor and output capacitors between the MOSFETs and the load. High frequency output decoupling capacitors (ceramic) should be placed as close as possible to the decoupling target, making use of the shortest connection paths to any internal planes. Place the components in such a way that the area under the IC has less noise traces with high dV/dt and di/dt, such as gate signals and phase node signals. VCC AND PVCC PINS Place the decoupling capacitors as close as practical to the IC. In particular, the PVCC decoupling capacitor should have a very short and wide connection to the PGND pin. The VCC decoupling capacitor should be referenced to GND pin. EN AND PGOOD PINS These are logic signals that are referenced to the GND pin. Treat as a typical logic signal. FN8390.0 December 10, 2012 ISL95873 VIASTO TO VIAS GROUND GROUND PLANE PLANE GND VOUT INDUCTOR INDUCTOR HIGH-SIDE MOSFETS HIGH-SIDE OSFETS OUTPUT APACITORS OUTPUT CAPACITORS SCHOTTKY SCHOTTKY IODE DIODE PHASE NODE VIN LOW-SIDE LOW-SIDE MOSFETS OSFETS INPUT INPUT APACITORS CAPACITORS FIGURE 18. TYPICAL POWER COMPONENT PLACEMENT OCSET AND VO PINS The current-sensing network consisting of ROCSET, RO, and CSEN needs to be connected to the inductor pads for accurate measurement of the DCR voltage drop. These components however, should be located physically close to the OCSET and VO pins with traces leading back to the inductor. It is critical that the traces are shielded by the ground plane layer all the way to the inductor pads. The procedure is the same for resistive current sense. FB, SREF, REFIN, AND RTN PINS The input impedance of these pins is high, making it critical to place the components connected to these pins as close as possible to the IC. LGATE, PGND, UGATE, BOOT, AND PHASE PINS The signals going through these traces are high dv/dt and high di/dt, with high peak charging and discharging current. The PGND pin can only flow current from the gate-source charge of the low-side MOSFETs when LGATE goes low. Ideally, route the trace from the LGATE pin in parallel with the trace from the PGND pin, route the trace from the UGATE pin in parallel with the trace from the PHASE pin. In order to have more accurate zero-crossing detection of inductor current, it is recommended to connect the PHASE pin to the drain of the low-side MOSFETs with Kelvin connection. These pairs of traces should be short, wide, and away from other traces with high input impedance; weak signal traces should not be in proximity with these traces on any layer. 15 FN8390.0 December 10, 2012 ISL95873 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION December 10, 2012 FN8390.0 CHANGE Initial Release. About Intersil Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. 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For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN8390.0 December 10, 2012 ISL95873 Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN) D L16.2.6x1.8A B 16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS 6 INDEX AREA 2X A N SYMBOL E 0.10 C 1 2 2X MIN NOMINAL MAX NOTES A 0.45 0.50 0.55 - A1 - - 0.05 - 0.10 C A3 TOP VIEW 0.10 C C A 0.05 C 0.127 REF - b 0.15 0.20 0.25 5 D 2.55 2.60 2.65 - E 1.75 1.80 1.85 - e 0.40 BSC - SEATING PLANE A1 SIDE VIEW K 0.15 - - - L 0.35 0.40 0.45 - L1 0.45 0.50 0.55 - N 16 2 Nd 4 3 Ne 4 3 e PIN #1 ID K 1 2 NX L L1 θ NX b 5 16X 0.10 M C A B 0.05 M C (DATUM B) (DATUM A) BOTTOM VIEW 0 - 4 12 Rev. 5 2/09 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on D and E side, respectively. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. CL (A1) NX (b) L 5 e SECTION "C-C" 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. TERMINAL TIP C C 8. Maximum allowable burrs is 0.076mm in all directions. 9. JEDEC Reference MO-255. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389. 3.00 1.80 1.40 1.40 2.20 0.90 0.40 0.20 0.50 0.20 0.40 10 LAND PATTERN 17 FN8390.0 December 10, 2012