1+$ + #$ 32K x 8 LOW POWER CMOS STATIC RAM FEATURES DESCRIPTION The 1+51 IC62C256 is a low power, 32,768 word by 8-bit CMOS static RAM. It is fabricated using 1+51 's high- Access time: 45, 70 ns Low active power: 200 mW (typical) Low standby power 250 µW (typical) CMOS standby 28 mW (typical) TTL standby Fully static operation: no clock or refresh required TTL compatible inputs and outputs Single 5V power supply performance, low power CMOS technology. When CS is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 250 µW (typical) at CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Select (CS) input and an active LOW Output Enable (OE) input. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IC62C256 is pin compatible with other 32K x 8 SRAMs in 330mil SOP or 8*13.4mm TSOP-1 package. FUNCTIONAL BLOCK DIAGRAM A0-A14 DECODER 32K X 8 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VCC GND I/O0-I/O7 CS OE CONTROL CIRCUIT WE ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. Integrated Circuit Solution Inc. ALSR010-0A 05/23/2001 1 1+$ + #$ PIN CONFIGURATION PIN CONFIGURATION 8x13.4mm TSOP-1 28-Pin SOP A14 1 28 VCC A12 2 27 WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CS A0 10 19 I/O7 I/O0 11 18 I/O6 I/O1 12 17 I/O5 I/O2 13 16 I/O4 GND 14 15 I/O3 PIN DESCRIPTIONS OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 21 20 19 18 17 16 15 14 13 12 11 10 9 8 22 23 24 25 26 27 28 1 2 3 4 5 6 7 A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 TRUTH TABLE A0-A14 Address Inputs Mode CS Chip Select Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Input/Output Vcc Power Not Selected (Power-down) Output Disabled Read Write GND Ground WE CS OE I/O Operation Vcc Current X H X High-Z ISB, ISB H H L L L L H L X High-Z DOUT DIN ICC, ICC ICC, ICC ICC, ICC ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TBIAS TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current (LOW) Value 0.5 to +7.0 55 to +125 65 to +150 0.5 20 Unit V °C °C W mA Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 Integrated Circuit Solution Inc. ALSR010-0A 05/23/2001 1+$ + #$ OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C 40°C to +85°C VCC 5V ± 10% 5V ± 10% DC ELECTRICAL CHARACTERISTICS Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Test Conditions VCC = Min., IOH = 1.0 mA VCC = Min., IOL = 2.1 mA Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled GND ≤ VIN ≤ VCC Com. Ind. Com. Ind. Min. 2.4 2.2 0.3 2 10 2 10 Max. 0.4 VCC + 0.5 0.8 2 10 2 10 Unit V V V V µA µA Note: 1. VIH=VCC +3.0V for pulse width less than 10ns. 2. VIL = 3.0V for pulse width less than 10 ns. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol ICC ICC ISB ISB Parameter Vcc Operating Supply Current Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., CS = VIL IOUT = 0 mA, f = 0 VCC = Max., CS = VIL IOUT = 0 mA, f = fMAX VCC = Max., VIN = VIH or VIL CS ≥ VIH, f = 0 VCC = Max., CS ≥ VCC 0.2V, VIN ≥ VCC 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. Com. Ind. Com. Ind. Com. Ind. -45 ns Min. Max. 60 70 70 80 5 10 0.5 1.0 -70 ns Min. Max. 60 70 65 75 5 10 0.5 1.0 Unit mA mA mA mA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 8 10 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V. Integrated Circuit Solution Inc. ALSR010-0A 05/23/2001 3 1+$ + #$ READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Min. -45 ns Max. -70 ns Min. Max. Unit tRC Read Cycle Time 45 70 ns tAA Address Access Time 45 70 ns tOHA Output Hold Time 2 2 ns tACS CS Access Time 45 70 ns tDOE OE Access Time 25 35 ns tLZOE OE to Low-Z Output 0 0 ns tHZOE OE to High-Z Output 0 20 0 25 ns CS to Low-Z Output 3 3 ns CS to High-Z Output 0 20 0 25 ns tPU! CS to Power-Up 0 0 ns tPD CS to Power-Down 30 50 ns tLZCS tHZCS ! Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 AC TEST LOADS 480 Ω 5V OUTPUT OUTPUT 100 pF Including jig and scope Figure 1. 4 480 Ω 5V 255 Ω 5 pF Including jig and scope 255 Ω Figure 2. Integrated Circuit Solution Inc. ALSR010-0A 05/23/2001 1+$ + #$ AC WAVEFORMS READ CYCLE NO. 1(1,2) t RC ADDRESS t AA t OHA t OHA DOUT DATA VALID PREVIOUS DATA VALID READ CYCLE NO. 2(1,3) t RC ADDRESS t AA t OHA OE t HZOE t DOE t LZOE CS t ACS t HZCS t LZCS DOUT HIGH-Z DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS = VIL. 3. Address is valid prior to or coincident with CS LOW transitions. Integrated Circuit Solution Inc. ALSR010-0A 05/23/2001 5 1+$ + #$ WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol -45 ns Min. Max. Parameter Min. -70ns Max. Unit tWC Write Cycle Time 45 70 ns tSCS CS to Write End 35 60 ns tAW Address Setup Time to Write End 25 60 ns tHA Address Hold from Write End 1 1 ns Address Setup Time 0 0 ns tPWE WE Pulse Width 25 55 ns tSD Data Setup to Write End 20 30 ns tHD Data Hold from Write End 0 0 ns tSA " Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CS LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 4. Tested with OE HIGH. AC WAVEFORMS WRITE CYCLE NO. 1(CS Controlled, OE is HIGH or LOW) (1 ) t WC VALID ADDRESS ADDRESS t SA t SCS t HA CS t AW t PWE1 t PWE2 WE t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN 6 t HD DATAIN VALID Integrated Circuit Solution Inc. ALSR010-0A 05/23/2001 1+$ + #$ AC WAVEFORMS WRITE CYCLE NO. 2(OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS t HA OE CS LOW t AW t PWE1 WE t SA DOUT t HZWE t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN WRITE CYCLE NO. 3(OE is LOW During Write Cycle) (1) t WC ADDRESS VALID ADDRESS OE LOW CS LOW t HA t AW t PWE2 WE t SA DOUT DATA UNDEFINED t HZWE t LZWE HIGH-Z t SD DIN t HD DATAIN VALID Notes: 1. The internal write time is defined by the overlap of Cs LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 2. I/O will assume the High-Z state if OE ≥ VIH. Integrated Circuit Solution Inc. ALSR010-0A 05/23/2001 7 1+$ + #$ DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. Max. Unit VDR Vcc for Data Retention See Data Retention Waveform 2.0 5.5 V IDR Data Retention Current Vcc =2.0V, CE ≥ Vcc 0.2V 250 500 µA tSDR Data Retention Setup Time See Data Retention Waveform 0 ns tRDR Recovery Time See Data Retention Waveform 5 ns DATA RETENTION WAVEFORM tSDR Com. Ind. (CE Controlled) Data Retention Mode tRDR VCC 5.0V 3.0V VDR CE GND 8 CE ≥ VCC - 0.2V Integrated Circuit Solution Inc. ALSR010-0A 05/23/2001 1+$ + #$ ORDERING INFORMATION Commerical Range: 0°C to +70°C Speed (ns) Order Part No. Package 45 IC62C256-45T IC62C256-45U 8*13.4mm TSOP-1 330mil SOP 70 IC62C256-70T IC62C256-70U 8*13.4mm TSOP-1 330mil SOP Integrated Circuit Solution Inc. ALSR010-0A 05/23/2001 ORDERING INFORMATION Industrial Range: 40°C to +85°C Speed (ns) Order Part No. Package 45 IC62C256-45TI IC62C256-45UI 8*13.4mm TSOP-1 330mil SOP 70 IC62C256-70TI IC62C256-70UI 8*13.4mm TSOP-1 330mil SOP 9 1+$ + #$ Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw 10 Integrated Circuit Solution Inc. ALSR010-0A 05/23/2001