IDT MCR03EZPJ000 Wireless power receiver for 15w application Datasheet

Wireless Power Receiver
for 15W Applications
P9221-R
Datasheet
Description
Features
The P9221-R is a high efficiency, Qi-compliant wireless power
receiver targeted for applications up to 15W. Using magnetic
inductive charging technology, the receiver converts an AC power
signal from a resonant tank into a regulated DC output voltage
setting with 9V and 12V. The integrated, low RDS (ON) synchronous rectifier and ultra-low dropout offer high efficiency making
the product ideally suited for battery-operated applications.

The P9221-R includes an industry-leading 32 bit ARM® Cortex®M0 processor offering a high level of programmability. In addition,
the device features proprietary alignment guide information for
optimum coupling between the receiver and the transmitter, a
programmable current limit, and a patented over-voltage protection
scheme eliminating the need for additional capacitors generally
used by the receivers, minimizing the external component count
and cost. Together with the P9242-R transmitter (TX), the P9221-R
is a complete wireless power system solution for power
applications up to 15W.


Single-chip solution supporting up to 15W applications
WPC-1.2.3 compliant
Patented over-voltage protection clamp eliminating external
capacitors
87% peak DC-to-DC efficiency with P9242-R TX
Proprietary coil alignment guide
Full synchronous rectifier with low RDS(ON) switches
Programmable output voltage: 9V and 12V
Embedded 32-bit ARM® Cortex®-M0 processor
Dedicated remote temperature sensing
Power transfer LED indicator
Programmable current limit
Active-low enable pin for electrical on/off
Open-drain interrupt flag
Supports I2C interface
0 to +85°C ambient operating temperature range

52-WLCSP (2.64  3.94 mm; 0.4mm pitch)












The P9221-R is available in a 52-WLCSP package and it is rated
for a 0 to 85°C ambient operating temperature range.
Typical Applications
Typical Application Circuit
Fast charge cellphone
 Tablets
 Accessories
 Medical

COMM1
CS
INT
AC1
SDA
P9221-R
SCL
AC2
© 2017 Integrated Device Technology, Inc.
1
GND
VDD18
VDD5V
BST2
OUT
VRECT
COMM2
LS
THM
RPPG
ILIM
RPPO
VSET
ALIGNY
BST1
ALIGNX
Programming
Resistors
COUT
April 4, 2017
P9221-R Datasheet
Contents
1.
Pin Assignments ...........................................................................................................................................................................................5
2.
Pin Descriptions............................................................................................................................................................................................5
3.
Absolute Maximum Ratings ..........................................................................................................................................................................8
4.
Thermal Characteristics................................................................................................................................................................................9
5.
Electrical Characteristics ..............................................................................................................................................................................9
6.
Typical Performance Characteristics ..........................................................................................................................................................12
7.
Function Block Diagram .............................................................................................................................................................................15
8.
Theory of Operation....................................................................................................................................................................................16
8.1
LDO – Low Dropout Regulators .......................................................................................................................................................16
8.2
Setting the Output Voltage – VOSET ...............................................................................................................................................16
8.3
SINK Pin ..........................................................................................................................................................................................17
8.4
Rectifier Voltage – VRECT...............................................................................................................................................................17
8.5
Over-Current Limit – ILIM.................................................................................................................................................................17
8.6
Interrupt Function – INT ...................................................................................................................................................................17
8.7
Enable Pin – EN ...............................................................................................................................................................................17
8.8
Thermal Protection ...........................................................................................................................................................................17
8.9
External Temperature Sensing – TS ................................................................................................................................................17
8.10 Alignment Guide – ALIGNX and ALIGNY ........................................................................................................................................18
8.11 Received Power Packet Offset and Gain Calibration – RPPO and RPPG ......................................................................................18
8.12 Advanced Foreign Object Detection (FOD) .....................................................................................................................................18
9.
Communication Interface............................................................................................................................................................................20
9.1
Modulation/Communication..............................................................................................................................................................20
9.2
Bit Encoding Scheme for ASK .........................................................................................................................................................21
9.3
Byte Encoding for ASK.....................................................................................................................................................................21
9.4
Packet Structure ..............................................................................................................................................................................21
10. WPC Mode Characteristics ........................................................................................................................................................................22
10.1 Selection Phase or Startup ..............................................................................................................................................................22
10.2 Ping Phase (Digital Ping) .................................................................................................................................................................22
10.3 Identification and Configuration Phase ............................................................................................................................................23
10.4 Negotiation Phase ............................................................................................................................................................................23
10.5 Calibration Phase .............................................................................................................................................................................23
10.6 Power Transfer Phase .....................................................................................................................................................................23
11. Functional Registers ...................................................................................................................................................................................24
12. Application Information ...............................................................................................................................................................................29
12.1 Power Dissipation and Thermal Requirements ................................................................................................................................29
12.2 Recommended Coils ........................................................................................................................................................................29
12.3 Typical Application Schematic .........................................................................................................................................................30
12.4 Bill of Materials (BOM) .....................................................................................................................................................................31
© 2017 Integrated Device Technology, Inc.
2
April 4, 2017
P9221-R Datasheet
13. Package Drawings......................................................................................................................................................................................32
14. Recommended Land Pattern ......................................................................................................................................................................33
15. Special Notes: AHG52 WLCSP-52 Package Assembly .............................................................................................................................34
16. Marking Diagram ........................................................................................................................................................................................34
17. Ordering Information...................................................................................................................................................................................34
18. Revision History..........................................................................................................................................................................................35
List of Figures
Figure 1. Pin Assignments ..................................................................................................................................................................................5
Figure 2. Efficiency vs. Output Load: VOUT = 12V .............................................................................................................................................12
Figure 3. Load Reg. vs. Output Load: VOUT = 12V ............................................................................................................................................12
Figure 4. Efficiency vs. Output Load: VOUT = 9V ...............................................................................................................................................12
Figure 5. Load Reg. vs. Output Load: VOUT = 9V ..............................................................................................................................................12
Figure 6. Efficiency vs. Output Load: VOUT = 5V ...............................................................................................................................................12
Figure 7. Load Reg. vs. Output Load: VOUT = 5V ..............................................................................................................................................12
Figure 8. Rectifier Voltage vs. Load: VOUT = 12V ..............................................................................................................................................13
Figure 9. Rectifier Voltage vs. Load: VOUT = 9V ................................................................................................................................................13
Figure 10. Rectifier Voltage vs. Load: VOUT = 5V ................................................................................................................................................13
Figure 11. Current Limit vs. VILIM ........................................................................................................................................................................13
Figure 12. X and Y Misalignment........................................................................................................................................................................13
Figure 13. Max. Power vs. Misalignment: VOUT=12V ..........................................................................................................................................13
Figure 14. Enable Startup: VOUT = 12V; IOUT = 1.2A ............................................................................................................................................14
Figure 15. Transient Resp: VOUT = 12V; IOUT = 0 to 1.2A ....................................................................................................................................14
Figure 16. Transient Resp: VOUT = 12V; IOUT = 1.3A to 0 ....................................................................................................................................14
Figure 17. Functional Block Diagram ..................................................................................................................................................................15
Figure 18. Example of Differential Bi-phase Decoding for FSK ..........................................................................................................................20
Figure 19. Example of Asynchronous Serial Byte Format for FSK .....................................................................................................................20
Figure 20. Bit Encoding Scheme ........................................................................................................................................................................21
Figure 21. Byte Encoding Scheme .....................................................................................................................................................................21
Figure 22. Communication Packet Structure ......................................................................................................................................................21
Figure 23. WPC Power Transfer Phases Flowchart ...........................................................................................................................................22
Figure 24. P9221-R Typical Application Schematic ............................................................................................................................................30
Figure 25. Package Outline Drawing ..................................................................................................................................................................32
Figure 26. AHG52 52-WLCSP Land Pattern ......................................................................................................................................................33
© 2017 Integrated Device Technology, Inc.
3
April 4, 2017
P9221-R Datasheet
List of Tables
Table 1.
Pin Descriptions...................................................................................................................................................................................5
Table 2.
Absolute Maximum Ratings .................................................................................................................................................................8
Table 3.
ESD Information ..................................................................................................................................................................................8
Table 4.
Package Thermal Information .............................................................................................................................................................9
Table 5.
Electrical Characteristics .....................................................................................................................................................................9
Table 6.
Setting the Output Voltage ................................................................................................................................................................16
Table 7.
Maximum Estimated Power Loss ......................................................................................................................................................19
Table 8.
Device Identification Register ............................................................................................................................................................24
Table 9.
Firmware Major Revision ...................................................................................................................................................................24
Table 10. Firmware Minor Revision ...................................................................................................................................................................24
Table 11. Status Registers ................................................................................................................................................................................24
Table 12. Interrupt Status Registers ..................................................................................................................................................................25
Table 13. Interrupt Enable Registers .................................................................................................................................................................25
Table 14. Battery Charge Status .......................................................................................................................................................................25
Table 15. End Power Transfer...........................................................................................................................................................................26
Table 16. Read Register – Output Voltage ........................................................................................................................................................26
Table 17. Read Register – VRECT Voltage ......................................................................................................................................................26
Table 18. Read Register – IOUT Current ..........................................................................................................................................................26
Table 19. Read Register – Die Temperature .....................................................................................................................................................27
Table 20. Read Register – Operating Frequency ..............................................................................................................................................27
Table 21. Alignment X Value Register ...............................................................................................................................................................27
Table 22. Alignment Y Value Register...............................................................................................................................................................27
Table 23. Command Register............................................................................................................................................................................28
Table 24. Recommended Coil Manufacturers ...................................................................................................................................................29
Table 25. P9221-R MM Evaluation Kit V2.1 Bill of Materials .............................................................................................................................31
© 2017 Integrated Device Technology, Inc.
4
April 4, 2017
P9221-R Datasheet
1. Pin Assignments
Figure 1.
Pin Assignments
6
5
4
3
2
COMM2
RPPG
VOSET
SCL
1
ALIGNX COMM1
A
RSV5
EN
ILIM
ALIGNY
SDA
RSV4
B
GND
DEN
RPPO
INT
SINK
GND
C
OUT
OUT
OUT
OUT
OUT
OUT
D
VRECT
VRECT
VRECT
VRECT
E
VDD18
VRECT
VRECT
VRECT
VRECT
VDD5V
F
BST2
AC2
RSV1
RSV3
AC1
BST1
G
AC2
AC2
TS
RSV2
AC1
AC1
H
GND
GND
GND
GND
GND
GND
J
Bottom View
2. Pin Descriptions
Table 1.
Pin Descriptions
Pins
Name
Type
A1
COMM1
O
Open-drain output used to communicate with the transmitter. Connect a 47nF capacitor from
AC1 to COMM1.
A2
ALIGNX
I
AC input for coil alignment guide. If not used, connect to GND through a 10kΩ resistor.
A3
SCL
I
I2C clock pin. Open-drain output. Connect a 5.1kΩ resistor to VDD18 pin.
A4
VOSET
I
Programming pin for setting the output voltage. Connect this pin to the center tap of a resistor
divider to set the output voltage. For more information, refer to section 8.2 for different output
voltage settings.
© 2017 Integrated Device Technology, Inc.
Function
5
April 4, 2017
P9221-R Datasheet
Pins
Name
Type
Function
A5
RPPG
I
Received power packet gain (RPPG) calibration pin for foreign object detection (FOD) tuning.
Connect this pin to the center tap of a resistor divider to set the gain of the FOD. The FOD is
disabled by connecting the center tap of two 10kΩ resistors to VDD18 pin and GND.
A6
COMM2
O
Open-drain output used to communicate with the transmitter. Connect a 47nF capacitor from
AC2 to COMM2.
B1
RSV4
B2
ALIGNY
I
B3
SDA
I/O
B4
ILIM
I
Programmable over-current limit pin. Connect this pin to the center tap of a resistor divider to
set the current limit. For more information about the current limit function, see section 8.5.
B5
̅̅̅̅
EN
I
Active-LOW enable pin. Pulling this pin to logic HIGH forces the device into Shut Down Mode.
When connected to logic LOW, the device is enabled. Do not leave this pin floating.
B6
RSV5
C1, C6, J1, J2,
J3,J4,J5,J6
GND
GND
C2
SINK
O
Open-drain output for controlling the rectifier clamp. Connect a 36Ω resistor from this pin to
the VRECT pin.
C3
̅̅̅̅
INT
O
Interrupt flag pin. This is an open-drain output that signals fault interrupts. It is pulled LOW if
any of these faults exists: an over-voltage is detected, an over-current condition is detected,
the die temperature exceeds 140°C, or an external over-temperature condition is detected on
the TS pin. It is also asserted LOW when EN is HIGH. Connect to VDD18 through a 10kΩ
resistor. See section 8.6 for additional conditions affecting the interrupt flag.
C4
RPPO
O
Received power packet offset (RPPO) calibration pin for FOD tuning. Connect to the center
tap of the resistor divider to set the offset of the FOD. The FOD is disabled by connecting the
center tap of two 10kΩ resistors to VDD18 pin and GND.
C5
DEN
I
Reserved. Must connect a 10kΩ resistor to the VDD18 pin.
D1, D2, D3,
D4, D5, D6
OUT
O
Regulated output voltage pin. Connect three 10μF capacitors from this pin to GND. The default
voltage is set to 12V when the VOSET pin is pulled up to VDD18 pin through a 10kΩ resister.
For more information about VOSET, see section 8.2.
E1, E2, E5, E6
F2, F3, F4, F5
VRECT
O
Output voltage of the synchronous rectifier bridge. Connect three 10μF capacitors from this pin
to GND. The rectifier voltage dynamically changes as the load changes. For more information,
see the typical waveforms in section 6.
F1
VDD5V
O
Internal 5V regulator output voltage for internal use. Connect a 1μF capacitor from this pin to
ground. Do not load the pin.
F6
VDD18
O
Internal 1.8V regulator output voltage. Connect a 1μF capacitor from this pin to ground. Do not
load the pin.
G1
BST1
O
Boost capacitor for driving the high-side switch of the internal rectifier. Connect a 15nF
capacitor from the AC1 pin to BST1.
G2, H1, H2,
AC1
I
AC input power. Connect to the resonant capacitor (CS).
G3
RSV3
I
Reserved pins. Must be connected to GND.
Reserved for internal use. Do not connect.
AC input for coil alignment guide. If not used, connect to GND through a 10KΩ resistor.
I2C data pin. Open-drain output. Connect a 5.1kΩ resistor to VDD18 pin.
Reserved for internal use. Do not connect.
© 2017 Integrated Device Technology, Inc.
Ground.
6
April 4, 2017
P9221-R Datasheet
Pins
Name
Type
Function
G4
RSV1
G5, H5, H6
AC2
I
AC input power. Connect to the Rx coil (LS).
G6
BST2
O
Boost capacitor for driving the high-side switch of the internal rectifier. Connect a 15nF
capacitor from the AC2 pin to BST2.
H3
RSV2
H4
TS
Reserved for internal use. Do not connect.
Reserved pins. Must be connected to GND.
I
© 2017 Integrated Device Technology, Inc.
Remote temperature sensor for over-temperature shutdown. Connect to the NTC thermistor
network. If not used, connect to VDD18 pin through the 10kΩ resistor.
7
April 4, 2017
P9221-R Datasheet
3. Absolute Maximum Ratings
Stresses greater than those listed as absolute maximum ratings in Table 2 could cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods might affect reliability.
Table 2.
Absolute Maximum Ratings
Pins [ a ]
Rating [ b ]
Units
AC1 [c], AC2 [c], COMM1, COMM2
-0.3 to 20
V
̅̅̅̅
EN
-0.3 to 28
V
SINK, VRECT
-0.3 to 24
V
DEN, ILIM, RPPG, RPPO, VDD18, VOSET
-0.3 to 2
V
̅̅̅̅, SCL, SDA, TS, VDD5V
ALIGNX, ALIGNY, INT
-0.3 to 6
V
-0.3 to AC1+6, AC2+6
V
-0.3 to 14.4
V
1
A
500
mA
2
A
BST1, BST2
OUT
Maximum Current on SINK
Maximum RMS Current on COMM1, COMM2
Maximum RMS Current from AC1, AC2
[a] Absolute maximum ratings are not provided for reserved pins (RSV1, RSV2, RSV3, RSV4, RSV5, and DEN). These pins
are not used in the application.
[b] All voltages are referred to ground unless otherwise noted.
[c] During synchronous rectifier dead time, the voltage on the AC1 and AC2 pins is developed by current across the power
FET’s body diodes, and it might be lower than -0.3 V. This is a normal behavior and does not negatively impact the
functionality or reliability of the product.
Table 3.
ESD Information
Test Model
HBM
CDM
Pins
Ratings
Units
All pins except RSV2 and RSV3
2
kV
RSV2, RSV3 pins
1
kV
500
V
All pins
© 2017 Integrated Device Technology, Inc.
8
April 4, 2017
P9221-R Datasheet
4. Thermal Characteristics
Table 4.
Package Thermal Information
Note: This thermal rating was calculated on a JEDEC 51 standard 4-layer board with dimensions 76.2 x 114.3 mm in still air conditions.
Symbol
Description
WLCSP Rating 8 Thermal Balls
Units
47
C/W
θJA
Thermal Resistance Junction to Ambient [a]
θJC
Thermal Resistance Junction to Case
0.202
C/W
θJB
Thermal Resistance Junction to Board
4.36
C/W
TJ
Operating Junction Temperature[a]
-5 to +125
C
TA
Ambient Operating Temperature [a]
0 to +85
C
-55 to +150
C
260
C
TSTG
Storage Temperature
TBUMP
Maximum Soldering Temperature (Reflow, Pb-Free)
[a] The maximum power dissipation is PD(MAX) = (TJ(MAX) - TA) / θJA where TJ(MAX) is 125°C. Exceeding the maximum allowable power dissipation will
result in excessive die temperature, and the device will enter thermal shutdown.
5. Electrical Characteristics
Table 5.
Electrical Characteristics
̅̅̅̅ = LOW, unless otherwise noted. TJ = 0C to 125C; typical values are at 25°C.
Note: VRECT = 5.5V; COUT = 4.7μF, EN
Symbol
Description
Conditions
Min
Typical
Max
Units
2.98
V
Under-Voltage Lock-Out (UVLO)
VUVLO_Rising
UVLO Rising
Rising voltage on VRECT
2.9
VUVLO_HYS
UVLO Hysteresis
VRECT falling
200
mV
Rising voltage
13.5
V
1
V
Over-Voltage Protection
VOVP-DC
DC Over-Voltage
Protection
VOVP-HYS
Over-Voltage Hysteresis
Quiescent Current
IACTIVE_SUPLY
Supply Current
EN
¯¯ = Low, No load; VRECT = 12.3V
3.0
mA
ISHD
Shut Down Mode Current
EN
¯¯ = High; VRECT = 12.3V
500
μA
VDD18 Pin Output
Voltage [a]
IVDD18 = 10mA, CVDD18 = 1µF
VDD18 Voltage
VVDD18
© 2017 Integrated Device Technology, Inc.
9
1.62
1.8
1.98
V
April 4, 2017
P9221-R Datasheet
Symbol
Description
Conditions
Min
Typical
Max
Units
4.5
5
5.5
V
VDD5V Voltage
VVDD5V
VDD5V Pin Output
Voltage [a]
IVDD5V = 10mA, CVDD5V = 1µF
Low Drop-Out (LDO) Regulator
IOUT_MAX
Maximum Output Current
VOUT_12V
12V Output Voltage
VOUT_9V
9V Output Voltage
1.25
A
VOSET > 1.5V, VRECT=12.3V
12
V
0.7V < VOSET < 1.2V, VRECT=9.3V
9
V
12
Bit
67.5
kSa/s
Analog to Digital Converter
N
Resolution
fSAMPLE
Sampling Rate
Channel
Number of Channels
VIN,FS
Full-Scale Input Voltage
8
2.1
V
̅̅̅̅ pin
EN
VIH
Input Threshold HIGH
1.4
VIL
Input Threshold LOW
IIL
Input Current LOW
VEN
¯¯ = 0V
IIH
Input Current HIGH
VEN
¯¯ = 5V
V
-1
0.25
V
1
μA
2.5
μA
VOSET, ILIM, TS, RPPO, RPPG
IIL
Input Current LOW
VVOSET, VILIM, VTS, VRPPO, VRPPG = 0V
-1
1
µA
IIH
Input Current HIGH
VVOSET, VILIM, VTS, VRPPO, VRPPG = 1.8V
-1
1
µA
-1
1
µA
0.36
V
0.7
V
̅̅̅̅ pins
ALIGNX, ALIGNY and INT
ILKG
Input Leakage Current
VALIGNX, VALIGNY, VINT = 0V and 5V
VOL
Output Logic LOW
IOL = 8mA
I2C Interface – SCL, SDA
VIL
Input Threshold LOW
VIH
Input Threshold HIGH
ILKG
Input Leakage Current
VSCL, VSDA = 0V and 5V
VOL
Output Logic LOW
IOL = 8mA
fSCL
Clock Frequency
tHD,STA
Hold Time (Repeated) for
START Condition
tHD:DAT
Data Hold Time
tLOW
tHIGH
1.4
-1
V
1
µA
0.36
V
400
kHz
0.6
µs
0
ns
Clock Low Period
1.3
µs
Clock High Period
0.6
µs
© 2017 Integrated Device Technology, Inc.
10
April 4, 2017
P9221-R Datasheet
Symbol
Description
Conditions
Min
Typical
Max
Units
tSU:STA
Set-up Time for Repeated
START Condition
0.6
µs
tBUF
Bus Free Time Between
STOP and START
Condition
1.3
µs
CB
Capacitive Load for each
Bus Line
CI
SCL, SDA Input
Capacitance
150
pF
5
pF
Rising [b]
140
°C
Falling
120
°C
Thermal Shutdown
TSD
[a]
[b]
Thermal Shutdown
Do not externally load. For internal biasing only.
If the die temperature exceeds 130°C, the Thermal_SHTDN_Status flag is set and an end power transfer (EPT) packet is sent (see Table 11).
© 2017 Integrated Device Technology, Inc.
11
April 4, 2017
P9221-R Datasheet
6. Typical Performance Characteristics
The following performance characteristics were taken using a P9242-R, 15 W wireless power transmitter at TA = 25°C unless otherwise noted.
Figure 2.
Efficiency vs. Output Load: VOUT = 12V
Figure 3.
100
Load Reg. vs. Output Load: VOUT = 12V
12.4
85°C
65°C
25°C
0°C
-25°C
-40°C
12.3
90
VOUT [V]
Efficiency [%]
12.2
80
70
60
12.1
12
11.9
11.8
50
11.7
40
11.6
0.1
0.3
0.5
0.7
0.9
1.1
1.3
0.1
0.3
OUTPUT CURRENT [A]
Efficiency vs. Output Load: VOUT = 9V
Figure 5.
90
85
80
75
70
65
60
55
50
45
40
0.9
1.1
1.3
Load Reg. vs. Output Load: VOUT = 9V
9.4
85°C
9.3
65°C
9.2
25°C
9.1
0°C
9.0
8.9
8.8
8.7
8.6
0.1
0.3
0.5
0.7
0.9
1.1
1.3
0.1
0.3
0.5
OUTPUT CURRENT [A]
Figure 6.
Efficiency vs. Output Load: VOUT = 5V
Figure 7.
90
85
80
75
70
65
60
55
50
45
40
0.1
0.3
0.5
0.7
0.9
1.1
0.9
1.1
1.3
Load Reg. vs. Output Load: VOUT = 5V
5.50
5.40
5.30
5.20
5.10
5.00
4.90
4.80
4.70
4.60
4.50
85°C
65°C
25°C
0°C
0.1
OUTPUT CURRENT [A]
© 2017 Integrated Device Technology, Inc.
0.7
OUTPUT CURRENT[A]
VOUT [V]
Efficiency [%]
0.7
OUTPUT CURRENT[A]
VOUT [V]
Efficiency [%]
Figure 4.
0.5
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
OUTPUT CURRENT[A]
12
April 4, 2017
P9221-R Datasheet
Figure 8.
Rectifier Voltage vs. Load: VOUT = 12V
13.2
12.4
VRECT [V]
85°C
65°C
25°C
0°C
-25°C
-40°C
12.8
12
11.6
0.1
0.3
0.5
0.7
0.9
1.1
Rectifier Voltage vs. Load: VOUT = 9V
10.0
9.9
9.8
9.7
9.6
9.5
9.4
9.3
9.2
9.1
9.0
8.9
8.8
1.3
85°C
65°C
25°C
0°C
0.1
0.3
0.5
OUTPUT CURRENT[A]
Figure 10. Rectifier Voltage vs. Load: VOUT = 5V
6.2
6.1
6.0
5.9
5.8
5.7
5.6
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
1.1
1.3
1600
85°C
1400
65°C
1200
25°C
0°C
1000
800
600
400
200
0
0.1
0.3
0.5
0.7
0.9
1.1
0
0.1
0.2
0.3
0.4
OUTPUT CURRENT[A]
0.5
0.6
0.7
0.8
0.9
1
VILIM [V]
Figure 12. X and Y Misalignment
Figure 13. Max. Power vs. Misalignment: VOUT=12V
120
100
18
16
100
90
80
EFFICIENCY [%]
Register Values
0.9
Figure 11. Current Limit vs. VILIM
ILIM [mA]
VRECT [V]
0.7
OUTPUT CURRENT[A]
60
X-Align
40
14
12
80
10
8
70
6
EFFICIENCY
Y-Align
60
20
0
4
OUTPUT POWER
50
0
2
4
6
8
10
12
© 2017 Integrated Device Technology, Inc.
2
0
-12 -10 -8
Misalignment [mm]
OUTPUT POWER [W]
VRECT [V]
Figure 9.
-6
-4
-2
0
2
4
6
8
10 12
Misalignment [mm]
13
April 4, 2017
P9221-R Datasheet
Figure 14. Enable Startup: VOUT = 12V; IOUT = 1.2A
Figure 15. Transient Resp: VOUT = 12V; IOUT = 0 to 1.2A
Figure 16. Transient Resp: VOUT = 12V; IOUT = 1.3A to 0
© 2017 Integrated Device Technology, Inc.
14
April 4, 2017
P9221-R Datasheet
7. Function Block Diagram
Figure 17. Functional Block Diagram
VRECT
BST2
LDO
5V
VDD5V
EN
EN
LDO
1.8V
VDD18
VRECT
VOUT
ISNS
VTDIE
ADC
ASK Modulator
COMM1
COMM2
OUT
UVLO
FSK
Demodulator
AC2
LDO
OVP
ISNS
AC1
SINK
UVLO
Synchronous Rectifier Control
Block
BST1
MUX
ILIM
VOSET
32-bit ARM
Processor
RPPO
RPPG
TS
I2C
Slave
SCL
SDA
ALIGNX
AC1
Peak detector
and LPF
Phase detector
ALIGNY
RSVx
INT
DEN
EN
GND
EN
© 2017 Integrated Device Technology, Inc.
15
April 4, 2017
P9221-R Datasheet
8. Theory of Operation
The P9221-R is a highly-integrated, wireless power receiver targeted for 15W applications. The device integrates a full-wave synchronous
rectifier, low-dropout (LDO) linear regulator, and a 32-bit ARM®-based M0 processor to manage all the digital control required to comply with
the WPC-1.2.2 communication protocol.
The rectifier voltage and the output current are sampled periodically and digitized by the analog-to-digital converter (ADC). The digital
equivalents of the voltage and current are supplied to the internal control logic, which determines whether the loading conditions on the VRECT
pin indicate that a change in the operating point is required. If the load is heavy enough and brings the voltage at VRECT below its target, the
transmitter is set to a lower frequency that is closer to resonance and to a higher output power. If the voltage at VRECT is higher than its target,
the transmitter is instructed to increase its frequency. To maximize efficiency, the voltage at VRECT is programmed to decrease as the LDO’s
load current increases. The internal temperature is continuously monitored to ensure proper operation.
In the event that the VRECT voltage increases above 13.5V, the control loop disables the LDO and sends error packets to the transmitter in an
attempt to bring the rectifier voltage back to a safe operating voltage level while simultaneously clamping the incoming energy using the
open-drain SINK pin for VRECT linear clamping. The clamp is released when the VRECT voltage falls below the VOVP-DC minus VOVP-HYS. See
Figure 17.
The receiver utilizes IDT’s proprietary voltage clamping scheme, which limits the maximum voltage at the rectifier pin to 13.5V, reducing the
voltage rating on the output capacitors while eliminating the need for over-voltage protection (OVP) capacitors. As a result, it provides a small
application area, making it an industry-leading wireless power receiver for high power density applications. Combined with the P9242-R
transmitter, the P9221-R is a complete wireless power system solution.
8.1
LDO – Low Dropout Regulators
The P9221-R has three low-dropout linear regulators. The main regulator is used to provide the power required by the battery charger where
the output voltage can be set to either 9V or 12V. For more information about setting the output voltage, see section 8.2. It is important to
connect a minimum of 30µF ceramic capacitance to the OUT pin.
The other two regulators, VDD5V and VDD18, are to bias the internal circuitry of the receiver. The LDOs must have local 1µF ceramic capacitors
placed as close as possible to the pins.
8.2
Setting the Output Voltage – VOSET
The output voltage on the P9221-R is programmed by connecting the center tap of the external resistors R34 and R33 to the VOSET pin as
shown in the application schematic in Figure 24. There are only two voltages available: 9.0V or 12V. The recommended settings for R33 and
R34 are summarized in Table 6.
The default output voltage is set to 12V in the P9221-R Evaluation Board. For applications where the transmitter is capable of delivering only
5W, the P9221-R will automatically switch to 5V to ensure 5W power delivery. The 5W option can be disabled by adding R33 as described in
Table 6.
Table 6.
Setting the Output Voltage
R34 (kΩ)
R33 (kΩ)
Output Voltage (V)
5V Output Option
10
OPEN
12
Enable
10
30
12
Disable
OPEN
10
9
Enable
10
3.3
9
Disable
© 2017 Integrated Device Technology, Inc.
16
April 4, 2017
P9221-R Datasheet
8.3
SINK Pin
The P9221-R has an internal automatic DC clamping to protect the device in the event of high voltage transients. The VRECT node must be
connected to the SINK pin at all times using a 36Ω resistor with a greater than ¼ W rating.
8.4
Rectifier Voltage – VRECT
The P9221-R uses a high‐efficiency synchronous rectifier to convert the AC signal from the coil to a DC signal on the VRECT pin. During startup,
the rectifier operates as a passive diode bridge. Once the voltage on VRECT exceeds the under-voltage lock-out level (UVLO; see Table 5),
the rectifier will switch into full synchronous bridge rectifier mode. A total capacitance of 30μF is recommended to minimize the output voltage
ripple.
8.5
Over-Current Limit – ILIM
The P9221-R has a programmable current limit function for protecting the device in the event of an over-current or short-circuit fault condition.
When the output current exceeds the programmed threshold, the P9221-R will limit the load current by reducing the output voltage. The current
limit should be set to 130% of the target maximum output current. See the ILIM pin description in Table 1 for further information.
8.6
Interrupt Function – ̅̅̅̅̅̅
INT
The P9221-R provides an open-drain, active-LOW interrupt output pin. It is asserted LOW when EN is HIGH or any of the following fault
conditions have been triggered: the die temperature exceeds 140°C, the external thermistor measurement exceeds the threshold (see section
8.9), or an over-current (OC) or over-voltage (OV) condition is detected.
During normal operation, the INT pin is pulled HIGH. This pin can be connected to the interrupt pin of a microcontroller. The source of the trigger
for the interrupt is available in the I2C interrupt register (see Table 12).
8.7
̅̅̅̅̅
Enable Pin – EN
The P9221-R can be disabled by applying a logic HIGH to the EN pin. When the EN pin is pulled HIGH, the device is in Shut Down Mode.
Connecting the enable pin to logic LOW activates the device.
8.8
Thermal Protection
The P9221-R integrates thermal shutdown circuitry to prevent damage resulting from excessive thermal stress that may be encountered under
fault conditions. This circuitry will shut down or reset the P9221-R if the die temperature exceeds 140°C.
8.9
External Temperature Sensing – TS
The P9221-R has a temperature sensor input, TS, which can be used to monitor an external temperature by using a thermistor. The built-in
comparator’s reference voltage was chosen to be 0.6V in the P9221-R, and it is used for monitoring the voltage level on the TS pin as described
by Equation 1.
VTS =VVDD18 ×
NTC
Equation 1
R+NTC
Where NTC is the thermistor’s resistance and R is the pull-up resistor connected to VDD18 pin. The over–temperature shutdown is trigged
when the TS pin voltage is lower than 0.6V; for more information, see Figure 24.
© 2017 Integrated Device Technology, Inc.
17
April 4, 2017
P9221-R Datasheet
8.10 Alignment Guide – ALIGNX and ALIGNY
This feature is used to provide directional information regarding the transmit coil and receive coil alignment while the wireless charger is in
normal operation mode. Sensing coils (see the basic application circuit on the first page) are placed on the wireless power receiver side between
the power RX coil and power TX coil. Special design enables the sensing coils to output zero voltage when the alignment is optimum while
misalignment between the transmitter and receiver coils will result in a voltage on the sensing coils. These signals are internally rectified, filtered,
and passed through the ADC providing quantitative information on the amount of misalignment. The higher the signal is, the more the coils are
misaligned.
Furthermore, the signal magnitude on ALIGNX and ALIGNY provides directional information by measuring the phase between the input power
AC signal and horizontal and vertical alignment signals. Once the signal passes through the ADC, the alignment information is represented by
two 8-bit signed numbers, which can be read from the Alignment X Value and Alignment Y Value I2C registers defined in Table 21 and Table
22 respectively, which indicate the misalignment direction and magnitude.
The application processor can provide 2D visual graphics that suggest how much the power coils are misaligned in each direction and can
suggest that the user move the device on the TX pad for the best alignment to improve the power transferred and reduce the charging time.
8.11 Received Power Packet Offset and Gain Calibration – RPPO and RPPG
The received power packet offset (RPPO) and received power packet gain (RPPG) calibrations have dedicated pins for tuning foreign object
detection (FOD). The offset calibration can be tuned by the voltage level of RPPO to a value between 0.1V to 2.1V, which corresponds to a
power offset range of 1.54W to 2.34W. The gain can be modified by setting the voltage level of the RPPG pin. The range of the control gain is
from 0.122 to 2.33 where the level is determined by a ratiometric voltage in the range of 0.1V to 2.1V on the RPPG pin.
To disable the FOD, the voltage on both RPPO and RPPG must be set to 0.1V. Neither pin should be floating. If FOD is not required, the RPPG
and RPPO must be set to 0.9V, which defaults to gain = 1 and offset = 0.
8.12 Advanced Foreign Object Detection (FOD)
When metallic objects are exposed to an alternating magnetic field, eddy currents cause such objects to heat up. Examples of such parasitic
metal objects are coins, keys, paper clips, etc. The amount of heating depends on the strength of the coupled magnetic field, as well as on the
characteristics of the object, such as its resistivity, size, and shape. In a wireless power transfer system, the heating manifests itself as a power
loss, and therefore a reduction in power-transfer efficiency. Moreover, if no appropriate measures are taken, the heating could be sufficient that
the foreign object could become heated to an undesirable temperature.
During the power transfer phase, the receiver periodically will communicate to the transmitter the amount of power received by means of a
received power packet. The transmitter will compare this power with the amount of power transmitted during the same time period. If there is a
significant unexplained loss of power, then the transmitter will shut off power delivery because a possible foreign object might be absorbing too
much energy.
For a WPC system to perform this function with sufficient accuracy, both the transmitter and receiver must account for and compensate for all
of their known losses. Such losses could be due to resistive losses or nearby metals that are part of the transmitter or receiver, etc. Because
the system accurately measures its power and accounts for all known losses, it can thereby detect foreign objects because they cause an
unknown loss. The WPC specification requires that a power receiver must report to the power transmitter its received power (PPR) in a receivedpower packet (RPP). The maximum value of the received power accuracy 𝑃Δ depends on the maximum power of the power receiver as defined
in Table 7.
The power receiver must determine its PPR with an accuracy of ±𝑃Δ, and report its received power as PRECEIVED = PPR + 𝑃Δ. This means that
the reported received power is always greater than or equal to the transmitted power (P PT) if there is no foreign object (FO) present on the
interface surface.
© 2017 Integrated Device Technology, Inc.
18
April 4, 2017
P9221-R Datasheet
Table 7.
Maximum Estimated Power Loss
Maximum Power [W]
Maximum 𝑷𝚫 [mW]
15
750
The compensation algorithm includes values that are programmable via either the I2C interface or OTP (one-time programmable) bits.
Programmability is necessary so that the calibration settings can be optimized to match the power transfer characteristics of each particular
WPC system to include the power losses of the transmit and receive coils, battery, shielding, and case materials under no-load to full-load
conditions. The values are based on the comparison of the received power against a reference power curve so that any foreign object can be
sensed when the received power is different than the expected system power.
© 2017 Integrated Device Technology, Inc.
19
April 4, 2017
P9221-R Datasheet
9. Communication Interface
9.1
Modulation/Communication
The wireless medium power charging system uses two-way communication: receiver-to-transmitter and transmitter-to receiver.
Receiver-to-transmitter communication is accomplished by modulating the load seen by the receiver's inductor; the communication is purely
digital and symbols 1’s and 0’s ride on top of the power signal that exists between the two coils. Modulation is done with amplitude-shift keying
(ASK) modulation using internal switches to connect external capacitors from AC1 and AC2 to ground (see Figure 17) with a bit rate of 2Kbps.
To the transmitter, this appears as an impedance change, which results in measurable variations of the transmitter’s output waveform. The
power transmitter detects this as a modulation of coil current/voltage to receive the packets.
Transmitter-to-receiver communication is accomplished by frequency-shift keying (FSK) modulation over the power signal frequency. The power
receiver P9221-R has the means to demodulate FSK data from the power signal frequency and use it in order to establish the handshaking
protocol with the power transmitter.
The P9221-R implements FSK communication when used in conjunction with WPC-compliant transmitters, such as the P9242-R. The FSK
communication protocol allows the transmitter to send data to the receiver using the power transfer link in the form of modulating the power
transfer signal. This modulation appears in the form of a change in the base operating frequency (fOP) to the modulated operating frequency
(fMOD) in periods of 256 consecutive cycles. Equation 2 should be used to compute the modulated frequency based on any given operating
frequency. The P9221-R will only implement positive FSK polarity adjustments; in other words, the modulated frequency will always be higher
than the operating frequency during FSK communication.
Communication packets are transmitted from transmitter to receiver with less than 1% positive frequency deviation following any receiver-totransmitter communication packet. The frequency deviation is calculated using Equation 2.
fMOD =
60000
[KHz]
60000
−3
fOP
Equation 2
Where fMOD is the changed frequency in the power signal frequency; fOP is the base operating frequency of the power transfer; and 60000kHz
is the internal oscillator responsible for counting the period of the power transfer signal.
The FSK byte-encoding scheme and packet structure comply with the WPC specification revision 1.2.2. The FSK communication uses a
bi-phase encoding scheme to modulate data bits into the power transfer signal. The start bit will consist of 512 consecutive fMOD cycles (or logic
‘0’). A logic ‘1’ value will be sent by sending 256 consecutive fOP cycles followed by 256 fMOD cycles or vice versa, and a logic ‘0’ is sent by
sending 512 consecutive fMOD or fOP cycles.
Figure 18. Example of Differential Bi-phase Decoding for FSK
tCLK = 256/fOP
512 cycles
ONE
ZERO
ONE
ZERO
256 cycles
ONE
ZERO
ONE
ZERO
Each byte will comply with the start, data, parity, and stop asynchronous serial format structure shown in Figure 19:
Figure 19. Example of Asynchronous Serial Byte Format for FSK
Start
b0
b1
b2
b3
b4
b5
© 2017 Integrated Device Technology, Inc.
b6
b7
Parity
Stop
20
April 4, 2017
P9221-R Datasheet
9.2
Bit Encoding Scheme for ASK
As required by the WPC, the P9221-R uses a differential bi-phase encoding scheme to modulate data bits onto the power signal. A clock
frequency of 2kHz is used for this purpose. A logic ONE bit is encoded using two narrow transitions, whereas a logic ZERO bit is encoded using
one wider transition as shown below:
Figure 20. Bit Encoding Scheme
t CLK
ONE
9.3
ZERO
ONE
ZERO
ONE
ZERO
ONE
ZERO
Byte Encoding for ASK
Each byte in the communication packet comprises 11 bits in an asynchronous serial format, as shown in Figure 21.
Figure 21. Byte Encoding Scheme
Start
b0
b1
b2
b3
b4
b5
b6
b7
Parity
Stop
Each byte has a start bit, 8 data bits, a parity bit, and a single stop bit.
9.4
Packet Structure
The P9221-R communicates with the base station via communication packets. Each communication packet has the following structure:
Figure 22. Communication Packet Structure
Preamble
Header
Message
© 2017 Integrated Device Technology, Inc.
Checksum
21
April 4, 2017
P9221-R Datasheet
10. WPC Mode Characteristics
The Extended Power Profile adds a negotiation phase, a calibration phase, and renegotiation phase to the basic system control functionality of
the Base line Power Profile, as shown in Figure 23.
Figure 23. WPC Power Transfer Phases Flowchart
Calibration failure or
error condition
Negotiation failure or
error condition or FOD
Selection
No response or
no power needed
START
Error
condition
Object
detected
Ping
Negotiation
Calibration
Negotiation
successful
Calibration
successful
Power receiver
present
Error condition
Identification and
Configuration
Renegotiation
Negotiation requested
Renegotiation
requested
No negotiation requested
(<= 5W power received only)
Power Transfer
Renegotiation
completed
Power transfer complete
or error condition
10.1 Selection Phase or Startup
In the selection phase, the power transmitter determines if it will proceed to the ping phase after detecting the placement of an object. In this
phase, the power transmitter typically monitors the interface surface for the placement and removal of objects using a small measurement
signal. This measurement signal should not wake up a power receiver that is positioned on the interface surface.
10.2 Ping Phase (Digital Ping)
In the ping phase, the power transmitter will transmit power and will detect the response from a possible power receiver. This response ensures
the power transmitter that it is dealing with a power receiver rather than some unknown object. When a mobile device containing the P9221-R
is placed on a WPC “Qi” charging pad, it responds to the application of a power signal by rectifying this power signal. When the voltage on
VRECT is greater than the UVLO threshold, then the internal bandgaps, reference voltage, and the internal voltage regulators (5V and 1.8V)
are turned on, and microcontroller’s startup is initiated enabling the WPC communication protocol.
If the power transmitter correctly receives a signal strength packet, the power transmitter proceeds to the identification and configuration phase
of the power transfer, maintaining the power signal output.
© 2017 Integrated Device Technology, Inc.
22
April 4, 2017
P9221-R Datasheet
10.3 Identification and Configuration Phase
The identification and configuration phase is the part of the protocol that the power transmitter executes in order to identify the power receiver
and establish a default power transfer contract. This protocol extends the digital ping in order to enable the power receiver to communicate the
relevant information.
In this phase, the power receiver identifies itself and provides information for a default power transfer contract:
 It sends the configuration packet.
 If the power transmitter does not acknowledge the request (does not transmit FSK modulation), the power receiver will assume 5W output
power.
10.4 Negotiation Phase
In the negotiation phase, the power receiver negotiates changes to the default power transfer contract. In addition, the power receiver verifies
that the power transmitter has not detected a foreign object.
10.5 Calibration Phase
In the calibration phase, the power receiver provides information that the power transmitter can use to improve its ability to detect foreign objects
during power transfer.
10.6 Power Transfer Phase
In this phase, the P9221-R controls the power transfer by means of the following control data packets:
Control Error Packets
Received Power Packet (RPP, FOD related)
 End Power Transfer (EPT) Packet


Once the “identification and configuration” phase is completed, the transmitter initiates the power transfer mode. The P9221-R control circuit
measures the rectifier voltage and sends error packets to the transmitter to adjust the rectifier voltage to the level required to maximize the
efficiency of the linear regulator and to send to the transmitter the actual received power packet for foreign object detection (FOD) to guarantee
safe, efficient power transfer.
In the event of an EPT issued by the application, the P9221-R turns off the LDO and continuously sends EPT packets until the transmitter
removes the power and the rectified voltage on the receiver side drops below the UVLO threshold.
© 2017 Integrated Device Technology, Inc.
23
April 4, 2017
P9221-R Datasheet
11. Functional Registers
The following tables provide the address locations, field names, available operations (R or RW), default values, and functional descriptions of
all the internally accessible registers contained within the P9221-R. The default I2 C slave address is 61HEX.
Table 8.
Device Identification Register
Address and Bit
Register Field Name
R/W
Default
Function and Description
00HEX [7:0]
Part_number_L
R
20HEX
Chip ID low byte
01HEX [7:0]
Part_number_H
R
92HEX
Chip ID high byte
Table 9.
Firmware Major Revision
Address and Bit
Register Field Name
R/W
Default
Function and Description
04HEX [7:0]
FW_Major_Rev_L
R
01HEX
Major firmware revision low byte
05HEX [7:0]
FW_Major_Rev_H
R
00HEX
Major firmware revision high byte
Table 10.
Firmware Minor Revision
Address and Bit
Register Field Name
R/W
Default
Function and Description
06HEX [7:0]
FW_Minor_Rev_L
R
26HEX
Minor firmware revision low byte
07HEX [7:0]
FW_Minor_Rev_H
R
04HEX
Minor firmware revision high byte
Table 11.
Status Registers
Address and Bit
Register Field Name
R/W
Default
Function and Description
34HEX [7]
Vout_Status
R
0BIN
34HEX [6]
Reserved
R
0BIN
34HEX [5]
Reserved
R
0BIN
34HEX [4]
Reserved
R
0BIN
34HEX [3]
Reserved
R
0BIN
34HEX [2]
Thermal_SHTDN_Status
R
0BIN
“0” indicates no over-temperature condition exists.
“1” indicates that die temperature exceeds 130°C or NTC is less
than 0.6V. The P9221-R sends an end power transfer (EPT)
packet to the transmitter.
34HEX [1]
VRECT_OV_ Status
R
0BIN
“1” indicates rectifier exceeds 20V for VOUT=12. EPT packet
send.
34HEX [0]
Current_Limit_Status
R
0BIN
“1” indicates current limit has been exceeded. The P9221-R
sends an end power transfer (EPT) packet to the transmitter.
35HEX [7:0]
Reserved
R
00HEX
© 2017 Integrated Device Technology, Inc.
“0” output voltage is off.
“1” output voltage is on.
24
April 4, 2017
P9221-R Datasheet
Table 12.
Interrupt Status Registers
Address and Bit
Register Field Name
R/W
Default
Function and Description
“0” output voltage has not changed.
“1” output voltage changed.
36HEX [7]
INT_Vout_Status
R
0BIN
36HEX [6]
Reserved
R
0BIN
36HEX [5]
Reserved
R
0BIN
36HEX [4]
Reserved
R
0BIN
36HEX [3]
Reserved
R
0BIN
36HEX [2]
INT_OVER_TEMP_Status
R
0BIN
“1” indicates over-temperature condition exists.
36HEX [1]
INT_VRECT_OV_ Status
R
0BIN
“1” indicates rectifier over-voltage condition exists.
36HEX [0]
INT_OC_Limit_Status
R
0
“1” indicates current limit has been exceeded.
37HEX [7:0]
Reserved
R
00HEX
Note: If any bit in the Interrupt Status register 36HEX is “1” and the corresponding bit in the Interrupt Enable register 38HEX is set to “1”, the
INT pin will be pulled down indicating an interrupt event has occurred.
Table 13.
Interrupt Enable Registers
Address and Bit
Register Field Name
R/W
Default
Function and Description
38HEX [7]
Vout_CHGN_INTR_EN
RW
0BIN
38HEX [6]
Reserved
R
0BIN
38HEX [5]
Reserved
R
0BIN
38HEX [4]
Reserved
R
1BIN
38HEX [3]
Reserved
R
0BIN
38HEX [2]
OVER_TEMP_INT_EN
R
0BIN
“0” disables the interrupt.
"1" enables the interrupt.
38HEX [1]
VRECT_OV_INT_EN
RW
0BIN
“0” disables the interrupt.
"1" enables the interrupt.
38HEX [0]
OC_Limit_INT_EN
RW
0BIN
“0” disables the interrupt.
"1" enables the interrupt.
39HEX [7:0]
Reserved
RW
00HEX
R/W
Default
Table 14.
Battery Charge Status
Address and Bit
3AHEX [7:0]
“0” disables the interrupt.
"1" enables the interrupt.
Register Field Name
Batt_Charg_status
R/W
00HEX
Function and Description
Battery charge status value sent to transmitter.[a]
[a] Firmware only forwards the data from the application processor to transmitter.
© 2017 Integrated Device Technology, Inc.
25
April 4, 2017
P9221-R Datasheet
Table 15.
End Power Transfer
The application processor initiates the end power transfer (EPT).
Address and Bit
3BHEX [7:0]
Table 16.
VOUT=
Register Field Name
EPT_Code
R/W
R/W
Default
00HEX
Function and Description
EPT_Code sent to transmitter.
Read Register – Output Voltage
ADC_VOUT ∗ 6 ∗ 2.1
4095
Address and Bit
Register Field Name
R/W
Default
Function and Description
3CHEX [7:0]
ADC_VOUT [7:0]
R
00HEX
8 LSB of VOUT ADC value.
3DHEX [7:4]
Reserved
R
0HEX
Reserved.
3DHEX [3:0]
ADC_VOUT [11:8]
R
0HEX
4 MSB of VOUT ADC value.
Table 17.
VRECT =
Read Register – VRECT Voltage
ADC_VRECT ∗ 10 ∗ 2.1
4095
Address and Bit
Register Field Name
R/W
Default
40HEX [7:0]
ADC_VRECT [7:0]
R
–
41HEX [7:4]
Reserved
R
0HEX
41HEX [3:0]
ADC_VRECT [11:8]
R
–
Table 18.
IOUT=
Function and Description
8 LSB of VRECT ADC value.
Reserved
4 MSB of VRECT ADC value.
Read Register – IOUT Current
RX_IOUT ∗ 2 ∗ 2.1
4095
Address and Bit
Register Field Name
R/W
Default
Function and Description
44HEX [7:0]
RX_IOUT [7:0]
RHEX
–
8 LSB of IOUT. Output current in mA.
45HEX [7:0]
RX_IOUT [15:8]
RHEX
–
8 MSB of IOUT. Output current in mA
© 2017 Integrated Device Technology, Inc.
26
April 4, 2017
P9221-R Datasheet
Table 19.
Read Register – Die Temperature
TDIE =(ADC_Die_Temp − 1350)
Address and Bit
83
444
– 273 where ADC_Die_Temp = 12 bits from ADC_Die_Temp_H and ADC_Die_Temp_L.
Register Field Name
R/W
Default
46HEX [7:0]
ADC_Die_Temp_L
R
-
47HEX [7:4]
Reserved
R
0HEX
47HEX [3:0]
ADC_Die_Temp_H
R
-
Table 20.
fOP =
Function and Description
8 LSB of current die temperature in °C.
Reserved
4 MSB of current die temperature in °C.
Read Register – Operating Frequency
64 ∗ 6000
OP_FREQ [15:0]
Address and Bit
Register Field Name
R/W
Default
Function and Description
48HEX [7:0]
OP_FREQ[7:0]
R
-
8 LSB AC signal frequency on the coil.
49HEX [7:0]
OP_FREQ[15:8]
R
-
8 MSB AC signal frequency on the coil.
Table 21.
Alignment X Value Register
Note: Valid only in presence of the alignment PCB coil. (See section 8.10 or the P9221-R Evaluation Kit User Manual for more information.)
Address and Bit
4BHEX [7:0]
Table 22.
Register Field Name
Align_X
R/W
R
Default
Function and Description
-
8-bit signed integer representing alignment between TX and RX
coil in the X-direction. The value is application-specific.
Alignment Y Value Register
Note: Valid only in presence of the alignment PCB coil. (See section 8.10 or the P9221-R Evaluation Kit User Manual for more information.)
Address and Bit
4CHEX [7:0]
Register Field Name
Align_Y
© 2017 Integrated Device Technology, Inc.
R/W
R
Default
Function and Description
-
8-bit signed integer representing alignment between TX and RX
coil in the Y-direction. The value is application-specific.
27
April 4, 2017
P9221-R Datasheet
Table 23.
Command Register
Address and Bit
Register Field Name
R/W
Default
Function and Description
4EHEX [7:6]
Reserved
R
0HEX
Reserved.
4EHEX [5]
Clear Interrupt
RW
0HEX
If application processor sets this bit to "1," the P9221-R clears
the interrupt pin.
4EHEX [4]
Reserved
R
0HEX
Reserved
4EHEX [3]
Send End of Power
RW
0HEX
If application processor sets this bit to "1," the P9221-R sends
the end power transfer packet (defined in the End of Power
Transfer register shown in Table 15) to the transmitter and then
sets this bit to "0."
4EHEX [2]
Reserved
R
0HEX
Reserved
4EHEX [1]
Toggle LDO On/OFF
RW
0HEX
If application processor sets this bit to "1,” the P9221-R toggles
the LDO output once (from on to off or from off to on), and then
sets this bit to “0.”
4EHEX [0]
Reserved
R
0HEX
Reserved
© 2017 Integrated Device Technology, Inc.
28
April 4, 2017
P9221-R Datasheet
12. Application Information
12.1 Power Dissipation and Thermal Requirements
The use of integrated circuits in low-profile and fine-pitch surface-mount packages requires special attention to power dissipation. Many systemdependent issues such as thermal coupling, airflow, added heat sinks, convection surfaces, and the presence of other heat-generating
components.
The P9221-R package has a maximum power dissipation of approximately 1.72W, which is governed by the number of thermal vias between
the package and the printed circuit board. The die’s maximum power dissipation is specified by the junction temperature and the package
thermal resistance. The WLCSP package has a typical θJA of 47ºC/W with 8 thermal vias and 77ºC/W with no thermal vias. Maximizing the
thermal vias is highly recommended. The ambient temperature surrounding the power IC will also have an effect on the thermal limits of the
PCB design. The main factors influencing thermal resistance (θJA) are the PCB characteristics and thermal vias. For example, in a typical stillair environment, a significant amount of the heat generated is absorbed by the PCB. Changing the design or configuration of the PCB changes
the overall thermal resistivity and therefore the board’s heat-sinking efficiency.
Three basic approaches for enhancing thermal performance are listed below:
Improving the power dissipation capability of the PCB design and improving the thermal coupling of the component to the PCB.
 Introducing airflow into the system.

First, the maximum power dissipation for a given situation should be calculated using Equation 3:
PD(MAX) =
Equation 3
(TJ(MAX) − TA )
θJA
Where
PD(MAX) = Maximum power dissipation
θJA = Package thermal resistance (°C/W)
TJ(MAX) = Maximum device junction temperature (°C)
TA = Ambient temperature (°C)
The maximum recommended junction temperature (TJ(MAX)) for the P9221-R device is 125°C. The thermal resistance of the 52-WLCSP package
(AHG52) is nominally θJA=47°C/W with 8 thermal vias. Operation is specified to a maximum steady-state ambient temperature (TA) of 85°C.
Therefore, the maximum recommended power dissipation is
PD(Max) = (125°C - 85°C) / 47°C/W ≅ 0.85 Watt
All the above-mentioned thermal resistances are the values found when the P9221-R is mounted on a standard board of the dimensions and
characteristics specified by the JEDEC 51 standard.
12.2 Recommended Coils
The following coil is recommended with the P9221-R receiver for 15W applications for optimum performance. The recommended vendor has
been tested and verified.
Table 24.
Recommended Coil Manufacturers
Output Power
Vendor
Part number
Inductance at 100kHz
ACR at 20°C
15W
AMOTECH
ASC-504060E00-S00
8.2µH
220 mΩ
© 2017 Integrated Device Technology, Inc.
29
April 4, 2017
30
AC2
L1
LC
C9
3.3nF
GND1
Vrect
AC2T
100nF/50V
C5
100nF/50V
C3
C2
100nF/50V
C1
100nF/50V
AlignX coil
AlignY coil
10uF
C33
10uF
10uF
C22
C15
NP
C14
47nF
C21
C7
NP
VRECT
THM
(SCL)
(SDA)
C6
47nF
I2C
1
2
3
4
5
0
R35
J1
10K
10K
R16
R15
C23
0.1uF
C16
15nF
C8
15nF
E1
E2
E5
E6
F2
F3
F4
F5
G6
B6
A6
G5
H5
H6
G1
B1
A1
G2
H1
H2
VRECT
VRECT
VRECT
VRECT
VRECT
VRECT
VRECT
VRECT
BST2
RSV5
COMM2
AC2
AC2
AC2
BST1
RSV4
COMM1
AC1
AC1
AC1
G3
H3
RSV3
RSV2
G4
H4
ALGX
U1
P9221-R
TS
RSV1
TS
INT
OD3
OD4
A3
B3
C3
A2
B2
GCOM
C1
C6
J1
J2
J3
J4
J5
J6
GND
GND
GND
GND
GND
GND
GND
GND
OUT
OUT
OUT
OUT
OUT
OUT
EN
VOSET
ILIM
RPPO
RPPG
DEN
VDD18
VDD5V
ALGY
C2
SINK
© 2017 Integrated Device Technology, Inc.
SCL
SDA
INT
ALIGNX
ALIGNY
A4
B4
C4
A5
C5
F6
F1
D1
D2
D3
D4
D5
D6
B5
R2
36
D7
5.1V
/EN
VPP18
VDD5V
C20
1uF
DEN
RPG
RPO
ILIM
VOSET
VPP18
10uF
C11
VRECT
10uF
C10
R17 10k
5.1V
D6
NP
C12
VDD5V
R39
10k
C18
1uF
SDA
SCL
I2CRAIL
WP
R29
10K
10K
10K
R30
5.1k
R1
LED
D1
VOSNS
R13
5.1k
R27
10K
R28
R14
5.1k
NP
R22
R38
10K
R18
NP
C25
NP
NP
R33
R34
10k
5
6
7
8
THM
SDA
SCL
WP
VCC
NP
R8
U2
0
R6 NP
VSS
A2
A1
A0
RTS
NP
R19
10K
VOUT
E_PAD
9
P9221-R MM EV Board V2.1
4
3
2
1
C31
0.1uF
GND
VOUT
VPP18
VDD5V
INT
INT
R23
10k
C19
0.1uF
VPP18
P9221-R Datasheet
12.3 Typical Application Schematic
Figure 24. P9221-R Typical Application Schematic
April 4, 2017
RX Power Coil
P9221-R Datasheet
12.4 Bill of Materials (BOM)
Table 25.
P9221-R MM Evaluation Kit V2.1 Bill of Materials
Item
Reference
Quantity
Value
Description
Part Number
PCB Footprint
1
AC2T, VDD5V, VPP18,
VOSET, TS, SDA, SCL,
RPO, RPG, INT, ILIM,
GCOM, DEN, ALGY,
ALGX, /EN
16
PTH_TP
Test Pad
10MIL_35PAD
2
AC2, LC
2
NP
Test Point
test_pt_sm_135x70
3
C1, C2, C3, C5
4
100nF/5
0V
4
C6, C14
2
5
C7, C15
6
CAP CER 0.1UF 50V X5R 0402
GRM155R61H104KE19D
402
47nF
CAP CER 0.047UF 50V X7R 0402
C1005X7R1H473K050BB
402
2
NP
CAP CER 0.047UF 50V X7R 0402
C1005X7R1H473K050BB
402
C8, C16
2
15nF
CAP CER 0.015UF 50V X7R 0402
GRM155R71H153KA12J
402
7
C9
1
3.3nF
CAP CER 3300PF 50V X7R 0402
CL05B332KB5NNNC
402
8
C10, C11, C21, C22,
C33
5
10uF
CAP CER 10UF 25V X5R 0603
CL10A106MA8NRNC
603
9
C12
1
NP
CAP CER 10UF 25V X5R 0603
CL10A106MA8NRNC
603
10
C18
1
NP
CAP CER 1UF 10V X5R 0402
GRM155R61A105KE15D
402
11
C20
1
1uF
CAP CER 1UF 10V X5R 0402
GRM155R61A105KE15D
402
12
C19, C25, C31
3
0.1uF
CAP CER 0.1UF 10V X5R 0201
C0603X5R1A104K030BC
201
13
C23
1
0.1uF
CAP CER 0.1UF 25V X5R 0201
CL03A104KA3NNNC
201
14
D1
1
LED
LED GREEN CLEAR 0603 SMD
150060GS75000
0603_diode
15
D6,D7
2
5.1V
DIODE ZENER 5.1V 100MW 0201
CZRZ5V1B-HF
201
16
GND1, VRECT, VOUT,
VOSNS, GND
5
Test
Point
TEST POINT PC MINIATURE SMT
5015
test_pt_sm_135x70
17
L1
1
RX coil
ASC-504060E00-S00
10MIL_35PAD
18
J1
1
NP
68002-205HLF
header_1x5_0p1Pitch60p42d
19
RTS
1
NP
20
R1, R13, R14
3
5.1k
21
R2
1
36
22
R6
1
23
R8
1
24
R15, R16
2
10K
25
R17, R19, R23, R27,
R28, R29, R30, R34,
R38, R39
10
26
R18, R22, ,R33
27
AMOTECH, Rx Power Coil
HEADER_1X5_0P1PITCH60P42D
NTC2
MCR01MRTJ512
402
RES SMD 36 OHM 5% 1/2W 0805
ERJ-P06J360V
805
NP
RES SMD 0.0OHM 1/10W 0402
ERJ-2GE0R00X
402
0
RES SMD 0.0OHM 1/10W 0402
ERJ-2GE0R00X
402
RES SMD 10KOHM 1% 1/10W 0603
RC0603FR-0710KL
603
10k
RES SMD 10K OHM 5% 1/10W 0402
ERJ-2GEJ103X
402
3
NP
RES SMD 10K OHM 5% 1/10W 0402
ERJ-2GEJ103X
402
R35
1
0
RES SMD 0.0OHM JUMPER 1/10W 0603
MCR03EZPJ000
603
28
U1
1
P9221-R
29
U2
1
NP
© 2017 Integrated Device Technology, Inc.
RES SMD 5.1K OHM 5% 1/16W 0402
Wireless power receiver
IC EEPROM 128KBIT 400KHZ 8TDFN
31
P9221-R
24AA128T-I/MNY
csp52_2p64x3p94_0p4mm
TDFN08
April 4, 2017
P9221-R Datasheet
13. Package Drawings
Figure 25. Package Outline Drawing
© 2017 Integrated Device Technology, Inc.
32
April 4, 2017
P9221-R Datasheet
14. Recommended Land Pattern
Figure 26. AHG52 52-WLCSP Land Pattern
© 2017 Integrated Device Technology, Inc.
33
April 4, 2017
P9221-R Datasheet
15. Special Notes: AHG52 WLCSP-52 Package Assembly
Unopened dry packaged parts have a one-year shelf life.
The HIC indicator card for newly-opened dry packaged parts should be checked. If there is any moisture content, the parts must be baked for
a minimum of 8 hours at 125˚C within 24 hours of the assembly reflow process.
16. Marking Diagram
IDT
P9221
YYWW**
$-R
1.
Line 1 company name.
2.
Truncated part number.
3.
“YYWW” is the last digit of the year and week that the part was assembled.
** is the lot sequential code.
4.
“$” denotes mark code, -R is part of the device part number
17. Ordering Information
Orderable Part Number
Description and Package
MSL Rating
Shipping Packaging
P9221-RAHGI8
P9221-R Wireless Power Receiver for 15W
Applications, 2.64  3.94 mm 52-WLCSP (AHG52)
MSL1
Tape and reel
P9221-R-EVK
P9221-R-EVK Evaluation Board
© 2017 Integrated Device Technology, Inc.
34
Ambient
Temperature
0°C to
+85°C
April 4, 2017
P9221-R Datasheet
18. Revision History
Revision Date
April 4, 2017
Description of Change









December 16, 2016
Update to WPC-1.2.3 compliant
Update for I2C slave address = 61HEX
Update for device identification register
Update for firmware revision number register
Updates for Table 13 and Table 16.
Update for recommended coil part number and related entry in BOM.
Update for disclaimer
Addition of R9221-R Evaluation Kit order code
Minor edits
Preliminary release.
Corporate Headquarters
Sales
Tech Support
6024 Silver Creek Valley Road
San Jose, CA 95138
www.IDT.com
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
www.IDT.com/go/support
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the ri ght to modify the products and/or specifications described herein at any time,
without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaran teed to perform the same
way when installed in customer products. The information contained herein is provided without representati on or warranty of any kind, whether express or implied, including, but not limited to, the suitability
of IDT's products for any particular purpose, an implied warranty of merchantability, or non -infringement of the intellectual property rights of others. This document is presented only as a guide and does not
convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life suppor t systems or similar devices where the failure or malfunction of an IDT product can be
reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the
property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. All contents of this document are copyright of Integrated
Device Technology, Inc. All rights reserved.
© 2017 Integrated Device Technology, Inc.
35
April 4, 2017