ON CM2009-05CP Vga or dvi-i port companion circuit Datasheet

VGA or DVI-I Port Companion Circuit
CM2009-05CP
Advance Information
Features
•
•
•
•
•
•
•
•
•
•
Includes ESD protection, level-shifting, buffering
and sync impedance matching
VESA VSIS Version 1 Revision 2 compatible
interface
Supports both source and sink devices
Supports optional NAVI signaling requirements
Seven channels of ESD protection for all VGA
port connector pins meeting IEC-61000-4-2 Level
4 ESD requirements (±8kV contact discharge)
Very low loading capacitance from ESD
protection diodes on VIDEO lines, 3pF maximum
Schmitt-triggered input buffers for HSYNC and
VSYNC lines
Bi-directional level shifting N-channel FETs
provided for DDC_CLK & DDC_DATA channels
Backdrive protection on all lines
RoHS-compliant, lead-free finishing in a 14bump, 5x4x5, 0.4mm Chip Scale Package (CSP)
Applications
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•
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Monitors
Video graphics controllers embedded in PCs
Graphics adapter cards
Set-top boxes
Product Description
The CM2009-05CP connects between the VGA or
DVI-I port connector and the internal analog or digital
flat panel controller logic. It can also be used for
source devices such as a set-top box. The CM200905CP incorporates ESD protection for all signals,
level shifting for the DDC signals and buffering for the
SYNC signals. ESD protection for the video, DDC
and SYNC lines is implemented with low-capacitance
current steering diodes.
All connector interface pins are designed to safely
handle the high current spikes specified by IEC61000-4-2 Level 4 (±8kV contact discharge). The
ESD protection for the DDC, SYNC and VIDEO
signal pins is designed to prevent "back current"
when the device is powered down while connected to
a video source or a video sink that is powered up.
Positive supply rails are provided for the VIDEO /
SYNC signals and DDC signals to facilitate
interfacing with low voltage video controller ICs and
microcontrollers to provide design flexibility in multisupply-voltage environments.
Two Schmitt-triggered non-inverting buffers redrive
and condition the HSYNC and VSYNC signals from
the video connector (SYNC1, SYNC2). These buffers
accept VESA VSIS compliant TTL input signals and
convert them to CMOS output levels that swing
between ground and VCC.
Two N-channel MOSFETs provide the level shifting
function required when the DDC controller or EDID
EEPROM is operated at a lower supply voltage than
the monitor. The gate terminals for these MOSFETS
should be connected to the supply rail (typically 3.3V,
2.5V etc.) that supplies power to the transceivers of
the DDC controller.
©2010 SCILLC. All rights reserved.
April 2010 Rev. P2
Publication Order Number:
CM2009-05CP/D
CM2009-05CP
Rev. P2 | Page 2 of 8 | www.onsemi.com
CM2009-05CP
PIN DESCRIPTIONS
LEAD(s)
NAME
DESCRIPTION
A1
GND
A2
VIDEO_1
Video signal ESD protection channel. This pin is typically tied one of the video lines between the
controller device and the video connector.
A3
VIDEO_2
Video signal ESD protection channel. This pin is typically tied one of the video lines between the
controller device and the video connector.
A4
VIDEO_3
Video signal ESD protection channel. This pin is typically tied one of the video lines between the
controller device and the video connector.
A5
VCC
This is a supply input for the SYNC_1 and SYNC_2 level shifters, video protection and the DDC
circuits.
B1
DDC_OUT1
DDC signal output. Connects to the DDC logic.
B2
DDC_OUT2
DDC signal output. Connects to the DDC logic.
B3
SYNC_OUT1
Sync signal buffer output. Connects to the monitor Sync logic.
1
B4
SYNC_OUT2
Sync signal buffer output. Connects to the monitor Sync logic.
1
C1
DDC_IN1
DDC signal input. Connects to the video connector side of one of the DDC lines.
C2
DDC_IN2
DDC signal input. Connects to the video connector side of one of the DDC lines.
C3
LV_EN
C4
SYNC_IN1
Sync signal buffer input. Connects to the video connector side of one of the Sync lines.
2
C5
SYNC_IN2
Sync signal buffer input. Connects to the video connector side of one of the Sync lines.
2
Ground reference supply pin.
Disables the Sync buffer outputs when low.
Note 1: Can also be connected to the VGA connector side if used for a source device.
Note 2: Can also be used to connect to the Video Chip Sync Logic if it is used for a source device.
Ordering Information
PART NUMBERING INFORMATION
Bumps
Package
Ordering Part Number1
Part Marking
14
CSP
CM2009-05CP
TJ
Note 1: Parts are shipped in Tape and Reel form.
Rev. P2 | Page 3 of 8 | www.onsemi.com
CM2009-05CP
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNITS
[GND - 0.5] to +6.0
V
[GND - 0.5] to [VCC + 0.5]
[GND - 0.5] to 6.0
[GND - 0.5] to 6.0
[GND - 0.5] to [VCC + 0.5]
V
V
V
V
Operating Temperature Range
-40 to +85
°C
Storage Temperature Range
-40 to +150
°C
500
mW
RATING
UNITS
-40 to +85
°C
5
V
VCC Supply Voltage Inputs
DC Voltage at Inputs
VIDEO_1, VIDEO_2, VIDEO_3
DDC_IN1, DDC_IN2
DDC_OUT1, DDC_OUT2
SYNC_IN1, SYNC_IN2, LV_EN
Package Power Rating (TA=25°C)
STANDARD OPERATING CONDITIONS
PARAMETER
Operating Temperature Range
VCC
Rev. P2 | Page 4 of 8 | www.onsemi.com
CM2009-05CP
ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1)
SYMBOL PARAMETER
ICC
CONDITIONS
VCC Supply Current
MIN
TYP
MAX UNITS
VCC = 5V; SYNC inputs at GND or VCC;
SYNC outputs unloaded, DDC_In and DDC_OUT
floating
1.0
mA
VCC = 5V; SYNC inputs at 3.0V;
SYNC outputs unloaded, DDC_In and DDC_OUT
floating
2.0
mA
1.1
V
VF
ESD Diode Forward Voltage
IF = 10mA
VIH
Logic High Input Voltage
VCC = 5.0V; Note 2
VIL
Logic Low Input Voltage
VCC = 5.0V; Note 2
VHYS
Hysteresis Voltage
VCC = 5.0V; Note 2
VOH
Logic High Output Voltage
IOH = 0mA, VCC = 5.0V; Note 2
VOL
Logic Low Output Voltage
IOL = 0mA, VCC = 5.0V; Note 2
ROUT
SYNC Driver Output Resistance
VCC = 5.0V; SYNC Inputs at GND or 3.0V
Input Current
VIDEO Inputs
VCC = 5.0V; VIN = VCC or GND
±10
μA
VCC = 5.0V; VIN = VCC or GND
±10
μA
(LV_EN - VDDC_IN) 0.4V; VDDC_OUT = LV_EN
10
μA
(LV_EN - VDDC_OUT) 0.4V; VDDC_IN = LV_EN
10
μA
IIN
SYNC_IN1, SYNC_IN2 Inputs
IOFF
IBACKDRIVE
VON
CIN_VID
Level Shifting N-MOSFET "OFF" State
Leakage Current
2.0
0.55
450
LV_EN = 2.5V; VS = GND; IDS = 3mA
VIDEO Input Capacitance
V
mV
4.0
V
0.15
V
Ω
65
Current conducted from input pins when Vcc VCC < VINPUT_PIN
is powered down.
Voltage Drop Across Level-shifting
N-MOSFET when "ON"
V
μA
10
0.18
V
VCC = 5.0V; VIN = 2.5V; f = 1MHz
3
pF
VCC = 2.5V; VIN = 1.25V; f = 1MHz
3.5
pF
tPLH
SYNC Driver L => H Propagation Delay
CL = 50pF; VCC = 5.0V; Input tR and tF 5ns
12
ns
tPHL
SYNC Driver H => L Propagation Delay
CL = 50pF; VCC = 5.0V; Input tR and tF 5ns
12
ns
tR, tF
SYNC Driver Output Rise & Fall Times
VCC = 5V
VESD
ESD Withstand Voltage
VCC = 5V; Note 3
7
±8
ns
kV
Note 1: All parameters specified over standard operating conditions unless otherwise noted.
Note 2: These parameters apply only to the SYNC drivers. Note that ROUT = RT + RBUFFER.
Note 3: Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. VCC must be bypassed to GND
via a low impedance ground plane with a 0.22μF, low inductance, chip ceramic capacitor at each supply pin. ESD pulse
is applied between the applicable pins and GND. ESD pulses can be positive or negative with respect to GND.
Rev. P2 | Page 5 of 8 | www.onsemi.com
CM2009-05CP
Application Information
Figure 1. Typical Application Connection Diagram
NOTES:
1
2
The CM2009-05CP should be placed as close to the VGA or DVI-I connector as possible.
The ESD protection channels VIDEO_1, VIDEO_2, VIDEO_3 may be used interchangeably between the R, G, B
signals.
3 If differential video signal routing is used, the RED, BLUE, and GREEN signal lines should be terminated with external
37.5 ohm resistors.
4 "VF" are external video filters for the RGB signals.
5 Supply bypass capacitors C1 and C2 must be placed immediately adjacent to the corresponding Vcc pins.
Connections to the Vcc pins and ground plane must be made with minimal length copper traces (preferably less than
5mm) for best ESD protection.
6 The bypass capacitor for the BYP pin has been omitted in this diagram. This results in a reduction in the maximum
ESD withstand voltage at the DDC_OUT pins from ±8kV to ±2kV. If 8kV ESD protection is required, a 0.22μF ceramic
bypass capacitor should be connected between BYP and ground.
7 The SYNC buffers may be used interchangeably between HSYNC and VSYNC.
8 The EMI filters at the SYNC_OUT and DDC_OUT pins (C5 to C12, and Ferrite Beads FB1 to FB4) are for reference
only. The component values and filter configuration may be changed to suit the application.
9 The DDC level shifters DDC_IN, DDC_OUT, may be used interchangeably between DDCA_CLK and DDCA_DATA.
10 R1, R2 are optional. They may be used, if required, to pull the DDC_CLK and DDC_DATA lines to VCC_5V when no
monitor is connected to the VGA connector. If used, it should be noted that "back current" may flow between the DDC
pins and VCC_5V via these resistors when VCC_5V is powered down.
Rev. P2 | Page 6 of 8 | www.onsemi.com
CM2009-05CP
Mechanical Specification
Package Specification
The CM2009-05CP is supplied in 14-bump, 5-4-5 Chip Scale Package (CSP).
PACKAGE DIMENSIONS
Package
Custom CSP
Bumps
14
Millimeters
Inches
Dim
Min
Nom
Max
Min
Nom
Max
A1
1.955 2.000 2.045 0.0770 0.0787 0.0805
A2
1.055 1.100 1.145 0.0415 0.0433 0.0451
B1
0.395 0.400 0.405 0.0156 0.0157 0.0159
B2
0.195 0.200 0.205 0.0077 0.0079 0.0081
B3
0.342 0.347 0.352 0.0135 0.0137 0.0139
B4
0.342 0.347 0.352 0.0135 0.0137 0.0139
C1
0.150 0.200 0.250 0.0059 0.0079 0.0098
C2
0.153 0.203 0.253 0.0060 0.0080 0.0100
D1
0.530 0.580 0.630 0.0209 0.0228 0.0248
D2
0.363 0.391 0.419 0.0143 0.0154 0.0165
# per tape and
reel
Figure 2. Package Dimensions for
CM2009-05CP 14-bump Chip Scale Package
3500
Controlling dimension: millimeters
Rev. P2 | Page 7 of 8 | www.onsemi.com
CM2009-05CP
CSP Tape and Reel Specifications
PART NUMBER
CHIP SIZE (mm)
POCKET SIZE (mm)
B0 x A0 x K0
TAPE WIDTH
W
REEL
DIAMETER
QTY PER
REEL
P0
P1
CM2009-05CP
2.00 x 1.10 x 0.58
2.20 x 1.22 x 0.73
8mm
178mm (7")
3500
4mm
4mm
+
+
+
Figure 3. Tape and Reel Mechanical Data
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any
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Rev. P2 | Page 8 of 8 | www.onsemi.com
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