ON MC74VHCT74ADT Dual d−type flip−flop with set and reset Datasheet

MC74VHCT74A
Dual D−Type Flip−Flop
with Set and Reset
The MC74VHCT74A is an advanced high speed CMOS D−type
flip−flop fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
The signal level applied to the D input is transferred to Q output
during the positive going transition of the Clock pulse.
Reset (RD) and Set (SD) are independent of the Clock (CP) and are
accomplished by setting the appropriate input Low.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because it
has full 5.0 V CMOS level output swings.
The VHCT74A input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
The output structures also provide protection when VCC = 0 V. These
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
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MARKING DIAGRAMS
14
SOIC−14
D SUFFIX
CASE 751A
1
1
14
High Speed: fmax = 60 MHz (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 4.5 V to 5.5 V Operating Range
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 128 FETs or 32 Equivalent Gates
Pb−Free Packages are Available
RD1
D1
CP1
SD1
1
RD2
2
5
3
6
4
D2
Q1
Q1
CP2
SD2
13
12
9
11
8
Q2
Q2
10
VHCT
74A
ALYWG
G
TSSOP−14
DT SUFFIX
CASE 948G
1
A
= Assembly Location 1
WL, L = Wafer Lot
Y
= Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
Features
•
•
•
•
•
•
•
•
•
•
•
VHCT74AG
AWLYWW
RD1
1
14
VCC
D1
2
13
RD2
CP1
3
12
D2
SD1
4
11
CP2
Q1
5
10
SD2
Q1
6
9
Q2
GND
7
8
Q2
Figure 1. Pin Assignment
FUNCTION TABLE
Inputs
Outputs
SD
RD
CP
D
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
H
L
X
X
X
L
H
Q
Q
H
L
L
H
H*
H*
H
L
L
H
No Change
No Change
No Change
*Both outputs will remain high as long as Set and Reset
are low, but the output states are unpredictable if Set
and Reset go high simultaneously.
Figure 2. Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 3 of
this data sheet.
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 5
1
Publication Order Number:
MC74VHCT74A/D
MC74VHCT74A
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MAXIMUM RATINGS
Symbol
Value
Unit
VCC
DC Supply Voltage
Parameter
–0.5 to + 7.0
V
Vin
DC Input Voltage
–0.5 to + 7.0
V
Vout
DC Output Voltage VCC = 0
High or Low State
–0.5 to + 7.0
–0.5 to VCC + 0.5
V
IIK
Input Diode Current
−20
mA
IOK
Output Diode Current (VOUT < GND; VOUT > VCC)
±20
mA
Iout
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±50
mA
PD
Power Dissipation in Still Air,
500
450
mW
Tstg
Storage Temperature
–65 to + 150
°C
SOIC Packages†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating − SOIC Packages: – 7 mW/°C from 65° to 125°C
TSSOP Package: − 6.1 mW/°C from 65° to 125°C
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RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
4.5
5.5
V
VCC
DC Supply Voltage
Vin
DC Input Voltage
0
5.5
V
Vout
DC Output Voltage VCC = 0
High or Low State
0
0
5.5
VCC
V
−40
+ 85
°C
0
20
ns/V
TA
Operating Temperature
tr, tf
Input Rise and Fall Time
VCC =5.0 V ± 0.5 V
DC ELECTRICAL CHARACTERISTICS
Min
2.0
Symbol
Parameter
VIH
Minimum High−Level Input Voltage
4.5 to 5.5
VIL
Maximum Low−Level Input Voltage
4.5 to 5.5
VOH
Minimum High−Level Output
Voltage
Vin = VIH or VIL
IOH = −50 mA
4.5
4.4
IOH = −8 mA
4.5
3.94
Maximum Low−Level Output
Voltage
Vin = VIH or VIL
IOL = 50 mA
4.5
IOL = 8 mA
VOL
Test Conditions
TA = 25°C
VCC
V
Typ
TA = − 40 to 85°C
Max
Min
Max
2.0
0.8
4.5
Unit
V
0.8
V
V
4.4
3.80
0.0
0.1
0.1
4.5
0.36
0.44
V
Iin
Maximum Input Leakage Current
Vin = 5.5 V or GND
0 to 5.5
±0.1
±1.0
mA
ICC
Maximum Quiescent Supply Current
Vin = VCC or GND
5.5
2.0
20.0
mA
ICCT
Quiescent Supply Current
Per Input: VIN = 3.4 V
Other Input: VCC or GND
5.5
1.35
1.50
mA
IOPD
Output Leakage Current
VOUT = 5.5 V
0
0.5
5.0
mA
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2
MC74VHCT74A
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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
Symbol
Parameter
Min
Test Conditions
TA = − 40 to 85°C
Typ
Max
Min
Max
Unit
tPLH,
tPHL
Maximum Propagation Delay,
CP to Q or Q
VCC = 5.0 ± 0.5V
CL = 15 pF
CL = 50 pF
5.8
6.3
7.8
8.8
1.0
1.0
9.0
10.0
ns
tPLH,
tPHL
Maximum Propagation Delay,
SD or RD to Q or Q
VCC = 5.0 ± 0.5V
CL = 15 pF
CL = 50 pF
7.6
8.1
10.4
11.4
1.0
1.0
12.0
13.0
ns
fmax
Maximum Clock Frequency
(50% Duty Cycle)
VCC = 5.0 ± 0.5V
CL = 15 pF
CL = 50 pF
Cin
Maximum Input Capacitance
100
80
160
140
80
65
4
MHz
10
10
pF
Typical @ 25°C, VCC = 5.0 V
CPD
24
Power Dissipation Capacitance (Note 1)
pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 2 (per flip−flop). CPD is used to determine the
no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
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TIMING REQUIREMENTS (Input tr = tf = 3.0 ns)
Symbol
Parameter
Guaranteed Limit
VCC
V
TA = 25°C
TA = − 40 to 85°C
Unit
tw
Minimum Pulse Width, CP
5.0 ± 0.5
5.0
5.0
ns
tw
Minimum Pulse Width, RD or SD
5.0 ± 0.5
5.0
5.0
ns
tsu
Minimum Setup Time, D to CP
5.0 ± 0.5
5.0
5.0
ns
th
Minimum Hold Time, D to CP
5.0 ± 0.5
0.0
0.0
ns
Minimum Recovery Time, SD or RD to CP
5.0 ± 0.5
3.5
3.5
ns
trec
ORDERING INFORMATION
Package
Shipping †
MC74VHCT74AD
SOIC−14
55 Units / Rail
MC74VHCT74ADR2
SOIC−14
2500 / Tape & Reel
MC74VHCT74ADR2G
SOIC−14
(Pb−Free)
2500 / Tape & Reel
MC74VHCT74ADT
TSSOP−14*
96 Units / Rail
MC74VHCT74ADTR2
TSSOP−14*
2500 / Tape & Reel
MC74VHCT74ADTR2G
TSSOP−14*
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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3
MC74VHCT74A
tw
SD or RD
3V
CP
1.5 V
GND
1.5V VCC
Q or Q
1/fmax
Q or Q
GND
tPHL
tw
tPLH
3V
1.5 V
tPLH
tPHL
VOH
1.5 V
3V
1.5V VCC
Q or Q
GND
trec
VOL
3V
1.5V
CP
Figure 3. Switching Waveform
GND
Figure 4. Switching Waveform
TEST POINT
VALID
D
tsu
CP
OUTPUT
3V
1.5 V
DEVICE
UNDER
TEST
GND
th
3V
1.5 V
C L*
GND
*Includes all probe and jig capacitance
Figure 5. Switching Waveform
Figure 6. Switching Waveform
INPUT
Figure 7. Input Equivalent Circuit
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4
MC74VHCT74A
PACKAGE DIMENSIONS
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE G
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
M
B
M
7
1
G
F
R X 45 _
C
−T−
SEATING
PLANE
D 14 PL
0.25 (0.010)
M
T B
J
M
K
S
A
S
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5
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
MC74VHCT74A
PACKAGE DIMENSIONS
TSSOP−14
DT SUFFIX
CASE 948G−01
ISSUE A
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
F
7
1
0.15 (0.006) T U
N
S
DETAIL E
K
A
−V−
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
J J1
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
G
H
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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Phone: 81−3−5773−3850
http://onsemi.com
6
ON Semiconductor Website: www.onsemi.com
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For additional information, please contact your local
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MC74VHCT74A/D
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