LODEV LF3347 High-speed image filter with coefficient ram Datasheet

LF3347
LF3347
DEVICES INCORPORATED
High-Speed Image Filter with Coefficient RAM
High-Speed Image Filter with Coefficient RAM
DEVICES INCORPORATED
FEATURES
DESCRIPTION
❑ 83 MHz Data Input and Computation Rate
❑ Four 12 x 12-bit Multipliers with
Individual Data and Coefficient
Inputs
❑ Four 256 x 12-bit Coefficient Banks
❑ 32-bit Accumulator
❑ Selectable 16-bit Data Output with
User-Defined Rounding and Limiting
❑
❑
❑
❑
Two’s Complement Operands
3.3 Volt Power Supply
5 Volt Tolerant I/O
120-pin PQFP
A 32-bit accumulator allows cumulative word growth which may be
internally rounded to 16-bits. Output
data is updated every clock cycle and
may be held under user control. The
data inputs/outputs and control
inputs are registered on the rising
edge of CLK. The Control/Coefficient Data Input, CC11-0, is registered
on the rising edge of CCCLK.
The LF3347 consists of an array of
four 12 x 12-bit registered multipliers
followed by two summers and a
32-bit accumulator. The LF3347
provides four 256 x 12-bit coefficient
banks which are capable of storing
256 different sets of filter coefficients
for the multiplier array. All multiplier data inputs are user accessible
and can be updated every clock cycle
with two’s complement data. The
pipelined architecture has fully
registered input and output ports and
an asynchronous three-state output
enable control to simplify the design
of complex systems.
The LF3347 is ideal for performing
pixel interpolation in image manipulation and filtering applications. The
LF3347 can perform a bilinear interpolation of an image (4-pixel kernels)
at real-time video rates when used
LF3347 BLOCK DIAGRAM
12
CC11-0
LF
INTERFACE
LD
CCCLK
ENBA
Coefficient
Bank 1
(256 x 12-bit)
8
A7-0
D111-0
Coefficient
Bank 2
(256 x 12-bit)
ENB1
12
D211-0
12
12
2
Coefficient
Bank 3
(256 x 12-bit)
ENB2
D311-0
12
12
2
ENB3
D411-0
12
ENB4
12
2
12
2
25
ACC
Coefficient
Bank 4
(256 x 12-bit)
25
3
SELRND3-0
4
SELLMT3-0
4
LMTEN
4
6
6
32
4
SHIFT4-0
5
5
5
Rounding
Selecting
Limiting
Circuit
4
Rounding/
Limiting
Registers
16
OCEN
OE
16
CLK
TO ALL REGISTERS
S15-0
NOTE: NUMBERS IN REGISTERS INDICATE
NUMBER OF PIPELINE DELAYS
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LF3347
DEVICES INCORPORATED
with an image resampling sequencer. Larger kernels or more
complex functions can be realized
by utilizing multiple devices.
High-Speed Image Filter with Coefficient RAM
FIGURE 1.
INPUT FORMATS
Data
Coefficient
Fractional Two's Complement
Unrestricted access to all data
ports and addressable coefficient
banks provides the LF3347 with
considerable flexibility in applications such as digital filters, adaptive FIR filters, mixers, and other
similar systems requiring highspeed processing.
11 10 9
–20 2–1 2–2
2 1 0
2–9 2–10 2–11
11 10 9
–20 2–1 2–2
(Sign)
2 1 0
2–9 2–10 2–11
(Sign)
Integer Two's Complement
11 10 9
–211 210 29
2 1 0
22 21 20
11 10 9
–211 210 29
2 1 0
22 21 20
(Sign)
(Sign)
SIGNAL DEFINITIONS
Power
TABLE 1. OUTPUT FORMATS
SHIFT4-0
S15 S14 S13
+3.3 V power supply. All pins must
be connected.
00000
F15 F14 F13
00001
F16 F15 F14
Clocks
00010
F17 F16 F15
VCC and GND
CLK — Master Clock
The rising edge of CLK strobes all
enabled registers.
·
·
·
·
·
·
·
·
·
·
·
·
01110
F29 F28 F27
CCCLK — Coefficient/Control Clock
01111
F30 F29 F28
When LD is LOW, the rising edge of
CCCLK latches data on CC11-0 into the
device.
10000
F31 F30 F29
Inputs
D111-0 – D411-0 — Data Input
D1–D4 are the 12-bit registered data
input ports. Data is latched on the
rising edge of CLK.
···
···
···
···
···
···
···
CC11-0 — Control/Coefficient Data Input
CC11-0 is used to load data into the
coefficient banks and control registers. Data present on CC11-0 is
latched on the rising edge of CCCLK
when LD is LOW.
Outputs
A7-0 — Row Address
S15-0 — Data Output
A7-0 determines which row in the
coefficient banks feed data to the
multipliers. A 7-0 is latched on the
rising edge of CLK. When a new
row address is loaded into the row
address register, data from the
coefficient banks will be latched into
the multiplier input registers on the
next rising edge of CLK.
S15-0 is the 16-bit registered data
output port.
Controls
S8
S7
F8
F7
F9
F8
F10
F9
·
·
·
·
·
·
F22 F21
F23 F22
F24 F23
···
···
···
···
···
···
···
S2
S1
S0
F2
F1
F0
F3
F2
F1
F4
F3
F2
·
·
·
·
·
·
·
·
·
F16 F15 F14
F17 F16 F15
F18 F17 F16
CLK. When ENBN is HIGH, data on
D N11-0 is not latched into the DN
register and the register contents
will not be changed.
ENBA — Row Address Input Enable
The ENBA input allows the row
address register to be updated on
each clock cycle. When ENBA is
LOW, data on A 7-0 is latched into
the row address register on the rising
edge of CLK. When ENBA is HIGH,
data on A 7-0 is not latched into the
row address register and the register
contents will not be changed.
ENB1–ENB4 — Data Input Enables
The ENBN (N = 1, 2, 3, or 4) inputs
allow the DN registers to be updated
on each clock cycle. When ENBN is
LOW, data on DN11-0 is latched into
the DN register on the rising edge of
OE — Output Enable
When OE is LOW, S15-0 is enabled for
output. When OE is HIGH, S15-0 is
placed in a high-impedance state.
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DEVICES INCORPORATED
TABLE 2.
High-Speed Image Filter with Coefficient RAM
REGISTER FORMATS
Register
Load Address
Bits
Register Description
A7-0
CS0
CS1
000H
001H
11-0
11-0
Coefficient Set 0
Coefficient Set 1
00H
01H
CS255
0FFH
11-0
Coefficient Set 255
FFH
RND0
RND1
800H
801H
31-0
31-0
Rounding Register 0
Rounding Register 1
0000
0001
RND15
80FH
31-0
Rounding Register 15
1111
LMT0
LMT1
C00H
C01H
31-16/15-0
31-16/15-0
Upper / Lower Limit Register 0
Upper / Lower Limit Register 0
0000
0001
LMT15
C0FH
31-16/15-0 Upper / Lower Limit Register 15
1111
·
··
·
··
··
·
·
··
·
··
··
·
·
··
·
··
··
·
OCEN — Output Clock Enable
When OCEN is LOW, the output
register is enabled for data loading.
When OCEN is HIGH, output register
loading is disabled and the register’s
contents will not change.
ACC — Accumulator Control
The ACC input determines whether
internal accumulation is performed. If
ACC is LOW, no accumulation is
performed, the prior accumulated sum
is cleared, and the current sum of
products is output. When ACC is
HIGH, the emerging product is added
to the sum of the previous products.
LD — Load Control
LD enables the loading of data into the
coefficient banks and control registers
(control registers are the round and limit
registers). When LD is LOW, data on
CC11-0 is latched into the device on the
rising edge of CCCLK. When LD is
HIGH, data cannot be loaded into the
coefficient banks and control registers.
When enabling the input circuitry for
data loading, the LF3347 requires a
HIGH to LOW transition of LD in order
to function properly. Therefore, LD
needs to be set HIGH immediately after
·
··
SELRND3-0 SELLMT3-0
·
··
·
··
·
··
··
·
power up to ensure proper operation of
the input circuitry.
It takes five CCCLK clock cycles to load
one coefficient set into the four coefficient
banks or to load one control register.
When the input circuitry is enabled (LD
goes LOW), the first value loaded into the
device on CC11-0 is an address which
determines what will be loaded (see
Table 2). The next four values loaded on
CC11-0 is the data to be loaded into the
coefficient banks or control register (see
Tables 3-5). After the last data value is
loaded, another coefficient bank address
or control register may be loaded by
feeding another address into CC11-0.
When all desired coefficient banks and
control registers are loaded, the input
circuitry must be disabled by setting LD HIGH.
SELRND3-0 — Round Select
SELRND3-0 allows the user to select
which rounding register will be used
in the rounding circuit to round/offset
the data.
··
·
FIGURE 2. ROUNDING, SELECTING,
LIMITING CIRCUITRY
32
RND31-0
RND
32
32
SHIFT4-0
SELECT
16
16
ULMT15-0
LLMT15-0
LIMIT
LMTEN
16
SELLMT3-0 — Limit Select
SELLMT3-0 allows the user to control
which limiting register will be used in
the limiting circuit to set the upper
and lower limits on the data.
LMTEN — Limit Enable
SHIFT4-0 — Shift
SHIFT4-0 determines which 16-bits of
the 32-bits from the accumulator are
passed to the output (see Table 1).
When LMTEN is LOW, limiting is
enabled and the selected limit register
is used to determine the valid range of
output values for the overall filter.
When HIGH, limiting is disabled.
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DEVICES INCORPORATED
FUNCTIONAL DESCRIPTION
Coefficient Banks
The LF3347 has four coefficient banks
which feed coefficient values to the
multipliers. Each bank can store 256
12-bit coefficients. In the example
shown in Table 3, address 10 in coefficient banks 1 through 4 is loaded with
the following values: ABCH, 789H,
456H, 123H. The coefficient banks are
not written to until all four coefficients
have been loaded into the device.
A7-0 determines which coefficient set is
sent to the multipliers. A value of 0 on
A7-0 selects set 0. A value of 1 selects
set 1 and so on.
Rounding/Offset
The accumulator output may be rounded
before being sent to the output select
section. Rounding is user-selectable and
is accomplished by adding the contents of
a round register to the accumulator
output (see Figure 2). There are sixteen
32-bit round registers. In the example in
Table 4, round register 10 is loaded with
76543210H. A round register is not
written to until all four data values have
been loaded into the device.
SELRND3-0 determines which round
register is used for rounding. A value of 0
on SELRND3-0 selects round register 0. A
value of 1 selects round register 1 and so
on. If rounding is not desired, a round
register should be loaded with 0 and
selected as the register for rounding.
Output Select
High-Speed Image Filter with Coefficient RAM
registers. Each limit register contains both
an upper and lower limit value. The
lower limit is stored in bits 15-0 and the
upper limit is stored in bits 31-16. If the
value fed to the limiting circuitry is less
than the lower limit, the lower limit is
passed to the device output. If the value
fed to the limiting circuitry is greater than
the upper limit, the upper limit is passed
to the device output. When loading limit
values into the device, the upper limit must
TABLE 3.
be greater than the lower limit. In the
example shown in Table 4, limit register
15 is loaded with a lower limit of 0123H
and an upper limit of 7FEDH. A limit
register is not written to until all four data
values have been loaded into the device.
SELLMT3-0 determines which limit
register is used for limiting. A value of 0
on SELLMT3-0 selects limit register 0. A
value of 1 selects limit register 1 and so on.
COEFFICIENT BANK LOADING FORMAT
CC11 CC10 CC9 CC8 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0
1st Word
Address
2nd Word
Bank 1
3rd Word
Bank 2
4th Word
Bank 3
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
0
0
1
0
1
0
0
0
1
0
1
0
1
1
0
5th Word
Bank 4
0
0
0
1
0
0
1
0
0
0
1
1
TABLE 4.
ROUND REGISTER LOADING FORMAT
CC11 CC10 CC9 CC8 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0
1st Word
Address
1
0
0
0
0
0
0
0
1
0
1
0
2nd Word
R
R
R
R
0
0
0
1
0
0
0
*0
3rd Word
R
R
R
R
0
0
1
1
0
0
1
0
4th Word
R
R
R
R
0
1
0
1
0
1
0
0
5th Word
R
R
R
R
**0
1
1
1
0
1
1
0
R = Reserved. Must be set to “0”.
* This bit represents the LSB of the Round Register.
** This bit represents the MSB of the Round Register.
TABLE 5.
LIMIT REGISTER LOADING FORMAT
The filter output word width is 32-bits.
However, only 16-bits may be sent to the
device output. SHIFT4-0 determines
which 16 bits are passed to the device
output (See Table 1).
1st Word
Address
2nd Word
1
1
0
0
0
0
0
0
1
1
1
1
R
R
R
R
0
0
1
0
0
0
1
1
Output Limiting
3rd Word
R
R
R
R
*0
0
0
0
0
0
0
1
4th Word
R
R
R
R
1
1
1
0
1
1
0
1
5th Word
R
R
R
R
**0
1
1
1
1
1
1
1
An output limiting function is provided
for the output of the filter. When limiting is
enabled (LMTEN LOW), the limit register
selected with SELLMT3-0 determines the
valid range of output values for the overall
filter. There are sixteen 32-bit limit
CC11 CC10 CC9 CC8 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0
R = Reserved. Must be set to “0”.
* This bit represents the MSB of the Lower Limit Register.
** This bit represents the MSB of Upper Limit Register.
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DEVICES INCORPORATED
High-Speed Image Filter with Coefficient RAM
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature ........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground ............................................................................ –0.5 V to +4.5 V
Input signal with respect to ground .......................................................................................... –0.5 V to 5.5 V
Signal applied to high impedance output ................................................................................. –0.5 V to 5.5 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
ESD Classification (MIL-STD-883E METHOD 3015.7) ...................................................................... Class 3
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode
Temperature Range (Ambient)
Active Operation, Commercial
Active Operation, Military
Supply Voltage
0°C to +70°C
3.00 V ≤ VCC ≤ 3.60 V
–55°C to +125°C
3.00 V ≤ VCC ≤ 3.60 V
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol
Parameter
Test Condition
Min
VOH
Output High Voltage
VCC = Min., IOH = –4 mA
2.4
VOL
Output Low Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input High Voltage
VIL
Input Low Voltage
(Note 3)
IIX
Input Current
IOZ
Typ
Max
Unit
V
0.4
V
2.0
VCC
V
0.0
0.8
V
Ground ≤ VIN ≤ VCC (Note 12)
±10
µA
Output Leakage Current
Ground ≤ VOUT ≤ VCC (Note 12)
±10
µA
ICC1
VCC Current, Dynamic
(Notes 5, 6)
150
mA
ICC2
VCC Current, Quiescent
(Note 7)
2
mA
CIN
Input Capacitance
TA = 25°C, f = 1 MHz
10
pF
COUT
Output Capacitance
TA = 25°C, f = 1 MHz
10
pF
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LF3347
DEVICES INCORPORATED
High-Speed Image Filter with Coefficient RAM
SWITCHING CHARACTERISTICS
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)
Symbol
LF3347–
1234567890123456
1234567890123456
1234567890123456
*
25
15
1234567890123456
1234567890123456
1234567890123456
Min
Max
Min
Max
1234567890123456
1234567890123456
25
15
1234567890123456
1234567890123456
1234567890123456
1234567890123456
10
7
1234567890123456
1234567890123456
1234567890123456
10
7
1234567890123456
1234567890123456
1234567890123456
8
5
1234567890123456
1234567890123456
1234567890123456
0
0
1234567890123456
1234567890123456
1234567890123456
13
10
1234567890123456
1234567890123456
1234567890123456
1234567890123456
15
12
1234567890123456
1234567890123456
1234567890123456
13
11
1234567890123456
Parameter
tCYC
Cycle Time
tPWL
Clock Pulse Width Low
tPWH
Clock Pulse Width High
tS
Input Setup Time
tH
Input Hold Time
tD
Output Delay
tDIS
Three-State Output Disable Delay (Note 11)
tENA
Three-State Output Enable Delay (Note 11)
12
Min
Max
12
5
5
3
0
8
10
8
MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)
Symbol
1234567890123456789012345678901212345678901234
LF3347–
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
*
25
15*
12*
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
Min
Max
Min
Max
Min
Max
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
25
15
12
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
10
7
5
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
10
7
5
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
8
5
3
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
0
0
0
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
13
10
8
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
15
12
10
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
13
11
8
1234567890123456789012345678901212345678901234
Parameter
tCYC
Cycle Time
tPWL
Clock Pulse Width Low
tPWH
Clock Pulse Width High
tS
Input Setup Time
tH
Input Hold Time
tD
Output Delay
tDIS
Three-State Output Disable Delay (Note 11)
tENA
Three-State Output Enable Delay (Note 11)
SWITCHING WAVEFORMS:
DATA I/O
1
2
3
4
5
6
7
CLK
tH
tS
tPWL
D111-0 – D411-0
DN
DN+1
A7-0
AN
AN+1
tPWH
tCYC
CONTROLS
(Except OE)
OE
tDIS
S15-0
tENA
tD
HIGH IMPEDANCE
SN-1
SN
123456789012345678901234
123456789012345678901234
123456789012345678901234
*DISCONTINUED SPEED GRADE
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LF3347
DEVICES INCORPORATED
High-Speed Image Filter with Coefficient RAM
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)
Symbol
12345678901234567
LF3347–
12345678901234567
12345678901234567
*
25
15
12345678901234567
12345678901234567
12345678901234567
Min
Max
Min
Max
12345678901234567
12345678901234567
12345678901234567
25
15
12345678901234567
12345678901234567
12345678901234567
10
7
12345678901234567
12345678901234567
12345678901234567
10
7
12345678901234567
12345678901234567
12345678901234567
8
5
12345678901234567
12345678901234567
12345678901234567
12345678901234567
0
0
12345678901234567
12345678901234567
12345678901234567
8
5
12345678901234567
12345678901234567
12345678901234567
0
0
12345678901234567
Parameter
tCCCYC Control Coefficient Interface Cycle Time
tCCWL
Control Coefficient Clock Pulse Width Low
tCCWH
Control Coefficient Clock Pulse Width High
tCCENS Control Coefficient Enable Setup Time
tCCENH Control Coefficient Enable Hold Time
tCCS
Control Coefficient Data Input Setup Time
tCCH
Control Coefficient Data Input Hold Time
12
Min
Max
12
5
5
3
0
5
0
MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)
Symbol
LF3347–
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
*
1234567890123456789012345678901212345678901234
25
15*
12*
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
Min
Max
Min
Max
Min
Max
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
25
15
12
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
10
7
5
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
10
7
5
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
8
5
3
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
0
0
0
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
8
5
5
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
0
0
0
1234567890123456789012345678901212345678901234
Parameter
tCCCYC Control Coefficient Interface Cycle Time
tCCWL
Control Coefficient Clock Pulse Width Low
tCCWH
Control Coefficient Clock Pulse Width High
tCCENS Control Coefficient Enable Setup Time
tCCENH Control Coefficient Enable Hold Time
tCCS
Control Coefficient Data Input Setup Time
tCCH
Control Coefficient Data Input Hold Time
SWITCHING WAVEFORMS:
COEFFICIENT BANK AND CONTROL REGISTER INPUT
1
2
3
4
5
6
CCCLK
tCCENS
tCCWL
LD
tCCS
CC11–0
tCCENH
tCCWH
W
tSCYC
tCCH
ADDRESS
C0
C1
C2
C3
W: Coefficient Banks/Control Registers written to on this clock cycle.
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*DISCONTINUED SPEED GRADE
Video Imaging Products
7
08/16/2000–LDS.3347-G
LF3347
DEVICES INCORPORATED
High-Speed Image Filter with Coefficient RAM
NOTES
1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond
those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tDIS test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified IOH and IOL at an output
voltage of VOH min and VOL max
2. The products described by this spec- respectively. Alternatively, a diode
ification include internal circuitry de- bridge with upper and lower current
signed to protect the chip from damagsources of IOH and I OL respectively,
ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be
cumulations of static charge. Never- used. Parasitic capacitance is 30 pF
theless, conventional precautions minimum, and may be distributed.
should be observed during storage,
handling, and use of these circuits in This device has high-speed outputs caorder to avoid exposure to excessive pable of large instantaneous current
electrical stress values.
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
3. This device provides hard clamping testing of this device. The following
of transient undershoot. Input levels measures are recommended:
below ground will be clamped beginning at –0.6 V. The device can with- a. A 0.1 µF ceramic capacitor should be
stand indefinite operation with inputs installed between VCC and Ground
or outputs in the range of –0.5 V to leads as close to the Device Under Test
+5.5 V. Device operation will not be (DUT) as possible. Similar capacitors
adversely affected, however, input cur- should be installed between device VCC
rent levels will be well in excess of 100 and the tester common, and device
mA.
ground and tester common.
4. Actual test conditions may vary from b. Ground and VCC supply planes
those designated but operation is guar- must be brought directly to the DUT
socket or contactor fingers.
anteed as specified.
5. Supply current for a given application can be accurately approximated
by:
NCV2 F
4
where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing every cycle and no load, at a 30 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
c. Input voltages on a test fixture
should be adjusted to compensate for
inductive ground and VCC noise to maintain required DUT input levels relative
to the DUT ground pin.
11. For the tENA test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the tDIS test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing voltage, V TH , is set at 3.0 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
S1
DUT
IOL
VTH
CL
IOH
FIGURE B. THRESHOLD LEVELS
tENA
OE
Z
tDIS
1.5 V
1.5 V
3.0V Vth
0
1.5 V
1.5 V
Z
1
VOL*
0.2 V
VOH*
0.2 V
0
Z
1
Z
0V Vth
VOL* Measured VOL with IOH = –10mA and IOL = 10mA
VOH* Measured VOH with IOH = –10mA and IOL = 10mA
10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the external system must supply at least that
much time to meet the worst-case requirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
Video Imaging Products
8
08/16/2000–LDS.3347-G
LF3347
DEVICES INCORPORATED
High-Speed Image Filter with Coefficient RAM
ORDERING INFORMATION
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
CLK
GND
SELRND3
SELRND2
SELRND1
SELRND0
ACC
ENB4
D411
D410
D49
D48
D47
D46
D45
D44
D43
D42
D41
D40
VCC
GND
ENB3
D311
D310
D39
D38
D37
D36
D35
120-pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
Top
View
D34
D33
D32
D31
D30
CC11
CC10
CC9
CC8
CC7
CC6
CC5
CC4
CC3
CC2
CC1
CC0
CCCLK
LD
ENBA
GND
VCC
A7
A6
A5
A4
A3
A2
A1
A0
VCC
GND
ENB1
D111
D110
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
VCC
GND
ENB2
D211
D210
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
SHIFT0
SHIFT1
SHIFT2
SHIFT3
SHIFT4
SELLMT0
SELLMT1
SELLMT2
SELLMT3
LMTEN
OCEN
OE
VCC
GND
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Plastic Quad Flatpack
(Q1)
Speed
0°C to +70°C — COMMERCIAL SCREENING
15 ns
12 ns
LF3347QC15
LF3347QC12
Video Imaging Products
9
08/16/2000–LDS.3347-G
LF3347
DEVICES INCORPORATED
High-Speed Image Filter with Coefficient RAM
ORDERING INFORMATION
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
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1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
120-pin
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1
2
3
4
5
6
7
8
9
10
11
12
13
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A
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CLK SRND2 SRND1 ENB4 D410 D47 D46 D43 D40 GND D310 D37 D34
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B
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SHIFT2 SHIFT1 GND SRND0 D411 D48 D44 D42 VCC D311 D39 D36 D31
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C
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SLMT0 SHIFT4 SHIFT0 SRND3 ACC D49 D45 D41 ENB3 D38 D35 D33 D30
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D
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D32 CC11 CC9
SLMT3 SLMT1 SHIFT3
KEY
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E
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CC10 CC8 CC7
OCEN LMTEN SLMT2
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F
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Top View
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GND VCC OE
CC6 CC5 CC4
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Through Package
G
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S13 S15 S14
CC2 CC1 CC3
(i.e., Component Side Pinout)
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H
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S12 S11 S10
LD CCCLK CC0
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J
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A7 GND ENBA
S9
S8
S6
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K
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S7
S5
S2
A3
A6 VCC
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L
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S4
S1 VCC D111 D17 D13 VCC D210 D26 D22 A0
A4
A5
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1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
M
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S3 GND D110 D18 D15 D12 D10 D211 D28 D25 D21 A1
A2
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
N
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S0 ENB1 D19 D16 D14 D11 GND ENB2 D29 D27 D24 D23 D20
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
Discontinued Package
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Ceramic Pin Grid Array
(G4)
Speed
0°C to +70°C — COMMERCIAL SCREENING
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
Video Imaging Products
10
08/16/2000–LDS.3347-G
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