Product Folder Order Now Support & Community Tools & Software Technical Documents ISO1042 SLLSF09 – DECEMBER 2017 1 Features 3 Description • The ISO1042 device is a galvanically-isolated controller area network (CAN) transceiver that meets the specifications of the ISO11898-2 (2016) standard. The ISO1042 device offers ±70-V DC bus fault protection and ±30-V common-mode voltage range. The device supports up to 5-Mbps data rate in CAN FD mode allowing much faster transfer of payload compared to classic CAN. This device uses a silicon dioxide (SiO2) insulation barrier with a withstand voltage of 5000 VRMS. Used in conjunction with isolated power supplies, the device prevents noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. The ISO1042 device is available for both basic and reinforced isolation (see Reinforced and Basic Isolation Options). 1 • • • • • • • • • • • Meets the ISO 11898-2:2016 and ISO 118985:2007 Physical Layer Standards Supports Classic CAN up to 1 Mbps and FD (Flexible Data Rate) up to 5 Mbps Low Loop Delay: 138 ns Protection Features – DC Bus Fault Protection Voltage: ±70 V – Driver Dominant Time Out (TXD DTO) Common-Mode Voltage Range: ±30 V Ideal Passive, High Impedance Bus and Logic Terminals When Unpowered High CMTI: 100 kV/µs VCC1 Voltage Range: 1.71 V to 5.5 V VCC2 Voltage Range: 4.5 V to 5.5 V Ambient Temperature Range: –40°C to +125°C 16-SOIC and Compact 8-SOIC Package Options Safety-Related Certifications: – 7071-VPK VIOTM and 1500-VPK VIORM (Reinforced and Basic Options) per DIN V VDE V0884-11 – 5000-VRMS Isolation for 1 Minute per UL 1577 – IEC 60950, IEC 60601 and EN 61010 certifications – CQC, TUV and CSA Certifications – All Certifications Planned The ISO1042 device supports a wide ambient temperature range of –40°C to +125°C. The device is available in the SOIC-16 (DW) package and a smaller SOIC-8 (DWV) package. Device Information(1) PART NUMBER ISO1042 AC and Servo Drives Solar Inverters PLC and DCS Communication Modules Elevators and Escalators Industrial Power Supplies Battery Charging and Management BODY SIZE (NOM) 5.85 mm × 7.50 mm SOIC (16) 10.30 mm × 7.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Reinforced and Basic Isolation Options 2 Applications • • • • • • PACKAGE SOIC (8) FEATURE ISO1042x ISO1042Bx Protection Level Reinforced Basic Surge Test Voltage 10000 VPK 6000 VPK Isolation Rating 5000 VRMS 5000 VRMS Working Voltage 1000 VRMS / 1500 VPK 1000 VRMS / 1500 VPK Application Diagram VCC1 1 VDD TXD MCU RXD DGND 2 3 4 Digital Ground VCC1 TXD VCC2 ISO1042 CANH CANL 8 VCC2 7 6 CAN Bus RXD GND1 GND2 Galvanic Isolation Barrier 5 ISO Ground Copyright © 2017, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. ADVANCE INFORMATION ISO1042 Isolated CAN Transceiver With 70-V Bus Fault Protection and Flexible Data Rate ISO1042 SLLSF09 – DECEMBER 2017 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 ADVANCE INFORMATION 7 7.2 Functional Block Diagram ....................................... 13 7.3 Feature Description................................................. 13 7.4 Device Functional Modes........................................ 17 1 1 1 2 3 5 8 Application and Implementation ........................ 18 8.1 Application Information............................................ 18 8.2 Typical Application .................................................. 18 9 Power Supply Recommendations...................... 20 10 Layout................................................................... 21 Absolute Maximum Ratings ...................................... 5 Transient Immunity.................................................... 5 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 5 Power Ratings........................................................... 6 Insulation Specifications............................................ 7 Safety-Related Certifications..................................... 8 Safety Limiting Values .............................................. 8 Electrical Characteristics - DC Specification............. 9 Switching Characteristics ...................................... 11 Insulation Characteristics Curves ......................... 12 10.1 Layout Guidelines ................................................. 21 10.2 Layout Example .................................................... 21 11 Device and Documentation Support ................. 23 11.1 11.2 11.3 11.4 11.5 11.6 Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resource............................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 23 23 23 23 23 23 12 Mechanical, Packaging, and Orderable Information ........................................................... 23 Detailed Description ............................................ 13 7.1 Overview ................................................................. 13 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 2 DATE REVISION NOTES December 2017 * Initial release. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1042 ISO1042 www.ti.com SLLSF09 – DECEMBER 2017 5 Pin Configuration and Functions DW Package 16-Pin SOIC Top View 1 16 VCC2 GND1 2 15 GND2 TXD 3 14 NC NC 4 13 CANH RXD 5 12 CANL NC 6 11 VCC2 NC 7 10 NC GND1 8 9 GND2 ADVANCE INFORMATION ISOLATION VCC1 Not to scale Pin Functions—16 Pins PIN NO. NAME I/O DESCRIPTION 1 VCC1 — Digital-side supply voltage, Side 1 2 GND1 — Digital-side ground connection, Side 1 3 TXD I 4 NC — Not connected 5 RXD O CAN receive data output (LOW for dominant and HIGH for recessive bus states) 6 NC — Not connected 7 NC — Not connected 8 GND1 — Digital-side supply voltage, Side 1 9 GND2 — Transceiver-side ground connection, Side 2 10 NC — Not connected 11 VCC2 — Transceiver-side supply voltage, Side 2 12 CANL I/O Low-level CAN bus line 13 CANH I/O High-level CAN bus line 14 NC — Not connected 15 GND2 — Transceiver-side ground connection, Side 2 16 VCC2 — Transceiver-side supply voltage, Side 2 CAN transmit data input (LOW for dominant and HIGH for recessive bus states) Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1042 3 ISO1042 SLLSF09 – DECEMBER 2017 www.ti.com VCC1 1 TXD 2 RXD 3 GND1 4 ISOLATION DWV Package 8-Pin SOIC Top View 8 VCC2 7 CANH 6 CANL 5 GND2 Not to scale Pin Functions—8 Pins PIN NO. 1 NAME VCC1 I/O — DESCRIPTION Digital-side supply voltage, Side 1 ADVANCE INFORMATION 2 TXD I CAN transmit data input (LOW for dominant and HIGH for recessive bus states) 3 RXD O CAN receive data output (LOW for dominant and HIGH for recessive bus states) 4 GND1 — Digital-side supply voltage, Side 1 5 GND2 — Transceiver-side ground connection, Side 2 6 CANL I/O Low-level CAN bus line 7 CANH I/O High-level CAN bus line 8 VCC2 — Transceiver-side supply voltage, Side 2 4 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1042 ISO1042 www.ti.com SLLSF09 – DECEMBER 2017 6 Specifications 6.1 Absolute Maximum Ratings (2) MIN MAX UNIT VCC1 Supply voltage, side 1 -0.5 6 V VCC2 Supply voltage, side 2 -0.5 6 VIO Logic input and output voltage range (TXD and RXD) -0.5 IO Output current on RXD pin -15 15 mA VBUS Voltage on bus pins (CANH, CANL) -70 70 V VBUS_DIFF Differential voltage on bus pins (CANH-CANL) -70 70 V TJ Junction temperature -40 150 ℃ TSTG Storage temperature -65 150 ℃ (1) (2) (3) V VCC1+0.5 (3) V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values. Maximum voltage must not exceed 6 V 6.2 Transient Immunity PARAMETER VPULSE TEST CONDITIONS ISO7637-2 Transients according to GIFT - ICT CAN EMC test specification VALUE UNIT Pulse 1; CAN bus terminals (CANH, CANL) to GND2 -100 V Pulse 2; CAN bus terminals (CANH, CANL) to GND2 75 V Pulse 3a; CAN bus terminals (CANH, CANL) to GND2 -150 V Pulse 3b; CAN bus terminals (CANH, CANL) to GND2 100 V 6.3 Recommended Operating Conditions VCC1 MIN MAX UNIT Supply Voltage, Side 1, 1.8-V operation 1.71 1.89 V Supply Voltage, Side 1, 2.5-V, 3.3-V and 5.5-V operation 2.25 5.5 V VCC2 Supply Voltage, Side 2 4.5 5.5 V TA Operating ambient temperature -40 125 °C 6.4 Thermal Information ISO1042 THERMAL METRIC (1) DW (SOIC) DWV (SOIC) 16 PINS 8 PINS UNIT RΘJA Junction-to-ambient thermal resistance 69.9 100 °C/W RΘJC(top) Junction-to-case (top) thermal resistance 31.8 40.8 °C/W RΘJB Junction-to-board thermal resistance 29.0 51.8 °C/W ΨJT Junction-to-top characterization parameter 13.2 16.8 °C/W ΨJB Junction-to-board characterization parameter 28.6 49.8 °C/W RΘJC(bot) Junction-to-case (bottom) thermal resistance - - °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1042 5 ADVANCE INFORMATION Over operating free-air temperature range (unless otherwise noted) (1) ISO1042 SLLSF09 – DECEMBER 2017 www.ti.com 6.5 Power Ratings PARAMETER PD PD1 PD2 TEST CONDITIONS Maximum power dissipation (both sides) VCC1 = VCC2 = 5.5 V, TJ = 150°C, RL = 50 Ω A repetitive pattern on TXD with 1 ms time period, 990 µs LOW time, and 10 µs HIGH time. Maximum power dissipation (side-1) VCC1 = VCC2 = 5.5 V, TJ = 150°C, RL = 50 Ω , Input a 2-V pk-pk 2.5-MHz 50% duty cycle differential square wave on CANH-CANL Maximum power dissipation (side-2) VCC1 = VCC2 = 5.5 V, TJ = 150°C, RL = 50 Ω A repetitive pattern on TXD with 1 ms time period, 990 µs LOW time, and 10 µs HIGH time. MIN TYP MAX UNIT 385 mW 25 mW 360 mW ADVANCE INFORMATION 6 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1042 ISO1042 www.ti.com SLLSF09 – DECEMBER 2017 6.6 Insulation Specifications PARAMETER SPECIFICATIONS TEST CONDITIONS DW-16 DWV-8 UNIT IEC 60664-1 CLR External clearance (1) Side 1 to side 2 distance through air >8 >8.3 mm CPG External Creepage (1) Side 1 to side 2 distance across package surface >8 >8.3 mm DTI Distance through the insulation Minimum internal gap (internal clearance) >17 >17 µm CTI Comparative tracking index IEC 60112; UL 746A >600 >600 V Material Group According to IEC 60664-1 I I Rated mains voltage ≤ 600 VRMS I-IV I-IV Rated mains voltage ≤ 1000 VRMS I-III I-III Overvoltage category VIORM VIOWM VIOTM Maximum repetitive peak isolation voltage AC voltage (bipolar) 1500 1500 VPK Maximum isolation working voltage AC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test; 1000 1000 VRMS DC voltage 1500 1500 VDC Maximum transient isolation voltage VTEST = VIOTM , t = 60 s (qualification); VTEST = 1.2 × VIOTM, t = 1 s (100% production) 7071 7071 VPK Maximum surge isolation voltage ISO1042 (3) Test method per IEC 62368-1, 1.2/50 µs waveform, VTEST = 1.6 × VIOSM = 10000 VPK (qualification) 6250 6250 VPK Maximum surge isolation voltage ISO1042B (3) Test method per IEC 62368-1, 1.2/50 µs waveform, VTEST = 1.3 × VIOSM = 6000 VPK (qualification) 4600 4600 VPK Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM , tm = 10 s ≤5 ≤5 Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; ISO1042: Vpd(m) = 1.6 × VIORM , tm = 10 s ISO1042B: Vpd(m) = 1.2 × VIORM , tm = 10 s ≤5 ≤5 Method b1: At routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s; ISO1042: Vpd(m) = 1.875 × VIORM , tm = 1 s ISO1042B: Vpd(m) = 1.5 × VIORM , tm = 1 s ≤5 VIOSM Apparent charge (4) qpd Barrier capacitance, input to output (5) CIO Insulation resistance, input to output (5) RIO VIO = 0.4 × sin (2 πft), f = 1 MHz pC ≤5 1 1 VIO = 500 V, TA = 25°C > 1012 > 1012 VIO = 500 V, 100°C ≤ TA ≤ 150°C > 1011 > 1011 9 9 VIO = 500 V at TS = 150°C ADVANCE INFORMATION DIN V VDE V 0884-11:2017-01 (2) > 10 pF Ω > 10 Pollution degree 2 2 Climatic category 40/125/ 21 40/125/ 21 5000 5000 UL 1577 VISO (1) (2) (3) (4) (5) Withstand isolation voltage VTEST = VISO , t = 60 s (qualification); VTEST = 1.2 × VISO , t = 1 s (100% production) VRMS Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications. ISO1042 is suitable for safe electrical insulation and ISO1042B is suitable for basic electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits. Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier. Apparent charge is electrical discharge caused by a partial discharge (pd). All pins on each side of the barrier tied together creating a two-pin device. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1042 7 ISO1042 SLLSF09 – DECEMBER 2017 www.ti.com 6.7 Safety-Related Certifications VDE CSA UL CQC TUV ADVANCE INFORMATION Plan to certify according to GB4943.1-2011 Plan to certify according to EN 61010-1:2010 (3rd Ed) and EN 609501:2006/A11:2009/A1:2010 /A12:2011/A2:2013 Maximum transient isolation voltage, 7071 VPK; Maximum repetitive peak isolation voltage, 1500 VPK; Maximum surge isolation voltage, ISO1042: 6250 VPK (Reinforced) ISO1042B: 4600 VPK (Basic) CSA 60950-1-07+A1+A2 and IEC 60950-1 2nd Ed., for pollution degree 2, material group I ISO1042: 800 VRMS rinforced isolation ISO1042B: 800 VRMS basic isolation Single protection, ---------------5000 VRMS CSA 60601- 1:14 and IEC 60601-1 Ed. 3.1, ISO1042: 2 MOPP (Means of Patient Protection) 250 VRMS (354 VPK) maximum working voltage Reinforced insulation, Altitude ≤ 5000 m, Tropical Climate, 400 VRMS maximum working voltage EN 61010-1:2010 (3rd Ed) ISO1042: 600 VRMS reinforced isolation ISO1042B: 600 VRMS basic isolation ---------------EN 609501:2006/A11:2009/A1:2010 /A12:2011/A2:2013 ISO1042: 800 VRMS reinforced isolation ISO1042B: 800 VRMS basic isolation Certificate planned Certificate planned Certificate planned Certificate planned Plan to certify according to DIN V VDE V 088411:2017- 01 Plan to certify according to IEC 60950-1, IEC 62368-1 and IEC 60601-1 Plan to certify according to UL 1577 Component Recognition Program Certificate planned 6.8 Safety Limiting Values Safety limiting (1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DW-16 PACKAGE IS Safety input, output, or supply current PS Safety input, output, or total power TS Maximum safety temperature RθJA = 69.9°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 1 325 RθJA = 69.9°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 1 496 RθJA = 69.9°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 1 650 RθJA = 69.9°C/W, VI = 1.89 V, TJ = 150°C, TA = 25°C, see Figure 1 946 RθJA = 69.9°C/W, TJ = 150°C, TA = 25°C, see Figure 3 mA 1788 mW 150 °C DWV-8 PACKAGE IS Safety input, output, or supply current PS Safety input, output, or total power TS Maximum safety temperature (1) 8 RθJA = 100°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 2 227 RθJA = 100°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 2 347 RθJA = 100°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 2 454 RθJA = 100°C/W, VI = 1.89 V, TJ = 150°C, TA = 25°C, see Figure 2 661 RθJA = 100°C/W, TJ = 150°C, TA = 25°C, see Figure 4 mA 1250 mW 150 °C The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be exceeded. These limits vary with the ambient temperature, TA. The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount packages. Use these equations to calculate the value for each parameter: TJ = TA + RθJA × P, where P is the power dissipated in the device. TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature. PS = IS × VI, where VI is the maximum input voltage. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1042 ISO1042 www.ti.com SLLSF09 – DECEMBER 2017 6.9 Electrical Characteristics - DC Specification Over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCC1 =1.71 V to 1.89 V, TXD = 0 V, bus dominant 2.3 3.5 mA VCC1 = 2.25 V to 5.5 V, TXD = 0 V, bus dominant 2.4 3.5 mA VCC1 = 1.71 V to 1.89 V, TXD = VCC1, bus recessive 1.2 2.1 mA VCC1 = 2.25 V to 5.5 V, TXD = VCC1, bus recessive 1.3 2.1 mA TXD = 0 V, bus dominant, RL = 60 Ω 43 73.4 mA TXD = VCC1, bus recessive, RL = 60 Ω 2.8 4.1 mA 1.7 V SUPPLY CHARACTERISTICS Supply current Side 1 ICC2 Supply current Side 2 UVVCC1 Rising under voltage detection, Side 1 UVVCC1 Falling under voltage detection, Side 1 1.0 VHYS(UVC Hysterisis voltage on VCC1 undervoltage lock-out C1) UVVCC2 Rising under voltage detection, side 2 UVVCC2 Falling under voltage detection, side 2 80.0 3.8 VHYS(UVC Hysterisis voltage on VCC2 undervoltage lock-out C2) V 150 mV 4.2 4.45 V 4.0 4.25 V 200 ADVANCE INFORMATION ICC1 mV TXD TERMINAL VIH High level input voltage VIL Low level input voltage IIH High level input leakage current TXD = VCC1 IIL Low level input leakage current TXD = 0V Input capacitance VIN = 0.4 x sin(2 x π x 2 x 106 x t) + 2.5 V, VCC1 = 5 V CI 0.7×VCC1 V 0.3×VCC1 V 1 uA -20 uA 3 pF RXD TERMINAL VOH VCC1 High level output voltage IO = -4 mA for 4.5 V ≤ VCC1 ≤ 5.5 V -0.4 -0.2 V IO = -2 mA for 3.0 V ≤ VCC1 ≤ 3.6 V -0.2 -0.07 V IO = -1 mA for 2.25 V ≤ VCC1 ≤ 2.75 V -0.1 -0.04 V IO = -1 mA for 1.71 V ≤ VCC1 ≤ 1.89 V -0.1 -0.045 IO = 4 mA for 4.5 V ≤ VCC1 ≤ 5.5 V VOL Low level output voltage IO = 2 mA for 3.0 V ≤ VCC1 ≤ 3.6 V V 0.2 0.4 V 0.07 0.2 V IO = 1 mA for 2.25 V ≤ VCC1 ≤ 2.75 V 0.035 0.1 V IO = 1 mA for 1.71 V ≤ VCC1 ≤ 1.89 V 0.04 0.1 V DRIVER ELECTRICAL CHARACTERISTICS Bus output voltage(Dominant), CANH TXD = 0 V, 50 Ω ≥ RL ≤ 65 Ω, and CL = open 2.75 4.5 V Bus output voltage(Dominant), CANL TXD = 0 V, 50 Ω ≥ RL ≤ 65 Ω, and CL = open 0.5 2.25 V Bus output voltage(recessive), CANH and CANL TXD = VCC1 and RL = open 2.0 3.0 V Differential output voltage(dominant) TXD = 0 V, 45 Ω < RL < 50 Ω, and CL = open 1.4 3.0 V VOD(DOM) Differential output voltage(dominant) TXD = 0 V, 50 Ω < RL < 65 Ω, and CL = open 1.5 3.0 V Differential output voltage(dominant) TXD = 0 V, RL = 2240 Ω, and CL = open 1.5 5.0 V Differential output voltage(recessive) TXD = VCC1, RL = 60 Ω, and CL = open -120.0 12.0 mV Differential output voltage(recessive) TXD = VCC1, RL = open, and CL = open -50.0 50.0 mV VO(DOM) VO(REC) VOD(REC) 0.5 x VCC2 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1042 9 ISO1042 SLLSF09 – DECEMBER 2017 www.ti.com Electrical Characteristics - DC Specification (continued) Over recommended operating conditions (unless otherwise noted) PARAMETER Output symmetry (VCC2 - VO(CANH) VO(CANL)) VSYM ISO(SS_DO Short circuit current steady state output current, dominant M) ISO(SS_RE Short circuit current steady state output current, recessive C) TEST CONDITIONS MIN RL = 60Ω and CL = open -400.0 VCANH = -5V, CANL = open, and TXD = 0V -100.0 TYP UNIT 400.0 mV mA VCANL = 40V, CANH = open, and TXD = 0V -27 < VBUS < 32V, VBUS = CANH = CANL, and TXD = VCC1 MAX -5.0 100.0 mA 5.0 mA RECEIVER ELECTRICAL CHARACTERISTICS VIT Differential input threshold voltage |VCM| <= 20V 500.0 900.0 Differential input threshold voltage 20 <= |VCM| <= 30V 400.0 1000.0 ADVANCE INFORMATION VHYS Hysteresis voltage for differential input threshold VCM Input common mode range IOFF(LKG) power-off bus input leakage current CANH = CANL = 5V, VCC to GND via 0Ω and 47kΩ resistor CI Input capacitance to ground TXD = VCC1 CID Differential input capacitance TXD = VCC1 RID Differential input resistance TXD = VCC1 ; -30 V ≤ VCM ≤ +30 V RIN Input resistance (CANH or CANL) TXD = VCC1 ; -30 V ≤ VCM ≤ +30 V RIN(M) Input resistance matching: (1 RIN(CANH)/RIN(CANL)) x 100% VCANH = VCANL = 5 V mV 120 -30.0 30.0 V 4.8 uA 24.0 30 pF 12.0 15 pF 30.0 80.0 kΩ 15.0 40.0 kΩ -2.0 2.0 % THERMAL SHUTDOWN TTSD Thermal shutdown temperature TTSD_HYS Thermal shutdown hysteresis 170 ℃ 5 ℃ T 10 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1042 ISO1042 www.ti.com SLLSF09 – DECEMBER 2017 6.10 Switching Characteristics Over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; 1.71 V<VCC1<1.89 V 70 125 198.0 ns RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; 2.25 V<VCC1<5.5 V 192.0 ns 70 122 RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; 1.71 V<VCC1<1.89 V 70 142 215.0 ns RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; 2.25<VCC1<5.5 V 210.0 ns 70 138 300.0 µs DEVICE SWITCHING CHARACTERISTICS OP1) tPROP(LO OP2) tUV_RE_E Total loop delay, driver input TXD to receiver RXD, recessive to dominant Total loop delay, driver input TXD to receiver RXD, dominant to recessive Re-enable time after Undervoltage event NABLE CMTI Time for device to return to normal operation from VCC1 or VCC2 under voltage event Common mode transient immunity 85 100 kV/µs ADVANCE INFORMATION tPROP(LO DRIVER SWITCHING CHARACTERISTICS tpHR Propagation delay time, HIGH TXD to driver recessive tpLD Propagation delay time, LOW TXD to driver dominant tsk(p) pulse skew (|tpHR - tpLD|) tR Differential output signal rise time tF Differential output signal fall time tTXD_DTO Dominant time out RL = 60 Ω and CL = 100 pF; input rise/fall time (10% to 90%) on TXD =1 ns 76 120 61 120 ns 12.5 45 45 RL = 60 Ω and CL = open 1.2 3.8 ms 60 130 ns 61 130 ns RECEIVER SWITCHING CHARACTERISTICS tpRH Propagation delay time, bus recessive input to RXD high output tpDL Propogation delay time, bus dominant input to RXD low output tR Output signal rise time(RXD) 1.7 ns tF Output signal fall time(RXD) 1.9 ns CL(RXD) = 15 pF, CANL = 1.5 V and CANH = 3.5 V FD TIMING PARAMETERS tBIT(BUS) tBIT(RXD) ∆tREC Bit time on CAN bus output pins with tBIT(TXD) = 500 ns RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns 435.0 Bit time on CAN bus output pins with tBIT(TXD) = 200 ns RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns 155.0 Bit time on RXD bus output pins with tBIT(TXD) = 500 ns RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns 400 Bit time on RXD bus output pins with tBIT(TXD) = 200 ns RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns 120.0 Receiver timing symmetry with tBIT(TXD) = RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; 500 ns input rise/fall time (10% to 90%) on TXD =1 ns; ΔtREC = tBIT(RXD) - tBIT(BUS) -65.0 Receiver timing symmetry with tBIT(TXD) = RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; 200 ns input rise/fall time (10% to 90%) on TXD =1 ns; ΔtREC = tBIT(RXD) - tBIT(BUS) -45.0 530.0 ns 210.0 ns 550.0 ns 220.0 ns 40.0 ns 15.0 ns Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1042 11 ISO1042 SLLSF09 – DECEMBER 2017 www.ti.com 6.11 Insulation Characteristics Curves 700 1000 VCC1 =1.89 V VCC1 = 2.75 V VCC1 = 3.6 V VCC1 = VCC2 = 5.5 V 800 700 600 500 400 300 200 400 300 200 0 0 0 50 100 150 Ambient Temperature (qC) 0 200 50 D003 ADVANCE INFORMATION Figure 1. Thermal Derating Curve for Limiting Current per VDE for DW-16 Package 100 150 Ambient Temperature (qC) 200 D001 Figure 2. Thermal Derating Curve for Limiting Current per VDE for DWV-8 Package 1400 2000 1800 1200 1600 Safety Limiting Power (mW) Safety Limiting Power (mW) 500 100 100 1400 1200 1000 800 600 400 1000 800 600 400 200 200 0 0 0 50 100 150 Ambient Temperature (qC) 200 0 D004 Figure 3. Thermal Derating Curve for Limiting Power per VDE for DW-16 Package 12 VCC1 = 1.89 V VCC1 = 2.75 V VCC1 = 3.6 V VCC1 = VCC2 = 5.5 V 600 Safety Limiting Current (mA) Safety Limiting Current (mA) 900 50 100 150 Ambient Temperature (qC) 200 D002 Figure 4. Thermal Derating Curve for Limiting Power per VDE for DWV-8 Package Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1042 ISO1042 www.ti.com SLLSF09 – DECEMBER 2017 7 Detailed Description 7.1 Overview The ISO1042 device is a digitally isolated CAN transceiver that offers ±70-V DC bus fault protection and ±30-V common-mode voltage range. The device supports up to 5-Mbps data rate in CAN FD mode allowing much faster transfer of payload compared to classic CAN. The ISO1042 device has an isolation withstand voltage of 5000 VRMS and is available in basic and reinforced isolation with a surge test voltage of 6 kVPK and 10 kVPK respectively. The device can operate from 1.8-V, 2.5-V, 3.3-V, and 5-V supplies on side 1 and a 5-V supply on side 2. This supply range is of particular advantage for applications operating in harsh industrial environments because the low voltage on side 1 enables the connection to low-voltage microcontrollers for power conservation, whereas the 5 V on side 2 maintains a high signal-to-noise ratio of the bus signals. 7.2 Functional Block Diagram VCC1 ± GND1 CANH CANL GND2 Copyright © 2017, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 CAN Bus States The CAN bus has two states during operation: dominant and recessive. A dominant bus state, equivalent to logic low, is when the bus is driven differentially by a driver. A recessive bus state is when the bus is biased to a common mode of VCC / 2 through the high-resistance internal input resistors of the receiver, equivalent to a logic high. The host microprocessor of the CAN node uses the TXD pin to drive the bus and receives data from the bus on the RXD pin. See Figure 5 and Figure 6. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1042 13 ADVANCE INFORMATION TXD + GALVANIC ISOLATION RXD VCC2 ISO1042 SLLSF09 – DECEMBER 2017 www.ti.com Feature Description (continued) Normal and Silent Mode Typical Bus Voltage (V) 4 CANH 3 Vdiff(D) 2 Vdiff(R) CANL 1 Dominant Logic L Recessive Logic H Figure 5. Bus States (Physical Bit Representation) CANH GALVANIC ISOLATION ADVANCE INFORMATION Time (t) Recessive Logic H VCC / 2 RXD CANL Figure 6. Simplified Recessive Common Mode Bias and Receiver 7.3.2 Digital Inputs and Outputs: TXD (Input) and RXD (Output) The VCC1 supply for the isolated digital input and output side of the device can be supplied by 1.8-V, 2.5-V, 3.3-V, and 5-V supplies and therefore the digital inputs and outputs are 1.8-V, 2.5-V, 3.3-V, and 5-V compatible. NOTE The TXD pin is very weakly internally pulled up to VCC1. An external pullup resistor should be used to make sure that the TXD pin is biased to recessive (high) level to avoid issues on the bus if the microprocessor does not control the pin and the TXD pin floats. The TXD pullup strength and CAN bit timing require special consideration when the device is used with an open-drain TXD output on the CAN controller of the microprocessor. An adequate external pullup resistor must be used to make sure that the TXD output of the microprocessor maintains adequate bit timing input to the input on the transceiver. 14 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1042 ISO1042 www.ti.com SLLSF09 – DECEMBER 2017 Feature Description (continued) 7.3.3 Protection Features 7.3.3.1 TXD Dominant Timeout (DTO) The TXD DTO circuit prevents the transceiver from blocking network communication in the event of a hardware or software failure where the TXD pin is held dominant longer than the timeout period, tTXD_DTO. The DTO circuit timer starts on a falling edge on the TXD pin. The DTO circuit disables the CAN bus driver if no rising edge occurs before the timeout period expires, which frees the bus for communication between other nodes on the network. The CAN driver is activated again when a recessive signal occurs on the TXD pin, clearing the TXD DTO condition. The receiver and RXD pin still reflect activity on the CAN bus, and the bus terminals are biased to the recessive level during a TXD dominant timeout. TXD fault stuck dominant Example: PCB failure or bad software TXD (driver) tTXD_DTO Fault is repaired and transmission capability is restored Driver disabled freeing bus for other nodes CAN Bus Signal ADVANCE INFORMATION Bus would be stuck dominant, blocking communication for the whole network but TXD DTO prevents this and frees the bus for communication after the tTXD_DTO time. Normal CAN communication tTXD_DTO Communication from repaired nodes Communication from other bus nodes RXD (receiver) Communication from local node Communication from repaired nodes Communication from other bus nodes Figure 7. Example Timing Diagram for TXD DTO NOTE The minimum dominant TXD time (tTXD_DTO) allowed by the TXD DTO circuit limits the minimum possible transmitted data rate of the device. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the tTXD_DTO minimum, limits the minimum data rate. Calculate the minimum transmitted data rate with Equation 1. Minimum Data Rate = 11 / tTXD_DTO (1) 7.3.3.2 Thermal Shutdown (TSD) If the junction temperature of the device exceeds the thermal shutdown threshold (TTSD), the device turns off the CAN driver circuits, blocking the TXD-to-bus transmission path. The CAN bus terminals are biased to the recessive level during a thermal shutdown, and the receiver-to-RXD path remains operational. The shutdown condition is cleared when the junction temperature drops at least the thermal shutdown hysteresis temperature (TTSD_HYS) below the thermal shutdown temperature (TTSD) of the device. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1042 15 ISO1042 SLLSF09 – DECEMBER 2017 www.ti.com Feature Description (continued) 7.3.3.3 Undervoltage Lockout and Default State The supply pins have undervoltage detection that places the device in protected or default mode which protects the bus during an undervoltage event on the VCC1 or VCC2 supply pins. If the bus-side power supply, VCC2, is less than about 4 V, the power shutdown circuits in the ISO1042 device disable the transceiver to prevent false transmissions because of an unstable supply. If the VCC1 supply is still active when this occurs, the receiver output (RXD) goes to a default HIGH (recessive) value. Table 1 summarizes the undervoltage lockout and failsafe behavior. Table 1. Undervoltage Lockout and Default State VCC1 VCC2 DEVICE STATE BUS OUTPUT RXD > UVVCC1 > UVVCC2 Functional Per Device State and TXD Mirrors Bus <UVVCC1 > UVVCC2 Protected Recessive High Impedance (tri-state) >UVVCC1 < UVVCC2 Protected High Impedance Recessive (Default High) ADVANCE INFORMATION NOTE After an undervoltage condition is cleared and the supplies have returned to valid levels, the device typically resumes normal operation in 300 µs. 7.3.3.4 Floating Pins Pullup and pulldown resistors should be used on critical pins to place the device into known states if the pins float. The TXD pin should be pulled up through a resistor to the VCC1 pin to force a recessive input level if the microprocessor output to the pin floats. 7.3.3.5 Unpowered Device The device is designed to be ideal passive or no load to the CAN bus if it is unpowered. The bus pins (CANH, CANL) have extremely low leakage currents when the device is unpowered to avoid loading down the bus which is critical if some nodes of the network are unpowered while the rest of the of network remains in operation. 7.3.3.6 CAN Bus Short Circuit Current Limiting The device has two protection features that limit the short circuit current when a CAN bus line has a short-circuit fault condition. The first protection feature is driver current limiting (both dominant and recessive states) and the second feature is TXD dominant state time out to prevent permanent higher short circuit current of the dominant state during a system fault. During CAN communication the bus switches between dominant and recessive states, therefore the short circuit current may be viewed either as the instantaneous current during each bus state or as an average current of the two states. For system current (power supply) and power considerations in the termination resistors and common-mode choke ratings, use the average short circuit current. Determine the ratio of dominant and recessive bits by the data in the CAN frame plus the following factors of the protocol and PHY that force either recessive or dominant at certain times: • Control fields with set bits • Bit stuffing • Interframe space • TXD dominant time out (fault case limiting) These factors ensure a minimum recessive amount of time on the bus even if the data field contains a high percentage of dominant bits. The short circuit current of the bus depends on the ratio of recessive to dominant bits and their respective short circuit currents. Use Equation 2 to calculate the average short circuit current. IOS(AVG) = %Transmit × [(%REC_Bits × IOS(SS)_REC) + (%DOM_Bits × IOS(SS)_DOM)] + [%Receive × IOS(SS)_REC] where • • • 16 IOS(AVG) is the average short circuit current %Transmit is the percentage the node is transmitting CAN messages %Receive is the percentage the node is receiving CAN messages Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1042 ISO1042 www.ti.com SLLSF09 – DECEMBER 2017 • • • • %REC_Bits is the percentage of recessive bits in the transmitted CAN messages %DOM_Bits is the percentage of dominant bits in the transmitted CAN messages IOS(SS)_REC is the recessive steady state short circuit current IOS(SS)_DOM is the dominant steady state short circuit current (2) NOTE Consider the short circuit current and possible fault cases of the network when sizing the power ratings of the termination resistance and other network components. 7.4 Device Functional Modes Table 2 and Table 3 list the driver and receiver functions. Table 4 lists the functional modes for the ISO1042 device. Table 2. Driver Function Table (1) OUTPUTS DRIVEN BUS STATE CANH (1) CANL (1) L H L Dominant H Z Z Recessive ADVANCE INFORMATION INPUT TXD (1) H = high level, L = low level, Z = common mode (recessive) bias to VCC / 2. See Figure 5 and Figure 6 for bus state and common mode bias information. Table 3. Receiver Function Table DEVICE MODE Normal (1) CAN DIFFERENTIAL INPUTS VID = VCANH – VCANL BUS STATE RXD PIN (1) L VID ≥ 0.9 V Dominant 0.5 V < VID < 0.9 V ? ? VID ≤ 0.5 V Recessive H Open (VID ≈ 0 V) Open H H = high level, L = low level, ? = indeterminate. Table 4. Function Table (1) DRIVER INPUTS (1) (2) OUTPUTS TXD CANH CANL L (2) H L H Z Z Open Z Z X Z Z RECEIVER DIFFERENTIAL INPUTS VID = CANH–CANL OUTPUT RXD BUS STATE DOMINANT VID ≥ 0.9 V L DOMINANT RECESSIVE 0.5 V < VID < 0.9 V ? ? RECESSIVE VID ≤ 0.5 V H RECESSIVE RECESSIVE Open H RECESSIVE BUS STATE H = high level; L = low level; X = irrelevant; ? = indeterminate; Z = high impedance Logic low pulses to prevent dominant time-out. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1042 17 ISO1042 SLLSF09 – DECEMBER 2017 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The ISO1042 device can be used with other components from Texas Instruments such as a microcontroller, a transformer driver, and a linear voltage regulator to form a fully isolated CAN interface. 8.2 Typical Application GND 4 D2 3 SN6505 3.3 V 1 8 EN VCC CLK D1 3 2 7 6 1 5 ADVANCE INFORMATION 2 1 2 VDD TXD RXD 3.3V GND Digital Ground NC 4 11,16 NC 14 TXD CANH ISO1042 RXD CANL 13 12 NC 10 Optional bus protection function 7 NC 8 5 GND1 6 NC 0V Protective Chasis Earth Ground 5 OUT EN TPS76350 DGND N PSU PE VCC2 4 NC MCU L1 3 VCC1 IN GND1 GND2 Galvanic Isolation Barrier 9,15 ISO Ground Copyright © 2017, Texas Instruments Incorporated Figure 8. Application Circuit With ISO1042 in 16-SOIC Package 18 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1042 ISO1042 www.ti.com SLLSF09 – DECEMBER 2017 Typical Application (continued) EN VCC CLK D1 1 3 SN6505 3.3 V 8 4 D2 3 2 7 6 1 5 2 3.3 V 1 VDD TXD MCU RXD DGND 2 3 4 Digital Ground VCC1 VCC2 TXD CANH ISO1042 CANL OUT 5 EN TPS76350 GND NC 4 8 7 6 RXD GND1 IN Optional bus protection function GND2 Galvanic Isolation Barrier 5 ISO Ground Copyright © 2017, Texas Instruments Incorporated Figure 9. Application Circuit With ISO1042 in 8-SOIC Package 8.2.1 Design Requirements Unlike an optocoupler-based solution, which requires several external components to improve performance, provide bias, or limit current, the ISO1042 device only requires external bypass capacitors to operate. 8.2.2 Detailed Design Procedure 8.2.2.1 Bus Loading, Length and Number of Nodes The ISO 11898-2 Standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m. However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a bus. A large number of nodes requires transceivers with high input impedance such as the ISO1042 transceivers. Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO 11898-2 Standard. These organizations and standards have made system-level trade-offs for data rate, cable length, and parasitic loading of the bus. Examples of some of these specifications are ARINC825, CANopen, DeviceNet, and NMEA2000. The ISO1042 device is specified to meet the 1.5-V requirement with a 50-Ω load, incorporating the worst case including parallel transceivers. The differential input resistance of the ISO1042 device is a minimum of 30 kΩ. If 100 ISO1042 transceivers are in parallel on a bus, this requirement is equivalent to a 300-Ω differential load worst case. That transceiver load of 300 Ω in parallel with the 60 Ω gives an equivalent loading of 50 Ω. Therefore, the ISO1042 device theoretically supports up to 100 transceivers on a single bus segment. However, for CAN network design margin must be given for signal loss across the system and cabling, parasitic loadings, network imbalances, ground offsets and signal integrity, therefore a practical maximum number of nodes is typically much lower. Bus length may also be extended beyond the original ISO 11898 standard of 40 m by careful system design and data-rate tradeoffs. For example, CANopen network design guidelines allow the network to be up to 1 km with changes in the termination resistance, cabling, less than 64 nodes, and a significantly lowered data rate. This flexibility in CAN network design is one of the key strengths of the various extensions and additional standards that have been built on the original ISO 11898-2 CAN standard. Using this flexibility requires the responsibility of good network design and balancing these tradeoffs. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1042 19 ADVANCE INFORMATION GND ISO1042 SLLSF09 – DECEMBER 2017 www.ti.com Typical Application (continued) 8.2.2.2 CAN Termination The ISO11898 standard specifies the interconnect to be a single twisted pair cable (shielded or unshielded) with 120-Ω characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line should be used to terminate both ends of the cable to prevent signal reflections. Unterminated drop-lines (stubs) connecting nodes to the bus should be kept as short as possible to minimize signal reflections. The termination may be in a node, but if nodes are removed from the bus, the termination must be carefully placed so that it is not removed from the bus. Node 1 Node 2 Node 3 Node n (with termination) MCU or DSP MCU or DSP MCU or DSP MCU or DSP CAN Controller CAN Controller CAN Controller CAN Controller CAN Transceiver CAN Transceiver CAN Transceiver CAN Transceiver ADVANCE INFORMATION RTERM RTERM Figure 10. Typical CAN Bus Termination may be a single 120-Ω resistor at the end of the bus, either on the cable or in a terminating node. If filtering and stabilization of the common-mode voltage of the bus is desired, then split termination can be used. (See Figure 11). Split termination improves the electromagnetic emissions behavior of the network by eliminating fluctuations in the bus common-mode voltages at the start and end of message transmissions. Standard Termination Split Termination CANH CANH RTERM / 2 CAN Transceiver RTERM CAN Transceiver CSPLIT RTERM / 2 CANL CANL Figure 11. CAN Bus Termination Concepts 9 Power Supply Recommendations To make sure operation is reliable at all data rates and supply voltages, a 0.1-µF bypass capacitor is recommended at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as possible. If only a single primary-side power supply is available in an application, isolated power can be generated for the secondary-side with the help of a transformer driver such as TI's SN6505B. For such applications, detailed power supply design, and transformer selection recommendations are available in the SN6505 Low-Noise 1-A Transformer Drivers for Isolated Power Supplies data sheet. 20 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1042 ISO1042 www.ti.com SLLSF09 – DECEMBER 2017 10 Layout 10.1 Layout Guidelines Suggested placement and routing of ISO1042 bypass capacitors and optional TVS diodes is shown in Figure 13 and Figure 14. In particular, place the VCC2 bypass capacitors on the top layer, as close to the device pins as possible, and complete the connection to the VCC2 and GND2 pins without using vias. Note that the SOIC-16 variant needs two VCC2 bypass capacitor, one on each VCC2 pin. If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly. For detailed layout recommendations, refer to the Digital Isolator Design Guide. 10.1.1 PCB Material For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and the self-extinguishing flammability-characteristics. 10.2 Layout Example High-speed traces 10 mils Ground plane 40 mils Keep this space free from planes, traces, pads, and vias FR-4 0r ~ 4.5 Power plane 10 mils Low-speed traces Figure 12. Recommended Layer Stack Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1042 21 ADVANCE INFORMATION A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 12). Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer. • Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link. • Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow. • Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pF/in2. • Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias. ISO1042 SLLSF09 – DECEMBER 2017 www.ti.com Layout Example (continued) Minimize distance to VCC VCC1 0.1 µF GND1 TXD MCU NC RXD x NC NC GND1 GND1 0.1 µF VCC2 VCC1 C Isolation Capacitor x C GND2 NC C1 CANH CANL D1 CAN BUS C2 VCC2 NC 0.1 µF C GND2 PLANE GND1 GND2 PLANE PLANE ADVANCE INFORMATION VCC2 Figure 13. 16-DW Layout Example Minimize distance to VCC C VCC1 TXD RXD MCU GND1 GND1 PLANE C VCC2 Isolation Capacitor VCC1 VCC2 C1 CANH D1 CANL CAN BUS C2 GND2 GND2 PLANE Figure 14. 8-DWV Layout Example 22 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1042 ISO1042 www.ti.com SLLSF09 – DECEMBER 2017 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: • Texas Instruments, Digital Isolator Design Guide • Texas Instruments, High-voltage reinforced isolation: Definitions and test methodologies • Texas Instruments, Isolation Glossary 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ISO1042 23 ADVANCE INFORMATION 11.3 Community Resource PACKAGE OPTION ADDENDUM www.ti.com 21-Dec-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ISO1042DWR PREVIEW SOIC DW 16 2000 TBD Call TI Call TI -40 to 125 XISO1042DWR ACTIVE SOIC DW 16 2000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples GENERIC PACKAGE VIEW DW 16 SOIC - 2.65 mm max height SMALL OUTLINE INTEGRATED CIRCUIT Images above are just a representation of the package family, actual package may vary. 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