RangeMAX™ ® TM LX1688 Multiple Lamp CCFL Controller P RODUCTION D ATA S HEET KEY FEATURES DESCRIPTION Safety and reliability features include a dual feedback control loop that permits regulation of maximum lamp strike voltage as well as lamp current. Regulating maximum lamp voltage permits the designer to provide for ample worst-case lamp strike voltage while conservatively limiting maximum open circuit voltage. In addition the controller features include auto shutdown for an open or broken lamp, and a lamp fault detection with a status reporting output. To improve design flexibility the IC includes the ability to select the polarity of both the chip enable and dim (BRITE) inputs. Also included is a switched VDD output of up to 10mA that will allow the user to power other circuitry that can be switched on and off with the inverters enable input. This preserves the micro power sleep mode with no additional components. Provision to Synchronize Lamp Current & Frequency With Other Controllers Dimming With Analog or Digital (PWM) Methods (>20:1) Programmable Fixed Frequency Adjustable Power-up Reset ENABLE/BRITE Polarity Selection Voltage Limiting on Step-up Transformer Secondary Winding Open Lamp Timeout Circuitry Switched VDD Output (10mA) Micro-Amp Sleep Mode Operates With 3.3V to 5V Supply 100mA Output Drive Capability WWW . Microsemi .C OM The LX1688 is a fixed frequency, dual current/voltage mode, switching regulator that provides the control function for Cold Cathode Fluorescent Lighting (CCFL). This controller can be used to drive a single lamp, but is specifically designed for multiple lamp LCD panels. The IC can be configured as a master or slave and synchronize up to 12 controllers. The LX1688 includes highly integrated universal ‘PWM or DC’ dim input that allows either a PWM or DC input to adjust brightness without requiring external conditioning, since a single external capacitor CPWM can be used to integrate a PWM input. Burst mode dimming is possible if the user supplies a low frequency PWM signal on the BRITE input and no CPWM capacitor is used. The controller utilizes Microsemi’s patented direct drive fixed frequency topology and patented resonant lamp strike generation technique. APPLICATIONS / BENEFITS Desktop LCD Monitors Multiple Lamp Panels Low Ambient Light Displays High Efficiency Lower Cost than Conventional Buck/Royer Inverter Topologies Improved Lamp Strike Capability Improved Over-Voltage Control IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com Protected by U.S. Patents 5,615,093; 5,923,129; 5,930,121; 6,198,234; Patents Pending PRODUCT HIGHLIGHT DIMMING (BRITE) ENABLE RAMP RESET 24 13 LX1688 MASTER FETS 12 INPUT CONNECTOR PHASE SYNC LAMPS STRIKE STATUS 125 Hz 5% Duty cycle Burst 65KHz run frequency FAULT 1 FAULT 1 BRITE ENABLE FAULT 2 24 13 FETS 12 LX1688 SLAVE STRIKE STATUS VDD FAULT 2 Ch3 10.0mV Ω Ch2 10.0mV Ω M100µs LX1688 Simplified Quad Lamp Inverter Showing Synchronized Output Waveforms PACKAGE ORDER INFO TJ (°C) MIN VDD MAX VDD 0 to 70 -40 to 85 3.0V 3.0V 5.5V 5.5V PW Plastic TSSOP 24-Pin RoHS compliant / Pb-free Transition DC: 0442 LX1688CPW LX1688IPW Note: Available in Tape & Reel. Append the letters “TR” to the part number. (i.e. LX1688CPW-TR) Copyright © 2001 Rev. 1.2, 2006-03-09 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 1 RangeMAX™ ® TM LX1688 Multiple Lamp CCFL Controller P RODUCTION D ATA S HEET ABSOLUTE MAXIMUM RATINGS PACKAGE PIN OUT AOUT VSS_P VSS BEPOL BRITE CPOR ENABLE I_R CPWM1 CPWM2 RMP_RST PHA_SYNC Note 1: Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of the specified terminal. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 BOUT VDD_P VDD VDDSW TRI_C OLSNS ISNS ICOMP VCOMP VSNS SLAVE FAULT PW PACKAGE (Top View) RoHS / Pb-free 100% matte Tin Lead Finish WWW . Microsemi .C OM Supply Voltage (VDD_P, VDD)................................................................................ 6.5V Digital Inputs ................................................................................... -0.3V to VDD +0.5V Analog Inputs.................................................................................. –0.1V to VDD +0.5V Digital Outputs................................................................................. -0.3V to VDD +0.5V Analog Outputs ................................................................................ -0.1V to VDD +0.5V Maximum Operating Junction Temperature ............................................................150°C Storage Temperature................................................................................. -65°C to 150°C Peak Package Solder Reflow Temp. (40 seconds max. exposure) ................260°C(+0.-5) THERMAL DATA PW Plastic TSSOP 24-Pin THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA 100°C/W Junction Temperature Calculation: TJ = TA + (PD x θJA). The θJA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow. Pin Name AOUT VSS_P VSS BEPOL BRITE CPOR ENABLE I_R CPWM1 Output Driver A Connects to dedicated GND for Aout and Bout Drivers Connects to analog GND Tri-mode input pin to control the polarity of the ENABLE and BRITE signal Analog/PWM input for brightness control Connects an external capacitor CPOR to VDD and is used for setting power-up reset pulse width. Used to enable or disable the chip VDD VDDSW Switchable VDD output controlled by ENABLE VDD_P TRI_C Connects to external capacitor CTRI OLSNS Analog input to detect open-lamp condition ISNS Connects to external resistor RI; for bias current setting for internal oscillator Connects to external capacitor CPWM, used for integrating an external digital PWM signal for analog dimming Connects to external capacitor CPWM, used for integrating an external digital PWM signal for analog dimming. Description Output Driver B Connects to dedicated VDD for Aout and Bout Drivers Connects to analog VDD BOUT ICOMP VCOMP VSNS Analog input from lamp current, has built-in 300mv offset Current error Amp’s output; connects to external capacitor CICOMP Voltage error Amp’s output; connects to external capacitor CVCOMP, can be used for soft-start Analog input from transformer output voltage RMP_RST If SLAVE = “0”, RMP_RST is a CMOS output; if SLAVE = “1”, it is a CMOS input that locks the ramp oscillation frequency to the master clock SLAVE Input control pin for setting the IC either in Master or Slave mode; “1” for slave mode and “0” for master mode. PHA_SYNC If SLAVE= “0”, PHA_SYNC is a CMOS output; if SLAVE = “1”, it is a CMOS input that make the AOUT/BOUT phase synchronous with the master FAULT Digital output to indicate maximum number of lamp striking attempts has occurred without lamp ignition. Copyright © 2001 Rev. 1.2, 2006-03-09 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 2 PACKAGE DATA CPWM2 FUNCTIONAL PIN DESCRIPTION Description Pin Name RangeMAX™ ® TM LX1688 Multiple Lamp CCFL Controller P RODUCTION D ATA S HEET RECOMMENDED OPERATING CONDITIONS Min Supply Voltage (VDD ,VDDP) BRITE Linear DC Voltage Range BRITE PWM Logic Signal Voltage Range Digital Inputs (SLAVE, PHA_SYNC, RMP_RST, BEPOL, ENABLE ) LX1688 Typ Max 3 1 0 0 5.5 2.5 VDD VDD Units V V V V ELECTRICAL CHARACTERISTICS O O Unless otherwise specified, specifications apply over the range: TA=-40 to 85 C, VDD (For LX1688IWP) & TA= 0 to 70 C, VDD (For LX1688CWP), VDD_P = 3.0 to 5.5V. RI = 80Kohms, CTRI = 0.083µF Parameter Symbol Test Conditions Min LX1688 Typ. Max WWW . Microsemi .C OM Parameter Units DIMMER Conventional¹ Dimming BRITE Input Voltage VBRITE_MAX VBEPOL = VDD 2.6 2.5 VBRITE_MIN VBEPOL = VDD 0.4 0.5 Reverse Dimming BRITE Input Voltage VBRITE_MAX VBEPOL = VSS or float 0.4 0.5 VBRITE_MIN VBEPOL = VSS or float 2.6 2.5 Max Brightness VBRT Voltage VBRT_FULL VBEPOL = VSS, VBRITE = 0.4V 1.90 2.0 2.05 Full-darkness VBRT voltage VBRT_DARK VBEPOL = VSS, VBRITE = 2.6V V V V 0 0.05 V ISNS input threshold voltage VTH_IAMP TA= 0 to 70 C 150 300 450 mV ISNS input threshold voltage VTH_IAMP TA= -40 to 85 C O 150 300 550 mV BRITE-to-ICOMP propagation delay TD_BRITE O 2 µS STRIKE AND RAMP GENERATOR Max. number of strike before fault Triangular Wave Generator Analog Output Peak Voltage Triangular Wave Generator Analog Output Valley Voltage Triangular Wave Generator Oscillation Frequency Max. Lamp Strike Frequency NFAULT 63 VP_TRI 2.3 2.5 2.6 V VV_TRI 0.15 0.3 0.40 V F_TRI 7 10 13 Hz 150 195 60 65 70 KHz 57 65 70 KHz 4 6 % /V 740 790 840 ‘mV 540 590 640 ‘mV 1 us FMAX_STK Lamp Run Frequency FLAMP Lamp Run Frequency FLAMP Lamp Run Frequency regulation over VDD FMAX_STK = FLAMP X ~2.5 VOLSNS > 0.65V; VDD=5V O TA= 0 to 70 C VOLSNS > 0.65V; VDD=5V O TA=-40 to 85 C VOLSNS > 0.65V FLAMP_REG VTH_OLSNS OLSNS hysteresis VH_OLSNS OLSNS-to-ICOMP propagation delay Fault, PHA_SYNC, RMP_RST, logic high threshold Fault, PHA_SYNC, RMP_RST, logic low threshold Minimum Fault-pin output current TD_OLSNS GBNT ² VDD – 0.5 VH V 0.7 VL I_FAULT 10 ELECTRICALS OLSNS threshold voltage KHz 15 1 V ‘mA ¹Conventional polarity means that the lamp brightness increases with increasing voltage on the BRITE pin. Reverse polarity means that brightness decreases with increasing voltage ² Guaranteed but not production tested Copyright © 2001 Rev. 1.2, 2006-03-09 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 3 RangeMAX™ ® TM LX1688 Multiple Lamp CCFL Controller P RODUCTION D ATA S HEET ELECTRICAL CHARACTERISTICS (CONTINUED) Symbol Test Conditions Min LX1688 Typ. Max Units STRIKE AND RAMP GENERATOR (CONTINUED) Minimum PHA_SYNC-pin output current I_PHA_SYNC VSLAVE = 0V 10 ‘mA Minimum RMP_RST-pin output current I_RMP_RST VSLAVE = 0V 10 Minimum A_SYNC output pulse duty-cycle DO_ASYNC VSLAVE = 0V 49 50 Minimum A_SYNC input pulse duty-cycle DI_ASYNC VSLAVE = VDD 48 50 % Minimum RMP_RST output pulse duty-cycle DO_RST VSLAVE = 0V 10 17 % Minimum RMP_RST input pulse duty-cycle DI_RST VSLAVE = VDD 5 mA % % OUTPUT BUFFER 100 ‘mA 100 ‘mA ISK_OUTBUF VAOUT, BOUT = 1V VDD = 5.5V VAOUT, BOUT = 4.5V VDD = 5.5V VAOUT, BOUT = 1V, VDD = 3V 50 ‘mA IS_OUTBUF VAOUT, BOUT = 2V, VDD = 3V 50 ‘mA ISK_OUTBUF VAOUT, BOUT = 1V, VDD = 5.5V 100 ‘mA Output Sink Current ISK_OUTBUF Output Source Current IS_OUTBUF Output Sink Current Output Source Current Output Sink Current WWW . Microsemi .C OM Parameter PWM VSNS threshold voltage VTH_VSNS VCOMP Discharge Current ID_VCOMP IAMP transconductance GM_IAMP 1.2 1.25 1.3 4 ΔISNS = 0.2V 100 200 V ‘mA 500 µmho VAMP, IAMP output source current IS_IAMP VCOMP, ICOMP = 0 75 VAMP, IAMP output sink current ISK_IAMP VCOMP, ICOMP =VDD 75 µA ICOMP discharge current ID_ICOMP 10 ‘mA VAMP transconductance GM_ICMP ICOMP-to-output propagation delay TD_ICOMP ΔVSNS = 0.1V 200 500 µA 800 1100 µmho nS BIAS Voltage at Pin I_R V_IR Pin I_R max. source current Power-on Reset Pulse Width 0.95 IMAX_IR 1.05 50 TPOR CPOR =.1uF Minimum VDDSW sourcing Current IMIN_VDDSW VDDSW Off Current IOFF_VDDSW (VDD – VDDSW ) < 0.2V VENABLE = 0.8V, VBEPOL = VDD VDDSW = 0V 10 V µA 31 mS 25 ‘mA 1 15 µA 5.5 8 mA 2 4 mA 1.7 2.4 V GENERAL Operating Current IDD Output buffer operating current IDD_P VTH_EN ENABLE threshold hysteresis VTH_EN 0.8 UVLO threshold VTH_UVLO UVLO hysteresis VH_UVLO Falling turn-off hysteresis Sleep-mode current (see table-1 for Pin ENABLE polarity) VDD_P Leakage in Sleep Mode IDD_SLEEP IDD_SLEEP IDD_SLEEP IDD_SLEEP Copyright © 2001 Rev. 1.2, 2006-03-09 V 0.2 VENABLE = 0.8V (VBEPOL = VDD or float) VENABLE = 2.5V (VBEPOL = VDD or float) VENABLE = 0.8V (VBEPOL = VSS) VENABLE = 2.5V (VBEPOL = VSS) Rising turn-on threshold ELECTRICALS ENABLE logic threshold VDD = VDD_P = 5V VOLSNS = VDD = VDD_P = 5V, CA = CB = 1000pF 20 50 20 50 20 300 20 300 2.8 2.9 µA 2.6 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 190 V mV Page 4 RangeMAX™ ® TM LX1688 Multiple Lamp CCFL Controller P RODUCTION D ATA S HEET ISNK STEP RESPONSE ISNS Input Threshold Voltage Vs Temperature 6 380 360 5.5 340 VDD=5.5V ISNS Input Threshold (V) VDD Input Current (mA) WWW . Microsemi .C OM RESPONSE VS WAVELENGTH Typical Operating Current (VDD) 5 4.5 VDD=3V 4 3.5 320 VDD=5.5V 300 280 260 240 VDD=3V 220 200 3 -40 180 -15 10 35 Temperature (°C) 60 85 -40 10 35 60 85 Temperature (°C) Under Voltage Lockout Vs Temperature Output Frequency Vs Temperature 2.9 70 2.85 68 VDD=5V 66 UVLO Thresholds (V) Output Frequency (KHz) -15 64 62 VDD=3V 60 58 Turn On 2.8 2.75 2.7 2.65 Turn Off 2.6 2.55 56 2.5 -40 -15 10 35 60 85 -40 -15 10 35 60 85 Temperature (°C) T emperature (°C) Power-on-Reset Pulse Width Vs Temperature VDD=5V I_R Voltage Vs Temperature VDD=V 1.010 40 1.008 35 TPOR(mS) I_R Voltage (V) 1.006 1.004 1.002 30 25 1.000 20 0.998 0.996 -40 10 35 Temperature (°C) 60 85 15 -40 -15 10 35 Temperature (°C) Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 60 85 CHARTS Copyright © 2001 Rev. 1.2, 2006-03-09 -15 Page 5 RangeMAX™ ® TM LX1688 Multiple Lamp CCFL Controller P RODUCTION D ATA S HEET TABLE 1 ENABLE POLARITY DIMMING POLARITY* VDD + (HI = CHIP_ON, LOW = CHIP_OFF CONVENTIONAL FLOAT + (HI = CHIP_ON, LOW = CHIP_OFF) REVERSE VSS - (LOW = CHIP_ON, HI = CHIP_OFF) REVERSE * Conventional polarity means that the lamp brightness increases with increasing voltage on the BRITE pin. Reverse polarity means that brightness decreases with increasing voltage OPERATIONAL MODES Controller Mode Master Slave Controller Operation Input Pin: OLSNS Input Pin: SLAVE Output Pin: FAULT Pin: RMP_RST Pin: A_SYNC Run > 0.6V VSS L Output: FINT Output: FINT / 2 Striking < 0.2V VSS L Output: FINT Output: FINT / 2 Fault X VSS H Output: FINT Output: FINT / 2 Run > 0.6V VDD L Input: FEXT Input: FEXT / 2 Striking < 0.2V VDD L Input: FEXT Input: FEXT / 2 Fault X VDD H Input: FEXT Input: FEXT / 2 Lamp Frequency WWW . Microsemi .C OM Pin BEPOL FINT / 2 Ramping up / down Off FEXT / 2 Ramping up / down Off SIMPLIFIED BLOCK DIAGRAM ISNS VSNS VCOMP ICOMP FEXT/2 ERROR AMP TFF R PHA_SYNC Q SLAVE RMP_RST PWR_ GD VAMP FINT RAMP RUN GENERATOR FEXT STRIKE GENERATOR 200K FAULT OUTPUT STEERING LOGIC Q + - 1V B OUT CURRENT COMPARATOR IAMP VSS_P + BRT 2.5 V BRITE PWR_ GD PWR_BD FAULT 300mV 1V A OUT Q 1.25V PWR_ BD T VDD_P VOLTAGE COMPARATOR 100K + - 100K 100K 100K 0-2V 800mV 600mV IGNITE CPW 1 CPW 2 1M 1M PWR_ BD TRI WAVE GEN 6 BIT COUNTER TRI_C VDD POLARITY DECODE BIAS GEN UVLO PWR_GD FAULT PWR_BD TTL BUF BLOCK DIAGRAM BEPOL ENABLE OLSNS 0.5 V TTL BUF FAULT INTERNAL VDD VDDSW VSS LX1688 VSS VDD I_R CPOR Figure – Simplified Block Diagram Copyright © 2001 Rev. 1.2, 2006-03-09 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 6 RangeMAX™ TM ® LX1688 Multiple Lamp CCFL Controller P RODUCTION D ATA S HEET DETAILED DESCRIPTION OPERATION FROM 3.3V AND/OR 5.0V INPUT SUPPLY The LX1688 is designed to operate and meet all specifications at 3.3V ±10% to 5.0V ±10%. The under voltage lockout is set at nominally 2.8V with a 190mV hysteresis. Copyright © 2001 Rev. 1.2, 2006-03-09 BEPOL INPUT The BEPOL pin is a tri-mode input that controls the polarity of the ENABLE and BRITE input signals. Depending on the state of this pin (VDD, floating, or VSS) the controller can be set to allow active high enable with active high full brightness or active high or low enable with active low full brightness (see Table 1). BRITE INPUT (DIMMING INPUT) The BRITE input is capable of accepting either a DC voltage (> .5V to < 2.5V) or a PWM digital signal that is clamped on chip (< .5V or > 2.5V). A digital signal can either be passed unfiltered to effect pulse ‘digital’ dimming or filtered with a capacitor to effect analog dimming with a digital PWM signal. Analog Dimming Methods: • Mechanical or digital potentiometer set to provide 1V to 2.5V on the wiper output. A filter cap from BRITE to signal ground is recommended. • D/A converter output directly connected to BRITE input. A R/C filter using a capacitor from the CPW1 input to ground for applications where the ADC output may contain noise sufficient to modulate the BRITE input. • A high frequency PWM digital logic pulse connected directly to the BRITE input. The Brightness (BRT, internal node) output will be sensitive only to the PWM duty cycle, and not to the PWM signal amplitude, so long as the amplitude exceeds 2.6V for a logic high (1) and is less than .4V for a logic (0). This pulse frequency will typically be between 1KHz and 100KHz and will not be synchronized with the LCD video frame rate. A capacitor (CPWM) between CPW1 and CPW2 will integrate the PWM signal for use by the controller. Digital Dimming Methods: • Low frequency PWM digital logic pulses connected directly to the BRITE input. As above the Brightness (BRT internal) will be sensitive only to the PWM duty cycle, and not to the PWM signal amplitude, so long as the amplitude exceeds 2.6V for a logic high (1) and is less than .4V for a logic (0). This pulse frequency will typically be in the range of 90-320Hz. Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 7 APPLICATIONS MASTER/SLAVE CLOCK SYNCHRONIZATION One or more controllers (up to 11) may be designated as slave controllers and receive ramp reset and phase synchronization from the designated master controller. This will allow up to 12 lamps (24 with two lamps in series/controller design) to all operate in phase and frequency synchronization. This is important to prevent random interference between lamps through unpredictably changing electric and magnetic fields that will inevitably link them. The LX1688 has two independent oscillators, one for lamp strike and one for the lamp run frequency. The strike oscillator ramps the operating frequency slowly up and down when the open lamp sense input (OLSNS) indicates the lamp is not ignited. During this lamp strike condition the operating frequency of each IC will vary up and down as needed to strike its lamp. The controller is so designed that the master controller clock remains at the pre-selected frequency for fully ignited lamps even while striking. Likewise the designated slave controller will not alter the frequency or phase of the master clock during its strike phase. Thus each controller will vary its frequency as needed to strike its lamp then it will synchronize to the master clock frequency and phase. The TRI_C wave generator (see Block Diagram) sets the rate of operating frequency variation during lamp strike. The TRI_C generator is connected to a 6-bit counter that times out after 63 cycles and then latches the FAULT output high if the OLSNS input indicates no lamp current is flowing. Even in the case of timeout fault the master controller clock will continue to provide synchronization to the slave controllers. When synchronizing more than one controller the Ramp Reset (RMP_RST), Phase Sync (PHA_SYNC), and Slave Input/Output are used. RMP_RST and PHA_SYNC should be connected between all the controllers. The master controller should have its SLAVE pin connected to VSS (GND) and the slave controllers SLAVE input to VDD (High). WWW . Microsemi .C OM The LX1688 is a backlight controller specifically designed with a special feature set needed in multiple lamp desktop monitors, and other multiple lamp displays. While utilizing the same architecture as Microsemi’s LX1686 controller it eliminates the synchronized digital dimming and adds, lamp ‘strike’ count out timer, lamp fault status output, and external clock input/output that permits multiple controllers to synchronize their output current both in frequency and phase. RangeMAX™ ® TM LX1688 Multiple Lamp CCFL Controller P RODUCTION D ATA S HEET DETAILED DESCRIPTION RMP_RST AND PHA_SYNC PIN TIMING REQUIREMENT WITH SLAVE MODE OPERATION When the LX1688 is configured for slave mode operation, and RMP_RST and PHA_SYNC is supplied from an external source, the signal timing should be met as outlined below. RMP_RST should be 2 times frequency of lamp frequency and duty should be 10 to 13%, and PHA_SYNC should be generated by divide by 2 of RMP_RST signal. Phase of these signals should be met the as shown, note the delay between the RMP_RST and PHA_SYNC signals: Min 150 10 49 T1 T2 T3 Typ 250 50 Tr, Tf Max 13 51 Unit nsec % % 100 nsec WWW . Microsemi .C OM and may or may not be externally synchronized to the LCD video frame rate. It will directly gate the signal BRT. CPWM should not be used in this case. FAULT PIN The fault pin is a digital output that indicates that the maximum numbers of strike attempts has occurred without lamp ignition. In this condition the FAULT pin will go active high with typically 20mA drive capability. Holding the OLSNS pin low (<200mV) will also force timeout and activate the FAULT pin. When used as a master, fault condition true does not inhibit master clock outputs PHA_SYNC and RMP_RST. I_R PIN The run mode frequency of the output is one half the internal ramp frequency, which is proportional to a bias current set by resistor RI of 80.6K. The output frequency can thus be adjusted by varying the value of RI-R, the typical range from about 50K to 100K. Since there is some variation in the frequency due to change in the input supply (VDD) it is recommended that the value of RI-R be selected at the nominal input voltage. SLEEP MODE (ENABLE SIGNAL) AND SWITCHED VDD (VDDSW) Since the LX1688 can be used in portable battery operated systems, a very low power sleep mode is included. The IC will consume less than 10µA quiescent current from both the VDD and VDD_P pins combined, when the ENABLE pin is deactivated. The polarity of the ENABLE pin is programmable by the BEPOL input (see table 1). In addition the controller provides a switched supply pin VDDSW this output supplies at least 10mA at VDD ─ .2V for external circuitry. This output can be used to power additional circuitry that can be enabled with the controller. T3 duty is 50% of operating frequency. T2 T3 T1 BIAS & TIMING EQUATIONS Formula 1: Formula 2: Triangular Wave Generator Frequency, FTRI Lamp Frequency (AOUT’s switching frequency), FLAMP FTRI = Formula 3: Minimum Current Error Amp Bandwidth, BWIEA_MIN BWIEA_MIN = Formula 5: Softstart time, TSS 1 [Hz] 200e-12 × RI Formula 4: Minimum Voltage Error Amp Bandwidth, BWVEA_MIN 0.000048 [Hz] CICOMP TSS = 4,500,000 × CVCOMP [sec] Copyright © 2001 Rev. 1.2, 2006-03-09 FLAMP = APPLICATIONS 1 [Hz] (25 × RI × CTRI ) BWVEA_MIN = 0.000048 [Hz] CVCOMP Formula 6: Minimum Power-on Reset Pulse Width, TMIN_POR TMIN_POR = 2.3e6 × CPOR [sec] Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 8 RangeMAX™ ® TM LX1688 Multiple Lamp CCFL Controller P RODUCTION D ATA S HEET APPLICATION CIRCUITS 1 VIN C1 VIN 2 GND 3 GND 4 5 VBRITE 6 RMP_RST 7 PHA_SYNC 8 ENABLE 9 10 VDDSW 10% 470nF 16V U2 SI9945AEY 8 RMP_RST PHA_SYNC R4 39 7 2 6 VDDP R5 39 5 4 C13 0.1uF 50V T1 1:75 5 3 2 4 1 2.2PF C14 VDDP PCB Q2 C12 BC847ALT1 BC847ALT1 Q1 + 1 220µ 25V 3 R8 100K 2 1 R6 C2 1 16V 10% 470nF 2 Analog Ground must connect to power ground at this point only 3 VDD 4 5 10nF 16V C3 10% R1 80.6K 1% 6 7 8 9 10 RMP_RST PHA_SYNC 11 12 AOUT BOUT VSS_P VSS VDD_P VDD BEPOL BRITE CPOR ENABLE VDD_SW TRI_C OLSNS ISNS ICOMP I_R CPWM1 VCOMP CPWM2 VSNS RMP_RST SLAVE PHA_SYNC FAULT 20 C6 82nF 17 16 15 14 2.2nF 50V 5% COG VDD VDDSW 18 10K C15 R2 47 22 19 D1 R7 3 BAW56 82 24 23 CN2 1 HV1 2 LV1 WWW . Microsemi .C OM CN1 16V 10% C8 C5 220nF 16V 10% C7 16V 10% 100nF 2.2nF 16V 5% C9 4.7nF C10 16V 10% 10nF 16V 10% C11 10nF 16V 10% C4 220nF 16V 10% VDD R9 1K R10 1M 1 2 D2 3 BAW56 R12 D3 3 BAV99 2 1 2.74K 1% C16 3.3nF COG 50V 5% R11 2.74K 1% 13 LED1 R3 220 OPTION Figure 1 – Schematic for LX1688 Inverter Module Configured as Master APPLICATIONS Copyright © 2001 Rev. 1.2, 2006-03-09 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 9 RangeMAX™ TM ® LX1688 Multiple Lamp CCFL Controller P RODUCTION D ATA S HEET APPLICATION INFORMATION Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 APPLICATIONS Copyright © 2001 Rev. 1.2, 2006-03-09 SETTING MASTER/SLAVE CONFIGURATION Simply connecting pin 14 to the ground for a master and to the VDD for a slave will do master and slave configuration. As shown in figure 2, module (A) configured as master and modules (B) and (C) configured as slaves. SYNCHRONIZATION OF FREQUENCY AND PHASE To synchronize the Lamp frequency and phase of all modules, it is required to connect the RMP_RST pin of all the modules together and connect PHA_SYNC pin of all the modules together. LAYOUT CONSIDERATION By designing the layout in a proper way we can reduce the overall noise and EMI for the module. The gate drivers for MOSFETs should have an independent loop that doesn’t interface with the more sensitive analog control function, therefore LX1688 provides two power inputs with separate ground pins (analog/signal), VDD feeds all analog signals and VDD_P feeds only the output drivers, as shown in figure1 these two pins (pin 23, 24) are separated and filtered by R14, C2 and C7. The connection of two ground pins should be at only one point as shown in figure1. The power traces should be short and wide as possible and all periphery components such capacitors should be located as closed as possible to the controller. OSCILLOSCOPE WAVEFORMS PICTURES The following oscilloscope waveform pictures are taken from the actual circuits and will show the operation of the modules in different modes when three identical modules are synchronized, one as a master, and two others as slaves. WWW . Microsemi .C OM APPLICATION EXAMPLE WITH LX1688 This section will highlight the features of LX1688 controller by showing a practical example. Three identical inverter modules are connected to each other and each module drives a single lamp. One module configured as a master and two others configured as slaves. A complete schematic hooked up a a master is given in Figure 1, the schematic provides all necessary functions such as high voltage feedback for regulation the peak lamp voltage, short-circuit protection, open lamp sensing and lamp current regulation needed for a typical application. The section follows with measurement waveforms and list of material of the actual modules. For more detail design procedure and circuit description please refer to application note (AN-13), which is available in Microsemi’s web site. INPUT VOLTAGE The LX1688 controller can operate at 3.3 to 5.0V ±10%, in this application all modules were driven by the same power voltage (a constant 5.0V), which provides VDD for controllers, and input voltage for the power section. Notice that VDD feeds all analog signals and VDD_P feeds only the output driver stage, these two signals should be filtered separately (Figure 1). SETTING LAMP FREQUENCY The value of R1 determines magnitude of internal current sources that set timing parameters. Equation (2) gives the relationship between Lamp frequency (FLAMP) and (RI_R), R1 in schematic. For this application we choose R6=80.6 KΩ, which results to a lamp frequency at 62.0 KHz. DIMMING The LX1688 includes highly integrated universal ‘PWM or DC’ dim input that allows either a PWM or DC input without requiring external conditioning. In this application we choose Digital Dimming by applying a PWM signal to BRITE pin. All modules were driven by the same PWM signals, but notice that it is possible to dim each module quite separately. BEPOL pin has three different modes (see table 1), in this application it is connected to VDD which means active high enable with active high full brightness. The PWM signal can be varied in frequency between 48-320 HZ. No capacitor between CPWM1 and CPWM2 is necessary. Page 10 RangeMAX™ ® TM LX1688 Multiple Lamp CCFL Controller P RODUCTION D ATA S HEET TYPICAL SLAVE APPLICATIONS 2 3 4 VIN VIN GND C2 470nF 16V 10% GND 5 6 7 8 9 1 0 WWW . Microsemi .C OM 1 VDDP C1 470nF 16V 10% CN 1 VBRITE 1 AOUT 24 BOUT 2 VSS_P RMP_RST 23 VDD_P 3 ENABLE VDD VDDSW VSS 22 VDD 21 BEPOL 20 BRITE 19 CPOR 18 ENABLE 17 I_R ICOMP CPWM1 VCOMP CPWM2 VSNS C9 C10 16 10 15 C11 11 14 RMP_RST SLAVE PHA_SYNC FAULT 12 PHA-SYNC C8 ISNS 8 Power Output Section C7 OLSNS 7 RMP_RST C6 TRI_C 6 R1 9 80.6K 1% C5 VDD_SW 5 C3 10nF 16V 10% C4 220nF 16v 10% VDDSW 4 VBRITE VDD R2 47 PHA_SYNC 13 R3 220 Master C5 : 220nF 16V 10% C6 : 82nF 16V 10% C7 : 100nF 16V 10% C8 : 2.2nF 50V 5% C9 : 4.7nF 16V 10% C10-11 : 10nF 16V 10% CN1 1 2 3 4 VIN 6 8 9 10 VDDP C1a 470nF 16V 10% CN1 1 VIN GND 2 3 C2a 470nF 16V 10% GND 5 7 LED1 VBRITE 1 AOUT 24 BOUT 4 2 VSS_P RMP_RST VDD_P 23 3 ENABLE VDD VSS 20 BRITE TRI_C CPOR OLSNS C2b 470nF 16V 10% ENABLE I_R 10 CPWM2 VSNS 11 12 VDD VDDSW VSS 24 23 21 20 BRITE TRI_C CPOR OLSNS I_R CPWM1 ICOMP 10 CPWM2 13 VSNS C11b 14 RMP_RST SLAVE 12 PHA-SYNC C9b 13 PHA_SYNC FAULT VDDSW R13a 100K C10b 15 11 RMP_RST C8b 17 16 VCOMP R3b 220 C5b: 220nF 16V 10% C6b: 82nF 16V 10% C7b: 100nF 16V 10% C8b: 2.2nF 50V 5% C9b: 4.7nF 16V 10% C10-11b: 10nF 16V 10% Slave 2 Power Output Section C7b 18 ISNS 8 C11a C6b 19 ENABLE 15 C5b VDD_SW 7 R1b 9 80.6K 1% C4b 220nF 16v 10% VDDSW 6 C3b 10nF 16V 10% VDD R2b 47 22 VDD 4 C9a LED1a VDD_P BEPOL C10a R3a 220 Slave 1 3 SLAVE PHA_SYNC FAULT BOUT VSS_P PHA_SYNC ENABLE 14 RMP_RST AOUT 2 Power Output Section 17 16 VCOMP 10 1 RMP_RST 5 C8a ISNS ICOMP CPWM1 9 VBRITE VBRITE C7a 18 8 C5a: 220nF 16V 10% C6a: 82nF 16V 10% C7a: 100nF 16V 10% C8a: 2.2nF 50V 5% C9a: 4.7nF 16V 10% C10-11a: 10nF 16V 10% VIN GND GND C6a 19 7 PHA-SYNC C5a VDD_SW 6 RMP_RST C4a 220nF 16v 10% VDDSW BEPOL R1a 9 80.6K 1% 8 21 5 C3a 10nF 16V 10% 7 22 VDD 4 VBRITE 6 VDD R2a 47 VDDP C1b 470nF 16V 10% 5 PHA_SYNC VDDSW VIN LED1b VDDSW R13b 100K Figure 2 – Schematic Modules Connected as a Master and Slave APPLICATIONS Copyright © 2001 Rev. 1.2, 2006-03-09 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 11 RangeMAX™ TM ® LX1688 Multiple Lamp CCFL Controller P RODUCTION D ATA S HEET THEORY OF OPERATION Strike Mode Every IC includes a separate strike controller that operates from the primary oscillator; therefore the strike controller is independent of the sync signals. The following oscilloscope waveform picture is taken when the master module is on striking mode and the salves are on running mode. Figure 3- Sync signals-Timing relationship to AOUT CH2= AOUT(Master), CH3=PHA_SYNC, CH4=RMP_RST WWW . Microsemi .C OM Multiple Lamp Sync The figure 3 shows the sync signals (PHA_SYNC and RMP_RST) timing relationship to Gate signal AOUT, for the master module. AOUT and PHA_SYNC running at the same frequency and RMP_RST signal has the twice frequency. Figure 5- Master is in striking mode while slaves are in running mode CH2= AOUT(Master), CH3=AOUT(Slave1), CH4=AOUT(Slave2) Output Drivers The figure 4 shows the gate signals of the modules, which are operating, in running mode during digital dimming with 95% duty cycle. As shown all signals are synchronized. The difference between each signal’s duty cycles is because each lamp has an independent control loop. Figure 4- Output drivers of both Master and Slaves. CH2=AOUT(Master), CH3=AOUT(Slave1), CH4=AOUT(Slave2) APPLICATIONS Copyright © 2001 Rev. 1.2, 2006-03-09 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 12 RangeMAX™ ® TM LX1688 Multiple Lamp CCFL Controller P RODUCTION D ATA S HEET THEORY OF OPERATION WWW . Microsemi .C OM Digital Dimming The following oscilloscope waveforms are showing gate signals of Master and slaves during digital dimming at 50% and 5% duty cycle. Figure 6- Gate signals during digital dimming with 50% duty cycle CH2= AOUT(Master), CH3=AOUT(Slave1), CH4=AOUT(Slave2) Figure 7- Gate signals during digital dimming with 5% duty cycle CH2= AOUT(Master), CH3=AOUT(Slave1), CH4=AOUT(Slave2) Output currents Figure 8 shows the output current of master and slaves during digital dimming with 5% duty cycle. The lamp currents are operating in phase and frequency synchronization. This prevents random interface between controllers and reduces EMI. Figure 8- Output current during digital dimming with 5% duty cycle R1= out(Master) R2=Iout(Slave1) R3=Iout(Slave2) Lamp Current at 10mA/Div APPLICATIONS Copyright © 2001 Rev. 1.2, 2006-03-09 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 13 RangeMAX™ ® TM LX1688 Multiple Lamp CCFL Controller P RODUCTION D ATA S HEET LX1688 MODULE BOARD LIST OF MATERIAL Part Description Manufacture Part Number U1 U2 Q1, Q2 D1, D2 D3 LED1 R1 R2 R3 Backlight Controller Dual N-Channel MOSFET NPN Transistor Dual Diode Dual Diode LED 80.6K 1% 1/16 W 47 ohm 5% 1/8 W 220 ohm 5% 1/8 W Microsemi Siliconix Motorola Motorola Philips LX1688 Si9945AEY BC847ALT1 BAW56 BAV99 R4, R5 R6 R7 R8 R9 R10 R11, R12 C1, C2 C3 C4 C5 C6 C7 C8 C9 C10, C11 C12 C13 C14 C15 C16 T1 39 ohm 5% 1/16 W 82 ohm 5% 1/16 W 10K 5% 1/16 W 100K 5% 1/16 W 1K 5% 1/16 W 1 M 5% 1/16 W 2.74K 1% 1/16 W 470nF 16V 10% X7R 1206 10nF 16V 10% 0805 220nF 16V 10% X7R 1206 220nF 16V 20% 0805 82nF 16V 10% X7R 0603 100nF 16V 20% X7R 2.2nF 50V 10% 4.7nF 16V 10% X7R 10nF 16V 10% X7R 220µF Tantalum 7343 220pF 2KV 5% COG 2.2pF PCB 2.2nF 50V 5% COG 3.3nF 50V 5% COG Low profile, High voltage xfmr, turns ratio 1:75 Connector, 10 pin Connector, 2 pin CN1 CN2 WWW . Microsemi .C OM Reference Designator NOVACAP AVX AVX AVX NOVACAP AVX AVX AVX NOVACAP 0805YC224MAT2A 0603YC823KAT2A 0603YC104MAT2A 0603B22K500NT 0603YC472KAT2A 0603YC103KAT2A AVX NOVACAP Microsemi 08055A222JAT2A 0805N332J500NT SGE2645-1 Molex Molex 53261-1090 1206N221J202NT MODULE Table 2- List of material for LX1688 inverter module Copyright © 2001 Rev. 1.2, 2006-03-09 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 14 RangeMAX™ ® TM LX1688 Multiple Lamp CCFL Controller P RODUCTION D ATA S HEET PACKAGE DIMENSIONS WWW . Microsemi .C OM PW 24-Pin Thin Small Shrink Outline (TSSOP) Package 3 21 P E F D A H SEATING PLANE Dim A B C D E F G H L M P *LC B G MILLIMETERS MIN MAX 0.85 0.95 0.19 0.30 0.09 0.20 7.70 7.90 4.30 4.50 0.65 BSC 0.05 0.15 – 1.10 0.50 0.75 0° 8° 6.25 6.55 – 0.10 L C M INCHES MIN MAX 0.033 0.037 0.007 0.012 0.0035 0.008 0.303 0.311 0.169 0.177 0.025 BSC 0.002 0.005 – .0433 0.020 0.030 0° 8° 0.246 0.258 – 0.004 * Lead Coplanarity Dimensions do not include mold flash or protrusions; these shall not exceed 0.155mm(.006”) on any side. Lead dimension shall not include solder coverage. Copyright © 2001 Rev. 1.2, 2006-03-09 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 15 MECHANICALS Note: RangeMAX™ TM ® LX1688 Multiple Lamp CCFL Controller P RODUCTION D ATA S HEET NOTES WWW . Microsemi .C OM NOTES PRODUCTION DATA – Information contained in this document is proprietary to Microsemi and is current as of publication date. This document may not be modified in any way without the express written consent of Microsemi. Product processing does not necessarily include testing of all parameters. Microsemi reserves the right to change the configuration and performance of the product and to discontinue product at any time. Copyright © 2001 Rev. 1.2, 2006-03-09 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 16