MC10110 Dual 3-Input/3-Ouput OR Gate The ability to control three parallel lines from a single point makes the MC10110 particularly useful in clock distribution applications where minimum clock skew is desired. Three VCC pins are provided and each one should be used. • PD = 80 mW typ/pkg (No Load) • tpd = 2.4 ns typ (All Outputs Loaded) • tr, tf = 2.2 ns typ (20%–80%) http://onsemi.com MARKING DIAGRAMS 16 CDIP–16 L SUFFIX CASE 620 LOGIC DIAGRAM 5 6 7 1 2 3 4 9 10 11 MC10110L AWLYYWW 16 PDIP–16 P SUFFIX CASE 648 12 13 14 MC10110P AWLYYWW 1 1 VCC1 = PIN 1, 15 VCC2 = PIN 16 VEE = PIN 8 PLCC–20 FN SUFFIX CASE 775 10101 AWLYYWW DIP PIN ASSIGNMENT VCC1 1 16 VCC2 AOUT 2 15 VCC1 AOUT 3 14 BOUT AOUT 4 13 BOUT AIN 5 12 BOUT AIN 6 11 BIN AIN 7 10 BIN VEE 8 9 BIN A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device Package Shipping MC10110L CDIP–16 25 Units / Rail MC10110P PDIP–16 25 Units / Rail MC10110FN PLCC–20 46 Units / Rail Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). Semiconductor Components Industries, LLC, 2000 March, 2000 – Rev. 7 1 Publication Order Number: MC10110/D MC10110 ELECTRICAL CHARACTERISTICS Test Limits Characteristic Symbol Pin Under Test Power Supply Drain Current IE 8 42 IinH 5, 6, 7 680 Input Current –30°C Min +25°C Max Min +85°C Max Unit 38 42 mAdc 425 425 µAdc Typ Max 30 0.5 Min µAdc IinL 5, 6, 7 0.5 Output Voltage Logic 1 VOH 2 3 4 –1.060 –1.060 –1.060 –0.890 –0.890 –0.890 –0.960 –0.960 –0.960 –0.810 –0.810 –0.810 –0.890 –0.890 –0.890 0.3 –0.700 –0.700 –0.700 Vdc Output Voltage Logic 0 VOL 2 3 4 –1.890 –1.890 –1.890 –1.675 –1.675 –1.675 –1.850 –1.850 –1.850 –1.650 –1.650 –1.650 –1.825 –1.825 –1.825 –1.615 –1.615 –1.615 Vdc Threshold Voltage Logic 1 VOHA 2 3 4 –1.080 –1.080 –1.080 Threshold Voltage Logic 0 VOLA 2 3 4 –0.980 –0.980 –0.980 –0.910 –0.910 –0.910 –1.655 –1.655 –1.655 –1.630 –1.630 –1.630 Vdc –1.595 –1.595 –1.595 Switching Times (50Ω Load) Propagation Delay Vdc ns t5+2+ t5–2– t5+3+ t5–3– t5+4+ t5–4– 2 2 3 3 4 4 1.4 1.4 1.4 1.4 1.4 1.4 3.5 3.5 3.5 3.5 3.5 3.5 1.4 1.4 1.4 1.4 1.4 1.4 2.4 2.4 2.4 2.4 2.4 2.4 3.5 3.5 3.5 3.5 3.5 3.5 1.5 1.5 1.5 1.5 1.5 1.5 3.8 3.8 3.8 3.8 3.8 3.8 Rise Time (20 to 80%) t2+ t3+ t4+ 2 3 4 1.0 1.0 1.0 3.5 3.5 3.5 1.1 1.1 1.1 2.2 2.2 2.2 3.5 3.5 3.5 1.2 1.2 1.2 3.8 3.8 3.8 Fall Time (20 to 80%) t2– t3– t4– 2 3 4 1.0 1.0 1.0 3.5 3.5 3.5 1.1 1.1 1.1 2.2 2.2 2.2 3.5 3.5 3.5 1.2 1.2 1.2 3.8 3.8 3.8 http://onsemi.com 2 MC10110 ELECTRICAL CHARACTERISTICS (continued) TEST VOLTAGE VALUES (Volts) Characteristic Power Supply Drain Current Input Current @ Test Temperature VIHmax VILmin VIHAmin VILAmax VEE –30°C –0.890 –1.890 –1.205 –1.500 –5.2 +25°C –0.810 –1.850 –1.105 –1.475 –5.2 +85°C –0.700 –1.825 –1.035 –1.440 –5.2 Symbol Pin Under Test IE 8 IinH 5, 6, 7 IinL 5, 6, 7 Output Voltage Logic 1 VOH 2 3 4 Output Voltage Logic 0 VOL 2 3 4 Threshold Voltage Logic 1 VOHA 2 3 4 Threshold Voltage Logic 0 VOLA 2 3 4 Switching Times TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VILmin (VCC) Gnd 8 1, 15, 16 8 1, 15, 16 8 1, 15, 16 8 8 8 1, 15, 16 1, 15, 16 1, 15, 16 8 8 8 1, 15, 16 1, 15, 16 1, 15, 16 8 8 8 1, 15, 16 1, 15, 16 1, 15, 16 5 6 7 8 8 8 1, 15, 16 1, 15, 16 1, 15, 16 Pulse In Pulse Out –3.2 V +2.0 V VILAmax * * 5 6 7 5 6 7 (50Ω Load) Propagation Delay VEE VIHAmin t5+2+ t5–2– t5+3+ t5–3– t5+4+ t5–4– 2 2 3 3 4 4 5 5 5 5 5 5 2 2 3 3 4 4 8 8 8 8 8 8 1, 15, 16 1, 15, 16 1, 15, 16 1, 15, 16 1, 15, 16 1, 15, 16 Rise Time (20 to 80%) t2+ t3+ t4+ 2 3 4 5 5 5 2 3 4 8 8 8 1, 15, 16 1, 15, 16 1, 15, 16 Fall Time (20 to 80%) t2– t3– t4– 2 3 4 5 5 5 2 3 4 8 8 8 1, 15, 16 1, 15, 16 1, 15, 16 * Individually test each input using the pin connections shown. Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner. http://onsemi.com 3 MC10110 PACKAGE DIMENSIONS PLCC–20 FN SUFFIX PLASTIC PLCC PACKAGE CASE 775–02 ISSUE C 0.007 (0.180) M T L–M B Y BRK –N– U N S 0.007 (0.180) M T L–M S S N S D –L– –M– Z W 20 D 1 G1 X V 0.010 (0.250) S T L–M S N S VIEW D–D A 0.007 (0.180) M T L–M S N S R 0.007 (0.180) M T L–M S N S 0.007 (0.180) M T L–M H S N S Z K1 K C E F 0.007 (0.180) M T L–M S 0.004 (0.100) G J –T– VIEW S G1 0.010 (0.250) S T L–M S N S VIEW S SEATING PLANE NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). http://onsemi.com 4 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 ––– 0.025 ––– 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 ––– 0.020 2_ 10 _ 0.310 0.330 0.040 ––– MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 ––– 0.64 ––– 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 ––– 0.50 2_ 10 _ 7.88 8.38 1.02 ––– N S MC10110 PACKAGE DIMENSIONS –A– 16 9 1 8 –B– CDIP–16 L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE T C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M –A– 9 1 8 B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S PDIP–16 P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R 16 S INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 T A M http://onsemi.com 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MC10110 Notes http://onsemi.com 6 MC10110 Notes http://onsemi.com 7 MC10110 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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