MPS NB639 High efficiency, fast transient, 8a, 28v synchronous step-down converter in a tiny qfn20 (3x4mm) package Datasheet

NB639
The Future of Analog IC Technology
High Efficiency, Fast Transient, 8A, 28V
Synchronous Step-down Converter
In a Tiny QFN20 (3x4mm) Package
DESCRIPTION
FEATURES
The NB639 is a fully integrated, high frequency
synchronous rectified step-down switch mode
converter. It offers a very compact solution to
achieve 8A continuous output current over a wide
input supply range with excellent load and line
regulation. The NB639 operates at high efficiency
over a wide output current load range.
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•
•
To further optimize efficiency at light load, this
device’s VCC supply is designed to be biased
externally.
Constant-On-Time (COT) control mode provides
fast transient response and eases loop
stabilization.
Full protection features include SCP, OCP, OVP,
UVP and thermal shutdown.
The NB639 requires a minimum number of readily
available standard external components and is
available in a space-saving QFN20 (3x4mm)
package.
•
•
•
•
•
•
•
•
Wide 4.5V to 28V Operating Input Range
8A Output Current
Internal 30mΩ High-Side, 12mΩ Low-Side
Power MOSFETs
Proprietary Switching Loss Reduction
Technique
1% Reference Voltage
Programmable Soft Start Time
Soft Shutdown
Programmable Switching Frequency
SCP, OCP, OVP, UVP Protection and
Thermal Shutdown
Output Adjustable from 0.8V to 13V
Available in a QFN20 (3x4mm) Package
APPLICATIONS
•
•
•
•
Notebook Systems and I/O Power
Networking Systems
Optical Communication Systems
Distributed Power POL Systems
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Quality Assurance.
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
NB639 Rev.1.13
4/18/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
1
NB639 – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
ORDERING INFORMATION
Part Number*
Package
Top Marking
NB639DL
QFN20 (3x4mm)
639
* For Tape & Reel, add suffix –Z (e.g. NB639DL–Z)
For RoHS compliant packaging, add suffix –LF (e.g. NB639DL–LF–Z)
PACKAGE REFERENCE
TOP VIEW
AGND
FREQ
VCC
IN
SW SW
20
19
18
17
1
IN
2
SW
FB
3
16
PGND
15
PGND
14
PGND
13
PGND
12
PGND
11
PGND
IN
SS
4
SW
EN
5
IN
PGOOD
6
7
8
9
10
BST IN SW SW
EXPOSED PAD
ON BACKSIDE
(4)
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance
Supply Voltage VIN ....................................... 30V
Supply Voltage VCC ........................................ 6V
VSW ........................................-0.3V to VIN + 0.3V
VBST ...................................................... VSW + 6V
IVIN (RMS) ........................................................ 3.5A
VPGOOD ...................................-0.3V to VCC +0.6V
All Other Pins ..................................-0.3V to +6V
(2)
Continuous Power Dissipation (TA = +25°C)
………………………………………………….2.6W
Junction Temperature ...............................150°C
Lead Temperature ....................................260°C
Storage Temperature............... -65°C to +150°C
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
Recommended Operating Conditions
θJA
θJC
QFN20 (3x4mm) ......................48 ...... 10 ... °C/W
(3)
Supply Voltage VIN ...........................4.5V to 28V
Supply Voltage VCC ........................................ 5V
Output Voltage VOUT .........................0.8V to 13V
Operating Junction Temp. (TJ). -40°C to +125°C
NB639 Rev.1.13
4/18/2012
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NB639 – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS
VIN = 12V, VCC=5V, TA = +25°C, unless otherwise noted.
Parameters
Input Supply Current
(Shutdown)
Input Supply Current
(Quiescent)
VCC Supply Current
(Quiescent)
HS Switch On Resistance (5)
LS Switch On Resistance (5)
Switch Leakage
Symbol
Condition
IIN
VEN = 0V
0
μA
IIN
VEN = 2V, VFB = 1V
40
μA
Ivcc
VEN = 2V, VFB = 1V
350
μA
30
12
mΩ
mΩ
HSRDS-ON
LSRDS-ON
SWLKG
Current Limit
ILIMIT
One-Shot On Time
TON
Minimum Off Time(5)
Fold-back Off Time(5)
OCP hold-off time(5)
Feedback Voltage
Feedback Current
Soft Start Charging Current
Soft Stop Discharging Current
Power Good Rising Threshold
Power Good Falling Threshold
Power Good Rising Delay
Power Good Rising Delay
Power Good Rising Delay
EN Rising Threshold
EN Threshold Hysteresis
EN Input Current
VCC Under-Voltage Lockout
Threshold Rising
VCC Under-Voltage Lockout
Threshold Hysteresis
VOUT Over-Voltage Protection
Threshold
VOUT Under-Voltage Detection
Threshold
Thermal Shutdown
Thermal Shutdown Hysteresis
Min
TOFF
TFB
TOC
VFB
IFB
+ISS
-ISS
PGOODVth-Hi
PGOODVth-Lo
TPGOOD
TPGOOD
TPGOOD
ENVth-Hi
ENVth-Hys
IEN
VCCUVVth
VEN = 0V, VSW = 0V or
12V
Typ
0
RFREQ=348kΩ,
VOUT=1.05V
ILIM=1 (HIGH)
ILIM=1 (HIGH)
807
VFB = 815mV
VSS=0V
VSS=0.815V
10
Units
μA
16.5
A
360
ns
100
7.5
ns
μs
μs
mV
nA
μA
μA
VFB
VFB
ms
ms
ms
V
mV
μA
815
10
8.5
8.5
0.9
0.85
Tss = 1ms
Tss = 2ms
Tss = 3ms
1.05
250
1.35
420
2
3.8
4.0
VEN = 2V
Max
40
823
50
1
1.5
2
1.60
550
4.2
V
VCCUVHYS
880
mV
VOVP
1.25
VFB
VUVP
0.7
VFB
TSD
150
25
°C
°C
TSD-HYS
Notes:
5) Guaranteed by design.
NB639 Rev.1.13
4/18/2012
www.MonolithicPower.com
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NB639 – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
PIN FUNCTIONS
Pin #
Name
Description
1
AGND
2
FREQ
3
FB
4
SS
5
EN
Analog Ground.
Frequency Set during CCM operation. The ON period is determined by the input
voltage and the frequency-set resistor connected to FREQ pin. Connect a resistor
to IN for line feed-forward. Decouple with a 1nF capacitor.
Feedback. An external resistor divider from the output to GND, tapped to the FB
pin, sets the output voltage.
Soft Start. Connect an external SS capacitor to program the soft start time for the
switch mode regulator. When the EN pin becomes high, an internal current source
(8.5uA) charges up the SS capacitor and the SS voltage slowly ramps up from 0 to
VFB smoothly. When the EN pin becomes low, an internal current source (8.5μA)
discharges the SS capacitor and the SS voltage slowly ramps down.
EN=1 to enable the NB639. For automatic start-up, connect EN pin to IN with a
100kΩ resistor. It includes an internal 1MΩ pull-down resistor.
Power Good Output. The output of this pin is an open drain and is high if the
output voltage is higher than 90% of the nominal voltage. There is delay from FB ≥
90% to PGOOD high, which is 50% of SS time plus 0.5ms.
Bootstrap. A capacitor connected between SW and BS pins is required to form a
floating supply across the high-side switch driver.
Supply Voltage. The NB639 operates from a +4.5V to +28V input rail. C1 is
needed to decouple the input rail. Use wide PCB traces and multiple vias to make
the connection.
Switch Output. Use wide PCB traces and multiple vias to make the connection.
System Ground. This pin is the reference ground of the regulated output voltage.
For this reason care must be taken in PCB layout.
External 5V Supply. This 5V supply has to be applied in order to bias the device.
Decouple with a 1µF capacitor as close to this pin as possible.
6
PGOOD
7
BST
8, 19
IN
9, 10, 17, 18
SW
11-16
PGND
20
VCC
NB639 Rev.1.13
4/18/2012
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NB639 – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN=12V, VOUT =1.05V, L=1.0µH, TA=+25°C, unless otherwise noted.
NB639 Rev.1.13
4/18/2012
www.MonolithicPower.com
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NB639 – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN=12V, VOUT =1.05V, L=1.0µH, TA=+25°C, unless otherwise noted.
NB639 Rev.1.13
4/18/2012
www.MonolithicPower.com
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NB639 – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN=12V, VOUT =1.05V, L=1.0µH, TA=+25°C, unless otherwise noted.
NB639 Rev.1.13
4/18/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
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NB639 – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
BLOCK DIAGRAM
Figure 1—Functional Block Diagram
NB639 Rev.1.13
4/18/2012
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NB639 – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
OPERATION
PWM Operation
The NB639 is a fully integrated synchronous
rectified step-down switch mode converter.
Constant-on-time (COT) control is employed to
provide fast transient response and easy loop
stabilization. At the beginning of each cycle, the
high-side MOSFET (HS-FET) is turned on when
the feedback voltage (VFB) is below the reference
voltage (VREF) which indicates insufficient output
voltage. The ON period is determined by the
input voltage and the frequency-set resistor as
follows:
TON (ns) =
12 × RFREQ (kΩ)
VIN (V) − 0.4
(1)
After the ON period elapses, the HS-FET is
turned off, or becomes OFF state. It is turned ON
again when VFB drops below VREF. By repeating
operation this way, the converter regulates the
output voltage. The integrated low-side MOSFET
(LS-FET) is turned on when the HS-FET is in its
OFF state to minimize the conduction loss. There
will be a dead short between input and GND if
both HS-FET and LS-FET are turned on at the
same time. It’s called shoot-through. In order to
avoid shoot-through, a dead-time (DT) is
internally generated between HS-FET off and LSFET on, or LS-FET off and HS-FET on.
As Figure 2 shows, when the output current is
high, the HS-FET and LS-FET repeat on/off as
described above. In this operation, the inductor
current will never go to zero. It’s called
continuous-conduction-mode (CCM) operation. In
CCM operation, the switching frequency (FSW) is
fairly constant.
Light-Load Operation
When the load current decreases, The NB639
reduces the switching frequency automatically to
maintain high efficiency. The light load operation
is shown in Figure 3. The VFB does not reach
VREF when the inductor current is approaching
zero. As the output current reduces from heavyload condition, the inductor current also
decreases, and eventually comes close to zero.
The LS-FET driver turns into tri-state (high Z)
whenever the inductor current reaches zero level.
A current modulator takes over the control of LSFET and limits the inductor current to less than
600μA. Hence, the output capacitors discharge
slowly to GND through LS-FET as well as R1 and
R2. As a result, the efficiency at light load
condition is greatly improved. At light load
condition, the HS-FET is not turned ON as
frequently as at heavy load condition. This is
called skip mode.
Heavy-Load Operation
Figure 3—Light Load Operation
Figure 2—Heavy Load Operation
NB639 Rev.1.13
4/18/2012
As the output current increases from the light
load condition, the time period within which the
current modulator regulates becomes shorter.
The HS-FET is turned on more frequently. Hence,
the switching frequency increases correspondingly.
The output current reaches the critical level when
the current modulator time is zero. The critical
level of the output current is determined as
follows:
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NB639 – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
IOUT =
(VIN − VOUT ) × VOUT
2 × L × FSW × VIN
(2)
It turns into PWM mode once the output current
exceeds the critical level. After that, the switching
frequency stays fairly constant over the output
current range.
Switching Frequency
Constant-on-time (COT) control is used in the
NB639 and there is no dedicated oscillator in the
IC. The input voltage is feed-forwarded to the ontime one-shot timer through the resistor RFREQ.
The duty ratio is kept as VOUT/VIN. Hence, the
switching frequency is fairly constant over the
input voltage range. The switching frequency
can be set as follows:
the VFB ripple dominates in noise immunity. The
magnitude of the VFB ripple doesn’t affect the
noise immunity directly.
V SLO PE1
VNOISE
V FB
V R EF
H S D river
Jitter
Figure 4—Jitter in PWM Mode
V SLO PE2
VNOISE
V FB
V REF
106
(3)
FSW (kHz) =
12 × RFREQ (kΩ) VIN (V)
×
+ TDELAY (ns)
VIN (V) − 0.4
VOUT (V)
Where TDELAY is the comparator delay. It’s about
40ns.
H S D river
Jitter
Figure 5—Jitter in Skip Mode
When the output capacitors are ceramic ones,
the ESR ripple is not high enough to stabilize the
system, and external ramp compensation is
needed.
IR4
IC4
IFB
NB639 is optimized to operate at high switching
frequency with high efficiency. High switching
frequency makes it possible to utilize small sized
LC filter components to save system PCB space.
RAMP Compensation
Figure 4 and Figure 5 show jitter occurring in
both PWM mode and skip mode. When there is
noise in the VFB downward slope, the ON time of
the HS-FET driver deviates from its intended
location and produces jitter. It is necessary to
understand that there is a relationship between a
system’s stability and the steepness of the VFB
ripple’s downward slope. The slope steepness of
NB639 Rev.1.13
4/18/2012
Figure 6—Simplified Circuit in PWM Mode
with External Ramp Compensation
In PWM mode, an equivalent circuit with HS-FET
off and the use of an external ramp
compensation circuit (R4, C4) is simplified in
Figure 6. The external ramp is derived from the
inductor ripple current. If one chooses C4, R1,
and R2 to meet the following condition:
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NB639 – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
1
2π × FSW × C4
<
1 ⎛ R1 × R 2 ⎞
×⎜
⎟
5 ⎝ R1 + R 2 ⎠
(4)
While in skip mode, the downward slope is not
related to the external ramp.
Then one can have:
IR4 = IC4 + IFB ≈ IC4
(5)
The downward slope of the VFB ripple can be
estimated as:
VSLOPE1 =
−VOUT
R4 × C4
From our bench experiments, it is recommended
to keep VSLOPE1 around 15~30V/ms.
(6)
In skip mode, the downward slope of the VFB
ripple is the same whether the external ramp is
used or not. Figure 8 shows an equivalent circuit
with HS-FET off and the current modulator
regulating the LS-FET. The downward slope of
the VFB ripple can be determined as follows (IMOD
is ignored here):
As one can see from equation (6), if there is
instability in PWM mode, one can reduce either
R4 or C4. If C4 can not be reduced further due to
limitation from equation (4), then one can only
reduce R4. From bench experiments, VSLOPE1
is expected to be around 20~40V/ms.
VSLOPE2 =
− VREF
R
+
( 1 R2 ) × COUT
(8)
In the case of POSCAP or other types of
capacitor with higher ESR, the external ramp is
not necessary.
IMOD
Figure 8—Simplified Circuit in Skip Mode
Figure 7—Simplified Circuit in PWM Mode
without External Ramp Compensation
Figure 7 shows the equivalent circuit in PWM
mode with the HS-FET off and without an
external ramp circuit. The ESR ripple dominates
the output ripple. The downward slope of the VFB
ripple is:
VSLOPE1 =
−ESR × VREF
L
(7)
From equation (7), one can see that the
downward slope of VFB ripple is proportional to
ESR/L. Therefore, it’s necessary to know the
minimum ESR value of the output capacitors
when no external ramp is used. There is also a
limitation with inductance in this case. The
smaller the inductance, the more stable it will be.
NB639 Rev.1.13
4/18/2012
To keep the system stable during light load
condition, the values of the FB resistors should
not be too big. It is recommended to keep the
VSLOPE2 value around 0.4~0.8mV/ms. It should
be noted that IMOD is excluded from the equation
because it does not impact the system’s stability
at light load conditions.
Bootstrap Charging
The floating power MOSFET driver is
recommended to be powered by an external VCC
through D2 as shown in Figure 9. This floating
driver has its own UVLO protection. This UVLO’s
rising threshold is 2.2V with a hysteresis of
150mV. U1 will regulate to maintain BST voltage
across C4 If (VCC-VSW) is less than 3.5V. The
recommended external BST diode D2 is IN4148,
and the BST cap C4 is 0.1~1μF.
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NB639 – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
of REF voltage, the PGOOD pin is pulled high
after a delay.
D1
VIN
The PGOOD delay time is determined as follows:
M1
D2
BST
VCC
U1
3.5V
VOUT
L1
C2
Figure 9—Bootstrap Charging Circuit
Soft Start/Stop
The NB639 employs soft start/stop (SS)
mechanism to ensure smooth output during
power-up and power shutdown. When the EN pin
becomes high, an internal current source (8.5μA)
charges up the SS CAP. The SS CAP voltage
takes over the VREF voltage to the PWM
comparator. The output voltage smoothly ramps
up with the SS voltage. Once the SS voltage
reaches the same level as the REF voltage, it
keeps ramping up while REF takes over the
PWM comparator. At this point, the soft start
finishes and it enters into steady state operation.
When the EN pin becomes low, the SS CAP
voltage is discharged through an 8.5μA internal
current source. Once the SS voltage reaches
REF voltage, it takes over the PWM comparator.
The output voltage will decrease smoothly with
SS voltage until zero level. The SS CAP value
can be determined as follows:
CSS (nF) =
TSS (ms) × ISS (μA)
VREF (V)
(9)
If the output capacitors have large capacitance
value, it’s not recommended to set the SS time
too small. A minimal value of 4.7nF should be
used if the output capacitance value is larger
than 330uF.
Power Good (PGOOD)
The NB639 has power-good (PGOOD) output.
The PGOOD pin is the open drain of a MOSFET.
It should be connected to VCC or other voltage
source through a resistor (e.g. 100k). After the
input voltage is applied, the MOSFET is turned
on, so that the PGOOD pin is pulled to GND
before SS ready. After FB voltage reaches 90%
NB639 Rev.1.13
4/18/2012
(10)
When the FB voltage drops to 85% of the REF
voltage, the PGOOD pin will be pulled low.
C4
SW
TPGOOD (ms) = 0.5 × TSS (ms) + 0.5
Over-Current Protection (OCP) and ShortCircuit Protection (SCP)
The NB639 has cycle-by-cycle over-current limit
control. The inductor current is monitored during
the ON state. Once it detects that the inductor
current is higher than the current limit, the HSFET is turned off. At the same time, the OCP
timer is started. The OCP timer is set as 40μs. If
in the following 40μs, the current limit is hit for
every cycle, then it’ll trigger OCP. The converter
needs power cycle to restart after it triggers OCP.
When the current limit is hit and the FB voltage is
lower than 50% of the REF voltage, the device
considers this as a dead short on the output and
triggers OCP immediately. This is short circuit
protection (SCP).
Over/Under-voltage Protection (OVP/UVP)
The NB639 monitors the output voltage through a
resistor divider feedback (FB) voltage to detect
overvoltage and undervoltage on the output.
When the FB voltage is higher than 125% of the
REF voltage, it’ll trigger OVP. Once it triggers
OVP, the LS-FET is always on while the HS-FET
is always off. It needs power cycle to power up
again. When the FB voltage is below 50% of the
REF voltage (0.815V), UVP will be triggered.
Usually, UVP accompanies a hit in current limit
and this results in SCP.
UVLO protection
The NB639 has under-voltage lock-out protection
(UVLO). When VCC is higher than the UVLO
rising threshold voltage, the NB639 will be
powered up. It shuts off when VCC is lower than
the UVLO falling threshold voltage. This is nonlatch protection.
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NB639 – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
Thermal Shutdown
Thermal shutdown is employed in the NB639.
The junction temperature of the IC is internally
monitored. If the junction temperature exceeds
the threshold value (typically 150ºC), the
converter shuts off. This is non-latch protection.
There is about 25ºC hysteresis. Once the
junction temperature drops to around 125ºC, it
initiates a soft start.
NB639 Rev.1.13
4/18/2012
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NB639 – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
APPLICATION INFORMATION
Setting the Output Voltage
The output voltage is set by using a resistor
divider from the output voltage to FB pin.
When there is no external ramp employed, the
output voltage is set by feedback resistors R1
and R2. First, choose a value for R2. A value
within 5kΩ-40kΩ is recommended to ensure
stable operation. Then, R1 is determined as
follows:
R1 =
VOUT − VREF
× R2
VREF
(11)
When low ESR ceramic capacitor is used in the
output, an external voltage ramp should be
added to FB through resistor R4 and capacitor
C4.The output voltage is influenced by ramp
voltage VRAMP except R divider. The VRAMP can be
calculated as shown in equation 19. Choose a
value within 5kΩ-40kΩ for R2. The value of R1
then is determined as follows:
R1 =
1
1
VREF + VRAMP
1
2
−
1
⎛
⎞ R4
R2 × ⎜ VOUT − VREF − VRAMP ⎟
2
⎝
⎠
(12)
Using equation 12 to calculate the output voltage
can be complicated. Furthermore, as VRAMP
changes due to changes in VOUT and VIN, VFB also
varies. To improve the output voltage accuracy
and simplify the calculation of R2 in equation 12,
a DC-blocking capacitor Cdc can be added.
Figure 10 shows a simplified circuit with external
ramp compensation and a DC-blocking capacitor.
With this capacitor, R1 can easily be obtained by
using equation 11.
Cdc is suggested to be 1-4.7μF for better DC
blocking performance.
Figure 10—Simplified Circuit with External
Ramp Compensation and DC-Blocking
Capacitor.
Input Capacitor
The input current to the step-down converter is
discontinuous. Therefore, a capacitor is required
to supply the AC current to the step-down
converter while maintaining the DC input voltage.
Ceramic capacitors are recommended for best
performance. In the layout, it’s recommended to
put the input capacitors as close to the IN pin as
possible.
The capacitance varies significantly over
temperature. Capacitors with X5R and X7R
ceramic dielectrics are recommended because
they are fairly stable over temperature.
The capacitors must also have a ripple current
rating greater than the maximum input ripple
current of the converter. The input ripple current
can be estimated as follows:
ICIN = IOUT ×
VOUT
V
× (1 − OUT )
VIN
VIN
(13)
The worst-case condition occurs at:
ICIN =
IOUT
2
(14)
For simplification, choose the input capacitor
whose RMS current rating is greater than half of
the maximum load current.
The input capacitance value determines the input
voltage ripple of the converter. If there is input
voltage ripple requirement in the system design,
choose the input capacitor that meets the
specification.
NB639 Rev.1.13
4/18/2012
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NB639 – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
The input voltage ripple can be estimated as
follows:
ΔVIN =
IOUT
V
V
× OUT × (1 − OUT )
FSW × CIN
VIN
VIN
(15)
The worst-case condition occurs at VIN = 2VOUT,
where:
ΔVIN =
IOUT
1
×
4 FSW × CIN
(16)
ΔVOUT =
Output Capacitor
The output capacitor is required to maintain the
DC output voltage. Ceramic or POSCAP
capacitors are recommended. The output voltage
ripple can be estimated as:
ΔVOUT =
VOUT
V
1
× (1 − OUT ) × (RESR +
) (17)
FSW × L
VIN
8 × FSW × COUT
Where RESR is the equivalent series resistance
(ESR) of the output capacitor.
In the case of ceramic capacitors, the impedance
at the switching frequency is dominated by the
capacitance. The output voltage ripple is mainly
caused by the capacitance. For simplification, the
output voltage ripple can be estimated as:
ΔVOUT =
VOUT
V
× (1 − OUT )
2
VIN
8 × FSW × L × COUT
(18)
The output voltage ripple caused by ESR is very
small. Therefore, an external ramp is needed to
stabilize the system. The voltage ramp is
expected to be around 30mV. The external ramp
can be generated through resistor R4 and
capacitor C4 using the following equation:
VRAMP =
(VIN − VOUT ) × TON
R4 × C4
In the case of POSCAP capacitors, the ESR
dominates the impedance at the switching
frequency. The ramp voltage generated from the
ESR is high enough to stabilize the system.
Therefore, an external ramp is not needed. A
minimum ESR value of 12mΩ is required to
ensure stable operation of the converter. For
simplification, the output ripple can be
approximated as:
(19)
VOUT
V
× (1 − OUT ) × RESR
FSW × L
VIN
(21)
Inductor
The inductor is required to supply constant
current to the output load while being driven by
the switching input voltage. A larger value
inductor will result in less ripple current that will
result in lower output ripple voltage. However, a
larger value inductor will have a larger physical
size, higher series resistance, and/or lower
saturation current. A good rule for determining
the inductor value is to allow the peak-to-peak
ripple current in the inductor to be approximately
30~40% of the maximum switch current limit.
Also, make sure that the peak inductor current is
below the maximum switch current limit. The
inductance value can be calculated as:
L=
VOUT
V
× (1 − OUT )
FSW × ΔIL
VIN
(22)
Where ΔIL is the peak-to-peak inductor ripple
current.
Choose an inductor that will not saturate under
the maximum inductor peak current. The peak
inductor current can be calculated as:
ILP = IOUT +
VOUT
V
× (1 − OUT )
2FSW × L
VIN
(23)
The C4 should be chosen so that it meets the
following condition:
1
1 R × R2
< ×( 1
)
(20)
2π × FSW × C4 5 R1 + R 2
NB639 Rev.1.13
4/18/2012
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NB639 – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
Table 1—Inductor Selection Guide
Part Number
Manufacturer
Inductance
(µH)
DCR
(mΩ)
Current
Rating (A)
Dimensions
L x W x H (mm3)
Switching
Frequency
(kHz)
PCMC-135T-R68MF
Cyntec
0.68
1.7
34
13.5 x 12.6 x 4.8
600
FDA1254-1R0M
TOKO
1
2
25.2
13.5 x 12.6 x 5.4
300~600
FDA1254-1R2M
TOKO
1.2
2.05
20.2
13.5 x 12.6 x 5.4
300~600
Table 4—700kHz, 12VIN
Typical Design Parameter Tables
The following tables include recommended
component values for typical output voltages
(1.05V, 1.2V, 1.8V, 2.5V, 3.3V) and switching
frequencies (300kHz, 500kHz, and 700kHz).
Refer to Tables 2-4 for design cases without
external ramp compensation and Tables 5-7 for
design cases with external ramp compensation.
External ramp is not needed when high-ESR
capacitors, such as electrolytic or POSCAPs are
used. External ramp is needed when low-ESR
capacitors, such as ceramic capacitors are used.
For cases not listed in this datasheet, a calculator
in excel spreadsheet can also be requested
through a local sales representative to assist with
the calculation.
Table 2—300kHz, 12VIN
VOUT
(V)
1.05
1.2
1.8
2.5
3.3
L
(μH)
2.2
2.2
2.2
2.2
2.2
R1
(kΩ)
12.1
12.1
19.6
30
40.2
R2
(kΩ)
43
24
15.8
14.7
13.3
RFREQ
(kΩ)
301
360
499
680
806
Table 3—500kHz, 12VIN
VOUT
(V)
1.05
1.2
1.8
2.5
3.3
L
(μH)
1
1
1
1
1
NB639 Rev.1.13
4/18/2012
R1
(kΩ)
12.1
12.1
19.6
30
40.2
R2
(kΩ)
43
24
15.8
14.7
13.3
RFREQ
(kΩ)
180
200
309
402
523
VOUT
(V)
1.05
1.2
1.8
2.5
3.3
L
(μH)
1
1
1
1
1
R1
(kΩ)
12.1
12.1
19.6
30
40.2
R2
(kΩ)
43
24
15.8
14.7
12.4
RFREQ
(kΩ)
120
140
210
309
402
Table 5—300kHz, 12VIN
VOUT
(V)
1.05
1.2
1.8
2.5
3.3
L
(μH)
2.2
2.2
2.2
2.2
2.2
R1
(kΩ)
12.1
12.1
19.6
30
40.2
R2
(kΩ)
43
24
15.2
14.7
13
R4
(kΩ)
330
330
499
499
604
C4
(pF)
220
220
220
220
220
RFREQ
(kΩ)
301
360
499
680
806
C4
(pF)
220
220
220
220
220
RFREQ
(kΩ)
180
196
309
402
522
C4
(pF)
220
220
220
220
220
RFREQ
(kΩ)
120
140
210
270
383
Table 6—500kHz, 12VIN
VOUT
(V)
1.05
1.2
1.8
2.5
3.3
L
(μH)
1
1
1
1
1
R1
(kΩ)
12.1
12.1
19.6
30
40.2
R2
(kΩ)
43
24
15.8
14.7
12
R4
(kΩ)
330
330
330
383
499
Table 7—700kHz, 12VIN
VOUT
(V)
1.05
1.2
1.8
2.5
3.3
L
(μH)
1
1
1
1
1
R1
(kΩ)
12.1
12.1
19.6
30
40.2
R2
(kΩ)
43
24
15.8
14.3
12
R4
(kΩ)
220
220
261
261
360
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NB639 – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL APPLICATION
Figure 11 — Typical Application Circuit with Low ESR Ceramic Capacitor
Figure 12 — Typical Application Circuit with No External Ramp
Figure 13 — Typical Application Circuit with Low ESR Ceramic Capacitor
and DC-Blocking Capacitor.
NB639 Rev.1.13
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NB639 – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
LAYOUT RECOMMENDATION
1. The high current paths (GND, IN, and SW)
should be placed very close to the device
with short, direct and wide traces.
2. Put the input capacitors as close to the IN
and GND pins as possible.
3. Put the decoupling capacitor as close to the
VCC and GND pins as possible.
4. Keep the switching node SW short and away
from the feedback network.
5. The external feedback resistors should be
placed next to the FB pin. Make sure that
there is no via on the FB trace.
6. Keep the BST voltage path (BST, CBST, and
SW) as short as possible.
7. Keep the bottom IN and SW pads connected
with large copper to achieve better thermal
performance.
8. Four-layer layout is strongly recommended to
achieve better thermal performance.
s
Inner1 Layer
R3
C3
2
1
3
AGND
FB
5
FREQ
6
4
EN
SS
PGOOD
C6
C6
R5
R3
R6
R3
D2
C6
GND
IN
IN
IN
SW
SW
PGND
PGND
PGND
PGND
PGND
PGND
16
13
15
12
14
11
Inner2 Layer
Top Layer
Bottom Layer
Figure 14—PCB Layout
NB639 Rev.1.13
4/18/2012
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NB639 – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
PACKAGE INFORMATION
QFN20 (3x4mm)
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
NB639 Rev. 1.13
4/18/2012
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19
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