Maxim MAX5820M Dual, 8-bit, low-power, 2-wire, serial voltage-output dac Datasheet

19-3538; Rev 0; 2/05
Dual, 8-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
The MAX5820 is a dual, 8-bit voltage-output, digital-toanalog converter (DAC) with an I 2 C*-compatible,
2-wire interface that operates at clock rates up to 400kHz.
The device operates from a single 2.7V to 5.5V supply
(115µA at VDD = 3.6V). A power-down mode decreases
current consumption to less than 1µA. The MAX5820 features three software-selectable power-down output
impedances: 100kΩ, 1kΩ, and high impedance. Other
features include internal precision rail-to-rail output
buffers and a power-on reset (POR) circuit that powers up
the DAC in the 100kΩ power-down mode.
The MAX5820 features a double-buffered I2C-compatible
serial interface that allows multiple devices to share a single bus. All logic inputs are CMOS-logic compatible and
buffered with Schmitt triggers, allowing direct interfacing
to optocoupled and transformer-isolated interfaces. The
MAX5820 minimizes digital noise feedthrough by disconnecting the clock (SCL) signal from the rest of the device
when an address mismatch is detected.
The MAX5820 is specified over the extended (-40°C to
+85°C) temperature range and is available in a small
8-pin µMAX ® package. Refer to the MAX5822 data
sheet for the 12-bit version and to the MAX5821 data
sheet for a 10-bit version.
Applications
Digital Gain and Offset Adjustments
Programmable Voltage and Current Sources
Features
♦ Ultra-Low Supply Current
115µA at VDD = 3.6V
135µA at VDD = 5.5V
♦ 300nA Low-Power Power-Down Mode
♦ Single 2.7V to 5.5V Supply Voltage
♦ Fast 400kHz I2C-Compatible 2-Wire
Serial Interface
♦ Schmitt-Trigger Inputs for Direct Interfacing
to Optocouplers
♦ Rail-to-Rail Output Buffer Amplifiers
♦ Three Software-Selectable Power-Down Output
Impedances
100kΩ, 1kΩ, and High Impedance
♦ Readback Mode for Bus and Data Checking
♦ Power-On Reset to Zero
♦ 8-Pin µMAX Package
Ordering Information
TEMP
RANGE
PART
PINPACKAGE
ADDRESS
MAX5820LEUA
-40°C to +85°C 8 µMAX
0111 00X
MAX5820MEUA
-40°C to +85°C 8 µMAX
1011 00X
Typical Operating Circuit
Programmable Attenuation
VCO/Varactor Diode Control
Low-Cost Instrumentation
VDD
VDD
Battery-Operated Instrumentation
µC
SDA
SCL
RP
RP
Pin Configuration
RS
TOP VIEW
SCL
RS
VDD
1
8
OUTB
GND
2
7
OUTA
ADD
3
6
REF
MAX5820
OUTA
REF
OUTB
RS
5
SDA
SDA
REF
µMAX
VDD
SCL
RS
SCL 4
VDD
SDA MAX5820
MAX5820
OUTA
OUTB
REF
µMAX is a registered trademark of Maxim Integrated Products, Inc.
*Purchase of I2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associate Companies, conveys a
license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the
I2C Standard Specification defined by Philips.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX5820
General Description
MAX5820
Dual, 8-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
ABSOLUTE MAXIMUM RATINGS
VDD, SCL, SDA to GND ............................................-0.3V to +6V
OUT_, REF, ADD to GND..............................-0.3V to VDD + 0.3V
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA = +70°C)
8-Pin µMAX (derate 4.5mW above +70°C) ...................362mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5kΩ, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are
at VDD = +5V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
±0.5
±1
LSB
±0.5
LSB
STATIC ACCURACY (NOTE 2)
Resolution
N
8
Integral Nonlinearity
INL
(Note 3)
Differential Nonlinearity
DNL
Guaranteed monotonic (Note 2)
Zero-Code Error
ZCE
Code = 00 hex, VDD = 2.7V
6
Zero-Code Error Tempco
Gain Error
40
GE
Code = FF hex
-0.8
PSRR
Code = FF hex, VDD = 4.5V to 5.5V
DC Crosstalk
mV
ppm/oC
2.3
Gain-Error Tempco
Power-Supply Rejection Ratio
Bits
-3
%FSR
0.26
ppm/oC
58.8
dB
30
µV
REFERENCE INPUT
Reference Input Voltage Range
VREF
0
Reference Input Impedance
65
Reference Current
Power-down mode
VDD
90
0.3
V
kΩ
1
µA
DAC OUTPUT
Output Voltage Range
No load (Note 4)
DC Output Impedance
Code = 80 hex
1.2
VDD = 5V, VOUT = full scale (short to GND)
42.2
VDD = 3V, VOUT = full scale (short to GND)
15.1
Short-Circuit Current
Wake-Up Time
0
VDD = 5V
8
VDD = 3V
8
Power-down mode = high impedance,
VDD = 5.5V, VOUT_ = VDD to GND
DAC Output Leakage Current
VDD
±0.1
V
Ω
mA
µs
±1
µA
DIGITAL INPUTS (SCL, SDA)
2
Input High Voltage
VIH
Input Low Voltage
VIL
0.7 x
VDD
_______________________________________________________________________________________
V
0.3 x
VDD
V
Dual, 8-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
(VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5kΩ, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are
at VDD = +5V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
0.05 x
VDD
Input Hysteresis
Input Leakage Current
V
±0.1
Digital inputs = 0 or VDD
Input Capacitance
UNITS
±1
6
µA
pF
DIGITAL OUTPUT (SDA)
Output Logic-Low Voltage
VOL
Tri-State Leakage Current
IL
ISINK = 3mA
±0.1
Digital inputs = 0 or VDD
Tri-State Output Capacitance
0.4
V
±1
µA
6
pF
0.5
V/µs
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
SR
Voltage-Output Settling Time
To 0.5 LSB code 40 hex to C0 hex or
C0 hex to 40 hex (Note 5)
Digital Feedthrough
Code = 00 hex, digital inputs from 0 to VDD
0.2
nV-s
Digital-to-Analog Glitch Impulse
Major carry transition (code = 7F hex to 80
hex and 80 hex to 7F hex)
12
nV-s
2.4
nV-s
4
DAC-to-DAC Crosstalk
12
µs
POWER SUPPLIES
Supply Voltage Range
VDD
Supply Current with No Load
IDD
Power-Down Supply Current
IDDPD
2.7
5.5
V
All digital inputs at 0 or VDD = 3.6V
115
205
All digital inputs at 0 or VDD = 5.5V
135
215
All digital inputs at 0 or VDD = 5.5V
0.3
1
µA
400
kHz
µA
TIMING CHARACTERISTICS (FIGURE 1)
Serial Clock Frequency
fSCL
0
Bus Free Time Between STOP
and START Conditions
tBUF
1.3
µs
tHD,STA
0.6
µs
tLOW
1.3
µs
µs
START Condition Hold Time
SCL Pulse-Width Low
SCL Pulse-Width High
tHIGH
0.6
Repeated START Setup Time
tSU,STA
0.6
Data Hold Time
tHD,DAT
0
Data Setup Time
tSU,DAT
100
µs
0.9
µs
ns
SDA and SCL Receiving
Rise Time
tr
(Note 5)
0
300
ns
SDA and SCL Receiving
Fall Time
tf
(Note 5)
0
300
ns
SDA Transmitting Fall Time
tf
(Note 5)
20 +
0.1Cb
250
ns
_______________________________________________________________________________________
3
MAX5820
ELECTRICAL CHARACTERISTICS (continued)
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5kΩ, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are
at VDD = +5V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
STOP Condition Setup Time
Cb
Maximum Duration of
Suppressed Pulse Widths
tSP
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
CONDITIONS
MIN
tSU,STO
Bus Capacitance
TYP
MAX
UNITS
400
pF
50
ns
0.6
µs
(Note 5)
0
All devices are 100% production tested at TA = +25°C and are guaranteed by design for TA = TMIN to TMAX.
Static specifications are tested with the output unloaded.
Linearity is guaranteed from codes 7 to 248.
Offset and gain error limit the FSR.
Guaranteed by design. Not production tested.
Typical Operating Characteristics
(VDD = +5V, RL = 5kΩ, TA = +25°C.)
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
0.75
1.25
MAX5820 toc02
1.25
MAX5820 toc01
1.00
INTEGRAL NONLINEARITY
vs. TEMPERATURE
1.00
MAX5820 toc03
INTEGRAL NONLINEARITY
vs. INPUT CODE
1.00
0
-0.25
-0.50
0.75
INL (LSB)
0.25
INL (LSB)
INL (LSB)
0.50
0.50
0.25
0.75
0.50
0.25
-0.75
0
-1.00
64
128
192
0
2.7
256
3.4
4.1
4.8
5.5
-40
-15
10
35
60
INPUT CODE
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
DIFFERENTIAL NONLINEARITY
vs. INPUT CODE
DIFFERENTIAL NONLINEARITY
vs. SUPPLY VOLTAGE
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE
0.75
0
-0.1
85
MAX5820 toc06
0
MAX5820 toc04
1.00
MAX5820 toc05
0
-0.1
0.50
0
-0.25
-0.50
-0.2
DNL (LSB)
0.25
DNL (LSB)
DNL (LSB)
MAX5820
Dual, 8-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
-0.3
-0.4
-0.2
-0.3
-0.4
-0.75
-0.5
-1.00
0
64
128
INPUT CODE
4
192
256
-0.5
2.7
3.4
4.1
SUPPLY VOLTAGE (V)
4.8
5.5
-40
-15
10
35
TEMPERATURE (°C)
_______________________________________________________________________________________
60
85
Dual, 8-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
ZERO-CODE ERROR
vs. TEMPERATURE
4
2
6
4
2
3.4
4.1
5.5
4.8
10
35
60
85
2.7
3.4
4.1
5.5
4.8
SUPPLY VOLTAGE (V)
GAIN ERROR vs. TEMPERATURE
DAC OUTPUT VOLTAGE
vs. OUTPUT SOURCE CURRENT (NOTE 6)
DAC OUTPUT VOLTAGE
vs. OUTPUT SINK CURRENT (NOTE 6)
-0.8
-0.4
4
3
2
2.0
1
-15
10
35
60
1.5
CODE = 40 hex
1.0
0.5
CODE = FF hex
NO LOAD
0
MAX5820 toc12
5
DAC OUTPUT VOLTAGE (V)
-1.2
2.5
MAX5820 toc11
MAX5820 toc10
6
DAC OUTPUT VOLTAGE (V)
0
85
0
0
2
4
6
8
10
0
2
4
6
OUTPUT SOURCE CURRENT (mA)
OUTPUT SINK CURRENT (mA)
SUPPLY CURRENT vs. INPUT CODE
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
140
120
100
160
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
160
140
120
102
153
INPUT CODE
204
256
160
140
120
CODE = FF hex
NO LOAD
NO LOAD
CODE = FF hex
100
51
180
MAX5820 toc15
180
MAX5820 toc13
180
10
8
TEMPERATURE (°C)
MAX5820 toc14
GAIN ERROR (%FSR)
-15
TEMPERATURE (°C)
-1.6
0
NO LOAD
0
-40
SUPPLY VOLTAGE (V)
-2.0
-40
-0.8
NO LOAD
0
2.7
-1.2
-0.4
NO LOAD
0
SUPPLY CURRENT (µA)
-1.6
GAIN ERROR (%FSR)
6
-2.0
MAX5820 toc08
8
ZERO-CODE ERROR (mV)
ZERO-CODE ERROR (mV)
8
GAIN ERROR vs. SUPPLY VOLTAGE
10
MAX5820 toc07
10
MAX5820 toc09
ZERO-CODE ERROR
vs. SUPPLY VOLTAGE
100
-40
-15
10
35
TEMPERATURE (°C)
60
85
2.7
3.4
4.1
4.8
5.5
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
5
MAX5820
Typical Operating Characteristics (continued)
(VDD = +5V, RL = 5kΩ, TA = +25°C.)
Typical Operating Characteristics (continued)
(VDD = +5V, RL = 5kΩ, TA = +25°C.)
POWER-DOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
POWER-UP GLITCH
MAX5820 toc16
ZOUT = HIGH IMPEDANCE
NO LOAD
400
300
EXITING SHUTDOWN
MAX5820 toc17
500
POWER-DOWN SUPPLY CURRENT (nA)
MAX5820
Dual, 8-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
MAX5820 toc18
5V
VDD
TA = -40°C
TA = +25°C
0
500mV/div
OUT_
200
10mV/div
OUT_
100
TA = +85°C
CLOAD = 200pF
CODE = 80 hex
0
2.7
3.4
4.1
100µs/div
2µs/div
MAJOR CARRY TRANSITION
(NEGATIVE)
SETTLING TIME
(POSITIVE)
5.5
4.8
SUPPLY VOLTAGE (V)
MAJOR CARRY TRANSITION
(POSITIVE)
MAX5820 toc19
MAX5820 toc20
5mV/div OUT_
OUT_
MAX5820 toc21
5mV/div OUT_
CLOAD = 200pF
RL = 5kΩ
CODE = 7F hex TO 80 hex
500mV/div
CLOAD = 200pF
RL = 5kΩ
CODE = 80 hex TO 7F hex
2µs/div
CLOAD = 200pF
CODE = 40 hex TO C0 hex
2µs/div
SETTLING TIME
(NEGATIVE)
2µs/div
DIGITAL FEEDTHROUGH
CROSSTALK
MAX5820 toc23
MAX5820 toc22
SCL
MAX5820 toc24
2V/div
VOUTA
2V/div
2mV/div
VOUTB
1mV/div
500mV/div
OUT_
OUT_
CLOAD = 200pF
fSCL = 12kHz
CODE = 00 hex
CLOAD = 200pF
CODE = C0 hex TO 40 hex
2µs/div
40µs/div
4µs/div
Note 6: The ability to drive loads greater than 5kΩ is not implied.
6
_______________________________________________________________________________________
Dual, 8-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
PIN
NAME
FUNCTION
1
VDD
Power Supply
2
GND
Ground
3
ADD
Address Select. A logic-high sets the address LSB to 1; a logic-low sets the address LSB to zero.
4
SCL
Serial Clock Input
5
SDA
Bidirectional Serial Data Interface
6
REF
Reference Input
7
OUTA
DAC A Output
8
OUTB
DAC B Output
Detailed Description
The MAX5820 is a dual, 8-bit, voltage-output DAC with
an I 2 C/SMBus™-compatible 2-wire interface. The
device consists of a serial interface, power-down circuitry, dual input and DAC registers, two 8-bit resistor
string DACs, two unity-gain output buffers, and output
resistor networks. The serial interface decodes the
address and control bits, routing the data to the proper
input or DAC register. Data can be directly written to
the DAC register, immediately updating the device output, or can be written to the input register without
changing the DAC output. Both registers retain data as
long as the device is powered.
DAC Operation
The MAX5820 uses a segmented resistor string DAC
architecture, which saves power in the overall system
and guarantees output monotonicity. The MAX5820’s
input coding is straight binary, with the output voltage
given by the following equation:
VOUT _ =
VREF × D
2N
where N = 8 (bits) and D = the decimal value of the
input code (0 to 255).
Output Buffer
The MAX5820 analog outputs are buffered by precision,
unity-gain followers that slew 0.5V/µs. Each buffer output
swings rail-to-rail, and is capable of driving 5kΩ in parallel
with 200pF. The output settles to ±0.5 LSB within 4µs.
Power-On Reset
The MAX5820 features an internal POR circuit that initializes the device upon power-up. The DAC registers
are set to zero scale and the device is powered down,
with the output buffers disabled and the outputs pulled
SMBus is a trademark of Intel Corporation.
to GND through the 100kΩ termination resistor.
Following power-up, a wake-up command must be initiated before any conversions are performed.
Power-Down Modes
The MAX5820 has three software-controlled low-power
power-down modes. All three modes disable the output
buffers and disconnect the DAC resistor strings from
REF, reducing supply current draw to 1µA and the reference current draw to less than 1µA. In power-down
mode 0, the device output is high impedance. In
power-down mode 1, the device output is internally
pulled to GND by a 1kΩ termination resistor. In powerdown mode 2, the device output is internally pulled to
GND by a 100kΩ termination resistor. Table 1 shows
the power-down mode command words.
Upon wake-up, the DAC output is restored to its previous value. Data is retained in the input and DAC registers during power-down mode.
Digital Interface
The MAX5820 features an I2C/SMBus-compatible 2wire interface consisting of a serial data line (SDA) and
a serial clock line (SCL). The MAX5820 is SMBus compatible within the range of VDD = 2.7V to 3.6V. SDA and
SCL facilitate bidirectional communication between the
MAX5820 and the master at rates up to 400kHz. Figure
1 shows the 2-wire interface timing diagram. The
MAX5820 is a transmit/receive slave-only device, relying upon a master to generate a clock signal. The master (typically a microcontroller) initiates data transfer on
the bus and generates SCL to permit that transfer.
A master device communicates to the MAX5820 by
transmitting the proper address followed by command
and/or data words. Each transmit sequence is framed
by a START (S) or REPEATED START (Sr) condition and
a STOP (P) condition. Each word transmitted over the
bus is 8 bits long and is always followed by an
acknowledge clock pulse.
_______________________________________________________________________________________
7
MAX5820
Pin Description
MAX5820
Dual, 8-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issuing a START condition. A START condition is a high-tolow transition on SDA with SCL high. A STOP condition
is a low-to-high transition on SDA, while SCL is high
(Figure 2). A START condition from the master signals
the beginning of a transmission to the MAX5820. The
master terminates transmission by issuing a not
acknowledge followed by a STOP condition (see the
Acknowledge Bit (ACK) section). The STOP condition
frees the bus. If a repeated START condition (Sr) is
generated instead of a STOP condition, the bus
remains active. When a STOP condition or incorrect
address is detected, the MAX5820 internally disconnects SCL from the serial interface until the next START
condition, minimizing digital noise and feedthrough.
Table 1. Power-Down Command Bits
POWER-DOWN
COMMAND BITS
MODE/FUNCTION
PD1
PD0
0
0
Power-up device. DAC output
restored to previous value.
0
1
Power-down mode 0. Power down
device with output floating.
1
0
Power-down mode 1. Power down
device with output terminated with
1kΩ to GND.
1
1
Power-down mode 2. Power down
device with output terminated with
100kΩ to GND.
The MAX5820 SDA and SCL drivers are open-drain outputs, requiring a pullup resistor to generate a logic high
voltage (see the Typical Operating Circuit). Series
resistors RS are optional. These series resistors protect
the input stages of the MAX5820 from high-voltage
spikes on the bus lines, and minimize crosstalk and
undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high are control signals (see the START
and STOP Conditions section). Both SDA and SCL idle
high when the I2C bus is not busy.
Early STOP Conditions
The MAX5820 recognizes a STOP condition at any
point during transmission except if a STOP condition
occurs in the same high pulse as a START condition
(Figure 3). This condition is not a legal I2C format; at
least one clock pulse must separate any START and
STOP conditions.
Repeated START Conditions
A repeated START (S r ) condition may indicate a
change of data direction on the bus. Such a change
occurs when a command word is required to initiate a
read operation. S r may also be used when the bus
master is writing to several I2C devices and does not
want to relinquish control of the bus. The MAX5820 serial interface supports continuous write operations with or
without an Sr condition separating them. Continuous
read operations require Sr conditions because of the
change in direction of data flow.
SDA
tSU, DAT
tBUF
tSU, STA
tHD, STA
tLOW
tHD, DAT
tSP
tSU, STO
SCL
tHIGH
tHD, STA
tR
tF
START CONDITION
REPEATED START CONDITION
STOP
CONDITION
Figure 1. 2-Wire Serial-Interface Timing Diagram
8
_______________________________________________________________________________________
START
CONDITION
Dual, 8-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
Sr
P
SCL
SDA
Figure 2. START and STOP Conditions
SCL
waits for a START condition followed by its slave
address. The serial interface compares each address
value bit-by-bit, allowing the interface to power down
immediately if an incorrect address is detected. The
LSB of the address word is the Read/Write (R/W) bit.
R/W indicates whether the master is writing to or reading from the MAX5820 (R/W = 0 selects the write condition, R/W = 1 selects the read condition). After
receiving the proper address, the MAX5820 issues an
ACK by pulling SDA low for one clock cycle.
The MAX5820 has four different factory/user-programmed addresses (Table 2). Address bits A6
through A1 are preset, while A0 is controlled by ADD.
Connecting ADD to GND sets A0 = 0. Connecting ADD
to V DD sets A0 = 1. This feature allows up to four
MAX5820s to share the same bus.
Table 2. MAX5820 I2C Slave Addresses
SDA
STOP
DEVICE ADDRESS
(A6–A0)
PART
VADD
MAX5820L
GND
0111 000
MAX5820L
VDD
0111 001
MAX5820M
GND
1011 000
MAX5820M
VDD
1011 001
START
LEGAL STOP CONDITION
SCL
SDA
START
ILLEGAL
STOP
ILLEGAL EARLY STOP CONDITION
Figure 3. Early STOP Conditions
Acknowledge Bit (ACK)
The acknowledge bit (ACK) is the ninth bit attached to
any 8-bit data word. ACK is always generated by the
receiving device. The MAX5820 generates an ACK
when receiving an address or data by pulling SDA low
during the ninth clock period. When transmitting data,
the MAX5820 waits for the receiving device to generate
an ACK. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer
occurs if a receiving device is busy or if a system fault
has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communication at a later time.
Slave Address
A bus master initiates communication with a slave
device by issuing a START condition followed by the 7bit slave address (Figure 4). When idle, the MAX5820
Write Data Format
In write mode (R/W = 0), data that follows the address
byte controls the MAX5820 (Figure 5). Bits C3–C0 configure the MAX5820 (Table 3). Bits D7–D0 are DAC
data. Bits S3–S0 are sub-bits and are always 0. Input
and DAC registers update on the falling edge of SCL
during the acknowledge bit. Should the write cycle be
prematurely aborted, data is not updated and the write
cycle must be repeated. Figure 6 shows two examplewrite data sequences.
Extended Command Mode
The MAX5820 features an extended command mode
that is accessed by setting C3–C0 = 1 and D7–D4 = 0.
S
A6
A5
A4
A3
A2
A1
R/W
A0
Figure 4. Slave-Address Byte Definition
C3
C2
C1
C0
D7
D6
D5
D4
Figure 5. Command-Byte Definition
_______________________________________________________________________________________
9
MAX5820
S
MAX5820
Dual, 8-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
MSB
S
LSB
A6
A5
A4
A3
A2
A1
A0
R/W
MSB
D3
MSB
ACK
C3
LSB
C2
C1
C0
D7
D6
D5
D4
ACK
LSB
D2
D1
D0
S3
S2
S1
S0
ACK
P
EXAMPLE-WRITE DATA SEQUENCE
MSB
S
LSB
A6
A5
A4
A3
A2
A1
A0
R/W
MSB
X
MSB
ACK
C3
LSB
C2
C1
C0
D7
D6
D5
D4
ACK
B
A
LSB
X
X
X
B
A
PD1
PD0
ACK
P
EXAMPLE-WRITE TO POWER-DOWN REGISTER SEQUENCE
Figure 6. Example-Write Command Sequences
The next command word writes to the power-down registers (Figure 7). Setting bits A or B to 1 sets that DAC
to the selected power-down mode based on the states
of PD0 and PD1 (Table 1). Any combination of the
DACs can be controlled with a single write sequence.
Read Data Format
In read mode (R/W = 1), the MAX5820 writes the contents of the DAC register to the bus. The direction of
data flow reverses following the address acknowledge
by the MAX5820. The device transmits the first byte of
data, waits for the master to acknowledge, then transmits the second byte. Figure 8 shows an example-read
data sequence.
I2C Compatibility
The MAX5820 is compatible with existing I2C systems.
SCL and SDA are high-impedance inputs; SDA has an
open drain that pulls the data line low during the ninth
clock pulse. The Typical Operating Circuit shows a typical I2C application. The communication protocol supports the standard I 2 C 8-bit communications. The
general call address is ignored. The MAX5820 address
is compatible with the 7-bit I2C addressing protocol
only. No 10-bit address formats are supported.
Digital-Feedthrough Suppression
When the MAX5820 detects an address mismatch, the
serial interface disconnects the SCL signal from the
core circuitry. This minimizes digital feedthrough
10
X
X
X
X
PD1
PD0
Figure 7. Extended Command Byte Format
caused by the SCL signal on a static output. The serial
interface reconnects the SCL signal once a valid
START condition is detected.
Applications Information
Digital Inputs and Interface Logic
The MAX5820 2-wire digital interface is I 2C/SMBus
compatible. The two digital inputs (SCL and SDA) load
the digital input serially into the DAC. Schmitt-trigger
buffered inputs allow slow-transition interfaces, such as
optocouplers to interface directly to the device. The
digital inputs are compatible with CMOS logic levels.
Power-Supply Bypassing and
Ground Management
Careful PC board layout is important for optimal system
performance. Keep analog and digital signals separate
to reduce noise injection and digital feedthrough. Use a
ground plane to ensure that the ground return from
GND to the power-supply ground is short and low
impedance. Bypass V DD with a 0.1µF capacitor to
ground as close to the device as possible.
______________________________________________________________________________________
Dual, 8-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
MAX5820
Table 3. Command Byte Definitions
SERIAL DATA INPUT
FUNCTION
C3
C2
C1
C0
D7
D6
D5
D4
0
0
0
0
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load DAC A input and DAC registers with new data.
Contents of DAC B input registers are transferred to the
DAC register. All outputs are updated.
0
0
0
1
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load DAC B input and DAC registers with new data.
Contents of DAC A input registers are transferred to the
DAC register. All outputs are updated.
0
1
0
0
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load DAC A input register with new data. DAC outputs
remain unchanged.
0
1
0
1
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load DAC B input register with new data. DAC outputs
remain unchanged.
1
0
0
0
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Data in all input registers is transferred to respective DAC
registers. All DAC outputs are updated simultaneously.
New data is loaded into DAC A input register.
1
0
0
1
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Data in all input registers is transferred to respective DAC
registers. All DAC outputs are updated simultaneously.
New data is loaded into DAC B input register.
1
1
0
0
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load all DACs with new data and update all DAC outputs
simultaneously. Both input and DAC registers are updated
with new data.
1
1
0
1
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load all input registers with new data. DAC outputs
remain unchanged.
1
1
1
0
X
X
X
X
Update all DAC outputs simultaneously. Device ignores
D7–D4. Do not send the data byte.
1
1
1
1
0
0
0
0
Extended command mode. The next word writes to the
power-down registers (see the Extended Command Mode
section).
1
1
1
1
0
0
0
1
Read DAC A data. The device expects an Sr condition
followed by an address word with R/W = 1.
1
1
1
1
0
0
1
0
Read DAC B data. The device expects an Sr condition
followed by an address word with R/W = 1.
______________________________________________________________________________________
11
MAX5820
Dual, 8-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
MSB
S
A6
LSB
A4
A5
A3
A2
A1
MSB
R/W
=0
A0
LSB
C3
ACK
C2
C1
C0
D7
D6
D5
D4
ACK
DATA BYTES GENERATED BY MASTER DEVICE
Sr
MSB
LSB
A6
R/W
=1
A4
A5
A3
A2
A1
A0
MSB
ACK
X
DATA BYTES GENERATED BY MAX5820
MSB
D3
LSB
X
PD1
PD0
D7
D6
D5
D4
ACK
ACK GENERATED BY
MASTER DEVICE
LSB
D2
D1
D0
S3
S2
S1
S0
ACK
P
Figure 8. Example-Read Word Data Sequence
Functional Diagram
REF
INPUT
REGISTER
A
MAX5820
8-BIT
DAC
A
MUX AND DAC
REGISTER
OUTA
RESISTOR
NETWORK
INPUT
REGISTER
B
8-BIT
DAC
B
MUX AND DAC
REGISTER
OUTB
RESISTOR
NETWORK
SERIAL
INTERFACE
SDA
ADD
SCL
POWER-DOWN
CIRCUITRY
VDD
GND
Chip Information
TRANSISTOR COUNT: 11,186
PROCESS: BiCMOS
12
______________________________________________________________________________________
Dual, 8-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
E
Ø0.50±0.1
8
INCHES
DIM
A
A1
A2
b
H
c
D
e
E
H
0.6±0.1
1
L
1
α
0.6±0.1
S
BOTTOM VIEW
D
MIN
0.002
0.030
MAX
0.043
0.006
0.037
0.014
0.010
0.007
0.005
0.120
0.116
0.0256 BSC
0.120
0.116
0.198
0.188
0.026
0.016
6∞
0∞
0.0207 BSC
8LUMAXD.EPS
4X S
8
MILLIMETERS
MAX
MIN
0.05
0.75
1.10
0.15
0.95
0.25
0.36
0.13
0.18
2.95
3.05
0.65 BSC
2.95
3.05
4.78
5.03
0.41
0.66
0∞
6∞
0.5250 BSC
TOP VIEW
A1
A2
e
A
c
b
α
L
SIDE VIEW
FRONT VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 8L uMAX/uSOP
APPROVAL
DOCUMENT CONTROL NO.
21-0036
REV.
J
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
MAX5820
Package Information