AD AD8051 Low cost, high speed, rail-to-rail amplifier Datasheet

Low Cost, High Speed,
Rail-to-Rail Amplifiers
AD8051/AD8052/AD8054
PIN CONNECTIONS (TOP VIEWS)
NC
7
+VS
+IN
3
6
VOUT
–VS 4
5
NC
NC = NO CONNECT
VOUT 1
–VS 2
–IN1
2
AD8052
–
+
+IN1 3
–
+
–VS 4
5 +VS
+ –
+IN 3
Figure 1. SOIC-8 (R)
OUT1 1
AD8051
01062-002
8
–IN 2
4 –IN
Figure 2. SOT-23-5 (RJ)
OUT D
OUT A 1
14
–IN A 2
13
–IN D
+IN A 3
12
+IN D
AD8054
8
+VS
V+ 4
11
V–
7
OUT
+IN B 5
10
+IN C
6
–IN2
–IN B 6
9
–IN C
5
+IN2
OUT B 7
8
OUT C
Figure 3. SOIC (R-8) and MSOP (RM-8)
01062-004
AD8051
NC 1
01062-003
High speed and fast settling on 5 V
110 MHz, −3 dB bandwidth (G = +1) (AD8051/AD8052)
150 MHz, −3 dB bandwidth (G = +1) (AD8054)
145 V/μs slew rate
50 ns settling time to 0.1%
Single-supply operation
Output swings to within 25 mV of either rail
Input voltage range: −0.2 V to +4 V; VS = 5 V
Video specifications (G = +2)
0.1 dB gain flatness: 20 MHz; RL = 150 Ω
Differential gain/phase: 0.03%/0.03°
Low distortion
−80 dBc total harmonic @ 1 MHz, RL = 100 Ω
Outstanding load drive capability
Drives 45 mA, 0.5 V from supply rails (AD8051/AD8052)
Drives 50 pF capacitive load (G = +1) (AD8051/AD8052)
Low power: 2.75 mA/amplifier (AD8054)
Low power: 4.4 mA/amplifier (AD8051/AD8052)
01062-001
FEATURES
Figure 4. SOIC (R-14) and TSSOP (RU-14)
APPLICATIONS
Active filters
A/D drivers
Consumer video
Professional cameras
CCD imaging systems
CD/DVD ROMs
Despite their low cost, the AD8051/AD8052/AD8054 provide
excellent overall performance and versatility. The output voltage
swings to within 25 mV of each rail, providing maximum output
dynamic range with excellent overdrive recovery.
The AD8051/AD8052/AD8054 are well suited for video
electronics, cameras, video switchers, or any high speed portable
equipment. Low distortion and fast settling make them ideal for
active filter applications.
5.0
4.5
4.0
3.5
VS = 5V
G = –1
RF = 2kΩ
RL = 2kΩ
3.0
2.5
2.0
1.5
1.0
0.5
0
0.1
1
FREQUENCY (MHz)
10
50
01062-005
The AD8051 (single), AD8052 (dual), and AD8054 (quad) are
low cost, high speed, voltage feedback amplifiers. The amplifiers
operate on +3 V, +5 V, or ±5 V supplies at low supply current.
They have true single-supply capability with an input voltage
range extending 200 mV below the negative rail and within 1 V
of the positive rail.
The AD8051/AD8052 in the 8-lead SOIC, the AD8052 in the
MSOP, the AD8054 in the 14-lead SOIC, and the 14-lead TSSOP
packages are available in the extended temperature range of
−40°C to +125°C.
PEAK-TO-PEAK OUTPUT VOLTAGE SWING
(THD ≤ 0.5%) (V)
GENERAL DESCRIPTION
Figure 5. Low Distortion Rail-to-Rail Output Swing
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD8051/AD8052/AD8054
TABLE OF CONTENTS
Features .............................................................................................. 1
Circuit Description .................................................................... 16
Applications....................................................................................... 1
Application Information................................................................ 17
General Description ......................................................................... 1
Overdrive Recovery ................................................................... 17
Pin Connections (Top Views) ......................................................... 1
Driving Capacitive Loads.......................................................... 17
Revision History ............................................................................... 2
Layout Considerations............................................................... 18
Specifications..................................................................................... 3
Active Filters ............................................................................... 18
Absolute Maximum Ratings............................................................ 9
A/D and D/A Applications ....................................................... 18
Maximum Power Dissipation ..................................................... 9
Sync Stripper ............................................................................... 19
ESD Caution.................................................................................. 9
Single-Supply Composite Video Line Driver ......................... 20
Typical Performance Characteristics ........................................... 10
Outline Dimensions ....................................................................... 21
Theory of Operation ...................................................................... 16
Ordering Guide .......................................................................... 22
REVISION HISTORY
5/06—Rev. F to Rev. G
Updated Format..................................................................Universal
Changes to Features, Applications, and General Description .....1
Changes to Figure 15...................................................................... 12
Changes to the Ordering Guide.................................................... 22
9/04—Rev. E to Rev. F
Changes to Ordering Guide .............................................................7
Changes to Figure 15...................................................................... 15
3/04—Rev. D to Rev. E
Changes to General Description .....................................................2
Changes to Specifications .................................................................3
Changes to Ordering Guide .............................................................6
2/03—Rev. C to Rev. D
Changes to General Description .....................................................1
Changes to Specifications.................................................................3
Changes to Absolute Maximum Ratings........................................6
1/03—Rev. B to Rev. C
Changes to General Description .....................................................1
Changes to Pin Connections............................................................1
Changes to Specifications.................................................................2
Changes to Absolute Maximum Ratings........................................9
Changes to Figure 2...........................................................................9
Changes to Ordering Guide .............................................................9
Updated Outline Dimensions........................................................20
Rev. G | Page 2 of 24
AD8051/AD8052/AD8054
SPECIFICATIONS
@ TA = 25°C, VS = 5 V, RL = 2 kΩ to 2.5 V, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Full Power Response
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion 1
Input Voltage Noise
Input Current Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Crosstalk
DC PERFORMANCE
Input Offset Voltage
Conditions
G = +1, VO = 0.2 V p-p
G = –1, +2, VO = 0.2 V p-p
G = +2, VO = 0.2 V p-p,
RL = 150 Ω to 2.5 V, RF = 806 Ω
for AD8051A/AD8052A
RF = 200 Ω for AD8054A
G = –1, VO = 2 V step
G = +1, VO = 2 V p-p
G = –1, VO = 2 V step
AD8051A/AD8052A
Min
Typ
Max
Min
70
110
50
20
80
100
145
35
50
140
fC = 5 MHz, VO = 2 V p-p, G = +2
f = 10 kHz
f = 10 kHz
G = +2, RL = 150 Ω to 2.5 V
RL = 1 kΩ to 2.5 V
G = +2, RL = 150 Ω to 2.5 V
RL = 1 kΩ to 2.5 V
f = 5 MHz, G = +2
−67
16
850
0.09
0.03
0.19
0.03
−60
1.7
TMIN − TMAX
Offset Drift
Input Bias Current
10
1.4
TMIN − TMAX
Input Offset Current
Open-Loop Gain
RL = 2 kΩ to 2.5 V
TMIN − TMAX
RL = 150 Ω to 2.5 V
TMIN − TMAX
86
76
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
VCM = 0 V to 3.5 V
72
RL = 10 kΩ to 2.5 V
RL = 2 kΩ to 2.5 V
0.1 to
4.9
0.3 to
4.625
RL = 150 Ω to 2.5 V
Output Current
Short-Circuit Current
Capacitive Load Drive
VOUT = 0.5 V to 4.5 V
TMIN − TMAX
Sourcing
Sinking
G = +1 (AD8051/AD8052)
G = +2 (AD8054)
Rev. G | Page 3 of 24
0.1
98
96
82
78
290
1.4
−0.2 to
+4
88
0.015 to
4.985
0.025 to
4.975
0.2 to
4.8
45
45
80
130
50
10
25
AD8054A
Typ
MHz
MHz
MHz
12
170
45
40
MHz
V/μs
MHz
MHz
−68
16
850
0.07
0.02
0.26
0.05
−60
dB
nV/√Hz
fA/√Hz
%
%
Degrees
Degrees
dB
15
2
82
74
70
0.125 to
4.875
0.55 to
4.4
Unit
150
60
1.7
2.5
3.25
0.75
Max
0.2
98
96
82
78
12
30
4.5
4.5
1.2
mV
mV
μV/°C
μA
μA
μA
dB
dB
dB
dB
300
1.5
−0.2 to
+4
86
kΩ
pF
V
0.03 to
4.975
0.05 to
4.95
0.25 to
4.65
30
30
45
85
V
40
dB
V
V
mA
mA
mA
mA
pF
pF
AD8051/AD8052/AD8054
Parameter
POWER SUPPLY
Operating Range
Quiescent Current/Amplifier
Power Supply Rejection Ratio
OPERATING TEMPERATURE RANGE
1
Conditions
AD8051A/AD8052A
Min
Typ
Max
Min
3
3
ΔVS = ±1 V
70
RJ-5
RM-8, R-8, RU-14, R-14
−40
−40
Refer to Figure 19.
Rev. G | Page 4 of 24
4.4
80
12
5
68
+85
+125
−40
AD8054A
Typ
2.75
80
Max
Unit
12
3.275
V
mA
dB
+125
°C
°C
AD8051/AD8052/AD8054
@ TA = 25°C, VS = 3 V, RL = 2 kΩ to 1.5 V, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Full Power Response
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion 1
Input Voltage Noise
Input Current Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Crosstalk
DC PERFORMANCE
Input Offset Voltage
Conditions
G = +1, VO = 0.2 V p-p
G = –1, +2, VO = 0.2 V p-p
G = +2, VO = 0.2 V p-p,
RL = 150 Ω to 2.5 V, RF = 402 Ω
for AD8051A/AD8052A
RF = 200 Ω for AD8054A
G = −1, VO = 2 V step
G = +1, VO = 1 V p-p
G = −1, VO = 2 V step
AD8051A/AD8052A
Min
Typ
Max
Min
70
110
50
17
80
90
135
65
55
110
fC = 5 MHz, VO = 2 V p-p,
G = −1, RL = 100 Ω to 1.5 V
f = 10 kHz
f = 10 kHz
G = +2, VCM = 1 V
RL = 150 Ω to 1.5 V
RL = 1 kΩ to 1.5 V
G = +2, VCM = 1 V
RL = 150 Ω to 1.5 V
RL = 1 kΩ to 1.5 V
f = 5 MHz, G = +2
10
150
85
55
MHz
V/μs
MHz
ns
–47
–48
dB
16
600
16
600
nV/√Hz
fA/√Hz
0.11
0.09
0.13
0.09
%
%
0.24
0.10
−60
0.3
0.1
−60
Degrees
Degrees
dB
1.6
10
1.3
RL = 2 kΩ
TMIN − TMAX
RL = 150 Ω
TMIN − TMAX
80
74
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
VCM = 0 V to 1.5 V
RL = 10 kΩ to 1.5 V
RL = 2 kΩ to 1.5 V
RL = 150 Ω to 1.5 V
Output Current
72
0.0.75 to
2.9
0.2 to
2.75
VOUT = 0.5 V to 2.5 V
TMIN − TMAX
Rev. G | Page 5 of 24
Unit
MHz
MHz
MHz
TMIN − TMAX
Input Offset Current
Open-Loop Gain
Max
135
65
TMIN − TMAX
Offset Drift
Input Bias Current
AD8054A
Typ
0.15
96
94
82
76
290
1.4
−0.2 to
+2
88
0.01 to
2.99
0.02 to
2.98
0.125 to
2.875
45
45
10
25
1.6
15
2
2.6
3.25
0.8
80
72
70
0.1 to
2.9
0.35 to
2.55
0.2
96
94
80
76
12
30
4.5
4.5
1.2
mV
mV
μV/°C
μA
μA
μA
dB
dB
dB
dB
300
1.5
−0.2 to
+2
86
kΩ
pF
V
0.025 to
2.98
0.35 to
2.965
0.15 to
2.75
25
25
V
dB
V
V
mA
mA
AD8051/AD8052/AD8054
Parameter
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current/Amplifier
Power Supply Rejection Ratio
OPERATING TEMPERATURE RANGE
1
Conditions
Sourcing
Sinking
G = +1 (AD8051/AD8052)
G = +2 (AD8054)
AD8051A/AD8052A
Min
Typ
Max
60
90
45
Min
AD8054A
Typ
30
50
Max
Unit
mA
mA
pF
pF
12
3.125
V
mA
dB
35
3
ΔVS = 0.5 V
68
RJ-5
RM-8, R-8, RU-14, R-14
−40
−40
Refer to Figure 19.
Rev. G | Page 6 of 24
4.2
80
12
4.8
3
68
+85
+125
−40
2.625
80
+125
°C
°C
AD8051/AD8052/AD8054
@ TA = 25°C, VS = ±5 V, RL = 2 kΩ to ground, unless otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Full Power Response
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
Input Voltage Noise
Input Current Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Crosstalk
DC PERFORMANCE
Input Offset Voltage
Conditions
G = +1, VO = 0.2 V p-p
G = –1, +2, VO = 0.2 V p-p
G = +2, VO = 0.2 V p-p,
RL = 150 Ω, RF = 1.1 kΩ
for AD8051A/AD8052A
RF = 200 Ω for AD8054A
G = −1, VO = 2 V step
G = +1, VO = 2 V p-p
G = −1, VO = 2 V step
AD8051A/AD8052A
Min
Typ
Max
Min
70
110
50
20
85
105
170
40
50
150
fC = 5 MHz, VO = 2 V p-p, G = +2
f = 10 kHz
f = 10 kHz
G = +2, RL = 150 Ω
RL = 1 kΩ
G = +2, RL = 150 Ω
RL = 1 kΩ
f = 5 MHz, G = +2
–71
16
900
0.02
0.02
0.11
0.02
–60
1.8
TMIN − TMAX
Offset Drift
Input Bias Current
10
1.4
TMIN − TMAX
Input Offset Current
Open-Loop Gain
RL = 2 kΩ
TMIN − TMAX
RL = 150 Ω
TMIN − TMAX
88
78
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
VCM = −5 V to +3.5 V
72
RL = 10 kΩ
RL = 2 kΩ
−4.85 to
+4.85
−4.45 to
+4.3
RL = 150 Ω
Output Current
Short-Circuit Current
Capacitive Load Drive
VOUT = −4.5 V to +4.5 V
TMIN − TMAX
Sourcing
Sinking
G = +1 (AD8051/AD8052)
G = +2 (AD8054)
Rev. G | Page 7 of 24
0.1
96
96
82
80
290
1.4
−5.2 to
+4
88
−4.98 to
+4.98
−4.97 to
+4.97
−4.6 to
+4.6
45
45
100
160
50
11
27
AD8054A
Typ
MHz
MHz
MHz
15
190
50
40
MHz
V/μs
MHz
MHz
–72
16
900
0.06
0.02
0.15
0.03
–60
dB
nV/√Hz
fA/√Hz
%
%
Degrees
Degrees
dB
15
2
84
76
70
−4.8 to
+4.8
−4.0 to
+3.8
Unit
160
65
1.8
2.6
3.5
0.75
Max
0.2
96
96
82
80
13
32
4.5
4.5
1.2
mV
mV
μV/°C
μA
μA
μA
dB
dB
dB
dB
300
1.5
−5.2 to
+4
86
kΩ
pF
V
−4.97 to
+4.97
−4.9 to
+4.9
−4.5 to
+4.5
30
30
60
100
V
40
dB
V
V
mA
mA
mA
mA
pF
pF
AD8051/AD8052/AD8054
Parameter
POWER SUPPLY
Operating Range
Quiescent Current/Amplifier
Power Supply Rejection Ratio
OPERATING TEMPERATURE RANGE
Conditions
AD8051A/AD8052A
Min
Typ
Max
Min
3
3
ΔVS = ±1
68
RJ-5
RM-8, R-8, RU-14, R-14
−40
−40
Rev. G | Page 8 of 24
4.8
80
12
5.5
68
+85
+125
−40
AD8054A
Typ
2.875
80
Max
Unit
12
3.4
V
mA
dB
+125
°C
°C
AD8051/AD8052/AD8054
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Supply Voltage
Internal Power Dissipation 1
SOIC Packages
SOT-23 Package
MSOP Package
TSSOP Package
Input Voltage (Common Mode)
Differential Input Voltage
Output Short-Circuit Duration
Storage Temperature Range (R)
Operating Temperature Range (A Grade)
Lead Temperature (Soldering 10 sec)
1
Specification is for device in free air:
8-Lead SOIC: θJA = 125°C/W
5-Lead SOT-23: θJA = 180°C/W
8-Lead MSOP: θJA = 150°C/W
14-Lead SOIC: θJA = 90°C/W
14-Lead TSSOP: θJA = 120°C/W.
Ratings
12.6 V
Observe Power
Derating Curves
Observe Power
Derating Curves
Observe Power
Derating Curves
Observe Power
Derating Curves
±VS
±2.5 V
Observe Power
Derating Curves
−65°C to +150°C
−40°C to +125°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD8051/AD8052/AD8054 is limited by the associated rise in
junction temperature. The maximum safe junction temperature
for plastic encapsulated devices is determined by the glass
transition temperature of the plastic, approximately 150°C.
Temporarily exceeding this limit can cause a shift in parametric
performance due to a change in the stresses exerted on the die
by the package. Exceeding a junction temperature of 175°C for
an extended period can result in device failure.
While the AD8051/AD8052/AD8054 are internally shortcircuit protected, this cannot be sufficient to guarantee that the
maximum junction temperature (150°C) is not exceeded under
all conditions. To ensure proper operation, it is necessary to
observe the maximum power derating curves.
SOIC-14
2.0
TSSOP-14
SOIC-8
1.5
1.0
MSOP-8
0.5
0
–55
SOT-23-5
–35
–15
5
15
35
55
75
95
AMBIENT TEMPERATURE (°C)
Figure 6. Maximum Power Dissipation vs.
Temperature for AD8051/AD8052/AD8054
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. G | Page 9 of 24
115
01062-006
MAXIMUM POWER DISSIPATION (W)
2.5
AD8051/AD8052/AD8054
TYPICAL PERFORMANCE CHARACTERISTICS
5
2
G = +5
RF = 2kΩ
–1
G = +1
RF = 0
G = +10
RF = 2kΩ
–3
–5
–6
–7
0.1
VS = 5V
GAIN AS SHOWN
RF AS SHOWN
RL = 2kΩ
VO = 0.2V p-p
1
10
FREQUENCY (MHz)
100
500
–4
G = +5
RF = 2kΩ
VS = +3V
4
GAIN (dB)
VS = ±5V
±5V
1
0
–5
–2
–6
–3
10
FREQUENCY (MHz)
100
500
+3V
+5V
–4
100k
01062-008
1
±5V
Figure 8. AD8051/AD8052 Gain vs. Frequency vs. Supply
4
2
3
VS = 5V
RL = 2kΩ TO 2.5V
CL = 5pF
G = +1
VO = 0.2V p-p
–40°C
2
0
1
GAIN (dB)
+85°C
–1
+25°C
–2
–3
100M
500M
+85°C
+25°C
–40°C
0
–1
–3
–4
100
500
–5
01062-009
10
FREQUENCY (MHz)
10M
FREQUENCY (Hz)
–2
VS = 5V
G = +1
RL = 2kΩ
VO = 0.2V p-p
TEMPERATURE AS SHOWN
1
1M
Figure 11. AD8054 Gain vs. Frequency vs. Supply
3
1
GAIN (dB)
+5V
2
–1
–7
0.1
500M
+3V
3
–3
–6
100M
G = +1
RL = 2kΩ
CL = 5pF
VO = 0.2V p-p
5
VS = +5V
–4
–5
10M
FREQUENCY (Hz)
Figure 10. AD8054 Normalized Gain vs. Frequency; VS = 5 V
–2
–4
1M
6
VS AS SHOWN
G = +1
RL = 2kΩ
VO = 0.2V p-p
–1
–7
0.1
G = +10
RF = 2kΩ
–3
–7
100k
0
GAIN (dB)
–2
–6
3
1
0
–1
–5
Figure 7. AD8051/AD8052 Normalized Gain vs. Frequency; VS = 5 V
2
1
01062-011
–4
2
G = +1
RF = 0
G = +2
RF = 2kΩ
1
10
FREQUENCY (MHz)
100
500
Figure 12. AD8054 Gain vs. Frequency vs. Temperature
Figure 9. AD8051/AD8052 Gain vs. Frequency vs. Temperature
Rev. G | Page 10 of 24
01062-012
–2
NORMALIZED GAIN (dB)
0
3
01062-007
NORMALIZED GAIN (dB)
1
VS = 5V
GAIN AS SHOWN
RF AS SHOWN
RL = 5kΩ
VO = 0.2V p-p
4
G = +2
RF = 2kΩ
01062-010
3
6.3
6.2
6.2
6.1
6.1
GAIN FLATNESS (dB)
6.3
5.9
5.8
5.7
5.3
0.1
5.7
5.5
5.4
100
1
10
FREQUENCY (MHz)
5.3
VS = +5V
VO = 2V p-p
8
6
6
5
5
GAIN (dB)
7
7
4
3
VS AS SHOWN
G = +2
RF = 2kΩ
RL = 2kΩ
VO AS SHOWN
–1
0.1
1
VS = ±5V
VO = 4V p-p
0
10
FREQUENCY (MHz)
100
500
VS AS SHOWN
G = +2
RF = 2kΩ
RL = 2kΩ
VO AS SHOWN
–1
0.1
1
10
FREQUENCY (MHz)
100
500
Figure 17. AD8054 Large Signal Frequency Response; G = +2
80
80
VS = 5V
RL = 2kΩ
70
60
20
PHASE
50° PHASE
MARGIN
–45
–90
10
0
–135
–10
–180
0.1
1
10
FREQUENCY (MHz)
100
500
OPEN-LOOP GAIN (dB)
0
PHASE MARGIN (Degrees)
GAIN
30
50
40
GAIN
180
30
20
PHASE
10
45° PHASE
MARGIN
0
–20
30k
Figure 15. AD8051/AD8052 Open-Loop Gain and Phase vs. Frequency
135
90
45
0
–10
01062-015
50
40
VS = 5V
RL = 2kΩ
CL = 5pF
70
60
OPEN-LOOP GAIN (dB)
VS = ±5V
VO = 4V p-p
3
1
Figure 14. AD8051/AD8052 Large Signal Frequency Response; G = +2
–20
0.01
100
VS = +5V
VO = 2V p-p
4
2
01062-014
GAIN (dB)
8
0
10
FREQUENCY (MHz)
9
9
1
1
Figure 16. AD8054 0.1 dB Gain Flatness vs. Frequency; G = +2
Figure 13. AD8051/AD8052 0.1 dB Gain Flatness vs. Frequency; G = +2
2
VS = 5V
RF = 200Ω
RL = 150Ω
G = +2
VO = 0.2V p-p
5.6
01062-017
5.4
5.8
PHASE MARGIN (Degrees)
5.5
VS = 5V
G = +2
RL = 150Ω
RF = 806Ω
VO = 0.2V p-p
5.9
100k
1M
10M
FREQUENCY (Hz)
100M
500M
01062-018
5.6
6.0
01062-016
6.0
01062-013
GAIN FLATNESS (dB)
AD8051/AD8052/AD8054
Figure 18. AD8054 Open-Loop Gain and Phase Margin vs. Frequency
Rev. G | Page 11 of 24
AD8051/AD8052/AD8054
VO = 2V p-p
1000
VS = 3V, G = –1
RF = 2kΩ, RL = 100Ω
–30
VOLTAGE NOISE (nA/√Hz)
VS = 5V, G = +2
RF = 2kΩ, RL = 100Ω
–40
VS = 5V, G = +1
RL = 100Ω
–50
–60
–70
–80
VS = 5V, G = +2
RF = 2kΩ, RL = 2kΩ
–90
VS = 5V, G = +1
RL = 2kΩ
VS = 5V
100
10
–110
1
2
3
4
5
6
FUNDAMENTAL FREQUENCY (MHz)
7
8 9 10
1
10
100
10M
Figure 22. Input Voltage Noise vs. Frequency
Figure 19. Total Harmonic Distortion
100
–30
VS = 5V
–40
CURRENT NOISE (pA/√Hz)
10MHz
–50
WORST HARMONIC (dBc)
1M
1k
10k
100k
FREQUENCY (Hz)
01062-022
–100
01062-019
TOTAL HARMONIC DISTORTION (dBc)
–20
–60
–70
–80
5MHz
–90
–100
1MHz
VS = 5V
RL = 2kΩ
G = +2
–110
–120
10
1
1.0
1.5 2.0
2.5 3.0 3.5
OUTPUT VOLTAGE (V p-p)
4.0
4.5
5.0
0.1
10
20
30
40
50
60
70
80
DIFFERENTIAL
GAIN ERROR (%)
90
100
RL = 1kΩ
RL = 150Ω
VS = 5V, G = +2
RF = 2kΩ, RL AS SHOWN
0
10
20
30
40
50
60
70
80
MODULATING RAMP LEVEL (IRE)
90
100
DIFFERENTIAL
PHASE ERROR (Degrees)
10
1M
10M
NTSC SUBSCRIBER (3.58MHz)
RL = 1kΩ
0.05
0.00
–0.05
–0.10
01062-021
DIFFERENTIAL
GAIN ERROR (%)
DIFFERENTIAL
PHASE ERROR (Degrees)
0
–0.05
–0.10
–0.15
–0.20
–0.25
RL = 1kΩ
VS = 5V, G = +2
RF = 2kΩ, RL AS SHOWN
0.10
0.05
0.00
0.10
RL = 150Ω
NTSC SUBSCRIBER (3.58MHz)
1k
10k
100k
FREQUENCY (Hz)
Figure 23. Input Current Noise vs. Frequency
Figure 20. Worst Harmonic vs. Output Voltage
0.10
0.08
0.06
0.04
0.02
0.00
–0.02
–0.04
–0.06
100
VS = 5V, G = +2
RF = 2kΩ, RL AS SHOWN
RL = 150Ω
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
0.3
0.2
0.1
RL = 1kΩ
0.0
–0.1
–0.2
–0.3
VS = 5V, G = +2
RF = 2kΩ, RL AS SHOWN
RL = 150Ω
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
MODULATING RAMP LEVEL (IRE)
Figure 24. AD8054 Differential Gain and Phase Errors
Figure 21. AD8051/AD8052 Differential Gain and Phase Errors
Rev. G | Page 12 of 24
01062-024
0.5
0
01062-020
–140
01062-023
–130
AD8051/AD8052/AD8054
–10
–10
VS = 5V
RF = 2kΩ
RL = 2kΩ
VO = 2V p-p
–20
–30
–40
–40
CROSSTALK (dB)
–50
–60
–70
–60
–70
–90
–90
10
FREQUENCY (MHz)
100
500
–110
0.1
01062-025
1
Figure 25. AD8052 Crosstalk (Output-to-Output) vs. Frequency
1
100
500
Figure 28. AD8054 Crosstalk (Output-to-Output) vs. Frequency
0
20
VS = 5V
10
0
–30
–10
–40
–20
–50
–60
–50
–60
–90
–70
500
–80
0.01
01062-026
100
+PSRR
–40
–80
1
10
FREQUENCY (MHz)
–PSRR
–30
–70
0.1
VS = 5V
0.1
100.000
500
70
VS =5V
G = +1
SETTLING TIME TO 0.1% (ns)
60
10.000
3.100
1.000
0.310
0.100
VS = 5V
G = –1
RL = 2kΩ
50
AD8051/AD8052
40
AD8054
30
20
10
1
10
FREQUENCY (MHz)
100
500
01062-027
0.031
0.010
0.1
100
Figure 29. PSRR vs. Frequency
Figure 26. CMRR vs. Frequency
31.000
1
10
FREQUENCY (MHz)
01062-029
PSRR (dB)
–20
–100
0.03
OUTPUT RESISTANCE (Ω)
10
FREQUENCY (MHz)
01062-028
–100
–100
0.1
CMRR (dB)
RL = 1kΩ
–80
–80
–10
RL = 100Ω
–50
Figure 27. Closed-Loop Output Resistance vs. Frequency
0
0.5
1.0
1.5
INPUT STEP (V p-p)
Figure 30. Settling Time vs. Input Step
Rev. G | Page 13 of 24
2.0
01062-030
CROSSTALK (dB)
–30
VS = ±5V
RF = 1kΩ
RL = AS SHOWN
VO = 2V p-p
–20
AD8051/AD8052/AD8054
1.000
VS = 5V
0.8
OUTPUT SATURATION VOLTAGE (V)
0.9
VOH = +85°C
VOH = +25°C
0.7
VOH = –40°C
VOL = +85°C
0.6
0.5
0.4
0.3
VOL = +25°C
0.2
VOL = –40°C
0.1
0
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85
LOAD CURRENT (mA)
100
90
RL = 150Ω
80
70
VS = 5V
0
0.5
1.0
1.5
2.0
2.5 3.0 3.5
OUTPUT VOLTAGE (V)
4.0
4.5
5.0
01062-032
OPEN-LOOP GAIN (dB)
RL = 2kΩ
60
0.750
Figure 32. Open-Loop Gain vs. Output Voltage
Rev. G | Page 14 of 24
+5V – VOH (+25°C)
0.625
+5V – VOH (–40°C)
0.500
0.375
0.250
VOL (+125°C)
0.125
0
Figure 31. AD8051/AD8052 Output Saturation Voltage vs. Load Current
+5V – VOH (+125°C)
0.875
VOL (–40°C)
0
3
6
9
VOL (+25°C)
12
15
18
21
LOAD CURRENT (mA)
24
27
30
Figure 33. AD8054 Output Saturation Voltage vs. Load Current
01062-033
VS = 5V
01062-031
OUTPUT SATURATION VOLTAGE (V)
1.0
AD8051/AD8052/AD8054
20ns
2.5
1V
Figure 34. 100 mV Step Response, G = +1
Figure 37. Output Swing; G = −1, RL = 2 kΩ
VS = 5V
G = +1
RL = 2kΩ
VS = 5V
G = +1
RL = 2kΩ
2.55
VOLTS
2.5
20ns
01062-035
50mV
50mV
Figure 35. AD8051/AD8052 200 mV Step Response; VS = 5 V, G = +1
Figure 38. AD8054 100 mV Step Response; VS = 5 V, G = +1
VIN = 1V p-p
G = +2
RL = 2kΩ
VS = 5V
VS = ±5V
G = +1
RL = 2kΩ
4
3
VOLTS
2
2.5
1
–1
–2
1.5
–3
0.5
500mV
20ns
–4
01062-036
VOLTS
40ns
01062-038
2.45
2.4
3.5
2.50
Figure 36. Large Signal Step Response; VS = 5 V, G = +2
1V
20ns
Figure 39. Large Signal Step Response; VS = ±5 V, G = +1
Rev. G | Page 15 of 24
01062-039
VOLTS
2.6
4.5
2µs
01062-037
VOLTS
1.5
20mV
VS = 5V
G = –1
RF = 2kΩ
RL = 2kΩ
5.0
01062-034
VOLTS
VIN = 0.1V p-p
G = +1
RL = 2kΩ
VS = 3V
AD8051/AD8052/AD8054
THEORY OF OPERATION
The AD8051/AD8052/AD8054 is fabricated on the Analog
Devices proprietary eXtra-Fast Complementary Bipolar (XFCB)
process, which enables the construction of PNP and NPN
transistors with similar fTs in the 2 GHz to 4 GHz region. The
process is dielectrically isolated to eliminate the parasitic and
latch-up problems caused by junction isolation. These features
allow the construction of high frequency, low distortion
amplifiers with low supply currents. This design uses a
differential output input stage to maximize bandwidth and
headroom (see Figure 40). The smaller signal swings required
on the first stage outputs (nodes SIP, SIN) reduce the effect of
nonlinear currents due to junction capacitances and improve
the distortion performance. This design achieves harmonic
distortion of −80 dBc @ 1 MHz into 100 Ω with VOUT = 2 V p-p
(Gain = +1) on a single 5 V supply.
The rail-to-rail output range of the AD8051/AD8052/AD8054
is provided by a complementary common-emitter output stage.
High output drive capability is provided by injecting all output
stage predriver currents directly into the bases of the output
devices Q8 and Q36. Biasing of Q8 and Q36 is accomplished by
I8 and I5, along with a common-mode feedback loop (not
shown). This circuit topology allows the AD8051/AD8052 to
drive 45 mA of output current and allows the AD8054 to drive
30 mA of output current with the outputs within 0.5 V of the
supply rails.
VCC
R26
I10
Q4
R39
I2
Q51
R23 R27
I5
Q21
Q2
R5
VOUT
Q27
C9
SIN
Q3
R21
Q8
Q11
Q24
R3
Q47
I11
I7
VEE
Rev. G | Page 16 of 24
VEE
C3
Q31
Q7
Q1
SIP
C7
Q39
Q23
Q22
VINN
The inputs of the device can handle voltages from −0.2 V below
the negative rail to within 1 V of the positive rail. Exceeding
these values will not cause phase reversal; however, the input
ESD devices will begin to conduct if the input voltages exceed
the rails by greater than 0.5 V. During this overdrive condition,
the output stays at the rail.
I9
Q50
Q36
Q5
VEE
Q13
Q25
Q40
R15 R2
VINP
I3
Figure 40. AD8051/AD8052 Simplified Schematic
I8
VCC
01062-045
CIRCUIT DESCRIPTION
AD8051/AD8052/AD8054
APPLICATION INFORMATION
OVERDRIVE RECOVERY
Overdrive of an amplifier occurs when the output and/or input
range is exceeded. The amplifier must recover from this
overdrive condition. As shown in Figure 41, the AD8051/
AD8052/AD8054 recovers within 60 ns from negative overdrive
and within 45 ns from positive overdrive.
VOLTS
2.55
2.50
2.45
2.40
VS = ±5V
G = +5
RF = 2kΩ
RL = 2kΩ
100ns
50mV
VOLTS
OUTPUT 2V/DIV
2.60
01062-042
INPUT 1V/DIV
VS = 5V
G = +1
RL = 2kΩ
CL = 50pF
Figure 43. AD8051/AD8052 200 mV Step Response: CL = 50 pF
10000
DRIVING CAPACITIVE LOADS
Consider the AD8051/AD8052 in a closed-loop gain of +1 with
+VS = 5 V and a load of 2 kΩ in parallel with 50 pF. Figure 42
and Figure 43 show their frequency and time domain responses,
respectively, to a small-signal excitation. The capacitive load
drive of the AD8051/AD8052/AD8054 can be increased by
adding a low value resistor in series with the load. Figure 44
and Figure 45 show the effect of a series resistor on the
capacitive drive for varying voltage gains. As the closed-loop
gain is increased, the larger phase margin allows for larger
capacitive loads with less peaking. Adding a series resistor with
lower closed-loop gains accomplishes the same effect. For large
capacitive loads, the frequency response of the amplifier will be
dominated by the roll-off of the series resistor and the load
capacitance.
RS = 0Ω
100
RG
1
RS
VIN
100mV
STEP
10
1
2
RF
VOUT
CL
50Ω
3
4
6
5
ACL (V/V)
01062-043
Figure 41. Overdrive Recovery
CAPACITIVE LOAD (pF)
100ns
RS = 3Ω
1000
Figure 44. AD8051/AD8052 Capacitive Load Drive vs. Closed-Loop Gain
8
6
1000
VS = 5V
≤ 30%
OVERSHOOT
CAPACITIVE LOAD (pF)
V/DIV AS SHOWN
01062-040
VS = 5V
≤ 30%
OVERSHOOT
RS = 10Ω
RS = 0Ω
100
RG
VIN
100mV
STEP
4
RF
RS
VOUT
CL
50Ω
–8
–10
–12
0.1
2
3
4
5
6
Figure 45. AD8054 Capacitive Load Drive vs. Closed-Loop Gain
–4
–6
1
ACL (V/V)
–2
VS = 5V
G = +1
RL = 2kΩ
CL = 50pF
VO = 200mV p-p
1
10
FREQUENCY (MHz)
100
500
Figure 42. AD8051/AD8052 Closed-Loop Frequency Response: CL = 50 pF
Rev. G | Page 17 of 24
01062-044
10
0
01062-041
GAIN (dB)
2
AD8051/AD8052/AD8054
R6
1kΩ
LAYOUT CONSIDERATIONS
C1
50pF
VIN
R1
3kΩ
2
1
R3
2kΩ
13
C2
50pF
6
7
R5
2kΩ
14
12
9
5
AD8054
8
10
AD8054
AD8054
BAND-PASS
FILTER OUTPUT
Figure 46. 2 MHz Biquad Band-Pass Filter Using AD8054
The frequency response of the circuit is shown in Figure 47.
0
–10
GAIN (dB)
The feedback resistor should be located close to the inverting
input pin to keep the parasitic capacitance at this node to a
minimum. Parasitic capacitance of less than 1 pF at the
inverting input can significantly affect high speed performance.
–20
–30
Stripline design techniques should be used for long signal traces
(greater than about 25 mm). These should be designed with a
characteristic impedance of 50 Ω or 75 Ω and be properly
terminated at each end.
10k
100k
1M
FREQUENCY (Hz)
10M
100M
01062-047
–40
ACTIVE FILTERS
Figure 47. Frequency Response of 2 MHz Band-Pass Biquad Filter
Active filters at higher frequencies require wider bandwidth op
amps to work effectively. Excessive phase shift produced by
lower frequency op amps can significantly affect active filter
performance.
Figure 46 shows an example of a 2 MHz biquad bandwidth filter
that uses three op amps of an AD8054. Such circuits are
sometimes used in medical ultrasound systems to lower the
noise bandwidth of the analog signal before A/D conversion.
Note that the unused amplifier’s inputs should be tied to
ground.
R4
2kΩ
3
The PCB should have a ground plane covering all unused
portions of the component side of the board to provide a low
impedance path. The ground plane should be removed from the
area near the input pins to reduce parasitic capacitance.
Chip capacitors should be used for supply bypassing. One end
should be connected to the ground plane and the other within
3 mm of each power pin. An additional large (4.7 μF to 10 μF)
tantalum electrolytic capacitor should be connected in parallel,
but not necessarily so close, to supply current for fast, large
signal changes at the output.
R2
2kΩ
01062-046
The specified high speed performance of the AD8051/AD8052/
AD8054 requires careful attention to board layout and
component selection. Proper RF design techniques and low
parasitic component selection are necessary.
A/D AND D/A APPLICATIONS
Figure 48 is a schematic showing the AD8051 used as a driver
for an AD9201, a 10-bit, 20 MSPS, dual A/D converter. This
converter is designed to convert I and Q signals in communications
systems. In this application, only the I channel is being driven.
The I channel is enabled by applying a logic high to SELECT
(Pin 13).
The AD8051 is running from a dual supply and is configured
for a gain of +2. The input signal is terminated in 50 Ω and the
output is 2 V p-p, which is the maximum input range of the
AD9201. The 22 Ω series resistor limits the maximum current
that flows and helps to lower the distortion of the A/D converter.
Rev. G | Page 18 of 24
AD8051/AD8052/AD8054
+5V
50Ω
2
10pF
22Ω
AD8051
22Ω
0.01µF
10µF
7
3
10pF
1kΩ
0.1µF
15
22Ω
0.1µF
6
10µF
1kΩ
4
0.1µF
10µF
10µF
–5V
+5V
0.1µF
10µF
INA-I
17
INB-I
18
REFT-I
D9 12
19
REFB-I
D8 11
20
AVSS
D7 10
21
REFSENSE
D6 9
22
VREF
D5 8
23
AVDD
24
REFB-Q
D2 5
25
REFT-Q
D1 4
26
INB-Q
AD9201
DATA OUT
D4 7
0.1µF
1kΩ
0.1µF
+VDD
SELECT 13
16
0.1µF
0.1µF
CLOCK 14
SLEEP
10µF
0.1µF
D3 6
0.1µF
D0 3
22Ω
10pF
22Ω
10pF
+5V
DVDD 2
0.1µF
DVSS 1
27
INA-Q
28
CHIP–SELECT
10µF
01062-048
0.33µF
Figure 48. The AD8051 Driving an AD9201, a 10-Bit, 20 MSPS A/D Converter
10
PART#
FUND
0
FUND 998.5kHz
–20
VIN
–0.51dB
–30
THD
–68.13
–40
SNR
54.97
–50
ENOB 8.80
–60
2ND
3RD
–80
4TH
5TH
6TH
7TH
8TH
9TH
–90
–100
–110
–120
0
1
2
3
4
5
6
7
FREQUENCY (MHz)
8
9
0
FFTSIZE 8192
–10
FCLK
20.0MHz
FUND
9.5MHz
–20
VIN
–0.44dB
–30
THD
–57.08
SNR
54.65
–40
–50
SINAD 52.69
ENOB 8.46
2ND
–60
–70
3RD
4TH
6TH
8TH
7TH
5TH
SFDR
60.18
2ND
–60.18
3RD
–60.23
–82.01
4TH
–90
5TH
6TH
–78.83
SFDR 71.66
–100
7TH
–77.28
2ND
–74.53
–110
8TH
–84.54
3RD
–76.06
9TH
–92.78
4TH
–76.35
–120
5TH
–79.05
6TH
–80.36
7TH
–75.08
8TH
–88.12
9TH
–77.87
SINAD 54.76
–70
PART#
FUND
0
–80
10
Figure 49. FFT Plot for AD8051 Driving the AD9201 at 1 MHz
With the sampling clock running at 20 MSPS, the A/D output
was analyzed with a digital analyzer. Two input frequencies
were used, 1 MHz and 9.5 MHz, which is just short of the
Nyquist frequency. These signals were well filtered to minimize
any harmonics.
0
1
2
3
4
5
6
7
FREQUENCY (MHz)
8
9
–81.28
10
Figure 50. FFT Plot for AD8051 Driving the AD9201 at 9.5 MHz
01062-049
AMPLITUDE (dB)
0
FFTSIZE 8192
FCLK 20.0MHz
–10
10
AMPLITUDE (dB)
The output of the op amp is ac-coupled into INA-I (Pin 16) via
two parallel capacitors to provide good high frequency and low
frequency coupling. The 1 kΩ resistor references the signal to
VREF that is applied to INB-I. Thus, INA-I swings both positive
and negative with respect to the bias voltage applied to INB-I.
Figure 49 shows the FFT response of the A/D for the case of a
1 MHz analog input. The SFDR is 71.66 dB, and the A/D is
producing 8.8 ENOB (effective number of bits). When the
analog frequency was raised to 9.5 MHz, the SFDR was reduced
to −60.18 dB and the A/D operated with 8.46 ENOBs as shown
in Figure 50. The inclusion of the AD8051 in the circuit did not
worsen the distortion performance of the AD9201.
01062-050
The AD9201 has differential inputs for each channel. These are
designated the A and B inputs. The B inputs of each channel are
connected to VREF (Pin 22), which supplies a positive reference
of 2.5 V. Each of the B inputs has a small low-pass filter that also
helps to reduce distortion.
SYNC STRIPPER
Synchronizing pulses are sometimes carried on video signals so
as not to require a separate channel to carry the synchronizing
information. However, for some functions, such as A/D
conversion, it is not desirable to have the sync pulses on the
video signal. These pulses reduce the dynamic range of the
video signal and do not provide any useful information for such
a function.
Rev. G | Page 19 of 24
AD8051/AD8052/AD8054
A sync stripper removes the synchronizing pulses from a video
signal while passing all the useful video information. Figure 51
shows a practical single-supply circuit that uses only a single
AD8051. It is capable of directly driving a reverse terminated
video line.
The worst case of composite video is not quite this demanding.
One bounding condition is a signal that is mostly black for an
entire frame but has a white (full amplitude) minimum width
spike at least once in a frame.
The other extreme is for a full white video signal. The blanking
intervals and sync tips of such a signal have negative-going
excursions in compliance with the composite video
specifications. The combination of horizontal and vertical
blanking intervals limit such a signal to being at the highest
(white) level for a maximum of about 75% of the time.
VIDEO WITHOUT SYNC
VIDEO WITH SYNC
VBLANK
GROUND
0.4V
GROUND
3V OR 5V
VIN
As a result of the duty cycles between the two extremes
previously presented, a 1 V p-p composite video signal that is
multiplied by a gain of 2 requires about 3.2 V p-p of dynamic
voltage swing at the output for an op amp to pass a composite
video signal of arbitrarily varying duty cycle without distortion.
+
10µF
7
3
AD8051
2
TO A/D
6
100Ω
4
R2
1kΩ
01062-051
R1
1kΩ
0.8V
(OR 2 × VBLANK )
Figure 51. Sync Stripper
The video signal plus sync is applied to the noninverting input
with the proper termination. The amplifier gain is set to 2 via
the two 1 kΩ resistors in the feedback circuit. A bias voltage
must be applied to R1 so that the input signal has the sync
pulses stripped at the proper level.
The blanking level of the input video pulse is the desired place
to remove the sync information. This level is multiplied by 2 by
the amplifier. This level must be at ground at the output for the
sync stripping action to take place. Since the gain of the amplifier
from the input of R1 to the output is −1, a voltage equal to 2 ×
VBLANK must be applied to make the blanking level come out at
ground.
SINGLE-SUPPLY COMPOSITE VIDEO LINE DRIVER
Many composite video signals have their blanking level at
ground and have video information that is both positive and
negative. Such signals require dual-supply amplifiers to pass
them. However, by ac level shifting, a single-supply amplifier
can be used to pass these signals. The following complications
can arise from such techniques.
Signals of bounded peak-to-peak amplitude that vary in duty
cycle require larger dynamic swing capacity than their
(bounded) peak-to-peak amplitude after they are ac-coupled.
As a worst case, the dynamic signal swing will approach twice
the peak-to-peak value. The two conditions that define the
maximum dynamic swing requirements are a signal that is
mostly low but goes high with a duty cycle that is a small
fraction of a percent, and the other extreme defined by the
opposite condition.
Some circuits use a sync tip clamp to hold the sync tips at a
relatively constant level to lower the amount of dynamic signal
swing required. However, these circuits can have artifacts, such
as sync tip compression, unless they are driven by a source with
a very low output impedance. The AD8051/AD8052/AD8054
have adequate signal swing when running on a single 5 V
supply to handle an ac-coupled composite video signal.
The input to the circuit in Figure 52 is a standard composite
(1 V p-p) video signal that has the blanking level at ground. The
input network level shifts the video signal by means of ac coupling.
The noninverting input of the op amp is biased to half of the
supply voltage.
The feedback circuit provides unity gain for the dc-biasing of
the input and provides a gain of 2 for any signals that are in the
video bandwidth. The output is ac-coupled and terminated to
drive the line.
The capacitor values were selected for providing minimum tilt
or field time distortion of the video signal. These values would
be required for video that is considered to be studio or broadcast
quality. However, if a lower consumer grade of video, sometimes
referred to as consumer video, is all that is desired, the values
and the cost of the capacitors can be reduced by as much as a
factor of five with minimum visible degradation in the picture.
5V
4.99kΩ
4.99kΩ
COMPOSITE
VIDEO
IN
RT
75Ω
47µF
+
+
10µF
0.1µF
7
3
AD8051
10kΩ
2
6
4
RF
1kΩ
+
10µF
1000µF
+
RBT
75Ω
0.1µF
VOUT
RG
1kΩ
220µF
Figure 52. Single-Supply Composite Video Line Driver
Rev. G | Page 20 of 24
RL
75Ω
01062-052
0.1µF
AD8051/AD8052/AD8054
OUTLINE DIMENSIONS
3.20
3.00
2.80
8.75 (0.3445)
8.55 (0.3366)
4.00 (0.1575)
3.80 (0.1496)
0.25 (0.0098)
0.10 (0.0039)
14
8
1
7
1.27 (0.0500)
BSC
SEATING
PLANE
8
3.20
3.00
2.80
0.50 (0.0197)
× 45°
0.25 (0.0098)
1.75 (0.0689)
1.35 (0.0531)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
6.20 (0.2441)
5.80 (0.2283)
5.15
4.90
4.65
5
1
4
PIN 1
0.65 BSC
0.95
0.85
0.75
8°
0.25 (0.0098) 0° 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
1.10 MAX
0.15
0.00
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.38
0.22
COPLANARITY
0.10
0.80
0.60
0.40
8°
0°
0.23
0.08
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 53. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-14)
Dimensions shown in millimeters and (inches)
Figure 55. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
2.90 BSC
5
8
4
4.00 (0.1574)
3.80 (0.1497) 1
2.80 BSC
1.60 BSC
1
2
1.27 (0.0500)
BSC
0.95 BSC
0.25 (0.0098)
0.10 (0.0040)
1.90
BSC
1.45 MAX
0.15 MAX
6.20 (0.2440)
4 5.80 (0.2284)
3
PIN 1
1.30
1.15
0.90
5
0.50
0.30
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
COPLANARITY
SEATING 0.31 (0.0122)
0.10
PLANE
0.22
0.08
10°
5°
0°
SEATING
PLANE
0.50 (0.0196)
× 45°
0.25 (0.0099)
8°
0.25 (0.0098) 0° 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.60
0.45
0.30
COMPLIANT TO JEDEC STANDARDS MO-178-AA
Figure 56. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
Figure 54. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
5.10
5.00
4.90
14
8
4.50
4.40
4.30
6.40
BSC
1
7
PIN 1
1.05
1.00
0.80
0.65
BSC
1.20
MAX
0.15
0.05
0.30
0.19
0.20
0.09
SEATING
COPLANARITY
PLANE
0.10
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 57. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
Rev. G | Page 21 of 24
0.75
0.60
0.45
AD8051/AD8052/AD8054
ORDERING GUIDE
Model
AD8051AR
AD8051AR-REEL
AD8051AR-REEL7
AD8051ARZ 1
AD8051ARZ-REEL1
AD8051ARZ-REEL71
AD8051ART-R2
AD8051ART-REEL
AD8051ART-REEL7
AD8051ARTZ-R21
AD8051ARTZ-REEL1
AD8051ARTZ-REEL71
AD8052AR
AD8052AR-REEL
AD8052AR-REEL7
AD8052ARZ1
AD8052ARZ-REEL1
AD8052ARZ-REEL71
AD8052ARM
AD8052ARM-REEL
AD8052ARM-REEL7
AD8052ARMZ1
AD8052ARMZ-REEL71
AD8054AR
AD8054AR-REEL
AD8054AR-REEL7
AD8054ARZ1
AD8054ARZ-REEL1
AD8054ARZ-REEL71
AD8054ARU
AD8054ARU-REEL
AD8054ARU-REEL7
AD8054ARUZ1
AD8054ARUZ-REEL1
AD8054ARUZ-REEL71
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
5-Lead SOT-23, 7" Tape and Reel
5-Lead SOT-23, 13" Tape and Reel
5-Lead SOT-23, 7" Tape and Reel
5-Lead SOT-23, 7" Tape and Reel
5-Lead SOT-23, 13" Tape and Reel
5-Lead SOT-23, 7" Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 7" Tape and Reel
14-Lead SOIC_N
14-Lead SOIC_N, 13" Tape and Reel
14-Lead SOIC_N, 7" Tape and Reel
14-Lead SOIC_N
14-Lead SOIC_N, 13" Tape and Reel
14-Lead SOIC_N, 7" Tape and Reel
14-Lead TSSOP
14-Lead TSSOP, 13" Tape and Reel
14-Lead TSSOP, 7" Tape and Reel
14-Lead TSSOP
14-Lead TSSOP, 13" Tape and Reel
14-Lead TSSOP, 7" Tape and Reel
Z = Pb-free part, # denotes lead-free product may be top or bottom marked.
Rev. G | Page 22 of 24
Package Option
R-8
R-8
R-8
R-8
R-8
R-8
RJ-5
RJ-5
RJ-5
RJ-5
RJ-5
RJ-5
R-8
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
RM-8
R-14
R-14
R-14
R-14
R-14
R-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
Branding
H2A
H2A
H2A
H06
H06
H06
H4A
H4A
H4A
H4A#
H4A#
AD8051/AD8052/AD8054
NOTES
Rev. G | Page 23 of 24
AD8051/AD8052/AD8054
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01062–0–5/06(G)
Rev. G | Page 24 of 24