ATMEL AT24C32D Ic-compatible (2-wire) serial eeprom Datasheet

AT24C32D
I2C-Compatible (2-Wire) Serial EEPROM
32-Kbit (4,096 x 8)
DATASHEET
Features
 Low-voltage and standard-voltage operation

VCC = 1.7V to 5.5V
 Internally organized as 4,096 x 8 (32K)
 I2C-compatible (2-Wire) serial interface
 Schmitt Trigger, filtered inputs for noise suppression
 Bidirectional data transfer protocol
 400kHz (1.7V) and 1MHz (2.5V, 2.7V, 5.0V) compatibility
 Write Protect pin for hardware protection
 32-byte Page Write mode

Partial Page Writes allowed
 Self-timed Write cycle (5ms max)
 High reliability


Endurance: 1,000,000 write cycles
Data retention: 100 years
 Lead-free/Halogen-free devices available
 Green package options (Pb/Halide-free/RoHS compliant)

8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, 8-pad XDFN, 5-lead SOT23,
5-ball WLCSP, and 8-ball VFBGA packages
 Die sale options: wafer form, waffle pack, and bumped wafers
Description
The Atmel® AT24C32D provides 32,768 bits of Serial Electrically Erasable and
Programmable Read-Only Memory (EEPROM) organized as 4,096 words of eight bits
each. The device’s cascading feature allows up to eight devices to share a common
2-wire bus. The device is optimized for use in many industrial and commercial
applications where low-power and low-voltage operation are essential. The devices are
available in space-saving 8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN,
8-pad XDFN, 5-lead SOT23, 5-ball WLCSP, and 8-ball VFBGA packages. In addition,
this device operates from 1.7V to 5.5V.
Atmel-8866A-SEEPROM-AT24C32D-Datasheet_082013
1.
Pin Configurations and Pinouts
Table 1-1.
Pin
Pin Configuration
Function
A0
Address Input
A1
Address Input
A2
Address Input
GND
Ground
SDA
Serial Data
SCL
Serial Clock Input
WP
Write Protect
VCC
Device Power Supply
Note:
When using the 5-lead SOT-23 or the
5-ball WLCSP, the software bits A2,
A1, and A0 must be set to Logic 0 to
properly communicate with the device.
8-lead SOIC
8-lead TSSOP
A0
1
8
VCC
A1
2
7
WP
A2
3
6
SCL
GND
4
5
SDA
A0
A1
A2
GND
1
8
2
7
3
6
4
5
VCC
WP
SCL
SDA
Top View
8-pad UDFN/XDFN
A0 1
8
VCC
A1 2
7
WP
A2 3
6
SCL
GND 4
5
SDA
5-lead SOT23
SCL
1
GND
2
SDA
3
Top View
SDA
SCL
WP
5
WP
4
VCC
Top View
5-ball WLCSP
GND
(1)
VCC
Ball Side View
(1)
8-ball VFBGA
VCC
8
1
A0
WP
7
2
A1
SCL
6
3
A2
SDA
5
4
GND
Bottom View
* Note: Drawings are not to scale
2.
Absolute Maximum Ratings*
Operating Temperature . . . . . . . . . . .−55°C to +125°C
Storage Temperature . . . . . . . . . . . −65°C to + 150°C
Voltage on any pin
with respect to ground . . . . . . . . . . . . . . − 1.0 V +7.0V
Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V
DC Output Current. . . . . . . . . . . . . . . . . . . . . . . 5.0mA
2
AT24C32D [DATASHEET]
Atmel-8866A-SEEPROM-AT24C32D-Datasheet_082013
*Notice: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions beyond those
indicated in the operational sections of this
specification are not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect device reliability.
3.
Block Diagram
VCC
GND
WP
Start
Stop
Logic
SDA
Serial
Control
Logic
LOAD
Device
Address
Comparator
A2
A1
A0
R/W
EN
H.V. Pump/Timing
COMP
LOAD
Data Word
Addr/Counter
Y DEC
Data Recovery
INC
X DEC
SCL
EEPROM
Serial MUX
DOUT/ACK
LOGIC
DIN
DOUT
4.
Pin Descriptions
Serial Clock (SCL): The SCL input is used to positive-edge clock data into each EEPROM device and negative-edge
clock data out of each device.
Serial Data (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open drain driven and may be
wire-ORed with any number of other open-drain or open-collector devices.
Device Addresses (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hard wired (directly to GND
or to VCC) for compatibility with other Atmel AT24C devices. When the pins are hard wired, as many as eight 32K devices
may be addressed on a single bus system. (Device addressing is discussed in detail in Section 7., “Device Addressing”
on page 9). A device is selected when a corresponding hardware and software match is true. If these pins are left
floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capacitive coupling that may
appear during customer applications, Atmel recommends always connecting the address pins to a known state. When
using a pull-up resistor, Atmel recommends using 10k or less.
Write Protect (WP): The Write Protect input, when connected to GND, allows normal write operations. When WP is
connected directly to VCC, all Write operations to the memory are inhibited. If the pin is left floating, the WP pin will be
internally pulled down to GND; however, due to capacitive coupling that may appear during customer applications, Atmel
recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using
10k or less.
Table 4-1.
Write Protect
WP Pin Status
Part of the Array Protected
At VCC
Full Array
At GND
Normal Read/Write Operations
AT24C32D [DATASHEET]
Atmel-8866A-SEEPROM-AT24C32D-Datasheet_082013
3
5.
Memory Organization
AT24C32D, 32K Serial EEPROM: The 32K is internally organized as 128 pages of 32-bytes each. Random word
addressing requires a 12-bit data word address.
Table 5-1.
Pin Capacitance(1)
Applicable over recommended operating range from: TA = 25°C, f = 1.0MHz, VCC = 5.5V
Symbol
Test Condition
CI/O
CIN
Note:
1.
Table 5-2.
Max
Units
Conditions
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
Input Capacitance (A0, A1, A2, and SCL)
6
pF
VIN = 0V
This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = 1.7V to 5.5V (unless otherwise noted).
Symbol
Parameter
VCC1
Supply Voltage
ICC1
Supply Current
VCC = 5.0V
Read at 400kHz
ICC2
Supply Current
VCC = 5.0V
Write at 400kHz
ISB1
Standby Current
ILI
Input Leakage
Current VCC = 5.0V
VIN = VCC or VSS
ILO
Output Leakage
Current VCC = 5.0V
VOUT = VCC or VSS
VIL
Input Low Level(1)
VIH
Input High Level((1)
VOL1
Output Low Level
VCC = 1.7V
VOL2
Output Low Level
VCC = 3.0V
Note:
4
1.
Test Condition
Min
Max
Units
5.5
V
0.4
1.0
mA
2.0
3.0
mA
1.0
μA
6.0
μA
0.10
3.0
μA
0.05
3.0
μA
-0.6
VCC x 0.3
V
VCC x 0.7
VCC + 0.5
V
IOL = 0.15mA
0.2
V
IOL = 2.1mA
0.4
V
1.7
VCC = 1.7V
VCC = 5.0V
VIN = VCC or VSS
VIL min and VIH max are reference only and are not tested.
AT24C32D [DATASHEET]
Atmel-8866A-SEEPROM-AT24C32D-Datasheet_082013
Typ
Table 5-3.
AC Characteristics (Industrial Temperature)
Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = 1.7V to 5.5V, CL = 100pF (unless
otherwise noted). Test conditions are listed in Note 2.
1.7V
Symbol
Parameter
Min
fSCL
Clock Frequency, SCL
tLOW
Clock Pulse Width Low
tHIGH
Clock Pulse Width High
2.5V, 5.0V
Max
Min
400
Max
Units
1000
kHz
1300
400
ns
600
400
ns
(1)
tI
Noise Suppression Time
100
tAA
Clock Low to Data Out Valid
tBUF
Time the bus must be free before a new transmission can start(1)
1300
500
ns
tHD.STA
Start Condition Hold Time
600
250
ns
tSU.STA
Start Condition Set-up Time
600
250
ns
tHD.DAT
Data In Hold Time
0
0
ns
tSU.DAT
Data In Set-up Time
100
100
ns
tR
Inputs Rise Time(1)
50
(1)
900
50
50
ns
550
ns
300
300
ns
300
100
ns
tF
Inputs Fall Time
tSU.STO
Stop Condition Set-up Time
600
250
ns
tDH
Data Out Hold Time
50
50
ns
tWR
Write Cycle Time
5
Endurance(1)
25°C, Page Mode, 3.3V
1,000,000
Notes: 1.
2.
5
ms
Write
Cycles
This parameter is ensured by characterization and is not 100% tested.
AC measurement conditions:

RL (connects to VCC): 1.3kΩ (2.5V, 5.5V), 10kΩ (1.7V)

Input pulse voltages: 0.3VCC to 0.7VCC

Input rise and fall times: ≤ 50ns

Input and output timing reference voltages: 0.5 x VCC
AT24C32D [DATASHEET]
Atmel-8866A-SEEPROM-AT24C32D-Datasheet_082013
5
6.
Device Operation
Clock and Data Transitions: The SDA pin is normally pulled high with an external device. Data on the SDA pin may
change only during SCL low time periods (See Figure 6-1). Data changes during SCL high periods will indicate a Start or
Stop condition as defined below.
Figure 6-1.
Data Validity
SDA
SCL
Data Stable
Data Stable
Data
Change
Start Condition: A high-to-low transition of SDA with SCL high is a Start condition that must precede every command
(See Figure 6-2).
Figure 6-2. Start Condition and Stop Condition Definition
SDA
SCL
Start
Condition
Stop
Condition
Stop Condition: A low-to-high transition of SDA with SCL high is a Stop condition. After a Read sequence, the Stop
condition will place the EEPROM in a standby power mode (See Figure 6-2).
Acknowledge: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
receiving device sends a zero during the ninth clock cycle to acknowledge that it has received each word. This zero
response is referred to as an Acknowledge (See Figure 6-6).
Standby Mode: AT24C32D features a low-power standby mode that is enabled upon power-up and after the receipt of
the Stop condition and the completion of any internal operations.
6
AT24C32D [DATASHEET]
Atmel-8866A-SEEPROM-AT24C32D-Datasheet_082013
Software Reset: After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset by
following these steps:
1.
Create a Start condition,
2.
Clock nine cycles,
3.
Create another Start condition followed by Stop condition as shown below.
The device is ready for next communication after above steps has been completed.
Figure 6-3. Software Reset
Dummy Clock Cycles
1
SCL
2
3
8
9
Start
Condition
Start
Condition
Stop
Condition
SDA
Figure 6-4. Bus Timing
tHIGH
tF
tR
tLOW
tLOW
SCL
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA In
tAA
tDH
tBUF
SDA Out
AT24C32D [DATASHEET]
Atmel-8866A-SEEPROM-AT24C32D-Datasheet_082013
7
Figure 6-5. Write Cycle Timing
SCL
SDA
8th Bit
ACK
WORDN
tWR
Start
Condition
Stop
Condition
Note:
1.
The Write cycle time tWR is the time from a valid Stop condition of a Write sequence to the end of
the internal Clear/Write cycle.
Figure 6-6. Output Acknowledge
1
SCL
8
9
Data In
Data Out
Start
Condition
8
(1)
AT24C32D [DATASHEET]
Atmel-8866A-SEEPROM-AT24C32D-Datasheet_082013
Acknowledge
7.
Device Addressing
The 32K EEPROM requires an 8-bit device address word following a Start condition to enable the chip for a Read or
Write operation. The device address word consists of a mandatory ‘1010’ sequence for the first four most significant
bits which is known as the device type identifier. These four bits are bit 7, bit 6, bit 5, and bit 4 as seen in Figure 7-1. This
is common to all 2-wire Serial EEPROM devices.
The next three bits are the A2, A1, and A0 hardware address select bits which allow as many as eight devices on the
same bus. These bits must compare to their corresponding hard wired input pins, A2, A1, and A0. The A2, A1, and A0 pins
use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.
When utilizing the 5-ball WLCSP or the 5-lead SOT-23 packages, the A2, A1, and A0 pins are not available. The A2, A1,
and A0 pins are internally pulled to ground and thus the A2, A1, and A0 device address bits must always be set to a
Logic 0 to communicate with the device. This condition is depicted in Figure 7-1 below.
The eighth bit of the device address is the Read/write operation select bit. A Read operation is initiated if this bit is a
Logic 1, and a Write operation is initiated if this bit is a Logic 0.
Upon a successful comparison of the device address, the EEPROM will output a zero during the following clock cycle. If
a compare is not made, the device will not acknowledge and will instead return to a standby state.
Figure 7-1. Device Addressing
Package
Device Type Identifier
Hardware Address Select Bits
R/W Select
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SOIC, TSSOP, UDFN,
XDFN, and VFBGA
1
0
1
0
A2
A1
A0
R/W
SOT-23 and WLCSP
1
0
1
0
0
0
0
R/W
MSB
LSB
Data Security:The AT24C32D has a hardware data protection scheme that allows the user to write protect the whole
memory when the WP pin is at VCC.
AT24C32D [DATASHEET]
Atmel-8866A-SEEPROM-AT24C32D-Datasheet_082013
9
8.
Write Operations
Byte Write: A Write operation requires two 8-bit data word addresses following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero then clock in the first
8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device, such as
a microcontroller, must then terminate the write sequence with a Stop condition. At this time, the EEPROM enters an
internally-timed Write cycle, tWR, to the nonvolatile memory (See Figure 6-5). All inputs are disabled during this Write
cycle and the EEPROM will not respond until the Write is complete (See Figure 8-1).
Figure 8-1. Byte Write
S
T
A
R
T
Device
Address
W
R
I
T
E
First
Word Address
Second
Word Address
S
T
O
P
Data
SDA Line
M
S
B
Note:
R A
/ C
W K
A
C
K
A
C
K
A
C
K
* = Don’t care bit.
Page Write: The 32K EEPROM is capable of 32-byte Page Writes.
A Page Write is initiated the same way as a Byte Write, but the microcontroller does not send a Stop condition after the
first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller
can transmit up to 31 more data words. The EEPROM will respond with a zero after each data word received. The
microcontroller must terminate the Page Write sequence with a Stop condition (See Figure 8-2).
Figure 8-2. Page Write
S
T
A
R
T
Device
Address
W
R
I
T
E
First
Word Address
Second
Word Address
Data (n)
S
T
O
P
Data (n + x)
SDA Line
M
S
B
Note:
R A
/ C
WK
A
C
K
A
C
K
A
C
K
A
C
K
* = Don’t care bit..
The data word address lower five bits are internally incremented following the receipt of each data word. The higher data
word address bits are not incremented, retaining the memory page row location. When the word address, internally
generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 32
data words are transmitted to the EEPROM, the data word address will roll-over and the previously loaded data will be
altered. The address roll-over during Write is from the last byte of the current page to the first byte of the same page.
Acknowledge Polling: Once the internally-timed Write cycle has started and the EEPROM inputs are disabled,
acknowledge polling can be initiated. This involves sending a Start condition followed by the device address word. The
Read/Write bit is representative of the operation desired. Only if the internal Write cycle has completed will the EEPROM
respond with a zero, allowing the Read or Write sequence to continue.
10
AT24C32D [DATASHEET]
Atmel-8866A-SEEPROM-AT24C32D-Datasheet_082013
9.
Read Operations
Read operations are initiated the same way as Write operations with the exception that the Read/Write select bit in the
device address word is set to one. There are three Read operations:

Current Address Read

Random Address Read

Sequential Read
Current Address Read: The internal data word address counter maintains the last address accessed during the last
Read or Write operation, incremented by one. This address stays valid between operations as long as the chip power is
maintained. The address roll-over during read is from the last byte of the last memory page, to the first byte of the first
page.
Once the device address with the Read/Write select bit set to one is clocked in and acknowledged by the EEPROM, the
current address data word is serially clocked out. The microcontroller does not respond with an zero but does generate a
Stop condition (See Figure 9-1).
Figure 9-1. Current Address Read
S
T
A
R
T
Device
Address
R
E
A
D
S
T
O
P
Data
SDA Line
M
S
B
N
O
R A
/ C
WK
A
C
K
Random Read: A Random Read requires a dummy Byte Write sequence to load in the data word address. Once the
device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must
generate another Start condition. The microcontroller now initiates a Current Address Read by sending a device address
with the Read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data
word. The microcontroller does not respond with a zero but does generate a Stop condition. (See Figure 9-2)
Figure 9-2. Random Read
S
T
A
R
T
Device
Address
W
R
I
T
E
First Word
Address
S
T
A
R
T
Second Word
Address
Device
Address
R
E
A
D
S
T
O
P
Data (n)
SDA LINE
M
S
B
R A
/ C
W K
A
C
K
Dummy Write
Note:
L A
S C
B K
R A
/ C
WK
N
O
A
C
K
* = Don’t care bit.
AT24C32D [DATASHEET]
Atmel-8866A-SEEPROM-AT24C32D-Datasheet_082013
11
Sequential Read: Sequential Reads are initiated by either a Current Address Read or a Random Address Read. After
the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an
acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the
memory address maximum address is reached, the data word address will roll-over and the Sequential Read will
continue from the beginning of the array. The Sequential Read operation is terminated when the microcontroller does not
respond with a zero but does generate a Stop condition (See Figure 9-3).
Figure 9-3. Sequential Read
S
T
A
R
T
W
R
I
T
E
Device
Address
First Word
Address
Second Word
Address
...
SDA LINE
R A
/ C
W K
M
S
B
L A
S C
B K
A
C
K
Dummy Write
S
T
A
R
T
Device
Address
R
E
A
D
Data (n)
Data (n + 1)
Data (n + 2)
S
T
O
P
Data (n + x)
...
R A
/ C
WK
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Note:
12
* = Don’t care bit.
AT24C32D [DATASHEET]
Atmel-8866A-SEEPROM-AT24C32D-Datasheet_082013
10.
Ordering Code Detail
AT2 4 C 3 2 D - S S H M - B
Atmel Designator
Shipping Carrier Option
B
T
Product Family
24C = Standard I2C Serial EEPROM
Device Density
32 = 32K
Device Revision
= Bulk (Tubes)
= Tape and Reel
Operating Voltage
M = 1.7V to 5.5V
Package Device Grade or
Wafer/Die Thickness
H
= Green, NiPdAu Lead Finish,
Industrial Temperature Range
(-40°C to +85°C)
U = Green, Matte Sn Lead Finish or
SnAgCu Solder Ball Finish,
Industrial Temperature Range
(-40°C to +85°C)
11 = 11mil Wafer Thickness
Package Option
SS
X
MA
ME
ST
U
C
WWU
WDT
= JEDEC SOIC
= TSSOP
= UDFN
= XDFN
= SOT23
= 5-ball, 3x3 Grid Array, WLCSP
= VFBGA
= Wafer Unsawn
= Die in Tape and Reel
AT24C32D [DATASHEET]
Atmel-8866A-SEEPROM-AT24C32D-Datasheet_082013
13
11.
Part Markings
AT24C32D: Package Marking Information
8-lead TSSOP
8-lead SOIC
ATHYWW
###% @
AAAAAAA
ATMLHYWW
###%
@
AAAAAAAA
5-lead SOT-23
8-pad UDFN
8-pad XDFN
2.0 x 3.0 mm Body
1.8 x 2.2 mm Body
###
H%@
YXX
###
YXX
8-ball VFBGA
5-ball WLCSP
1.5 x 2.0 mm Body
###%U
YMXX
Note 1:
Top Mark
%U
###
YXX
Bottom Mark
###U
YMXX
PIN 1
designates pin 1
Note 2: Package drawings are not to scale
Catalog Number Truncation
AT24C32D
Truncation Code ###: 32D
Date Codes
Y = Year
2: 2012
3: 2013
4: 2014
5: 2015
Voltages
6: 2016
7: 2017
8: 2018
9: 2019
M = Month
A: January
B: February
...
L: December
WW = Work Week of Assembly
02: Week 2
04: Week 4
...
52: Week 52
Country of Assembly
Lot Number
@ = Country of Assembly
AAA...A = Atmel Wafer Lot Number
Trace Code
% = Minimum Voltage
M: 1.7V min
Grade/Lead Finish Material
H: Industrial/NiPdAu
U: Industrial/Matte Tin/SnAgCu
Atmel Truncation
XX = Trace Code (Atmel Lot Numbers Correspond to Code)
Example: AA, AB.... YZ, ZZ
AT: Atmel
ATM: Atmel
ATML: Atmel
3/19/13
TITLE
Package Mark Contact:
[email protected]
14
24C32DSM, AT24C32D Package Marking Information
AT24C32D [DATASHEET]
Atmel-8866A-SEEPROM-AT24C32D-Datasheet_082013
DRAWING NO.
REV.
24C32DSM
A
12.
Ordering Codes
12.1
AT24C32D Ordering Information
Ordering Code
Lead Finish
Package
Voltage
Operating Range
1.7V to 5.5V
Industrial Temperature
(−40°C to 85°C)
AT24C32D-SSHM-B(1)
8S1
AT24C32D-SSHM-T(2)
AT24C32D-XHM-B(1)
(2)
AT24C32D-XHM-T
NiPdAu
(Lead-free/Halogen-free)
AT24C32D-MAHM-T(2)
8MA2
AT24C32D-MEHM-T(2)
AT24C32D-STUM-T(2)
AT24C32D-UUM-T(2)
AT24C32D-CUM-T(2)
8ME1
Matte Tin
(Lead-free/Halogen-free)
SnAgCu
(Lead-free/Halogen-free)
AT24C32D-WWU11M(3)
Notes: 1.
3.
—
5TS1
5U-3
8U2-1
Wafer Sale
Bulk delivery in tubes:

2.
8X
SOIC and TSSOP = 100 per tube
Tape and reel delivery:

SOIC = 4k per reel

TSSOP, UDFN, XDFN, SOT23, WLCSP, and VFBGA = 5k per reel
Contact Atmel Sales for Wafer sales.
Package Type
8S1
8-lead, 0.150” wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8X
8-lead, 4.40mm body, Plastic Thin Shrink Small Outline (TSSOP)
8MA2
8-pad, 2.00mm x 3.00mm body, 0.50mm pitch, Dual No Lead (UDFN)
8ME1
8-pad, 1.80mm x 2.20mm body, 0.40mm pitch, Extra Thin DFN (XDFN)
5TS1
5-lead, 2.90mm x 1.60mm Plastic Think Shrink Small Outline (SOT23)
5U-3
5-ball, 3x3 Grid Array, Wafer Level Chip Scale (WLCSP)
8U2-1
8-ball, Die Ball Grid Array (VFBGA)
AT24C32D [DATASHEET]
Atmel-8866A-SEEPROM-AT24C32D-Datasheet_082013
15
13.
Packaging Information
13.1
8S1 — 8-lead JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
D
SIDE VIEW
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
SYMBOL MIN
A
1.35
NOM
MAX
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.05
E1
3.81
–
3.99
E
5.79
–
6.20
e
NOTE
1.27 BSC
L
0.40
–
1.27
Ø
0°
–
8°
6/22/11
Package Drawing Contact:
[email protected]
16
TITLE
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
AT24C32D [DATASHEET]
Atmel-8866A-SEEPROM-AT24C32D-Datasheet_082013
GPC
SWB
DRAWING NO.
REV.
8S1
G
13.2
8X — 8-lead TSSOP
C
1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
A
b
A1
e
A2
MIN
NOM
MAX
A
-
-
1.20
A1
0.05
-
0.15
A2
0.80
1.00
1.05
D
2.90
3.00
3.10
E1
4.30
4.40
4.50
3, 5
b
0.19
–
0.30
4
SYMBOL
D
Side View
Notes:
COMMON DIMENSIONS
(Unit of Measure = mm)
1. This drawing is for general information only.
Refer to JEDEC Drawing MO-153, Variation AA, for proper
dimensions, tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25mm
(0.010in) per side.
4. Dimension b does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.08mm total in excess
of the b dimension at maximum material condition. Dambar
cannot be located on the lower radius of the foot. Minimum
space between protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
E
NOTE
2, 5
6.40 BSC
e
0.65 BSC
L
0.45
0.60
0.75
L1
1.00 REF
C
0.09
-
0.20
6/22/11
TITLE
Package Drawing Contact:
[email protected]
8X, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP)
GPC
TNR
DRAWING NO.
8X
AT24C32D [DATASHEET]
Atmel-8866A-SEEPROM-AT24C32D-Datasheet_082013
REV.
D
17
13.3
8MA2 — 8-pad UDFN
E
1
8
Pin 1 ID
2
7
3
6
4
5
D
C
A2
A
A1
E2
COMMON DIMENSIONS
(Unit of Measure = mm)
b (8x)
8
1
7
2
Pin#1 ID
6
D2
3
5
4
e (6x)
K
L (8x)
SYMBOL
MIN
NOM
MAX
D
1.90
2.00
2.10
E
2.90
3.00
3.10
D2
1.40
1.50
1.60
E2
1.20
1.30
1.40
A
0.50
0.55
0.60
A1
0.0
0.02
0.05
A2
–
–
0.55
C
L
NOTE
0.152 REF
0.30
e
0.35
0.40
0.50 BSC
b
0.18
0.25
0.30
K
0.20
–
–
3
9/6/12
Package Drawing Contact:
[email protected]
18
TITLE
8MA2, 8-pad, 2 x 3 x 0.6 mm Body, Thermally
Enhanced Plastic Ultra Thin Dual Flat No
Lead Package (UDFN)
AT24C32D [DATASHEET]
Atmel-8866A-SEEPROM-AT24C32D-Datasheet_082013
GPC
YNZ
DRAWING NO.
8MA2
REV.
C
13.4
8ME1 — 8-pad XDFN
D
7
8
6
5
E
PIN #1 ID
2
1
3
4
A1
Top View
A
Side View
e1
b
L
COMMON DIMENSIONS
(Unit of Measure = mm)
0.10
PIN #1 ID
0.15
b
e
End View
SYMBOL
MIN
NOM
MAX
A
–
–
0.40
A1
0.00
–
0.05
D
1.70
1.80
1.90
E
2.10
2.20
2.30
b
0.15
0.20
0.25
e
0.40 TYP
e1
1.20 REF
L
0.26
0.30
NOTE
0.35
9/10/2012
Package Drawing Contact:
[email protected]
TITLE
GPC
DRAWING NO.
REV.
8ME1, 8-pad (1.80mm x 2.20mm body) Extra Thin DFN
(XDFN)
DTP
8ME1
B
AT24C32D [DATASHEET]
Atmel-8866A-SEEPROM-AT24C32D-Datasheet_082013
19
13.5
5TS1 — 5-lead SOT23
e1
C
4
5
E1
C
L
E
L1
1
3
2
END VIEW
TOP VIEW
b
A2
SEATING
PLANE
e
A
A1
D
SIDE VIEW
COMMON DIMENSIONS
(Unit of Measure = mm)
1. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash,
protrusions or gate burrs shall not exceed 0.15 mm per end. Dimension E1 does
not include interlead flash or protrusion. Interlead flash or protrusion shall not
exceed 0.15 mm per side.
2. The package top may be smaller than the package bottom. Dimensions D and E1
are determined at the outermost extremes of the plastic body exclusive of mold
flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch
between the top and bottom of the plastic body.
3. These dimensions apply to the flat section of the lead between 0.08 mm and 0.15
mm from the lead tip.
4. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion
shall be 0.08 mm total in excess of the "b" dimension at maximum material
condition. The dambar cannot be located on the lower radius of the foot. Minimum
space between protrusion and an adjacent lead shall not be less than 0.07 mm.
This drawing is for general information only. Refer to JEDEC
Drawing MO-193, Variation AB for additional information.
SYMBOL
MIN
A
A1
A2
c
D
E
E1
L1
e
e1
b
0.00
0.70
0.08
NOM
0.90
2.90 BSC
2.80 BSC
1.60 BSC
0.60 REF
0.95 BSC
1.90 BSC
0.30
-
MAX
1.00
0.10
1.00
0.20
0.50
NOTE
3
1,2
1,2
1,2
3,4
5/31/12
Package Drawing Contact:
[email protected]
20
TITLE
GPC
5TS1, 5-lead 1.60mm Body, Plastic Thin
Shrink Small Outline Package (Shrink SOT)
TSZ
AT24C32D [DATASHEET]
Atmel-8866A-SEEPROM-AT24C32D-Datasheet_082013
DRAWING NO.
5TS1
REV.
D
13.6
5U-3 — 5-ball, WLCSP
TOP VIEW
Pin 1
2
1
BALL SIDE
3
2
3
-B-
Pin 1
1
d1
A
A
E
B
e1
B
C
d
C
Øb
D
-A0.03 (4X)
e2
j
n 0.015m
n 0.05 m
C
C A B
SIDE VIEW
d
-C0.03 C
A2
A
A1
PIN ASSIGNMENT MATRIX
COMMON DIMENSIONS
(Unit of Measure = mm)
1
2
3
SYMBOL
MIN
TYP
MAX
A
GND
n/a
SDA
A
0.270
0.309
0.348
B
n/a
SCL
n/a
C
WP
n/a
Vcc
A1
0.078
-
0.139
A2
0.175
0.200
0.225
E
Contact Atmel for details
e1
0.529
e2
0.400
D
Contact Atmel for details
d1
0.600
b
NOTE
0.148
0.168
0.188
7/25/13
Package Drawing Contact:
[email protected]
TITLE
GPC
DRAWING NO.
REV.
5U-3, 5-ball Wafer Level Chip Scale Package
(WLCSP) - AT24C32D
GCQ
5U-3
A
AT24C32D [DATASHEET]
Atmel-8866A-SEEPROM-AT24C32D-Datasheet_082013
21
13.7
8U2-1 — 8-ball VFBGA
f 0.10 C
d 0.10
A1 BALL
PAD
CORNER
(4X)
d 0.08 C
C
A
D
A1 BALL PAD CORNER
2
1
Øb
A
j n0.15 m C A B
j n0.08 m C
B
e
E
C
D
(e1)
A1
B
d
A2
(d1)
A
TOP VIEW
BOTTOM VIEW
SIDE VIEW
8 SOLDER BALLS
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
Notes:
1. This drawing is for general information.
2. Dimension 'b' is measured at the maximum solder ball diameter.
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
A
A1
A2
b
D
E
e
e1
d
d1
MIN
0.81
0.15
0.40
0.25
NOM
0.91
0.20
0.45
0.30
2.35 BSC
3.73 BSC
0.75 BSC
0.74 REF
0.75 BSC
0.80 REF
MAX
NOTE
1.00
0.25
0.50
0.35
3/20/12
TITLE
Package Drawing Contact:
[email protected]
22
8U2-1, 8-ball, 2.35 x 3.73 mm Body, 0.75 mm pitch,
VFBGA Package
AT24C32D [DATASHEET]
Atmel-8866A-SEEPROM-AT24C32D-Datasheet_082013
GPC
DRAWING NO.
GWW
8U2-1
REV.
F
14.
Revision History
Doc. Rev.
Date
Comments
Split AT24C32D from AT24C64D due to growing differences in package offerings.
8866A
08/2013
Add 5-ball WLCSP package.
Update template and Atmel logos.
AT24C32D [DATASHEET]
Atmel-8866A-SEEPROM-AT24C32D-Datasheet_082013
23
XXXXXX
Atmel Corporation
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T: (+1)(408) 441.0311
F: (+1)(408) 436.4200
|
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© 2013 Atmel Corporation. / Rev.: Atmel-8866A-SEEPROM-AT24C32D-Datasheet_082013.
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