AR0130CS
1/3‐inch CMOS Digital
Image Sensor
Description
ON Semiconductor AR0130 is a 1/3−inch CMOS digital image
sensor with an active−pixel array of 1280H x 960V. It captures images
with a rolling−shutter readout. It includes sophisticated camera
functions such as auto exposure control, windowing, and both video
and single frame modes. It is programmable through a simple
two−wire serial interface. The AR0130 produces extraordinarily clear,
sharp digital pictures, and its ability to capture both continuous video
and single frames makes it the perfect choice for a wide range of
applications, including gaming systems, surveillance, and HD video.
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Table 1. KEY PERFORMANCE PARAMETERS
Parameter
PLCC48 11.43 y 11.43
CASE 776AL
Typical Value
Optical Format
1/3-inch (6 mm)
Active Pixels
1280 (H) × 960 (V) = 1.2 Mp
Pixel Size
3.75 mm
Color Filter Array
Monochrome, RGB Bayer
Shutter Type
Electronic Rolling Shutter
Input Clock Range
6 – 50 MHz
Output Clock Maximum
74.25 MHz
Output
Parallel
12-bit
Max. Frame Rates
1.2 Mp (Full FOV)
720p HD (Reduced FOV)
VGA (Full FOV)
VGA (Reduced FOV)
800 x 800 (Reduced FOV)
45 fps
60 fps
45 fps
60 fps
60 fps
Responsivity at 550 nm
Monochrome
RGB Green
6.5 V/lux−sec
5.6 V/lux−sec
SNRMAX
44 dB
Dynamic Range
82 dB
Supply Voltage
I/O
Digital
Analog
1.8 or 2.8 V
1.8 V
2.8 V
Power Consumption
270 mW (1280 x 720 60 fps)
Operating Temperature
–30°C to + 70°C (Ambient)
–30°C to + 80°C (Junction)
•
Package Options
PLCC
Applications
ILCC48 10 y 10
CASE 847AB
ILCC48 10 y 10
CASE 847AC
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Features
• Superior Low-light Performance Both in
•
•
•
•
•
•
•
•
• Gaming Systems
• Video Surveillance
• 720p60 Video Applications
10 × 10 mm 48-pin iLCC
Bare Die
© Semiconductor Components Industries, LLC, 2016
May, 2017 − Rev. 13
VGA Mode and HD Mode
Excellent Near IR Performance
HD Video (720p60)
On-chip AE and Statistics Engine
Auto Black Level Calibration
Context Switching
Progressive Scan
Supports 2:1 Scaling
Internal Master Clock Generated by
On−chip Phase Locked Loop (PLL)
Oscillator
Parallel Output
1
Publication Order Number:
AR0130CS/D
AR0130CS
ORDERING INFORMATION
Table 2. ORDERABLE PART NUMBERS
Part Number
Base Description
Variant Description
AR0130CSSC00SPBA0−DP1
RGB Bayer 48−Pin PLCC
Dry Pack with Protective Film
AR0130CSSC00SPBA0−DR1
RGB Bayer 48−Pin PLCC
Dry Pack without Protective Film
AR0130CSSC00SPCA0−DPBR1
RGB Bayer 48−Pin iLCC
Dry Pack with Protective Film, Double Side BBAR Glass
AR0130CSSC00SPCA0−DRBR1
RGB Bayer 48−Pin iLCC
Dry Pack without Protective Film, Double Side BBAR Glass
AR0130CSSC00SPCAH−GEVB
RGB Bayer headboard iLCC
AR0130CSSC00SPCAH−S115−GEVB
RGB Bayer headboard iLCC
AR0130CSSC00SPCAH−S213A−GEVB
RGB Bayer headboard iLCC
AR0130CSSC00SPCAW−GEVB
RGB Bayer headboard iLCC
AR0130CSSM00SPCA0−DRBR1
Monochrome 48−Pin iLCC
AR0130CSSM00SPCAH−S213A−GEVB
Monochrome headboard iLCC
See the ON Semiconductor Device Nomenclature
document (TND310/D) for a full description of the naming
convention used for image sensors. For reference
Dry Pack without Protective Film, Double Side BBAR Glass
documentation, including information on evaluation kits,
please visit our web site at www.onsemi.com.
GENERAL DESCRIPTION
The ON Semiconductor AR0130 can be operated in its
default mode or programmed for frame size, exposure, gain,
and other parameters. The default mode output is a
960p−resolution image at 45 frames per second (fps). It
outputs 12−bit raw data over the parallel port. The device
may be operated in video (master) mode or in single frame
trigger mode.
FRAME_VALID and LINE_VALID signals are output on
dedicated pins, along with a synchronized pixel clock in
parallel mode.
The AR0130 includes additional features to allow
application−specific tuning: windowing and offset,
adjustable auto−exposure control, and auto black level
correction. Optional register information and histogram
statistic information can be embedded in first and last 2 lines
of the image frame.
FUNCTIONAL OVERVIEW
The AR0130 is a progressive−scan sensor that generates
a stream of pixel data at a constant frame rate. It uses an
on−chip, phase−locked loop (PLL) that can be optionally
enabled to generate all internal clocks from a single master
input clock running between 6 and 50 MHz The maximum
output pixel rate is 74.25 Mp/s, corresponding to a clock rate
of 74.25 MHz. Figure 1 shows a block diagram of the sensor.
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2
AR0130CS
OTPM
Power
Trigger
Two-wire
Serial
Interface
Active Pixel Sensor
(APS)
Array
Timing and Control
(Sequencer)
Memory
External
Clock
Auto Exposure
and Stats Engine
Pixel Data Path
(Signal Processing)
Analog Processing and
A/D Conversion
PLL
Parallel
Output
Control Registers
Figure 1. Block Diagram
columns is sequenced through an analog signal chain
(providing offset correction and gain), and then through an
analog−to−digital converter (ADC). The output from the
ADC is a 12−bit value for each pixel in the array. The ADC
output passes through a digital processing signal chain
(which provides further data path corrections and applies
digital gain). The pixel data are output at a rate of up to
74.25 Mp/s, in parallel to frame and line synchronization
signals.
User interaction with the sensor is through the two−wire
serial bus, which communicates with the array control,
analog signal chain, and digital signal chain. The core of the
sensor is a 1.2 Mp Active− Pixel Sensor array. The timing
and control circuitry sequences through the rows of the
array, resetting and then reading each row in turn. In the time
interval between resetting a row and reading that row, the
pixels in the row integrate incident light. The exposure is
controlled by varying the time interval between reset and
readout. Once a row has been read, the data from the
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3
1.5 kW 2,3
1.5 kW 2
AR0130CS
Digital Digital
I/O
Core
Power1 Power1
PLL Analog Analog
Power1 Power1 Power1
VDD_IO
VDD_PLL
Master Clock
(6 − 50 MHz)
VDD
VAA VAA_PIX
DOUT [11:0]
EXTCLK
PIXCLK
LINE_VALID
FRAME_VALID
SADDR
SDATA
SCLK
TRIGGER
OE_BAR
STANDBY
RESET_BAR
From Controller
To Controller
Reserved
VDD_IO
VDD
VDD_PLL
VAA
DGND
AGND
Digital
Ground
Analog
Ground
VAA_PIX
Notes:
1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two−wire speed.
3. This pull−up resistor is not required if the controller drives a valid logic level on SCLK at all times.
4. ON Semiconductor recommends that VDD_SLVS pad (only available in bare die) is left unconnected.
5. ON Semiconductor recommends that 0.1 mF and 10 mF decoupling capacitors for each power supply are mounted as
close as possible to the pad. Actual values and results may vary depending on layout and design considerations.
Check the AR0130 demo headboard schematics for circuit recommendations.
6. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital
power planes is minimized.
7. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage current.
Figure 2. Typical Configuration: Parallel Pixel Data Interface
Table 3. PAD DESCRIPTIONS
Name
Type
Description
STANDBY
Input
VDD_PLL
Power
Standby−mode enable pin (active HIGH).
PLL power.
VAA
Power
Analog power.
EXTCLK
Input
VDD_SLVS
Power
External input clock.
Digital power (do not connect).
DGND
Power
Digital ground.
VDD
Power
Digital power.
AGND
Power
Analog ground.
SADDR
Input
Two−Wire Serial Interface address select.
SCLK
Input
Two−Wire Serial Interface clock input.
SDATA
I/O
Two−Wire Serial Interface data I/O.
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AR0130CS
Table 3. PAD DESCRIPTIONS
Name
Type
Description
VAA_PIX
Power
Pixel power.
LINE_VALID
Output
Asserted when DOUT line data is valid.
FRAME_VALID
Output
Asserted when DOUT frame data is valid.
PIXCLK
Output
Pixel clock out. DOUT is valid on rising edge of this clock.
VDD_IO
Power
I/O supply power.
DOUT8
Output
Parallel pixel data output.
DOUT9
Output
Parallel pixel data output.
DOUT10
Output
Parallel pixel data output.
DOUT11
Output
Parallel pixel data output (MSB)
Reserved
Input
DOUT4
Output
Parallel pixel data output.
DOUT5
Output
Parallel pixel data output.
DOUT6
Output
Parallel pixel data output.
DOUT7
Output
Parallel pixel data output.
TRIGGER
Input
Exposure synchronization input.
OE_BAR
Input
Output enable (active LOW).
DOUT0
Output
Parallel pixel data output (LSB)
DOUT1
Output
Parallel pixel data output.
DOUT2
Output
Parallel pixel data output.
DOUT3
Output
Parallel pixel data output.
RESET_BAR
Input
FLASH
Output
NC
Input
Connect to DGND.
Asynchronous reset (active LOW). All settings are restored to factory default.
Flash control output.
Do not connect.
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DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
4
3
2
1
48
47
46
NC
VDD_PLL
5
DGND
EXTCLK
6
DOUT0
DGND
AR0130CS
45
44
43
DOUT7
7
42
NC
DOUT8
8
41
NC
DOUT9
9
40
VAA
DOUT10
10
39
AGND
DOUT11
11
38
VAA
VDD_IO
12
37
AA
PIXCLK
13
36
AA
VDD
14
35
AGND
SCLK
15
34
VAA
SDATA
16
33
NC
17
32
NC
31
NC
27
28
29
LINE_VALID
Figure 3. 48−Pin iLCC Pinout Diagram
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30
DGND
26
FRAME_VALID
25
TRIGGER
24
FLASH
23
RESERVED
22
SADDR
21
OE_BAR
20
STANDBY
19
NC
18
NC
VDD_IO
VDD
RESET_BAR
AGND
VAA
VAA
VAA
AGND
AGND
VDD_PLL
DGND
VDD
VDD
DGND
DGND
AR0130CS
AGND
VDD_IO
VAA_PIX
VDD_IO
VAA_PIX
SCLK
SADDR
AGND
EXTCLK
AGND
PIXCLK
NC
FLASH
NC
SDATA
NC
VDD
FRAME_VALID
TRIGGER
LINE_VALID
Figure 4. 48−Pin PLCC Pinout Diagram
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RESET_BAR
Top View
STANDBY
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
Reserved
DOUT7
DOUT10
DOUT8
OE_BAR
DOUT9
DOUT11
AR0130CS
PIXEL DATA FORMAT
Pixel Array Structure
format is 1280 x 960, the additional active columns and
active rows are included for use when horizontal or vertical
mirrored readout is enabled, to allow readout to start on the
same pixel. The pixel adjustment is always performed for
monochrome or color versions. The active area is
surrounded with optically transparent dummy pixels to
improve image uniformity within the active area. Not all
dummy pixels or barrier pixels can be read out.
The AR0130 pixel array is configured as 1412 columns by
1028 rows, (see Figure 5). The dark pixels are optically
black and are used internally to monitor black level. Of the
right 108 columns, 64 are dark pixels used for row noise
correction. Of the top 24 rows of pixels, 12 of the dark rows
are used for black level correction. There are 1296 columns
by 976 rows of optically active pixels. While the sensor’s
1412
1028
2 Light Dummy +
4 Barrier +
24 Dark +
4 Barrier +
6 Dark Dummy
2 Light Dummy +
4 Barrier +
100 Dark +
4 Barrier
1296 × 976 (1288 × 968 Active)
4.86 × 3.66 mm2 (4.83 × 3.63 mm2)
2 Light Dummy +
4 Barrier +
6 Dark Dummy
2 Light Dummy +
4 Barrier
Dark Pixel
Light Dummy
Pixel
Barrier Pixel
Active Pixel
Figure 5. Pixel Array Description
…
Column Readout Direction
Row Readout Direction
Active Pixel (0, 0)
Array Pixel (112, 44)
…
R G R G R
G R G
G B G B G
B G B
R G R G R
G R G
G B G B G
B G B
R G R G R
G R G
G B G B G
B G B
Figure 6. Pixel Color Pattern Detail (Top Right Corner)
Default Readout Order
By convention, the sensor core pixel array is shown with
the first addressable (logical) pixel (0,0) in the top right
corner (see Figure 6). This reflects the actual layout of the
array on the die. Also, the physical location of the first pixel
data read out of the sensor in default condition is that of pixel
(112, 44).
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AR0130CS
When the sensor is imaging, the active surface of the
sensor faces the scene as shown in Figure 7. When the image
is read out of the sensor, it is read one row at a time, with the
rows and columns sequenced as shown in Figure 7.
Lens
Scene
Sensor (rear view)
Order
Column Readout Order
Pixel (0,0)
Figure 7. Imaging a Scene
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AR0130CS
OUTPUT DATA FORMAT
The AR0130 image data is read out in a progressive scan.
Valid image data is surrounded by horizontal and vertical
blanking (see Figure 8). The amount of horizontal row time
(in clocks) is programmable through R0x300C. The amount
of vertical frame time (in rows) is programmable through
R0x300A. LINE_VALID (LV) is HIGH during the shaded
region of Figure 8. Optional Embedded Register setup
information and Histogram statistic information are
available in first 2 and last row of image data.
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
P0,0 P 0,1 P 0,2 .....................................P
0,n−1 P0,n
P1,0 P 1,1 P 1,2 .....................................P
1,n−1 P1,n
HORIZONTAL
VALID IMAGE
BLANKING
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
Pm−1,0 P m−1,1 .....................................P
m−1,n−1 Pm−1,n
Pm,0 P m,1 .....................................P
m,n−1 Pm,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
VERTICAL/HORIZONTAL
VERTICAL BLANKING
BLANKING
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
Figure 8. Spatial Illustration of Image Readout
Readout Sequence
968 rows of 1288 columns each. The FV and LV signals
indicate the boundaries between frames and lines,
respectively. PIXCLK can be used as a clock to latch the
data. For each PIXCLK cycle, with respect to the falling
edge, one 12−bit pixel datum outputs on the DOUT pins.
When both FV and LV are asserted, the pixel is valid.
PIXCLK cycles that occur when FV is de−asserted are called
vertical blanking. PIXCLK cycles that occur when only LV
is de−asserted are called horizontal blanking.
Typically, the readout window is set to a region including
only active pixels. The user has the option of reading out
dark regions of the array, but if this is done, consideration
must be given to how the sensor reads the dark regions for
its own purposes.
Parallel Output Data Timing
The output images are divided into frames, which are
further divided into lines. By default, the sensor produces
Figure 9. Default Pixel Output Timing
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AR0130CS
LV and FV
of FV by 6 PIXCLKs. Normally, LV will only be asserted if
FV is asserted; this is configurable as described below.
The timing of the FV and LV outputs is closely related to
the row time and the frame time.
FV will be asserted for an integral number of row times,
which will normally be equal to the height of the output
image.
LV will be asserted during the valid pixels of each row.
The leading edge of LV will be offset from the leading edge
LV Format Options
The default situation is for LV to be de−asserted when FV
is de−asserted. By configuring R0x306E[1:0], the LV signal
can take two different output formats. The formats for
reading out four lines and two vertical blanking lines are
shown in Figure 10.
FV
Default
LV
FV
Continuous LV
LV
Figure 10. LV Format Options
The timing of an entire frame is shown in Figure 11: “Line
Timing and FRAME_VALID/LINE_VALID Signals”.
Frame Time
The pixel clock (PIXCLK) represents the time needed to
sample 1 pixel from the array. The sensor outputs data at the
maximum rate of 1 pixel per PIXCLK. One row time (tROW)
is the period from the first pixel output in a row to the first
pixel output in the next row. The row time and frame time are
defined by equations in Table 4.
Figure 11. Line Timing and FRAME_VALID/LINE_VALID Signals
Table 4. FRAME TIME (Example Based on 1280 x 960, 45 Frames Per Second)
Name
Equation
A
Parameter
Active data time
Context A: R0x3008 − R0x3004 + 1
Context B: R0x308E − R0x308A + 1
1280 pixel clocks
= 17.23 ms
P1
Frame start blanking
6 (fixed)
6 pixel clocks
= 0.08 ms
P2
Frame end blanking
6 (fixed)
6 pixel clocks
= 0.08 ms
Q
Horizontal blanking
R0x300C − A
370 pixel clocks
= 4.98 ms
A+Q (tROW)
Line (Row) time
R0x300C
1650 pixel clocks
= 22.22 ms
V
Vertical blanking
Context A: (R0x300A−(R0x3006−R0x3002+1)) x (A + Q)
Context B: ((R0x30AA−(R0x3090−R0x308C+1)) x (A + Q)
49,500 pixel clocks
= 666.66 ms
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Timing at 74.25 MHz
AR0130CS
Table 4. FRAME TIME (Example Based on 1280 x 960, 45 Frames Per Second)
Parameter
Name
Equation
Timing at 74.25 MHz
Nrows x (tROW)
Frame valid time
Context A: ((R0x3006−R0x3002+1)*(A+Q))−Q+P1+P2
Context B: ((R0x3090−R0x308C+1)*(A+Q))−Q+P1+P2
1,583,642 pixel clocks
= 21.33 ms
F
Total frame time
V + (Nrows x (A + Q))
1,633,500 pixel clocks
= 22.22 ms
Sensor timing is shown in terms of pixel clock cycles (see
Figure 8). The recommended pixel clock frequency is
74.25 MHz. The vertical blanking and the total frame time
equations assume that the integration time (coarse
integration time plus fine integration time) is less than the
number of active lines plus the blanking lines:
WindowHeight ) VerticalBlanking
control is programmed with 2000 rows and the fine shutter
width total is zero.
For Master mode, if the integration time registers exceed
the total readout time, then the vertical blanking time is
internally extended automatically to adjust for the additional
integration time required. This extended value is not written
back to the frame_length_lines register. The
frame_length_lines register can be used to adjust
frame−to−frame readout time. This register does not affect
the exposure time but it may extend the readout time.
(eq. 1)
If this is not the case, the number of integration lines must
be used instead to determine the frame time, (see Table 5).
In this example, it is assumed that the coarse integration time
Table 5. FRAME TIME: LONG INTEGRATION TIME
Parameter
F’
NOTE:
Name
Total frame time (long
integration time)
Equation
Context A: (R0x3012 x (A + Q)) + R0x3014 + P1 + P2
Context B: (R0x3016 x (A + Q)) + V R0x3018 + P1 + P2
Timing at 74.25 MHz
3,300,012 pixel clocks
= 44.44 ms
The AR0130 uses column parallel analog−digital converters; thus short line timing is not possible. The minimum total line time is
1390 columns (horizontal width + horizontal blanking). The minimum horizontal blanking is 110.
• Number of Lines of Integration (Auto Exposure
Exposure
Total
integration
time
is
the
result
of
Coarse_Integration_Time and Fine_Integration_Time
registers, and depends also on whether manual or automatic
exposure is selected.
The actual total integration time, tINT is defined as:
t INT + t INTCoarse * 410 * t INTFine
•
(eq. 1)
= (number of lines of integration x line time) − (410 pixel
clocks of conversion time overhead) − (number of pixels of
integration x pixel time)
where:
• Number of Lines of Integration (Auto Exposure
Control: Enabled)
When automatic exposure control (AEC) is enabled, the
number of lines of integration may vary from frame to
frame, with the limits controlled by R0x311E
(minimum auto exposure time) and R0x311C
(maximum auto exposure time).
Control: Disabled)
If AEC is disabled, the number of lines of integration
equals the value in R0x3012 (context A) or R0x3016
(context B).
Number of Pixels of Integration
The number of fine shutter width pixels is independent
of AEC mode (enabled or disabled):
♦ Context A: the number of pixels of integration
equals the value in R0x3014.
♦ Context B: the number of pixels of integration
equals the value in R0x3018.
Typically, the value of the Coarse_Integration_Time
register is limited to the number of lines per frame (which
includes vertical blanking lines), such that the frame rate is
not affected by the integration time. For more information
on coarse and fine integration time settings limits, please
refer to the Register Reference document.
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AR0130CS
REAL−TIME CONTEXT SWITCHING
In the AR0130, the user may switch between two full
register sets (listed in Table 6) by writing to a context switch
change bit in R0x30B0[13]. This context switch will change
all registers (no shadowing) at the frame start time and have
the new values apply to the immediate next exposure and
readout time.
Table 6. REAL−TIME CONTEXT−SWITCHABLE REGISTERS
Register Number
Context A
Context B
Y_Addr_Start
R0x3002
R0x308C
X_Addr_Start
R0x3004
R0x308A
Y_Addr_End
R0x3006
R0x3090
X_Addr_End
R0x3008
R0x308E
Coarse_Integration_Time
R0x3012
R0x3016
Fine_Integration_Time
R0x3014
R0x3018
Y_Odd_Inc
R0x30A6
R0x30A8
Green1_Gain (GreenR)
R0x3056
R0x30BC
Blue_Gain
R0x3058
R0x30BE
Red_Gain
R0x305A
R0x30C0
Green2_Gain (GreenB)
R0x305C
R0x30C2
Global_Gain
R0x305E
R0x30C4
Analog Gain
R0x30B0[5:4]
R0x30B0[9:8]
R0x300A
R0x30AA
R0x3032[1:0]
R0x3032[5:4]
Register Description
Frame_Length_Lines
Digital_Binning
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AR0130CS
FEATURES
new frame. This bit is a self−resetting bit and also returns to
“0” during two−wire serial interface reads.
See the AR0130 Register Reference for additional details.
Reset
The AR0130 may be reset by using RESET_BAR (active
LOW) or the reset register.
Clocks
Hard Reset of Logic
The RESET_BAR pin can be connected to an external RC
circuit for simplicity. The recommended RC circuit uses a
10 kW resistor and a 0.1 mF capacitor. The rise time for the
RC circuit is 1 ms maximum.
PLL−Generated Master Clock
The PLL contains a prescaler to divide the input clock
applied on EXTCLK, a VCO to multiply the prescaler
output, and two divider stages to generate the output clock.
The clocking structure is shown in Figure 12. PLL control
registers can be programmed to generate desired master
clock frequency.
NOTE: The PLL control registers must be programmed
while the sensor is in the software Standby state.
The effect of programming the PLL divisors
while the sensor is in the streaming state is
undefined.
The AR0130 requires one clock input (EXTCLK).
Soft Reset of Logic
Soft reset of logic is controlled by the R0x301A Reset
register. Bit 0 is used to reset the digital logic of the sensor
while preserving the existing two−wire serial interface
configuration. Furthermore, by asserting the soft reset, the
sensor aborts the current frame it is processing and starts a
PLL Input
Clock
EXTCLK
PLL Output
Clock
SYSCLK
Pre PLL
PLL
PLL Output
PLL Output
Div 1
Div 2
Div
Multiplier
(PFD)
(VCO)
Pre_pll_clk_div
pll_multiplier
vt_sys_clk_div
PIXCLK
vt_pix_clk_div
Figure 12. PLL−Generated Master Clock PLL Setup
4. Set R0x301A[2]=1 to enable streaming and to
switch from EXTCLK to the PLL−generated
clock.
The PLL is enabled by default on the AR0130.
To Configure and Use the PLL:
1. Bring the AR0130 up as normal; make sure that
fEXTCLK is between 6 and 50MHz and ensure the
sensor is in software standby (R0x301A[2]= 0).
PLL control registers must be set in software
standby.
2. Set pll_multiplier, pre_pll_clk_div,
vt_sys_clk_div, and vt_pix_clk_div based on the
desired input (fEXTCLK) and output (fPIXCLK )
frequencies. Determine the M, N, P1, and P2
values to achieve the desired fPIXCLK using this
formula:
fPIXCLK= (fEXTCLK × M) / (N × P1 x P2)
where
M = PLL_Multiplier (R0x3030)
N = Pre_PLL_Clk_Div (R0x302E)
P1 = Vt_Sys_Clk_Div (R0x302C)
P2 = Vt_PIX_Clk_Div (R0x302A)
NOTES:
1. The PLL can be bypassed at any time (sensor will
run directly off EXTCLK) by setting
R0x30B0[14]=1. However, only the parallel data
interface is supported with the PLL bypassed. The
PLL is always bypassed in software standby mode.
To disable the PLL, the sensor must be in standby
mode (R0x301A[2] = 0)
2. The following restrictions apply to the PLL tuning
parameters:
32 ≤ M ≤ 255
1 ≤ N ≤ 63
1 ≤ P1 ≤ 16
4 ≤ P2 ≤ 16
Additionally, the VCO frequency, defined as
fVCO = fEXTCLK × M / N
must be within 384 −768 MHz and the EXTCLK
3. Wait 1 ms to ensure that the VCO has locked.
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AR0130CS
must be within 2 MHz ≤ fEXTCLK / N ≤ 24 Mhz
The user can utilize the Register Wizard tool
accompanying DevWare to generate PLL settings
given a supplied input clock and desired output
frequency.
Soft Standby
Soft Standby is a low power state that is controlled
through register R0x301A[2]. Depending on the value of
R0x301A[4], the sensor will go to standby after completion
of the current frame readout (default behavior) or after the
completion of the current row readout. When the sensor
comes back from Soft Standby, previously written register
settings are still maintained.
A specific sequence needs to be followed to enter and exit
from Soft Standby.
To Enter Soft Standby:
1. R0x301A[12] = 1 if serial mode was used
2. Set R0x301A[2] = 0
3. External clock can be turned off to further
minimize power consumption (Optional)
To Exit Soft Standby:
1. Enable external clock if it was turned off
2. R0x301A[2] = 1
3. R0x301A[12] = 0 if serial mode is used
Spread−Spectrum Clocking
To facilitate improved EMI performance, the external
clock input allows for spread spectrum sources, with no
impact on image quality. Limits of the spread spectrum input
clock are:
• 5% maximum clock modulation
• 35 KHz maximum modulation frequency
• Accepts triangle wave modulation, as well as sine or
modified triangle modulations.
Stream/Standby Control
The sensor supports two standby modes: Hard Standby
and Soft Standby. In both modes, external clock can be
optionally disabled to further minimize power consumption.
If this is done, then the “Power−Up Sequence” on page 44
must be followed.
FV
EXTCLK
50 E X T C L K s
S DAT A
Register Writes Valid
Register Writes Not Valid
750 E X T C L K s
S T AN DB Y
Figure 13. Enter Standby Timing
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15
AR0130CS
28 rows + CIT
FV
EXTCLK
S DAT A
Register Writes Not Valid
Register Writes Valid
10 E X T C L K s
S T AN DB Y
1ms
T R IG G E R
Figure 14. Exit Standby Timing
from the frame_length_lines register. The minimum
vertical blanking is 26 lines.
Hard Standby
Hard Standby puts the sensor in lower power state;
previously written register settings are still maintained.
A specific sequence needs to be followed to enter and exit
from Hard Standby.
To Enter Hard Standby:
1. R0x301A[8] = 1
2. R0x301A[12] = 1 if serial mode was used
3. Assert STANDBY pin
4. External clock can be turned off to further
minimize power consumption (Optional)
To Exit Hard Standby:
1. Enable external clock if it was turned off
2. De−assert STANDBY pin
3. Set R0x301A[8] = 0
The actual imager timing can be calculated using Table 4
and Table 5, which describe the Line Timing and FV/LV
signals.
Readout Modes
Digital Binning
By default, the resolution of the output image is the full
width and height of the FOV as defined above. The output
resolution can be reduced by digital binning. For RGB and
monochrome mode, this is set by the register R0x3032. For
Context A, use bits [1:0], for Context B, use bits [5:4].
Available settings are:
00 = No binning
01 = Horizontal binning
10 = Horizontal and vertical binning
Window Control
Registers x_addr_start, x_addr_end, y_addr_start, and
y_addr_end control the size and starting coordinates of the
image window.
The exact window height and width out of the sensor is
determined by the difference between the Y address start and
end registers or the X address start and end registers,
respectively.
The AR0130 allows different window sizes for context A
and context B.
Binning gives the advantage of reducing noise at the cost
of reduced resolution. When both horizontal and vertical
binning are used, a 2x improvement in SNR is achieved
therefore improving low light performance
Bayer Space Resampling
All of the pixels in the FOV contribute to the output image
in digital binning mode. This can result in a more pleasing
output image with reduced subsampling artifacts. It also
improves low−light performance. For RGB mode,
resampling can be enabled by setting of register
0x306E[4] = 1.
Blanking Control
Horizontal blank and vertical blank times are controlled
by the line_length_pck and frame_length_lines registers,
respectively.
• Horizontal blanking is specified in terms of pixel
clocks. It is calculated by subtracting the X window
size from the line_length_pck register. The minimum
horizontal blanking is 110 pixel clocks.
• Vertical blanking is specified in terms of numbers of
lines. It is calculated by subtracting the Y window size
Mirror
Column Mirror Image
By setting R0x3040[14] = 1, the readout order of the
columns is reversed, as shown in Figure 15. The starting
color, and therefore the Bayer pattern, is preserved when
mirroring the columns.
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AR0130CS
When using horizontal mirror mode, the user must
retrigger column correction. Please refer to the column
correction section to see the procedure for column
correction retriggering. Bayer resampling must be enabled,
by setting bit 4 of register 0 x 306E[4] = 1.
LV
Normal readout
G0[11:0] R0[11:0] G1[11:0] R1[11:0] G2[11:0] R2[11:0]
DOUT[11:0]
Reverse readout
G2[11:0] R2[11:0] G1[11:0] R1[11:0] G0[11:0] R0[11:0]
DOUT[11:0]
Figure 15. Six Pixels In Normal and Column Mirror Readout Modes
imaging array. When using horizontal mirror mode, the user
must retrigger column correction. Please refer to the column
correction section to see the procedure for column
correction retriggering.
Row Mirror Image
By setting R0x3040[15] = 1, the readout order of the rows
is reversed as shown in Figure 16. The starting Bayer color
pixel is maintained in this mode by a 1−pixel shift in the
FV
Normal readout
Row0 [11:0] Row1 [11:0] Row2 [11:0] Row3 [11:0] Row4 [11:0] Row5 [11:0]
DOUT[11:0]
Reverse readout
DOUT[11:0]
Row5 [11:0] Row4 [11:0] Row3 [11:0] Row2 [11:0] Row1 [11:0]
Row0[11:0]
Figure 16. Six Rows In Normal and Row Mirror Readout Modes
• read_mode
Maintaining a Constant Frame Rate
Maintaining a constant frame rate while continuing to
have the ability to adjust certain parameters is the desired
scenario. This is not always possible, however, because
register updates are synchronized to the read pointer, and the
shutter pointer for a frame is usually active during the
readout of the previous frame. Therefore, any register
changes that could affect the row time or the set of rows
sampled causes the shutter pointer to start over at the
beginning of the next frame.
By default, the following register fields cause a “bubble”
in the output rate (that is, the vertical blank increases for one
frame) if they are written in video mode, even if the new
value would not change the resulting frame rate. The
following list shows only a few examples of such registers;
a full listing can be seen in the AR0130 Register Reference.
• x_addr_start
• x_addr_end
• y_addr_start
• y_addr_end
• frame_length_lines
• line_length_pclk
• coarse_integration_time
• fine_integration_time
The size of this bubble is (Integration_Time × tROW),
calculating the row time according to the new settings.
The Coarse_Integration_Time and
Fine_Integration_Time fields may be written to without
causing a bubble in the output rate under certain
circumstances. Because the shutter sequence for the next
frame often is active during the output of the current frame,
this would not be possible without special provisions in the
hardware. Writes to these registers take effect two frames
after the frame they are written, which allows the integration
time to increase without interrupting the output or producing
a corrupt frame (as long as the change in integration time
does not affect the frame time).
Synchronizing Register Writes to Frame Boundaries
Changes to most register fields that affect the size or
brightness of an image take effect on the frame after the one
during which they are written. These fields are noted as
“synchronized to frame boundaries” in the AR0130 Register
Reference. To ensure that a register update takes effect on
the next frame, the write operation must be completed after
the leading edge of FV and before the trailing edge of FV.
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AR0130CS
As a special case, in single frame mode, register writes
that occur after FV but before the next trigger will take effect
immediately on the next frame, as if there had been a Restart.
However, if the trigger for the next frame occurs during FV,
register writes take effect as with video mode.
Fields not identified as being frame−synchronized are
updated immediately after the register write is completed.
The effect of these registers on the next frame can be difficult
to predict if they affect the shutter pointer.
Continuous Trigger
In certain applications, multiple sensors need to have their
video streams synchronized (E.g. surround view or
panorama view applications). The TRIGGER pin can also
be used to synchronize output of multiple image sensors
together and still get a video stream. This is called
continuous trigger mode. Continuous trigger is enabled by
holding the TRIGGER pin high. Alternatively, the
TRIGGER pin can be held high until the stream bit is
enabled (R0x301A[2]=1) then can be released for
continuous synchronized video streaming.
If the TRIGGER pins for all connected AR0130 sensors
are connected to the same control signal, all sensors will
receive the trigger pulse at the same time. If they are
configured to have the same frame timing, then the usage of
the TRIGGER pin guarantees that all sensors will be
synchronized within 1 PIXCLK cycle if PLL is disabled, or
2 PIXCLK cycles if PLL is enabled.
With continuous trigger mode, the application can now
make use of the video streaming mode while guaranteeing
that all sensor outputs are synchronized. As long as the initial
trigger for the sensors takes place at the same time, all
subsequent video streams will be synchronous.
Restart
To restart the AR0130 at any time during the operation of
the sensor, write a “1” to the Restart register (R0x301A[1]
= 1). This has two effects: first, the current frame is
interrupted immediately. Second, any writes to
frame−synchronized registers and the shutter width registers
take effect immediately, and a new frame starts (in video
mode). The current row completes before the new frame is
started, so the time between issuing the Restart and the
beginning of the next frame can vary by about tROW.
Image Acquisition Modes
The AR0130 supports two image acquisition modes:
video (also known as master) and single frame.
Automatic Exposure Control
Video
The video mode takes pictures by scanning the rows of the
sensor twice. On the first scan, each row is released from
reset, starting the exposure. On the second scan, the row is
sampled, processed, and returned to the reset state. The
exposure for any row is therefore the time between the first
and second scans. Each row is exposed for the same
duration, but at slightly different point in time, which can
cause a shear in moving subjects as is typical with electronic
rolling shutter sensors.
The integrated automatic exposure control (AEC) is
responsible for ensuring that optimal settings of exposure
and gain are computed and updated every other frame. AEC
can be enabled or disabled by R0x3100[0].
When AEC is disabled (R0x3100[0] = 0), the sensor uses
the manual exposure value in coarse and fine shutter width
registers and the manual gain value in the gain registers.
When AEC is enabled (R0x3100[0]=1), the target luma
value is set by R0x3102. For the AR0130 this target luma has
a default value of 0x0800 or about half scale.
The exposure control measures current scene luminosity
by accumulating a histogram of pixel values while reading
out a frame. It then compares the current luminosity to the
desired output luminosity. Finally, the appropriate
adjustments are made to the exposure time and gain. All
pixels are used, regardless of color or mono mode.
AEC does not work if digital binning is enabled.
Single Frame
The single−frame mode operates similar to the video
mode. It also scans the rows of the sensor twice, first to reset
the rows and second to read the rows. Unlike video mode
where a continuous stream of images are output from the
image sensor, the single−frame mode outputs a single frame
in response to a high state placed on the TRIGGER input pin.
As long as the TRIGGER pin is held in a high state, new
images will be read out. After the TRIGGER pin is returned
to a low state, the image sensor will not output any new
images and will wait for the next high state on the TRIGGER
pin.
The TRIGGER pin state is detected during the vertical
blanking period (i.e. the FV signal is low). The pin is level
sensitive rather than edge sensitive. As such, image
integration will only begin when the sensor detects that the
TRIGGER pin has been held high for 3 consecutive clock
cycles.
During integration time of single−frame mode and video
mode, the FLASH output pin is at high.
Embedded Data and Statistics
The AR0130 has the capability to output image data and
statistics embedded within the frame timing. There are two
types of information embedded within the frame readout:
1. Embedded Data: If enabled, these are displayed on
the two rows immediately before the first active
pixel row is displayed.
2. Embedded Statistics: If enabled, these are
displayed on the two rows immediately after the
last active pixel row is displayed.
NOTE: Both embedded statistics and data must be
enabled and disabled together.
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AR0130CS
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
Register Data
Image
HBlank
Status & Statistics Data
VBlank
Figure 17. Frame Format with Embedded Data Lines Enabled
transferred over 2 pixels where the register data will be
broken up into 8 MSB and 8 LSB. The alignment of the 8−bit
data will be on the 8 MSB bits of the 12−bit pixel word. For
example, of a register value of 0x1234 is to be transmitted,
it will be transmitted over 2, 12−bit pixels as follows: 0x120,
0x340.
The first pixel of each line in the embedded data is a tag
value of 0x0A0. This signifies that all subsequent data is 8
bit data aligned to the MSB of the 12−bit pixel.
The figure below summarizes how the embedded data
transmission looks like. It should be noted that data, as
shown in Figure 18, is aligned to the MSB of each word:
Embedded Data
The embedded data contains the configuration of the
image being displayed. This includes all register settings
used to capture the current frame. The registers embedded
in these rows are as follows:
Line 1:
Registers R0x3000 to R0x312F
Line 2:
Registers R0x3136 to R0x31BF, R0x31D0 to R0x31FF
NOTE: All undefined registers will have a value of 0.
In parallel mode, since the pixel word depth is
12−bits/pixel, the sensor 16−bit register data will be
data_format_
code =8’h0A
8’hAA
{register_
address_MSB}
{register_
address_LSB}
8’hA5
8’h5A
{register_
value_MSB}
8’h5A
Data line 1
data_format_
code =8’h0A
Data line 2
8’hAA
{register_
value_LSB}
8’h5A
{register_
address_MSB}
8’hA5
{register_
value_LSB}
{register_
address_LSB}
8’h5A
{register_
value_MSB}
8’h5A
8’h5A
Figure 18. Format of Embedded Data Output within a Frame
•
•
•
•
•
•
•
•
The data embedded in these rows are as follows:
• 0x0A0 − identifier
• 0xAA0
• Register Address MSB of the first register
• 0xA50
• Register Address LSB of the first register
• 0x5A0
• Register Value MSB of the first register addressed
0x5A0
Register Value LSB of the first register addressed
0x5A0
Register Value MSB of the register at first address + 2
0x5A0
Register Value LSB of the register at first address + 2
0x5A0
etc.
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AR0130CS
The first pixel of each line in the embedded statistics is a
tag value of 0x0B0. This signifies that all subsequent
statistics data is 10 bit data aligned to the MSB of the 12−bit
pixel.
The figure below summarizes how the embedded
statistics transmission looks like. It should be noted that
data, as shown in Figure 19, is aligned to the msb of each
word:
Embedded Statistics
The embedded statistics contain frame identifiers and
histogram information of the image in the frame. This can be
used by downstream auto−exposure algorithm blocks to
make decisions about exposure adjustment.
This histogram is divided into 244 bins with a bin spacing
of 64 evenly spaced bins for digital code values 0 to 212, 120
evenly spaced bins for values 212 to 216, 60 evenly spaced
bins for values 216 to 220.
data_format_
code =8’h0B
#words =
10’h1EC
{2’b00, frame
_count MSB}
{2’b00, frame {2’b00, frame
_ID MSB}
_ID LSB}
{2’b00, frame
_count LSB}
histogram
bin0 [19:10]
histogram
bin0 [9:0]
stats line 1
histogram
bin1 [19:10]
data_format_
code =8’h0B
stats line 2
#words =
10’h1C
mean [ 19:10]
histogram
bin1 [9:0]
histogram
bin243 [19:10]
hist_begin
[19:10]
mean [9:0]
lowEndMean lowEndMean
[9:0]
[19:10]
hist_begin
[9:10]
perc_lowEnd perc_lowEnd
[9:0]
[19:10]
histogram
bin243 [9:0]
hist_end
[19:10]
8’h07
8’h07
hist_end
[9:10]
norm_abs_dev lnorm_abs_dev
[9:0]
[19:10]
8’h07
Figure 19. Format of Embedded Statistics Output within a Frame
There are two stages of analog gain, the first stage can be
set to 1x, 2x, 4x or 8x. This is can be set in
R0x30B0[5:4](Context A) or R0x30B0[9:8] (Context B).
The second stage is capable of setting an additional 1x or
1.25x gain which can be set in R0x3EE4[8].
This allows the maximum possible analog gain to be set
to 10x.
The statistics embedded in these rows are as follows:
Line 1:
• 0x0B0 − identifier
• Register 0x303A − frame_count
• Register 0x31D2 − frame ID
• Histogram data − histogram bins 0−243
•
•
•
•
•
•
•
Line 2:
0x0B0 (identifier)
Mean
Histogram Begin
Histogram End
Low End Histogram Mean
Percentage of Pixels Below Low End Mean
Normal Absolute Deviation
Black Level Correction
Black level correction is handled automatically by the
image sensor. No adjustments are provided except to enable
or disable this feature. Setting R0x30EA[15] disables the
automatic black level correction. Default setting is for
automatic black level calibration to be enabled.
The automatic black level correction measures the
average value of pixels from a set of optically black lines in
the image sensor. The pixels are averaged as if they were
light−sensitive and passed through the appropriate gain.
This line average is then digitally low−pass filtered over
many frames to remove temporal noise and random
instabilities associated with this measurement. The new
filtered average is then compared to a minimum acceptable
level, low threshold, and a maximum acceptable level, high
threshold. If the average is lower than the minimum
acceptable level, the offset correction value is increased by
a predetermined amount. If it is above the maximum level,
the offset correction value is decreased by a predetermined
amount. The high and low thresholds have been calculated
to avoid oscillation of the black level from below to above
the targeted black level. At high gain, long exposure, and
high temperature conditions, the performance of this
function can degrade.
Gain
Digital Gain
Digital gain can be controlled globally by R0x305E
(Context A) or R0x30C4 (Context B). There are also
registers that allow individual control over each Bayer color
(GreenR, GreenB, Red, Blue).
The format for digital gain setting is xxx.yyyyy where
0b00100000 represents a 1x gain setting and 0b00110000
represents a 1.5x gain setting. The step size for yyyyy is
0.03125 while the step size for xxx is 1. Therefore to set a
gain of 2.09375 one would set digital gain to 01000011.
Analog Gain
The AR0130 has a column parallel architecture and
therefore has an Analog gain stage per column.
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AR0130CS
Row−wise Noise Correction
9. Disable streaming (R0x301A[2] = 0) or drive the
TRIGGER pin LOW.
After this, the sensor has calculated the proper column
correction coefficients and the sensor is ready for streaming.
Any other settings (including gain, integration time and
conversion gain etc.) can be done afterwards without
affecting column correction.
Row (Line)−wise Noise Correction is handled
automatically by the image sensor. No adjustments are
provided except to enable or disable this feature. Clearing
R0x3044[10] disables the row noise correction. Default
setting is for row noise correction to be enabled.
Row−wise noise correction is performed by calculating an
average from a set of optically black pixels at the start of
each line and then applying each average to all the active
pixels of the line.
Column Correction Retriggering Due to Mode Change
Since column offsets is sensitive to changes in the analog
signal path, such changes require column correction
circuitry to be retriggered for the new path. Examples of
such mode changes include: horizontal mirror, vertical
mirror, changes to column correction settings.
When such changes take place, the following sequence
needs to take place:
1. Disable streaming (R0x301A[2]=0) or drive the
TRIGGER pin LOW.
2. Enable streaming (R0x301A[2]=1) or drive the
TRIGGER pin HIGH.
3. Wait 9 frames to settle.
NOTE: The above steps are not needed if the sensor is
being reset (soft or hard reset) upon the mode
change.
Column Correction
The AR0130 uses column parallel readout architecture to
achieve fast frame rate. Without any corrections, the
consequence of this architecture is that different column
signal paths have slightly different offsets that might show
up on the final image as structured fixed pattern noise.
AR0130 has column correction circuitry that measures
this offset and removes it from the image before output. This
is done by sampling dark rows containing tied pixels and
measuring an offset coefficient per column to be corrected
later in the signal path.
Column correction can be enabled/disabled via
R0x30D4[15]. Additionally, the number of rows used for
this offset coefficient measurement is set in R0x30D4[3:0].
By default this register is set to 0x7, which means that 8 rows
are used. This is the recommended value. Other control
features regarding column correction can be viewed in the
AR0130 Register reference. Any changes to column
correction settings need to be done when the sensor
streaming is disabled and the appropriate triggering
sequence must be followed as described below.
Test Patterns
The AR0130 has the capability of injecting a number of
test patterns into the top of the datapath to debug the digital
logic. With one of the test patterns activated, any of the
datapath functions can be enabled to exercise it in a
deterministic fashion. Test patterns are selected by
Test_Pattern_Mode register (R0x3070). Only one of the test
patterns can be enabled at a given point in time by setting the
Test_Pattern_Mode register according to Table 7. When test
patterns are enabled the active area will receive the value
specified by the selected test pattern and the dark pixels will
receive the value in Test_Pattern_Green (R0x3074 and
R0x3078) for green pixels, Test_Pattern_Blue (R0x3076)
for blue pixels, and Test_Pattern_Red (R0x3072) for red
pixels.
NOTE: Turn off black level calibration (BLC) when
Test Pattern is enabled.
Column Correction Triggering
Column correction requires a special procedure to trigger
depending on which state the sensor is in.
Column Triggering on Startup
When streaming the sensor for the first time after
power−up, a special sequence needs to be followed to make
sure that the column correction coefficients are internally
calculated properly.
1. Follow proper power up sequence for power
supplies and clocks
2. Apply sequencer settings if needed
3. Apply frame timing and PLL settings as required
by application
4. Set analog gain to 1x and low conversion gain
5. Enable column correction and settings
6. Disable auto re−trigger for change in conversion
gain or col_gain, and enable column correction
always. (R0x30BA = 0x0008).
7. Enable streaming (R0x301A[2] = 1) or drive the
TRIGGER pin HIGH.
8. Wait 9 frames to settle. (First frame after coming
up from standby is internally column correction
disabled.)
Table 7. TEST PATTERN MODES
Test_Pattern_Mode
Test Pattern Output
0
No test pattern (normal operation)
1
Solid color test pattern
2
100% color bar test pattern
3
Fade−to−gray color bar test pattern
256
Walking 1s test pattern (12−bit)
Color Field
When the color field mode is selected, the value for each
pixel is determined by its color. Green pixels will receive the
value in Test_Pattern_Green, red pixels will receive the
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AR0130CS
value in Test_Pattern_Red, and blue pixels will receive the
value in Test_Pattern_Blue.
Walking 1s
When the walking 1s mode is selected, a walking 1s
pattern will be sent through the digital pipeline. The first
value in each row is 1.
Vertical Color Bars
When the vertical color bars mode is selected, a typical
color bar pattern will be sent through the digital pipeline.
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AR0130CS
TWO-WIRE SERIAL REGISTER INTERFACE
The two−wire serial interface bus enables read/write
access to control and status registers within the AR0130.
This interface is designed to be compatible with the
electrical characteristics and transfer protocols of the
two−wire serial interface specification.
The interface protocol uses a master/slave model in which
a master controls one or more slave devices. The sensor acts
as a slave device. The master generates a clock (SCLK) that
is an input to the sensor and is used to synchronize transfers.
Data is transferred between the master and the slave on a
bidirectional signal (SDATA). SDATA is pulled up to VDD_IO
off−chip by a 1.5 kW resistor. Either the slave or master
device can drive SDATA LOW − the interface protocol
determines which device is allowed to drive SDATA at any
given time.
The protocols described in the two−wire serial interface
specification allow the slave device to drive SCLK LOW; the
AR0130 uses SCLK as an input only and therefore never
drives it LOW.
bit [0] indicates a WRITE, and a “1” indicates a READ.
The default slave addresses used by the AR0130CS are 0x20
(write address) and 0x21 (read address) in accordance with
the specification. Alternate slave addresses of 0x30 (write
address) and 0x31 (read address) can be selected by enabling
and asserting the SADDR input.
An alternate slave address can also be programmed
through R0x31FC.
Message Byte
Message bytes are used for sending register addresses and
register write data to the slave device and for retrieving
register read data.
Acknowledge Bit
Each 8-bit data transfer is followed by an acknowledge bit
or a no-acknowledge bit in the SCLK clock period following
the data transfer. The transmitter (which is the master when
writing, or the slave when reading) releases SDATA.
The receiver indicates an acknowledge bit by driving SDATA
LOW. As for data transfers, SDATA can change when SCLK
is LOW and must be stable while SCLK is HIGH.
Protocol
Data transfers on the two-wire serial interface bus are
performed by a sequence of low-level protocol elements:
1. a (repeated) start condition
2. a slave address/data direction byte
3. an (a no) acknowledge bit
4. a message byte
5. a stop condition
No-Acknowledge Bit
The no-acknowledge bit is generated when the receiver
does not drive SDATA LOW during the SCLK clock period
following a data transfer. A no-acknowledge bit is used to
terminate a read sequence.
Typical Sequence
A typical READ or WRITE sequence begins by the
master generating a start condition on the bus. After the start
condition, the master sends the 8−bit slave address/data
direction byte. The last bit indicates whether the request is
for a read or a write, where a “0” indicates a write and a “1”
indicates a read. If the address matches the address of the
slave device, the slave device acknowledges receipt of the
address by generating an acknowledge bit on the bus.
If the request was a WRITE, the master then transfers the
16−bit register address to which the WRITE should take
place. This transfer takes place as two 8−bit sequences and
the slave sends an acknowledge bit after each sequence to
indicate that the byte has been received. The master then
transfers the data as an 8−bit sequence; the slave sends an
acknowledge bit at the end of the sequence. The master stops
writing by generating a (re)start or stop condition.
If the request was a READ, the master sends the 8−bit
write slave address/data direction byte and 16−bit register
address, the same way as with a WRITE request. The master
then generates a (re)start condition and the 8−bit read slave
address/data direction byte, and clocks out the register data,
eight bits at a time. The master generates an acknowledge bit
after each 8−bit transfer. The slave’s internal register address
is automatically incremented after every 8 bits are
transferred. The data transfer is stopped when the master
sends a no−acknowledge bit.
The bus is idle when both SCLK and SDATA are HIGH.
Control of the bus is initiated with a start condition, and the
bus is released with a stop condition. Only the master can
generate the start and stop conditions.
Start Condition
A start condition is defined as a HIGH-to-LOW transition
on SDATA while SCLK is HIGH. At the end of a transfer, the
master can generate a start condition without previously
generating a stop condition; this is known as a “repeated
start” or “restart” condition.
Stop Condition
A stop condition is defined as a LOW-to-HIGH transition
on SDATA while SCLK is HIGH.
Data Transfer
Data is transferred serially, 8 bits at a time, with the MSB
transmitted first. Each byte of data is followed by an
acknowledge bit or a no-acknowledge bit. This data transfer
mechanism is used for the slave address/data direction byte
and for message bytes.
One data bit is transferred during each SCLK clock period.
SDATA can change when SCLK is LOW and must be stable
while SCLK is HIGH.
Slave Address/Data Direction Byte
Bits [7:1] of this byte represent the device slave address
and bit [0] indicates the data transfer direction. A “0” in
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23
AR0130CS
Single READ from Random Location
This sequence (Figure 20) starts with a dummy WRITE to
the 16-bit address that is to be used for the READ. The
master terminates the WRITE by generating a restart
condition. The master then sends the 8-bit read slave
address/data direction byte and clocks out one byte of
register data. The master terminates the READ by
generating a no-acknowledge bit followed by a stop
condition. Figure 20 shows how the internal register address
maintained by the AR0130 is loaded and incremented as the
sequence proceeds.
Previous Reg Address, N
S
Slave Address
0 A
S = Start Condition
P = Stop Condition
Sr = Restart Condition
A = Acknowledge
A = No-acknowledge
Reg
Address[15:8]
Reg Address, M
Reg
Address[7:0]
A
A Sr
Slave Address
1 A
M+1
Read Data
A
P
Slave to Master
Master to Slave
Figure 20. Single READ from Random Location
Single READ from Current Location
The master terminates the READ by generating
a no-acknowledge bit followed by a stop condition.
The figure shows two independent READ sequences.
This sequence (Figure 21) performs a read using the
current value of the AR0130 internal register address.
Previous Reg Address, N
S
Slave Address
1 A
Reg Address, N+1
Read Data
A P
S
Slave Address
N+2
1 A
Read Data
A P
Figure 21. Single READ from Current Location
Sequential READ, Start from Random Location
This sequence (Figure 22) starts in the same way as the
single READ from random location (Figure 20). Instead of
generating a no-acknowledge bit after the first byte of data
has been transferred, the master generates an acknowledge
bit and continues to perform byte READs until “L” bytes
have been read.
Previous Reg Address, N
S
Slave Address
0 A Reg Address[15:8]
M+1
Read Data
A Reg Address[7:0]
M+2
A
Read Data
Reg Address, M
M+3
A Sr
Slave Address
M+L−2
A
Read Data
1 A
M+L−1
A
Read Data
Figure 22. Sequential READ, Start from Random Location
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24
M+1
Read Data
M+L
A P
A
AR0130CS
Sequential READ, Start from Current Location
This sequence (Figure 23) starts in the same way as the
single READ from current location (Figure 21). Instead of
generating a no-acknowledge bit after the first byte of data
Previous Reg Address, N
S Slave Address 1 A
has been transferred, the master generates an acknowledge
bit and continues to perform byte READs until “L” bytes
have been read.
N+1
Read Data
A
N+2
Read Data
A
N+L−1
Read Data
A
N+L
Read Data
A
P
Figure 23. Sequential READ, Start from Current Location
Single WRITE to Random Location
then LOW bytes of the register address that is to be written.
The master follows this with the byte of write data.
The WRITE is terminated by the master generating a stop
condition.
This sequence (Figure 24) begins with the master
generating a start condition. The slave address/data
direction byte signals a WRITE and is followed by the HIGH
Previous Reg Address, N
S
Slave Address
0 A
Reg Address[15:8]
Reg Address, M
A
A
Reg Address[7:0]
M+1
A
A
Write Data
P
Figure 24. Single WRITE to Random Location
Sequential WRITE, Start at Random Location
has been transferred, the master generates an acknowledge
bit and continues to perform byte WRITEs until “L” bytes
have been written. The WRITE is terminated by the master
generating a stop condition.
This sequence (Figure 25) starts in the same way as the
single WRITE to random location (Figure 24). Instead of
generating a no-acknowledge bit after the first byte of data
Previous Reg Address, N
S
Slave Address
0 A
M+1
Write Data
Reg Address[15:8]
A
M+2
A
Write Data
Reg Address, M
Reg Address[7:0]
M+3
A
Write Data
M+L−2
A
Write Data
25
A
M+L−1
A
Figure 25. Sequential WRITE, Start at Random Location
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M+1
Write Data
M+L
A
A
P
AR0130CS
SPECTRAL CHARACTERISTICS
90
80
Quantum Efficiency (%)
70
60
50
40
30
20
10
0
350
450
550
650
750
850
950
1050
1150
Wavelength (nm)
Figure 26. Quantum Efficiency − Monochrome Sensor
80
re d
g re e n
blue
70
Quantum Efficiency (%)
60
50
40
30
20
10
0
350
400
450
500
550
600
650
700
750
800
850
900
Wavelength (nm)
Figure 27. Quantum Efficiency − Color Sensor
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26
950
1000
1050
1100
1150
AR0130CS
ELECTRICAL SPECIFICATIONS
Unless otherwise stated, the following specifications
apply to the following conditions:
VDD = 1.8 V –0.10/+0.15;
VDD_IO = VDD_PLL = VAA = VAA_PIX = 2.8 V ±0.3 V;
VDD_SLVS = 0.4 V –0.1/+0.2;
TA = −30°C to +70°C;
Output Load = 10 pF;
Frequency = 74.25 MHz.
Two-Wire Serial Register Interface
The electrical characteristics of the two-wire serial
register interface (SCLK, SDATA) are shown in Figure 28 and
Table 8.
SDATA
tLOW
tf
tSU;DAT
tr
tf
tHD;STA
tBUF
tr
SCLK
tHD;STA
tHD;DAT
S
NOTE:
tSU;STA
tHIGH
tSU;STO
Sr
P
S
Read sequence: For an 8-bit READ, read waveforms start after READ command and register address are issued.
Figure 28. Two-Wire Serial Bus Timing Parameters
Table 8. TWO-WIRE SERIAL BUS CHARACTERISTICS
(fEXTCLK = 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; TA = 25°C)
Standard Mode
Fast-Mode
Symbol
Min
Max
Min
Max
Unit
fSCL
0
100
0
400
kHz
tHD;STA
4.0
−
0.6
−
ms
LOW Period of the SCLK Clock
tLOW
4.7
−
1.3
−
ms
HIGH Period of the SCLK Clock
tHIGH
4.0
−
0.6
−
ms
Set-up Time for a Repeated
START Condition
tSU;STA
4.7
−
0.6
−
ms
Data Hold Time
tHD;DAT
0 (Note 4)
3.45 (Note 5)
0 (Note 6)
0.9 (Note 5)
ms
Data Set-up Time
tSU;DAT
250
−
100 (Note 6)
−
ns
Rise Time of both SDATA and
SCLK Signals
tr
−
1000
20 + 0.1Cb
(Note 7)
300
ns
Fall Time of both SDATA and SCLK
Signals
tf
−
300
20 + 0.1Cb
(Note 7)
300
ns
Set-up Time for STOP Condition
tSU;STO
4.0
−
0.6
−
ms
Parameter
SCLK Clock Frequency
After This Period, the First Clock
Pulse is Generated
1.
2.
3.
4.
I2C
This table is based on
standard (v2.1 January 2000). Philips Semiconductor.
Two-wire control is I2C-compatible.
All values referred to VIHmin = 0.9 VDD_IO and VILmax = 0.1 VDD_IO levels. Sensor EXTCLK = 27 MHz.
A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of
SCLK.
5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal.
6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This
will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW
period of the SCLK signal, it must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCLK line is released.
7. Cb = total capacitance of one bus line in pF.
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27
AR0130CS
Table 8. TWO-WIRE SERIAL BUS CHARACTERISTICS (continued)
(fEXTCLK = 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; TA = 25°C)
Standard Mode
Fast-Mode
Symbol
Min
Max
Min
Max
Unit
tBUF
4.7
−
1.3
−
ms
Capacitive Load for each Bus Line
Cb
−
400
−
400
pF
Serial Interface Input Pin Capacitance
CIN_SI
−
3.3
−
3.3
pF
CLOAD_SD
−
30
−
30
pF
RSD
1.5
4.7
1.5
4.7
kW
Parameter
Bus Free Time between a STOP
and START Condition
SDATA Max Load Capacitance
SDATA Pull-up Resistor
I2C
1.
2.
3.
4.
This table is based on
standard (v2.1 January 2000). Philips Semiconductor.
Two-wire control is I2C-compatible.
All values referred to VIHmin = 0.9 VDD_IO and VILmax = 0.1 VDD_IO levels. Sensor EXTCLK = 27 MHz.
A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of
SCLK.
5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal.
6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This
will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW
period of the SCLK signal, it must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCLK line is released.
7. Cb = total capacitance of one bus line in pF.
I/O Timing
By default, the AR0130 launches pixel data, FV and LV
with the falling edge of PIXCLK. The expectation is that the
user captures DOUT[11:0], FV and LV using the rising edge
of PIXCLK.
tR
See Figure 29 and Table 9 for I/O timing (AC)
characteristics.
tF
90%
10%
tRP
tFP
90%
90%
10%
10%
90%
10%
tEXTCLK
EXTCLK
PIXCLK
tPD
Data[11:0]
Pxl_0
Pxl_1
Pxl_2
Pxl_n
tPFL
tPLL
tPLH
tPFH
LINE_VALID/
FRAME_VALID
FRAME_VALID Leads LINE_VALID
by 6 PIXCLKs
FRAME_VALID Trails LINE_VALID
by 6 PIXCLKs
Figure 29. I/O Timing Diagram
Table 9. I/O TIMING CHARACTERISTICS (2.8 V VDD_IO) (Note 8)
Conditions: fPIXCLK = 74.25 MHz (720 P 60 fps) VDD_IO = 2.8 V;
Slew Rate Setting = 4 for PIXCLK; Slew Rate Setting = 7 for Parallel Ports
Symbol
Definition
Condition
Min
Typ
Max
Unit
fEXTCLK
Input Clock Frequency
PLL Enabled
6
−
50
MHz
tEXTCLK
Input Clock Period
PLL Enabled
20
−
166
ns
tR
Input Clock Rise Time
−
3
−
ns
tF
Input Clock Fall Time
−
3
−
ns
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28
AR0130CS
Table 9. I/O TIMING CHARACTERISTICS (2.8 V VDD_IO) (Note 8)
Conditions: fPIXCLK = 74.25 MHz (720 P 60 fps) VDD_IO = 2.8 V;
Slew Rate Setting = 4 for PIXCLK; Slew Rate Setting = 7 for Parallel Ports
Symbol
Min
Typ
Max
Unit
Input Clock Duty Cycle
45
50
55
%
tJITTER
(Note 9)
Input Clock Jitter at
27 MHz
−
600
−
ps
tcp
EXTCLK to PIXCLK
Propagation Delay
12
−
20
ns
fPIXCLK
PIXCLK Frequency
(Note 9)
6
−
74.25
MHz
tRP
PIXCLK Rise Time
Slew Rate Setting = 4
1.60
2.70
7.50
ns
tFP
PIXCLK Fall Time
Slew Rate Setting = 4
tPIXJITTER
Definition
Condition
Nominal Voltages, PLL Disabled,
PIXCLK Slew Rate = 4
1.50
2.60
7.20
ns
PIXCLK Duty Cycle
45
50
55
%
Jitter on PIXCLK
−
1
−
ns
tPD
PIXCLK to Data[11:0]
PIXCLK Slew Rate = 4, Parallel Slew Rate = 7
−2.5
−
3.5
ns
tPFH
PIXCLK to FV HIGH
PIXCLK Slew Rate = 4, Parallel Slew Rate = 7
−2.5
−
0.5
ns
tPLH
PIXCLK to LV HIGH
PIXCLK Slew Rate = 4, Parallel Slew Rate = 7
−3.0
−
0.0
ns
tPFL
PIXCLK to FV LOW
PIXCLK Slew Rate = 4, Parallel Slew Rate = 7
−2.5
−
0.5
ns
tPLL
PIXCLK to LV LOW
PIXCLK Slew Rate = 4, Parallel Slew Rate = 7
−3.0
−
0.0
ns
Output Load
Capacitance
−
10
−
pF
Input Pin Capacitance
−
2.5
−
pF
CLOAD
CIN
8. Minimum and maximum values are for the spec limits: 3.1 V, −30°C and 2.50 V, 70°C. All values are taken at the 50% transition point.
9. Jitter from PIXCLK is already taken into account as the data of all the output parameters.
Table 10. I/O TIMING CHARACTERISTICS (1.8 V VDD_IO) (Note 10)
Conditions: fPIXCLK = 74.25 MHz (720 P 60 fps) VDD_IO = 1.8 V;
Slew Rate Setting = 4 for PIXCLK; Slew Rate Setting = 7 for Parallel Ports
Symbol
Definition
Condition
Min
Typ
Max
Unit
fEXTCLK
Input Clock Frequency
PLL Enabled
6
−
50
MHz
tEXTCLK
Input Clock Period
PLL Enabled
20
−
166
ns
tR
Input Clock Rise Time
−
3
−
ns
tF
Input Clock Fall Time
−
3
−
ns
Input Clock Duty Cycle
45
50
55
%
tJITTER
(Note 11)
Input Clock Jitter at
27 MHz
−
600
−
ps
tcp
EXTCLK to PIXCLK
Propagation Delay
12
−
20
ns
fPIXCLK
PIXCLK Frequency
(Note 11)
74.25
MHz
Nominal Voltages, PLL Disabled,
Slew Setting = 4
6
tRP
Pixel Rise Time
Slew Rate Setting = 4
2.50
4.30
7.10
ns
tFP
Pixel Fall Time
Slew Rate Setting = 4
2.20
3.80
6.50
ns
PIXCLK Duty Cycle
PLL Enabled
45
50
55
%
tPIXJITTER
−
1
−
ns
tPD
Jitter on PIXCLK
PIXCLK to Data Valid
PIXCLK Slew Rate = 4, Parallel Slew Rate = 7
−4.5
−
2.0
ns
tPFH
PIXCLK to FV HIGH
PIXCLK Slew Rate = 4, Parallel Slew Rate = 7
−4.0
−
−0.5
ns
tPLH
PIXCLK to LV HIGH
PIXCLK Slew Rate = 4, Parallel Slew Rate = 7
−4.0
−
−0.5
ns
10. Minimum and maximum values are are for the spec limits: 1.95 V, −30°C and 1.70 V, 70°C. All values are taken at the 50% transition point.
11. Jitter from PIXCLK is already taken into account as the data of all the output parameters.
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29
AR0130CS
Table 10. I/O TIMING CHARACTERISTICS (1.8 V VDD_IO) (Note 10)
Conditions: fPIXCLK = 74.25 MHz (720 P 60 fps) VDD_IO = 1.8 V;
Slew Rate Setting = 4 for PIXCLK; Slew Rate Setting = 7 for Parallel Ports(continued)
Symbol
Definition
Condition
Min
Typ
Max
Unit
−
−0.5
ns
tPFL
PIXCLK to FV LOW
PIXCLK Slew Rate = 4, Parallel Slew Rate = 7
−4.0
tPLL
PIXCLK to LV LOW
PIXCLK Slew Rate = 4, Parallel Slew Rate = 7
CLOAD
CIN
−4.0
−
−0.5
ns
Output Load
Capacitance
−
10
−
pF
Input Pin Capacitance
−
2.5
−
pF
10. Minimum and maximum values are are for the spec limits: 1.95 V, −30°C and 1.70 V, 70°C. All values are taken at the 50% transition point.
11. Jitter from PIXCLK is already taken into account as the data of all the output parameters.
Table 11. I/O RISE SLEW RATE (2.8 V VDD_IO) (Note 12)
Parallel Slew (R0x306E[15:13])
Condition
Min
Typ
Max
Unit
7
Default
1.50
2.50
3.90
V/ns
6
Default
0.98
1.62
2.52
V/ns
5
Default
0.71
1.12
1.79
V/ns
4
Default
0.52
0.82
1.26
V/ns
3
Default
0.37
0.58
0.88
V/ns
2
Default
0.26
0.40
0.61
V/ns
1
Default
0.17
0.27
0.40
V/ns
0
Default
0.10
0.16
0.23
V/ns
12. Minimum and maximum values are taken at 70°C, 2.5 V and −30°C, 3.1 V. The loading used is 10 pF.
Table 12. I/O FALL SLEW RATE (2.8 V VDD_IO) (Note 13)
Parallel Slew (R0x306E[15:13])
Condition
Min
Typ
Max
Unit
7
Default
1.40
2.30
3.50
V/ns
6
Default
0.97
1.61
2.48
V/ns
5
Default
0.73
1.21
1.86
V/ns
4
Default
0.54
0.88
1.36
V/ns
3
Default
0.39
0.63
0.88
V/ns
2
Default
0.27
0.43
0.66
V/ns
1
Default
0.18
0.29
0.44
V/ns
0
Default
0.11
0.17
0.25
V/ns
13. Minimum and maximum values are taken at 70°C, 2.5 V and −30°C, 3.1 V. The loading used is 10 pF.
Table 13. I/O RISE SLEW RATE (1.8 V VDD_IO) (Note 14)
Parallel Slew (R0x306E[15:13])
Condition
Min
Typ
Max
Unit
7
Default
0.57
0.91
1.55
V/ns
6
Default
0.39
0.61
1.02
V/ns
5
Default
0.29
0.46
0.75
V/ns
4
Default
0.22
0.34
0.54
V/ns
3
Default
0.16
0.24
0.39
V/ns
2
Default
0.12
0.17
0.27
V/ns
1
Default
0.08
0.11
0.18
V/ns
0
Default
0.05
0.07
0.10
V/ns
14. Minimum and maximum values are taken at 70°C, 1.7 V and −30°C, 1.95 V. The loading used is 10 pF.
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AR0130CS
Table 14. I/O FALL SLEW RATE (1.8 V VDD_IO) (Note 15)
Parallel Slew (R0x306E[15:13])
Condition
Min
Typ
Max
Unit
7
Default
0.57
0.92
1.55
V/ns
6
Default
0.40
0.64
1.08
V/ns
5
Default
0.31
0.50
0.82
V/ns
4
Default
0.24
0.38
0.61
V/ns
3
Default
0.18
0.27
0.44
V/ns
2
Default
0.13
0.19
0.31
V/ns
1
Default
0.09
0.13
0.20
V/ns
0
Default
0.05
0.08
0.12
V/ns
15. Minimum and maximum values are taken at 70°C, 1.7 V and −30°C, 1.95 V. The loading used is 10 pF.
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AR0130CS
DC Electrical Characteristics
The DC electrical characteristics are shown in Table 15,
Table 16, Table 17, and Table 18.
Table 15. DC ELECTRICAL CHARACTERISTICS
Symbol
Definition
VDD
Condition
Min
Typ
Max
Unit
1.7
1.8
1.95
V
1.7/2.5
1.8/2.8
1.9/3.1
V
Core Digital Voltage
VDD_IO
I/O Digital Voltage
Analog Voltage
2.5
2.8
3.1
V
VAA_PIX
VAA
Pixel Supply Voltage
2.5
2.8
3.1
V
VDD_PLL
PLL Supply Voltage
2.5
2.8
3.1
V
VDD_SLVS
−
−
−
V
VIH
Input HIGH Voltage
VDD_IO * 0.7
–
–
V
VIL
Input LOW Voltage
–
–
VDD_IO * 0.3
V
IIN
Input Leakage Current
20
–
–
mA
VOH
Output HIGH Voltage
VDD_IO – 0.3
–
–
V
VOL
Output LOW Voltage
–
–
0.4
V
IOH
Output HIGH Current
At Specified VOH
–22
–
–
mA
IOL
Output LOW Current
At Specified VOL
–
–
22
mA
CAUTION:
Digital Supply Voltage
Do not connect.
No Pull-up Resistor;
VIN = VDD_IO or DGND
Stresses greater than those listed in Table 16 may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied.
Table 16. ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VSUPPLY
Power Supply Voltage (All Supplies)
ISUPPLY
Total Power Supply Current
Minimum
Maximum
Unit
–0.3
4.5
V
–
200
mA
IGND
Total Ground Current
–
200
mA
VIN
DC Input Voltage
–0.3
VDD_IO + 0.3
V
VOUT
DC Output Voltage
–0.3
VDD_IO + 0.3
V
TSTG
Storage Temperature (Note 16)
–40
+85
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
16. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
17. To keep dark current and shot noise artifacts from impacting image quality, keep operating temperature at a minimum.
Table 17. OPERATING CURRENT CONSUMPTION IN PARALLEL OUTPUT
(Operating currents are measured at the following conditions: VAA = VAA_PIX = VDD_IO = VDD_PLL = 2.8 V; VDD = 1.8 V;
PLL Enabled and PIXCLK = 74.25 MHz; TA = 25°C)
Symbol
IDD1
Parameter
Condition
Min
Typ
Max
Unit
Digital Operating Current
Streaming, 1280 x 960 45 fps
−
40
65
mA
I/O Digital Operating Current
Streaming, 1280 x 960 45 fps
−
35
–
mA
Analog Operating Current
Streaming, 1280 x 960 45 fps
−
30
55
mA
IAA_PIX
Pixel Supply Current
Streaming, 1280 x 960 45 fps
−
10
15
mA
IDD_PLL
PLL Supply Current
Streaming, 1280 x 960 45 fps
−
7
−
mA
Digital Operating Current
Streaming, 720p 60 fps
−
40
−
mA
I/O Digital Operating Current
Streaming, 720p 60 fps
−
35
–
mA
Analog Operating Current
Streaming, 720p 60 fps
−
30
−
mA
IDD_IO
IAA
IDD1
IDD_IO
IAA
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32
AR0130CS
Table 17. OPERATING CURRENT CONSUMPTION IN PARALLEL OUTPUT (continued)
(Operating currents are measured at the following conditions: VAA = VAA_PIX = VDD_IO = VDD_PLL = 2.8 V; VDD = 1.8 V;
PLL Enabled and PIXCLK = 74.25 MHz; TA = 25°C)
Symbol
Parameter
IAA_PIX
Pixel Supply Current
IDD_PLL
PLL Supply Current
Condition
Min
Typ
Max
Unit
Streaming, 720p 60 fps
−
10
15
mA
Streaming, 720p 60 fps
−
7
−
mA
Table 18. STANDBY CURRENT CONSUMPTION
(Analog − VAA + VAA_PIX + VDD_PLL; Digital − VDD + VDD_IO + VDD_SLVS)
Definition
Condition
Min
Analog, 2.8 V
Digital, 1.8 V
Analog, 2.8 V
Digital, 1.8 V
Soft Standby (Clock Off)
Soft Standby (Clock On)
Digital, 1.8 V
Hard Standby (Clock Off)
Hard Standby (Clock On)
Typ
Max
Unit
–
70
200
mA
–
640
900
mA
–
275
−
mA
–
1.55
−
mA
Analog, 2.8 V
–
70
200
mA
Digital, 1.8 V
–
640
900
mA
Analog, 2.8 V
–
275
−
mA
–
1.55
−
mA
70
60
PSRR (dB)
50
40
30
20
10
0
1,000
10,000
100,000
Frequency (Hz)
Figure 30. Power Supply Rejection Ratio
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33
1,000,000
AR0130CS
POWER-ON RESET AND STANDBY TIMING
Power-Up Sequence
The recommended power-up sequence for the AR0130 is
shown in Figure 31. The available power supplies (VDD_IO,
VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have
the separation specified below.
1. Turn on VDD_PLL power supply.
2. After 0−10 ms, turn on VAA and VAA_PIX power
supply.
3. After 0−10 ms, turn on VDD power supply.
4. After 0−10 ms, turn on VDD_IO power supply.
VDD_PLL (2.8)
5. After the last power supply is stable, enable
EXTCLK.
6. Assert RESET_BAR for at least 1 ms.
7. Wait 150,000 EXTCLKs (for internal initialization
into software standby).
8. Configure PLL, output, and image settings to
desired values.
9. Wait 1 ms for the PLL to lock.
10. Set streaming mode (R0x301a[2] = 1).
t0
VAA_PIX
VAA (2.8)
t1
t2
VDD (1.8)
VDD_IO (1.8/2.8)
t3
VDD_SLVS
EXTCLK
t4
RESET_BAR
t5
tX
Hard
Reset
t6
Internal Initialization
Software
Standby
PLL Clock
Streaming
Figure 31. Power Up
Table 19. POWER-UP SEQUENCE
Symbol
Definition
Min
Typ
Max
Unit
t0
VDD_PLL to VAA/VAA_PIX (Note 20)
0
10
–
ms
t1
VAA/VAA_PIX to VDD
0
10
–
ms
t2
VDD to VDD_IO
0 (Note 21)
10
–
ms
t3
VDD_IO to VDD_SLVS
0
10
–
ms
tX
Xtal Settle Time
–
30 (Note 18)
–
ms
t4
Hard Reset
1 (Note 19)
–
–
ms
t5
Internal Initialization
150,000
–
–
EXTCLKs
t6
PLL Lock Time
1
–
–
ms
18. Xtal settling time is component-dependent, usually taking about 10–100 ms.
19. Hard reset time is the minimum time required after power rails are settled. In a circuit where hard reset is held down by RC circuit, then the
RC time must include the all power rail settle time and Xtal settle time.
20. It is critical that VDD_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the
others. If the case happens that VDD_PLL is powered after other supplies then the sensor may have functionality issues and will experience
high current draw on this supply.
21. For the case where VDD_IO is 2.8 V and VDD is 1.8 V, it is recommended that the minimum time be 5 ms.
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34
AR0130CS
Power-Down Sequence
The recommended power-down sequence for the AR0130
is shown in Figure 32. The available power supplies
(VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX)
must have the separation specified below.
1. Disable streaming if output is active by setting
standby R0x301a[2] = 0.
2. The soft standby state is reached after the current
row or frame, depending on configuration, has
ended.
3. Turn off VDD_SLVS, if used.
4. Turn off VDD_IO.
5. Turn off VDD.
6. Turn off VAA/VAA_PIX.
7. Turn off VDD_PLL.
VDD_SLVS
t0
VDD_IO (1.8/2.8)
t1
VDD (1.8)
t2
VAA_PIX
VAA (2.8)
t3
VDD_PLL (2.8)
EXTCLK
t4
Power Down until Next
Power Up Cycle
Figure 32. Power Down
Table 20. POWER-DOWN SEQUENCE
Symbol
Parameter
Min
Typ
Max
Unit
t0
VDD_SLVS to VDD_IO
0
–
–
ms
t1
VDD_IO to VDD
0
–
–
ms
t2
VDD to VAA/VAA_PIX
0
–
–
ms
t3
VAA/VAA_PIX to VDD_PLL
0
–
–
ms
t4
PwrDn until Next PwrUp Time
100
–
–
ms
22. t4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged.
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35
AR0130CS
PACKAGE DIMENSIONS
PLCC48 11.43x11.43
CASE 776AL
ISSUE O
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36
AR0130CS
PACKAGE DIMENSIONS
ILCC48 10x10
CASE 847AB
ISSUE O
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37
AR0130CS
PACKAGE DIMENSIONS
ILCC48 10x10
CASE 847AC
ISSUE O
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38
AR0130CS
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AR0130CS/D