GA10JT12-CAL Normally – OFF Silicon Carbide Junction Transistor VDS RDS(ON) ID (Tc = 25°C) hFE (Tc = 25°C) Features = = = = 1200 V 120 mΩ 25 A 80 Package 250 °C Maximum Operating Temperature Gate Oxide Free SiC Switch Exceptional Safe Operating Area Excellent Gain Linearity Temperature Independent Switching Performance Low Output Capacitance Positive Temperature Coefficient of RDS,ON Suitable for Connecting an Anti-parallel Diode D G S Advantages Applications Compatible with Si MOSFET/IGBT Gate Drive ICs > 20 µs Short-Circuit Withstand Capability Lowest-in-class Conduction Losses High Circuit Efficiency Minimal Input Signal Distortion High Amplifier Bandwidth Down Hole Oil Drilling, Geothermal Instrumentation Hybrid Electric Vehicles (HEV) Solar Inverters Switched-Mode Power Supply (SMPS) Power Factor Correction (PFC) Induction Heating Uninterruptible Power Supply (UPS) Motor Drives Table of Contents Section I: Absolute Maximum Ratings .......................................................................................................... 1 Section II: Static Electrical Characteristics................................................................................................... 2 Section III: Dynamic Electrical Characteristics ............................................................................................ 2 Section IV: Figures .......................................................................................................................................... 3 Section V: GA10JT12-CAL Gate Drive Theory of Operation ....................................................................... 5 Section VI: Mechanical Parameters ............................................................................................................... 6 Section VII: Chip Dimensions ......................................................................................................................... 6 Section VIII: SPICE Model Parameters .......................................................................................................... 8 Section I: Absolute Maximum Ratings Parameter Drain – Source Voltage Continuous Drain Current Continuous Drain Current Continuous Gate Current Symbol VDS ID ID IG Turn-Off Safe Operating Area RBSOA Short Circuit Safe Operating Area SCSOA Reverse Gate – Source Voltage Reverse Drain – Source Voltage Power Dissipation Storage Temperature VSG VSD Ptot Tstg Sept 2014 Conditions VGS = 0 V TC = 25°C TC = 155°C TVJ = 250 oC, Clamped Inductive Load TVJ = 250 oC, IG = 1 A, VDS = 800 V, Non Repetitive TC = 25 °C / 155 °C, tp > 100 ms Value 1200 25 10 1.3 ID,max = 10 @ VDS ≤ VDSmax Unit V A A A >20 µs 30 25 170 / 22 -55 to 250 V V W °C http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/ Notes A Pg1 of 7 GA10JT12-CAL Section II: Static Electrical Characteristics Parameter Symbol Conditions Min. Value Typical Max. Unit Notes mΩ Fig. 5 V Fig. 4 – Fig. 5 μA Fig. 6 A: On State Drain – Source On Resistance RDS(ON) ID = 10 A, Tj = 25 °C ID = 10 A, Tj = 125 °C ID = 10 A, Tj = 175 °C Gate On Voltage VGS,ON ID = 10 A, VDS = 30 V, Tj = 25 °C ID = 10 A, VDS = 30 V, Tj = 175 °C hFE VDS = 5 V, ID = 10 A, Tj = 25 °C VDS = 5 V, ID = 10 A, Tj = 125 °C VDS = 5 V, ID = 10 A, Tj = 175 °C Drain Leakage Current IDSS VDS = 1200 V, VGS = 0 V, Tj = 25 °C VDS = 1200 V, VGS = 0 V, Tj = 125 °C VDS = 1200 V, VGS = 0 V, Tj = 175 °C Gate Leakage Current ISG VSG = 20 V, Tj = 25 °C DC Current Gain 120 164 208 3.5 3.2 80 56 50 B: Off State 1 1 10 20 nA Section III: Dynamic Electrical Characteristics Parameter Symbol Input Capacitance Reverse Transfer/Output Capacitance Output Capacitance Stored Energy Effective Output Capacitance, time related Effective Output Capacitance, energy related Gate-Source Charge Gate-Drain Charge Gate Charge - Total Internal Gate Resistance – zero bias Internal Gate Resistance – ON Sept 2014 Ciss Crss/Coss EOSS Conditions Min. VGS = 0 V, VDS = 800 V, f = 1 MHz VDS = 800 V, f = 1 MHz VGS = 0 V, VDS = 800 V, f = 1 MHz Value Typical 1403 30 9 Max. Unit Notes pF pF µJ Fig. 9 Fig. 9 Fig. 10 Coss,tr ID = constant, VGS = 0 V, VDS = 0…800 V 55 pF Coss,er VGS = 0 V, VDS = 0…800 V 40 pF QGS QGD QG VGS = -5…3 V VGS = 0 V, VDS = 0…800 V 11 44 55 nC nC nC 2.6 Ω 0.19 Ω f = 1 MHz, V = 50 mV, V = 0 V, DS RG(INT-ZERO) V = 0 V, T AC GS j = 175 ºC RG(INT-ON) VGS > 2.5 V, VDS = 0 V, Tj = 175 ºC http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/ Pg2 of 7 GA10JT12-CAL Section IV: Figures Figure 1: Typical Output Characteristics at 25 °C Figure 2: Typical Output Characteristics at 125 °C Figure 3: Typical Output Characteristics at 175 °C Figure 4: Drain-Source Voltage vs. Gate Current Figure 5: DC Current Gain and Normalized On-Resistance vs. Temperature Figure 6: DC Current Gain vs. Drain Current Sept 2014 http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/ Pg3 of 7 GA10JT12-CAL Figure 7: Typical Transfer Characteristics Figure 8: Typical Blocking Characteristics Figure 9: Input, Output, and Reverse Transfer Capacitance Figure 10: Output Capacitance Stored Energy Sept 2014 http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/ Pg4 of 7 GA10JT12-CAL Section V: GA10JT12-CAL Gate Drive Theory of Operation The SJT transistor is a current controlled transistor which requires a positive gate current for turn-on as well as to remain in on-state. An ideal gate current waveform for ultra-fast switching of the SJT, while maintaining low gate drive losses, is shown in Figure 11. Figure 11: Idealized Gate Current Waveform A: Gate Currents, IG,pk/-IG,pk and Voltages during Turn-On and Turn-Off An SJT is rapidly switched from its blocking state to on-state, when the necessary gate charge, QG, for turn-on is supplied by a burst of high gate current, IG,on, until the gate-source capacitance, CGS, and gate-drain capacitance, CGD, are fully charged. , As an example, an IG,pon ≥ 2.5 A is required to achieve a 18 ns VDS fall time for a 800 V switching transition, due to the gate-drain charge, QGD of 44 nC for the GA10JT12-CAL. The IG,pon pulse should ideally terminate, when the drain voltage falls to its on-state value, in order to avoid unnecessary drive losses during the steady on-state. In practice, the rise time of the IG,on pulse is affected by the parasitic inductances, Lpar in the TO-247 package and drive circuit. A voltage developed across the parasitic inductance in the source path, Ls, can de-bias the gate-source junction, when high drain currents begin to flow through the device. The applied gate voltage should be maintained high enough, above the VGS,ON (see Figure 7) level to counter these effects. A high negative peak current, -IG,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from the gate, and achieve rapid turn-off. While satisfactory turn off can be achieved with VGS = 0 V, a negative gate voltage VGS may be used in order to speed up the turn-off transition. B: Steady On-State After the device is turned on, IG may be advantageously lowered to IG,steady for reducing unnecessary gate drive losses. The IG,steady is determined by noting the DC current gain, hFE, of the device from Figures 5 and 6. The desired IG,steady is determined by the peak device junction temperature TJ during operation, drain current ID, DC current gain hFE, and a 50 % safety margin to ensure operating the device in the saturation region with low on-state voltage drop by the equation: , Sept 2014 , 1.5 http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/ Pg5 of 7 GA10JT12-CAL Section VI: Mechanical Parameters 2.10 x 2.10 mm 2 83 x 83 mil 2 4.41/3.31 mm 2 6836/5134 mil 2 Thickness 360 µm 14 mil Wafer Size 100 mm 3937 mil 0 deg 0 deg Raster Size Area total / active Flat Position Passivation frontside Polyimide Pad Metal (Anode) 4000 nm Al Backside Metal (Cathode) 400 nm Ni + 200 nm Au -system Die Bond Electrically conductive glue or solder Wire Bond Al ≤ 10 mil (Source) Al ≤ 3 mil (Gate) Reject ink dot size Φ ≥ 0.3 mm Recommended storage environment Store in original container, in dry nitrogen, < 6 months at an ambient temperature of 23 °C Section VII: Chip Dimensions DIE SOURCE WIREBONDABLE GATE WIREBONDABLE mm mil A 2.10 83 B 2.10 83 C 1.47 58 D 1.52 60 E 0.17 7 F 0.40 16 G 0.30 12 H 0.30 12 NOTE 1. CONTROLLED DIMENSION IS INCH. DIMENSION IN BRACKET IS MILLIMETER. 2. DIMENSIONS DO NOT INCLUDE END FLASH, MOLD FLASH, MATERIAL PROTRUSIONS Sept 2014 http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/ Pg6 of 7 GA10JT12-CAL Revision History Date Revision Comments 2014/09/12 0 Initial release Supersedes Published by GeneSiC Semiconductor, Inc. 43670 Trade Center Place Suite 155 Dulles, VA 20166 GeneSiC Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice. GeneSiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any intellectual property rights is granted by this document. Unless otherwise expressly indicated, GeneSiC products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal injury and/or property damage. Sept 2014 http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/ Pg7 of 7 GA10JT12-CAL Section VIII: SPICE Model Parameters This is a secure document. Please copy this code from the SPICE model PDF file on our website (http://www.genesicsemi.com/images/products_sic/sjt/GA10JT12-CAL_SPICE.pdf) into LTSPICE (version 4) software for simulation of the GA10JT12-CAL. * MODEL OF GeneSiC Semiconductor Inc. * * $Revision: 2.0 $ * $Date: 12-SEP-2014 $ * * GeneSiC Semiconductor Inc. * 43670 Trade Center Place Ste. 155 * Dulles, VA 20166 * * COPYRIGHT (C) 2014 GeneSiC Semiconductor Inc. * ALL RIGHTS RESERVED * * These models are provided "AS IS, WHERE IS, AND WITH NO WARRANTY * OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED * TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE." * Models accurate up to 2 times rated drain current. * .model GA10JT12 NPN + IS 5.00E-47 + ISE 1.26E-28 + EG 3.23 + BF 85 + BR 0.55 + IKF 5000 + NF 1 + NE 2 + RB 4.67 + IRB 0.001 + RBM 0.16 + RE 0.005 + RC 0.099 + CJC 427.39E-12 + VJC 3.1004 + MJC 0.4752 + CJE 1373E-12 + VJE 10.6442 + MJE 0.21376 + XTI 3 + XTB -1.27 + TRC1 6.8E-3 + VCEO 1200 + ICRATING 10 + MFG GeneSiC_Semiconductor * * End of GA10JT12 SPICE Model Sept 2014 http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/ Pg1 of 1