Holtek HT82V38 16-bit ccd/cis analog signal processor Datasheet

HT82V38
16-Bit CCD/CIS Analog Signal Processor
Features
· Operating voltage: 3.3V (typ.)
· Internal voltage reference
· Low Power CMOS: 300 mW (typ.)
· Multiplexed byte-wide output (8+8 format)
· Power-Down Mode: 10mA (max.)
· Programmable 3-wire serial interface
· 16-Bit 30 MSPS A/D converter
· 3 .3V digital I/O compatibility
· Guaranteed won¢t miss codes
· 3-Channel operation up to 30 MSPS
· 1~5.85x programmable gain
· 2-Channel (even-odd) operation up to 30 MSPS
· Correlated double sampling
· 1-Channel operation up to 20 MSPS
· ±250 mV programmable offset
· 28-pin SSOP (209mil) package
· Input clamp circuitry
Applications
· Flatbed document scanners
· Digital color copiers
· Film scanners
· Multifunction peripherals
General Description
The 16-bit digital output is multiplexed into an 8-bit output word that is accessed using two read cycles. The internal registers are programmed through a 3-wire serial
interface, and provide adjustment of the gain, offset, and
operating mode.
The HT82V38 is a complete analog signal processor for
CCD imaging applications. It features a 3 channel architecture designed to sample and condition the outputs of
trilinear color CCD arrays. Each channel consists of an
input clamp, Correlated Double Sampler (CDS), offset
DAC and Programmable Gain Amplifier (PGA), multiplexed to a high performance 16-bit A/D converter.
The CDS amplifiers may be disabled for use with sensors such as Contact Image Sensors (CIS) and CMOS
active pixel sensors, which do not require CDS.
Block Diagram
A V D D
V IN R
A V S S
R E F T
R E F B
+
A V D D
C D S
A V S S
D V D D
P G A
O E
9 - B it
D A C
V IN G
+
B A N D G A P
R e fe re n c e
C D S
C D S
O F F S E T
C D S C L K 1
Rev. 1.00
1 6
1 6 :8
M U X
8
D O U T
+
C o n fig u r a tio n
R e g is te r
M U X
R e g is te r
P G A
6
In p u t
C la m p
B ia s
1 6 - B it
A D C
3 .1
M U X
P G A
9 - B it
D A C
V IN B
D V S S
9 - B it
D A C
9
R E D
G R E E N
B L U E
R E D
G R E E N
B L U E
G a in
R e g is te r s
D ig ita l
C o n tro l
In te rfa c e
S C L K
S L O A D
S D A T A
O ffs e t
R e g is te r s
C D S C L K 2
A D C C L K
1
July 23, 2009
HT82V38
Pin Assignment
C D S C L K 1
1
2 8
A V D D
C D S C L K 2
2
2 7
A V S S
A D C C L K
3
2 6
V IN R
O E
4
2 5
O F F S E T
D V D D
5
2 4
V IN G
D V S S
6
2 3
C M L
D 7 (M S B )
7
2 2
V IN B
D 6
8
2 1
R E F T
D 5
9
2 0
R E F B
D 4
1 0
1 9
A V S S
D 3
1 1
1 8
A V D D
D 2
1 2
1 7
S L O A D
D 1
1 3
1 6
S C L K
D 0 (L S B )
1 4
1 5
S D A T A
H T 8 2 V 3 8
2 8 S S O P -A
Pin Description
Pin No.
Pin Name
I/O
Description
1
CDSCLK1
DI
CDS Reference Clock Pulse Input
2
CDSCLK2
DI
CDS Data Clock Pulse Input
3
ADCCLK
DI
A/D Sample Clock Input for 3-channels Mode
4
OE
DI
Output Enable, Active Low
Internal pull-low 50W
5
DVDD
P
Digital Power
6
DVSS
P
Digital Ground
7~14
D7~D0
DO
15
SDATA
DI/DO
16
SCLK
DI
17
SLOAD
DI
Serial Interface Load Pulse
18, 28
AVDD
P
Analog Supply
19, 27
AVSS
P
Analog Ground
20
REFB
AO
Reference Decoupling
21
REFT
AO
Reference Decoupling
Digital Data Output
Serial Data Input/Output
Clock Input for Serial Interface
22
VINB
AI
Analog Input, Blue
23
CML
AO
Internal Reference Output
24
VING
AI
Analog Input, Green
25
OFFSET
AO
Clamp Bias Level Decoupling
26
VINR
AI
Analog Input, Red
Note:
AI=Analog Input, AO=Analog Output, DI=Digital Input, DO=Digital Output, P=Power
Rev. 1.00
2
July 23, 2009
HT82V38
Absolute Maximum Ratings
Supply Voltage ..........................VSS-0.3V to VSS+4.3V
Storage Temperature ...........................-50°C to 125°C
Input Voltage .............................VSS-0.3V to VDD+0.3V
Operating Temperature ..............................0°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
Parameter
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
Logic Inputs
VIH
High Level Input Voltage
¾
¾
0.8VDD
¾
¾
V
VIL
Low Level Input Voltage
¾
¾
¾
¾
0.2VDD
V
IIH
High Level Input Current
¾
¾
¾
¾
1
mA
IIL
Low Level Input Current
¾
¾
¾
¾
1
mA
CIN
Input Capacitance
¾
¾
¾
5
¾
pF
Logic Outputs
VOH
High Level Output Voltage
¾
IOH=3mA
DVDD-0.5
¾
¾
V
VOL
Low Level Output Voltage
¾
IOL=3mA
¾
¾
0.5
V
Min.
Typ.
Max.
Unit
A.C. Characteristics
Symbol
Parameter
Test Conditions
VDD
Conditions
Power Supplies
AVDD
AVDD
¾
¾
3.15
3.3
3.45
V
DVDD
DVDD
¾
¾
3.15
3.3
3.45
V
3-channel Mode with CDS
¾
¾
30
¾
¾
MPS
2-channel Mode with CDS
¾
¾
30
¾
¾
MPS
1-channel Mode with CDS
¾
¾
20
¾
¾
MPS
ADC Resolution
¾
¾
¾
16
¾
Bits
Integral Nonlinear (INL)
¾
¾
¾
±32
¾
LSB
Differential Nonlinear (DNL)
¾
¾
-1
¾
+1
mV
Offset Error
¾
¾
-100
¾
+100
mV
Gain Error
¾
¾
¾
5
¾
%FSR
Maximum Conversion Rate
tMAX
Accuracy (Entire Signal Path)
Rev. 1.00
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July 23, 2009
HT82V38
Symbol
Parameter
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
Analog Inputs
RFS
Full-scale Input Range
¾
¾
¾
1.6/2.0
¾
V
Vi
Input Limits
¾
¾
AVSS-0.3
¾
AVDD+0.3
V
Ci
Input Capacitance
¾
¾
¾
10
¾
pF
Ii
Input Current
¾
¾
¾
10
¾
mA
PGA Gain at Minimum
¾
¾
¾
1
¾
V/V
PGA Gain at Maximum
¾
¾
¾
5.85
¾
V/V
PGA Gain Resolution
¾
¾
¾
6
¾
Bits
Programmable Offset at Minimum
¾
¾
¾
-250
¾
mV
Programmable Offset at Maximum
¾
¾
¾
250
¾
mV
Offset Resolution
¾
¾
¾
9
¾
Bits
¾
¾
¾
4
¾
Bits
Clamp DAC output voltage at code 0
¾
0.45
¾
V
Clamp DAC output voltage at code F
¾
2.7
¾
V
Clamp DAC Step size
¾
0.15
¾
V/Step
-50
¾
50
mV
Amplifiers
Clamp DAC Circuit
tA
Clamp DAC resolution
Clamp DAC deviation (AVDD=3.300V)
Temperature Range
tA
Operating
¾
¾
0
¾
70
°C
¾
¾
¾
300
¾
mW
Power Consumption
Ptot
Total Power Consumption
Timing Specification
Symbol
AVDD=DRVDD=3.3V, AVSS=DRVSS=0V, Ta=25°C, ADCCLK=30MHz unless otherwise stated
Parameter
Min.
Typ.
Max.
Unit
Clock Parameters
tPRA
3-Channel Pixel Rate
100
¾
¾
ns
tPRB
2-Channel Pixel Rate
66
¾
¾
ns
tPRC
1-Channel Pixel Rate
50
¾
¾
ns
tADCLK
ADCCLK Pulse Width
16
¾
¾
ns
tC1
CDSCLK1 Pulse Width
10
¾
¾
ns
tC2
CDSCLK2 Pulse Width
10
¾
¾
ns
tC1C2
CDSCLK1 Falling to CDSCLK2 Rising
0
¾
¾
ns
tADC2
ADCCLK Falling to CDSCLK2 Rising
2
¾
¾
ns
tC2ADR
CDSCLK2 Rising to ADCCLK Rising
2
¾
¾
ns
tC2ADF
CDSCLK2 Falling to ADCCLK Falling
20
¾
¾
ns
tADC1
ADCCLK Falling to CDSCLK1 Rising
0
¾
¾
ns
tAD
Aperture Delay for CDS Clocks
¾
3
¾
ns
Rev. 1.00
4
July 23, 2009
HT82V38
Symbol
Parameter
Min.
Typ.
Max.
Unit
Serial Interface
fSCLK
Maximum SCLK Frequency
10
¾
¾
MHz
tLS
SLOAD to SCLK Setup Time
10
¾
¾
ns
tLH
SCLK to SLOAD Hold Time
10
¾
¾
ns
tDS
SDATA to SCLK Rising Setup Time
10
¾
¾
ns
tDH
SCLK Rising to SDATA Hold Time
10
¾
¾
ns
tRDV
SCLK Falling to SDATA Valid
10
¾
¾
ns
Output Delay (output load 10pF)
¾
10
¾
ns
Latency (Pipeline Delay)
¾
9
¾
Cycles
Data Output
tOD
Functional Description
Integral Nonlinear (INL)
Gain Error
Integral nonlinearity error refers to the deviation of each
individual code from a line drawn from ²zero scale²
through ²positive full scale². The point used as ²zero
scale² occurs 1/2 LSB before the first code transition.
²Positive full scale² is defined as a level 1/2 LSB beyond
the last code transition. The deviation is measured from
the middle of each particular code to the true straight
line.
The last code transition should occur for an analog
va l u e 1 /2 L S B b e l o w t h e f u l l - sca l e vo l t a g e
(2´(REFT-REFB)). Gain error is the deviation of the actual difference between first and last code transitions
and the ideal difference between the first and last code
transitions.
Aperture Delay
The aperture delay is the time delay that occurs from
when a sampling edge is applied to the HT82V38 until
the actual sample of the input signal is held. Both
CDSCLK1 and CDSCLK2 sample the input signal during the transition from high to low, so the aperture delay
is measured from each clock¢s falling edge to the instant
the actual internal sample is taken.
Differential Nonlinear (DNL)
An ideal ADC exhibits code transitions that are exactly 1
LSB apart. DNL is the deviation from this ideal value.
Thus every code must have a finite width. No missing
codes guaranteed to 16-bit resolution indicates that all
4096 codes, respectively, must be present over all operating ranges.
Offset Error
The first ADC code transition should occur at a level 1/2
LSB above the nominal zero scale voltage. The offset
error is the deviation of the actual first code transition
level from the ideal level.
Rev. 1.00
5
July 23, 2009
HT82V38
Internal Register Descriptions
Address
Data Bits
Register
Name
A2
A1
A0
D8
D7
D6
D5
D4
D3
D2
Configuration
0
0
0
0
0
Clamp
Int
3
CH
CDS
on
0
Pwr Dn
MUX
0
0
1
0
RGB/
BGR
ClapC[3]
ClapC[2]
Red PGA
0
1
0
0
0
0
MSB
LSB
Green PGA
0
1
1
0
0
0
MSB
LSB
Blue PGA
1
0
0
0
0
0
MSB
LSB
Red Offset
1
0
1
MSB
LSB
Green Offset
1
1
0
MSB
LSB
Blue Offset
1
1
1
MSB
LSB
Red Green Blue
D1
D0
Full scale
1byte out
input range
ClapC[1]
ClapC[0]
Internal Register Map
Configuration Register
The Configuration Register controls the HT82V38¢s operating mode and bias levels. Bits D6 controls reference clamp
voltage. Setting this bit low change OFFSET to high-Z, allowing OFFSET to be driven from external power source. Bit
D5 will configure the HT82V38 for the 3-Channel (high) mode of operation. Setting Bit D4 high will enable the CDS
mode of operation, and setting this bit low will enable the SHA mode of operation. Bit D3 should always be set low. Bit
D2 controls the power-down mode. Setting Bit D2 high will place the HT82V38 into a very low power ²sleep² mode. All
register contents are retained while the HT82V38 is in the powered-down state. Bit D1 controls full-scale input range.
D1=1, full scale input range will be 2V, D1=0 full scale input range will be 1.6V. Bit D0 controls the output mode of the
HT82V38. Setting bit D0 high will enable a single byte output mode where only 8 MSBs of the 16-bit ADC will be output.
If bit D0 is set low, then the 16-bit ADC output is multiplexed into two bytes.
D8
Set
to
0
D7
Set
to
0
D6
D5
D4
D3
D2
D1
D0
ClampInt
3 Channels
CDS
operation
¾
Power-down
Full scale
input range
1 byte out
1=Internal*
1=On*
1=CDS mode*
¾
1=On
1=2V
1=On
0*
0=Off
(Normal)*
0=1.6V*
0=Off *
0=External
0=Off
0=SHA mode
Note: * Power-on default value
Configuration Register Settings
Rev. 1.00
6
July 23, 2009
HT82V38
MUX Register
The MUX Register controls the sampling channel order in the HT82V38. Bits D8 should always be set low. Bit D7 is
used when operating in 3-Channel Mode. Setting Bit D7 high will sequence the MUX to sample the red channel first,
then the green channel, and then the blue channel. When in this mode, the CDSCLK2 rising edge always resets the
MUX to sample the red channel first (see Timing Figure). When Bit D7 is set low, the channel order is reversed to blue
first, green second, and red third. The CDSCLK2 rising edge pulse will always reset the MUX to sample the blue channel first. Bits D6, D5, and D4 are used when operating in 1-Channel Mode. Bit D6 is set high to sample the red channel.
Bit D5 is set high to sample the green channel. Bit D4 is set high to sample the blue channel. The MUX will remain stationary during 1-Channel Mode. Bit D3 to Bit D0 control 4 bits DAC clamp voltage from 0.45V to 2.7V.
D8
Set
to
0
D7
D6
D5
D4
D3
D2
D1
D0
3-Channel
1-Channel
1-Channel
1-Channel
Clap[3]
Clap[2]
Clap[1]
Clap[0]
1=R-G-B*
0=B-G-R
1=RED*
0=Off
1=GREEN
0=Off*
1111=2.7V*
1110=2.55V
:
:
0001=0.6V
0000=0.45V
1=BLUE
0=Off *
Note: * Power-on default value
MUX Register Settings
PGA Gain Register
There are three PGA registers for individually programming the gain in the red, green, and blue channels. Bits D8, D7,
and D6 in each register must be set low, and bits D5 through D0 control the gain range in 64 increments. See Figure for
a graph of the PGA Gain versus PGA register code. The coding for the PGA registers is straight binary, with an all ²zeros² word corresponding to the minimum gain setting (1x) and an all ²ones² word corresponding to the maximum gain
setting (5.85x).
The PGA has a gain range from 1´(0dB) to 5.85´(15.3dB), adjustable in 64 steps. The Figure shows the PGA gain as a
function of the PGA register code. Although the gain curve is approximately linear in dB, the gain in V/V varies in nonlinear proportion with the register code, according to the following the equation:
76
76 - G
Gain=
Where ²G² is the decimal value of the gain register contents, and varies from 0 to 63.
5 .8 5
1 5 .3 4
5 .0
4 .0
6
3 .0
3
2 .0
G A IN -d B (
9
G A IN -V /V (
)
)
1 2
1 .0
0
0
4
8
1 2
1 6
2 0
2 4
2 8
3 2
3 6
4 0
4 4
4 8
5 2
5 6
6 0 6 3
P G A r e g is te r v a lu e - - D e c im a l
PGA Gain Transfer Function
Rev. 1.00
7
July 23, 2009
HT82V38
D8
D7
D6
D5
D4
Set to 0
Set to 0
Set to 0
MSB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
D3
D2
D1
D0
Gain
(V/V)
Gain
(dB)
1.0
1.013
:
:
5.43
5.85
0.0
0.11
:
:
14.7
15.34
LSB
0
0
:
:
1
1
0
0
0
0
0*
1
1
1
1
1
0
1
Note: * Power-on default value
PGA Gain Register Settings
Offset Register
There are three PGA registers for individually programming the offset in the red, green, and blue channels. Bits D8
through D0 control the offset range from -250mV to +250mV in 512 increments. The coding for the offset registers is
sign magnitude, with D8 as the sign bit. Table shows the offset range as a function of the Bits D8 through D0.
D8
D7
D6
D5
D4
D3
D2
D1
D0
MSB
Offset
(mV)
LSB
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
1
0
0
:
:
1
0
0
:
:
1
0
0
0
0
0*
1
1
0
0
1
0
0
1
0
1
1
1
1
0
+0.98
:
:
+250
0
-0.98
:
:
-250
Note: * Power-on default value
Offset Register Settings
Timing Diagrams
S D A T A
A 2
R /W b
tD
A 1
A 0
H
tD
D 8
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
S
S C L K
tL
tL
S
H
S L O A D
Serial Write Operation Timing
S D A T A
R /W b
A 2
A 1
A 0
D 8
tR
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
D V
S C L K
tL
tL
S
H
S L O A D
Serial Read Operation Timing
Rev. 1.00
8
July 23, 2009
HT82V38
A n a lo g In p u t
(R , G , B )
tA
tC
P ix e l ( N + 2 )
D
1
tA
P ix e l ( N + 3 )
tP
D
P ix e l ( N + 4 )
R A
C D S C L K 1
tC
tC
1 C 2
tC
2
2 A D F
tA
C D S C L K 2
tA
tC
D C L K
tA
D C 1
2 A D R
tA
D C 2
D C L K
A D C C L K
tO
O u tp u t D a ta
D 7 ~ D 0
G
(N -2 )
G
(N -2 )
H ig h
B y te
B (N -2 )
B (N -2 )
R (N -1 )
R (N -1 )
H ig h
B y te
L o w
B y te
H ig h
B y te
L o w
B y te
L o w
B y te
G
(N -1 ) G
H ig h
B y te
(N -1 )
L o w
B y te
B (N -1 )
B (N -1 )
R (N )
R (N )
G
H ig h
B y te
L o w
B y te
H ig h
B y te
L o w
B y te
H ig h
B y te
D
(N )
G
(N )
L o w
B y te
B (N )
H ig h
B y te
3-Channel CCD Mode Timing (select R-G-B mode)
P ix e l ( N + 4 )
A n a lo g In p u t
(G , B )
tC
1
tA
P ix e l ( N + 5 )
P ix e l ( N + 6 )
D
tA
tP
P ix e l ( N + 7 )
R B
D
C D S C L K 1
tC
tC
1 C 2
2
tC
2 A D F
tA
C D S C L K 2
tC
D C 1
2 A D R
tA
tA
D C 2
tA
D C L K
D C L K
A D C C L K
tO
O u tp u t D a ta
D 7 ~ D 0
B (N -2 )
B (N -2 )
H ig h
B y te
L o w
B y te
G
(N -1 ) G
H ig h
B y te
(N -1 )
L o w
B y te
B (N -1 )
B (N -1 )
H ig h
B y te
L o w
B y te
G
(N )
G
H ig h
B y te
(N )
L o w
B y te
B (N )
B (N )
H ig h
B y te
L o w
B y te
G
(N + 1 ) G
H ig h
B y te
D
(N + 1 ) B (N + 1 ) B (N + 1 ) G
L o w
B y te
H ig h
B y te
L o w
B y te
(N + 2 )
H ig h
B y te
2-Channel CCD Mode Timing (select G-B mode)
Rev. 1.00
9
July 23, 2009
HT82V38
P ix e l
(N + 8 )
P ix e l
(N + 9 )
P ix e l
(N + 1 0 )
P ix e l
(N + 1 1 )
A n a lo g In p u t
tA
tA
D
tC
D
tP
1
R C
C D S C L K 1
tC
tC
1 C 2
2
tA
D C 1
C D S C L K 2
tC
tA
2 A D F
D C L K
tA
A D C C L K
D C L K
tO
O u tp u t D a ta
D 7 ~ D 0
P ix e l
(N -2 )
P ix e l
(N -2 )
P ix e l
(N -1 )
P ix e l
(N -1 )
P ix e l
(N )
H IG H
B Y T E
L O W
B Y T E
H IG H
B Y T E
L O W
B Y T E
H IG H
B Y T E
P ix e l
(N )
P ix e l
(N + 1 )
L O W
B Y T E
D
P ix e l
(N + 1 )
H IG H
B Y T E
P ix e l
(N + 2 )
L O W
B Y T E
H IG H
B Y T E
1-Channel CCD Mode Timing
P IX E L
(N + 2 )
A n a lo g In p u t
(R , G , B )
P IX E L
(N + 3 )
tA
tC
P IX E L
(N + 4 )
D
2
tC
tP
2 A D F
R A
C D S C L K 2
tC
tA
D C L K
tA
2 A D R
tA
D C 2
D C L K
A D C C L K
tO
O u tp u t D a ta
D 7 ~ D 0
G
(N -2 )
H ig h
B y te
G
(N -2 )
L o w
B y te
B (N -2 ) B (N -2 )
H ig h
B y te
L o w
B y te
R (N -1 )
R (N -1 )
H ig h
B y te
L o w
B y te
G
(N -1 ) G
H ig h
B y te
(N -1 )
L o w
B y te
B (N -1 )
B (N -1 )
H ig h
B y te
L o w
B y te
R (N )
R (N )
G
H ig h
B y te
L o w
B y te
H ig h
B y te
D
(N )
G
(N )
L o w
B y te
B (N )
H ig h
B y te
3-Channel SHA Mode Timing (select R-G-B mode)
Rev. 1.00
10
July 23, 2009
HT82V38
P IX E L
(N + 4 )
A n a lo g In p u t
(G , B )
tC
P IX E L
(N + 6 )
P IX E L
(N + 5 )
tA
2
tC
P IX E L
(N + 7 )
D
tP
2 A D F
R B
C D S C L K 2
tA
D C L K
tA
tC
2 A D R
tA
D C 2
D C L K
A D C C L K
tO
O u tp u t D a ta
D 7 ~ D 0
B (N -2 )
B (N -2 )
H ig h
B y te
L o w
B y te
G
(N -1 ) G
H ig h
B y te
(N -1 )
L o w
B y te
B (N -1 )
B (N -1 )
H ig h
B y te
L o w
B y te
G
(N )
H ig h
B y te
G
(N )
L o w
B y te
B (N )
B (N )
H ig h
B y te
L o w
B y te
G
(N + 1 ) G
D
(N + 1 ) B (N + 1 ) B (N + 1 ) G
H ig h
B y te
L o w
B y te
H ig h
B y te
L o w
B y te
(N + 2 )
H ig h
B y te
2-Channel SHA Mode Timing (select G-B mode)
P IX E L
(N + 9 )
P IX E L
(N + 8 )
A n a lo g In p u t
tA
tC
2 A D F
tC
P IX E L
(N + 1 0 )
P IX E L
(N + 1 1 )
D
P IX E L
(N + 1 2 )
tP
2
R C
C D S C L K 2
tA
tA
D C 2
D C L K
tA
A D C C L K
tO
O u tp u t D a ta
D 7 ~ D 0
D C L K
D
P ix e l
(N -2 )
P ix e l
(N -2 )
P ix e l
(N -1 )
P ix e l
(N -1 )
P ix e l
(N )
P ix e l
(N )
P ix e l
(N + 1 )
P ix e l
(N + 1 )
P ix e l
(N + 2 )
P ix e l
(N + 2 )
H ig h
B y te
L o w
B y te
H ig h
B y te
L o w
B y te
H ig h
B y te
L o w
B y te
H ig h
B y te
L o w
B y te
H ig h
B y te
L o w
B y te
1-Channel SHA Mode Timing
Rev. 1.00
11
July 23, 2009
HT82V38
Application Circuits
Circuit and Layout Recommendations
The recommended circuit configuration for 3-Channel CDS mode operation is shown in Figure. The recommended input coupling capacitor value is 0.1mF (see Circuit Operation section for more details). A single ground plane is recommended for the HT82V38. A separate power supply may be used for DRVDD, the digital driver supply, but this supply pin
should still be decoupled to the same ground plane as the rest of the HT82V38. The loading of the digital outputs should
be minimized, either by using short traces to the digital ASIC, or by using external digital buffers. To minimize the effect
of digital transients during major output code transitions, the falling edge of CDSCLK2 should occur coincident with or
before the transient edge of ADCCLK. All 0.1mF decoupling capacitors should be located as close as possible to the
HT82V38 pins. When operating in single channel mode, the unused analog inputs should be grounded.
3 .3 V
C lo c k
In p u ts
1
2
3
A V D D
C D S C L K 2
A V S S
A D C C L K
3 .3 V
4
O E
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
D a ta
In p u ts
C D S C L K 1
V IN R
O F F S E T
D V D D
V IN G
D V S S
C M L
D 7 (M S B )
V IN B
D 6
R E F T
D 5
R E F B
D 4
A V S S
D 3
A V D D
D 2
S L O A D
D 1
S C L K
D 0 (L S B )
S D A T A
2 8
0 .1 m F
2 7
2 6
0 .1 m F
0 .1 m F
2 5
2 4
0 .1 m F
2 3
2 2
0 .1 m F
0 .1 m F
2 0
1 8
1 7
0 .1 m F 1 0 m F
H T 8 2 V 3 8 (C D S M o d e )
0 .1 m F
0 .1 m F
3 .3 V
1 6
1 5
1 .0 m F
0 .1 m F
2 1
1 9
R e d In p u t
G re e n In p u t
B lu e In p u t
S e r ia l
In p u ts
CDS Application Circuit
Figure shows the recommended circuit configuration for 3-Channel SHA mode. All of the above considerations also apply for this configuration, except that the analog input signals are directly connected to the HT82V38 without the use of
coupling capacitors. The analog input signals must already be dc-biased (relative to OFFSET pin) between 0V and
1.60V/2.0V.
3 .3 V
C lo c k
In p u ts
1
2
3
A V D D
C D S C L K 2
A V S S
A D C C L K
3 .3 V
4
O E
5
6
7
8
9
1 0
1 1
1 2
1 3
D a ta
In p u ts
C D S C L K 1
1 4
V IN R
O F F S E T
D V D D
V IN G
D V S S
C M L
D 7 (M S B )
V IN B
D 6
R E F T
D 5
R E F B
D 4
A V S S
D 3
A V D D
D 2
S L O A D
D 1
S C L K
D 0 (L S B )
S D A T A
H T 8 2 V 3 8 (S H A M o d e )
2 8
0 .1 m F
R e d In p u t
G re e n In p u t
B lu e In p u t
2 7
2 6
2 5
2 4
2 3
D C
L e v e l
0 .1 m F
2 2
2 1
0 .1 m F
2 0
1 9
1 8
1 7
1 6
1 5
0 .1 m F 1 0 m F
0 .1 m F
0 .1 m F
3 .3 V
S e r ia l
In p u ts
SHA Application Circuit
Rev. 1.00
12
July 23, 2009
HT82V38
Package Information
28-pin SSOP (209mil) Outline Dimensions
1 5
2 8
A
B
1 4
1
C
C '
G
H
D
E
a
F
· MO-150
Symbol
A
Rev. 1.00
Dimensions in mm
Min.
Nom.
Max.
7.40
¾
8.20
B
5.00
¾
5.60
C
0.22
¾
0.33
C¢
9.90
¾
10.50
D
¾
2.00
E
¾
0.65
¾
F
0.05
¾
¾
G
0.55
¾
0.95
H
0.09
¾
0.21
a
0°
¾
8°
13
July 23, 2009
HT82V38
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SSOP 28S (209mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330.0±1.0
B
Reel Inner Diameter
100.0±1.5
C
Spindle Hole Diameter
13.0
+0.5/-0.2
D
Key Slit Width
T1
Space Between Flange
28.4
T2
Reel Thickness
31.1 (max.)
Rev. 1.00
2.0±0.5
14
+0.3/-0.2
July 23, 2009
HT82V38
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
B 0
C
D 1
P
K 0
A 0
R e e l H o le
IC
p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .
SSOP 28S (209mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24.0±0.3
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.10
F
Cavity to Perforation (Width Direction)
D
Perforation Diameter
1.5
D1
Cavity Hole Diameter
1.50
P0
Perforation Pitch
4.0±0.2
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
8.4±0.1
B0
Cavity Width
10.65±0.10
K0
Cavity Depth
2.4±0.1
11.5±0.1
+0.1/-0.0
+0.25/-0.00
t
Carrier Tape Thickness
0.30±0.05
C
Cover Tape Width
21.3±0.1
Rev. 1.00
15
July 23, 2009
HT82V38
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2009 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
16
July 23, 2009
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