MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
D Low Supply-Voltage Range, 1.8 V to 3.6 V
D Ultralow-Power Consumption:
D
D
D
D
D
D
D
D
D
Active Mode: 250 μA at 1 MHz, 2.2 V
Standby Mode: 1.1 μA
Off Mode (RAM Retention): 0.1 μA
Five Power Saving Modes
Wake-Up From Standby Mode in Less
Than 6 μs
16-Bit RISC Architecture,
125-ns Instruction Cycle Time
16-Bit Sigma-Delta A/D Converter With
Internal Reference and Five Differential
Analog Inputs
12-Bit D/A Converter
Two Configurable Operational Amplifiers
16-Bit Timer_A With Three
Capture/Compare Registers
Brownout Detector
Bootstrap Loader
D Serial Onboard Programming,
D
D
D
D
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
Integrated LCD Driver With Contrast
Control for up to 56 Segments
MSP430FG42x0 Family Members Include:
MSP430FG4250: 16KB+256B Flash Memory
256B RAM
MSP430FG4260: 24KB+256B Flash Memory
256B RAM
MSP430FG4270: 32KB+256B Flash Memory
256B RAM
For Complete Module Descriptions, See
MSP430x4xx Family User’s Guide,
Literature Number SLAU056
For Additional Device Information, See
MSP430FG42x0 Device Erratasheet,
Literature Number SLAZ038
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 6 μs.
The MSP430FG42x0 is a microcontroller configuration with a 16-bit timer, a high-performance 16-bit
sigma-delta A/D converter, 12-bit D/A converter, two configurable operational amplifiers, 32 I/O pins, and a liquid
crystal display driver.
Typical applications for this device include analog and digital sensor systems, digital motor control, remote
controls, thermostats, digital timers, hand-held meters, etc.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
−40°C
40 C to 85°C
85 C
PLASTIC 48-PIN SSOP
(DL)
PLASTIC 48-PIN QFN
(RGZ)
MSP430FG4250IDL
MSP430FG4250IRGZ
MSP430FG4260IDL
MSP430FG4260IRGZ
MSP430FG4270IDL
MSP430FG4270IRGZ
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2007, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
pin designation, DL package
DL PACKAGE
(TOP VIEW)
TDO/TDI
TDI/TCLK
TMS
TCK
RST/NMI
DVCC
DVSS
XIN
XOUT
AVSS
AVCC
VREF
P6.0/A0+/OA0O
P6.1/A0−/OA0FB
P6.2/A1+/OA1O
P6.3/A1−/OA1FB
P6.4/OA0I1
P6.5/OA0I2
P6.6/OA1I1
P6.7/OA1I2
P1.7/A2+
P1.6/A2−/OA0I0
P1.5/TACLK/ACLK/A3+
P1.4/A3−/OA1I0/DAC0
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
MSP430FG42x0IDL
POST OFFICE BOX 655303
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
• DALLAS, TEXAS 75265
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P2.0/S13/SW0C
P2.1/S12/SW1C
P2.2/S11
P2.3/S10
P2.4/S9
P2.5/S8
P2.6/S7
P2.7/S6
S5
P5.7/S4
P5.6/S3
P5.5/S2
P5.0/S1
P5.1/S0
LCDCAP/R23
LCDREF/R13
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1/A4−
P1.3/TA2/A4+
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
47 46 45 44 43 42 41 40 39 38
P2.1/S12/SW1C
COM0
P5.2/COM1
P5.3/COM2
P5.4/COM3
TDO/TDI
TDI/TCLK
TMS
TCK
RST/NMI
DVCC
RGZ PACKAGE
(TOP VIEW)
P2.0/S13/SW0C
pin designation, RGZ package
P2.2/S11
2
35
P2.3/S10
XOUT
3
34
P2.4/S9
AVSS
4
33
P2.5/S8
AVCC
5
32
P2.6/S7
VREF
6
31
P2.7/S6
P6.0/A0+/OA0O
7
30
S5
P6.1/A0−/OA0FB
8
29
P5.7/S4
P6.2/A1+/OA1O
9
28
P5.6/S3
P6.3/A1−/OA1FB
10
27
P5.5/S2
P6.4/OA0I1
11
26
P5.0/S1
P6.5/OA0I2
12
25
P5.1/S0
MSP430FG42x0IRGZ
POST OFFICE BOX 655303
LCDREF/R13
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1/A4−
P1.3/TA2/A4+
P1.5/TACLK/ACLK/A3+
P1.4/A3−/OA1I0/DAC0
P1.6/A2−/OA0I0
P1.7/A2+
14 15 16 17 18 19 20 21 22 23
P6.7/OA1I2
XIN
P6.6/OA1I1
1
• DALLAS, TEXAS 75265
LCDCAP/R23
36
DVSS
3
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
functional block diagram
XIN
XOUT
DVCC
DVSS
AVCC
AVSS
P1
P6
P5
P2
8
8
8
8
ACLK
Oscillator
FLL+
SMCLK
MCLK
8 MHz
CPU
incl. 16
Registers
Flash
RAM
Port 1
Port 2
Port 5
Port 6
32KB
24KB
16KB
256B
8 I/O
Interrupt
Capability
8 I/O
Interrupt
Capability
8 I/O
8 I/O
Timer_A3
Basic
Timer 1
OA0, OA1
2 Op
Amps
+
GND
Switches
DAC12
MAB
MDB
Emulation
Module
POR/
Brownout
Watchdog
Timer+
WDT+
3 CC Reg
15/16-Bit
JTAG
Interface
1 Interrupt
Vector
LCD_A
56
Segments
1,2,3,4 MUX
RST/NMI
4
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SD16_A
16 Bit
12 Bit
1 Channel
Voltage Out
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
Terminal Functions
TERMINAL
NAME
DESCRIPTION
DL
NO.
RGZ
NO.
I/O
TDO/TDI
1
43
I/O
TDI/TCLK
2
44
I
Test data input / test clock input. The device protection fuse is connected to TDI/TCLK.
TMS
3
45
I
Test mode select. TMS is used as an input port for device programming and test.
TCK
4
46
I
Test clock. TCK is the clock input port for device programming and test.
RST/NMI
5
47
I
General-purpose digital I/O / reset input / nonmaskable interrupt input
DVCC
6
48
DVSS
7
1
XIN
8
2
I
Input terminal of crystal oscillator XT1
XOUT
9
3
O
Output terminal of crystal oscillator XT1
AVSS
10
4
AVCC
11
5
VREF
12
6
I/O
Analog reference voltage
P6.0/A0+/OA0O
13
7
I/O
General-purpose digital I/O / analog input A0+ / OA0 output
P6.1/A0−/OA0FB
14
8
I/O
General-purpose digital I/O / analog input A0− / OA0 feedback input
P6.2/A1+/OA1O
15
9
I/O
General-purpose digital I/O / analog input A1+ / OA1 output
P6.3/A1−/OA1FB
16
10
I/O
General-purpose digital I/O / analog input A1− / OA1 feedback input
P6.4/OA0I1
17
11
I/O
General-purpose digital I/O / OA0 input multiplexer on −terminal
P6.5/OA0I2
18
12
I/O
General-purpose digital I/O / OA0 input multiplexer on −terminal
P6.6/OA1I1
19
13
I/O
General-purpose digital I/O / OA1 input multiplexer on −terminal
P6.7/OA1I2
20
14
I/O
General-purpose digital I/O / OA1 input multiplexer on −terminal
P1.7/A2+
21
15
I/O
General-purpose digital I/O / analog input A2+
P1.6/A2−/OA0I0
22
16
I/O
General-purpose digital I/O / analog input A2− / OA0 input multiplexer on +terminal
P1.5/TACLK/ACLK/A3+
23
17
I/O
General-purpose digital I/O / Timer_A, clock signal TACLK input /
ACLK output (divided by 1, 2, 4, or 8) / analog input A3+
P1.4/A3−/OA1I0/DAC0
24
18
I/O
General-purpose digital I/O / analog input A3− /
OA1 input multiplexer on +terminal / DAC12 output
P1.3/TA2/A4+
25
19
I/O
General-purpose digital I/O / Timer_A, Capture: CCI2A, compare: Out2 output /
analog input A4+
P1.2/TA1/A4−
26
20
I/O
General-purpose digital I/O / Timer_A, Capture: CCI1A, compare: Out1 output /
analog input A4−
P1.1/TA0/MCLK
27
21
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0B / MCLK output. Note: TA0 is only an
input on this pin / BSL Receive
P1.0/TA0
28
22
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL
transmit
LCDREF/R13
29
23
External LCD reference voltage input / input port of third most positive analog LCD level (V4
or V3)
LCDCAP/R23
30
24
Capacitor connection for LCD charge pump /
input port of second most positive analog LCD level (V2)
P5.1/S0
31
25
I/O
General-purpose digital I/O / LCD segment output 0
P5.0/S1
32
26
I/O
General-purpose digital I/O / LCD segment output 1
P5.5/S2
33
27
I/O
General-purpose digital I/O / LCD segment output 2
P5.6/S3
34
28
I/O
General-purpose digital I/O / LCD segment output 3
P5.7/S4
35
29
I/O
General-purpose digital I/O / LCD segment output 4
S5
36
30
O
LCD segment output 5
P2.7/S6
37
31
I/O
General-purpose digital I/O / LCD segment output 6
P2.6/S7
38
32
I/O
General-purpose digital I/O / LCD segment output 7
Test data output. TDO/TDI data output or programming data input terminal
Digital supply voltage, positive terminal
Digital supply voltage, negative terminal
Analog supply voltage, negative terminal
Analog supply voltage, positive terminal
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• DALLAS, TEXAS 75265
5
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
Terminal Functions (Continued)
TERMINAL
NAME
DESCRIPTION
DL
NO.
RGZ
NO.
I/O
P2.5/S8
39
33
I/O
General-purpose digital I/O / LCD segment output 8
P2.4/S9
40
34
I/O
General-purpose digital I/O / LCD segment output 9
P2.3/S10
41
35
I/O
General-purpose digital I/O / LCD segment output 10
P2.2/S11
42
36
I/O
General-purpose digital I/O / LCD segment output 11
P2.1/S12/SW1C
43
37
I/O
General-purpose digital I/O / LCD segment output 12 / Low resistance switch to VSS
P2.0/S13/SW0C
44
38
I/O
General-purpose digital I/O / LCD segment output 13 / Low resistance switch to VSS
COM0
45
39
O
Common output. COM0−COM3 are used for LCD backplanes.
P5.2/COM1
46
40
I/O
General-purpose digital I/O / common output. COM0−COM3 are used for LCD backplanes.
P5.3/COM2
47
41
I/O
General-purpose digital I/O / common output. COM0−COM3 are used for LCD backplanes.
P5.4/COM3
48
42
I/O
General-purpose digital I/O / common output. COM0−COM3 are used for LCD backplanes.
QFN Pad
NA
None
NA
QFN package pad connection to DVSS is recommended.
6
POST OFFICE BOX 655303
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MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats. Table 2 lists the address
modes.
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g., ADD R4,R5
R4 + R5 −−−> R5
Single operands, destination only
e.g., CALL
PC −−>(TOS), R8−−> PC
Relative jump, un/conditional
e.g., JNE
R8
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
S D
SYNTAX
EXAMPLE
Register
F F
MOV Rs,Rd
MOV R10,R11
Indexed
F F
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
Symbolic (PC relative)
F F
MOV EDE,TONI
Absolute
F F
MOV & MEM, & TCDAT
OPERATION
R10
—> R11
M(2+R5)—> M(6+R6)
M(EDE) —> M(TONI)
M(MEM) —> M(TCDAT)
Indirect
F
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) —> M(Tab+R6)
Indirect
autoincrement
F
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) —> R11
R10 + 2—> R10
F
MOV #X,TONI
MOV #45,TONI
Immediate
NOTE: S = source
#45
—> M(TONI)
D = destination
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7
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode (AM)
−
All clocks are active
D Low-power mode 0 (LPM0)
−
CPU is disabled
ACLK and SMCLK remain active, MCLK is available to modules
FLL+ loop control remains active
D Low-power mode 1 (LPM1)
−
CPU is disabled
ACLK and SMCLK remain active, MCLK is available to modules
FLL+ loop control is disabled
D Low-power mode 2 (LPM2)
−
CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D Low-power mode 3 (LPM3)
−
CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
D Low-power mode 4 (LPM4)
−
8
CPU is disabled
ACLK is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
POST OFFICE BOX 655303
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MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 3. Interrupt Sources, Flags, and Vectors of MSP430FG42x0 Configuration
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD
ADDRESS
PRIORITY
Reset
0FFFEh
15, highest
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh
14
0FFFAh
13
0FFF8h
12
Power-Up
External Reset
Watchdog
Flash Memory
PC Out-of-Range (see Note 4)
WDTIFG
KEYV
(see Note 1)
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
SD16_A
SD16CCTLx SD16OVIFG,
SD16CCTLx SD16IFG
(see Notes 1 and 2)
Maskable
Watchdog Timer
WDTIFG
Maskable
0FFF6h
11
0FFF4h
10
0FFF2h
9
0FFF0h
8
0FFEEh
7
Timer_A3
TACCR0 CCIFG0 (see Note 2)
Maskable
0FFECh
6
Timer_A3
TACCR1 CCIFG1 and TACCR2 CCIFG2,
TAIFG (see Notes 1 and 2)
Maskable
0FFEAh
5
I/O Port P1 (Eight Flags)
P1IFG.0 to P1IFG.7 (see Notes 1 and 2)
Maskable
0FFE8h
4
DAC12
DAC12_0IFG
(see Note 2)
Maskable
0FFE6h
3
0FFE4h
2
I/O Port P2 (Eight Flags)
P2IFG.0 to P2IFG.7 (see Notes 1 and 2)
Maskable
0FFE2h
1
Basic Timer1
BTIFG
Maskable
0FFE0h
0, lowest
NOTES: 1.
2.
3.
4.
Multiple source flags
Interrupt flags are located in the module.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h−01FFh) or from
within unused address ranges (MSP430FG4270, MSP430FG4260: from 0300h to 0BFFh and from 01100h to 07FFFh,
MSP430FG4250: from 0300h to 0BFFh and from 01100h to 0BFFFh).
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9
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
special function registers (SFRs)
The MSP430 SFRs are located in the lowest address space and are organized as byte-mode registers. SFRs
should be accessed with byte instructions.
interrupt enable registers 1 and 2
7
Address
6
0h
5
4
ACCVIE
NMIIE
OFIE
WDTIE
rw–0
rw–0
rw–0
rw–0
3
2
1
WDTIE:
Watchdog-timer interrupt enable. Inactive if watchdog mode is selected.
Active if watchdog timer is configured as a general-purpose timer.
OFIE:
Oscillator-fault-interrupt enable
NMIIE:
Nonmaskable-interrupt enable
ACCVIE:
Flash access violation interrupt enable
7
Address
6
5
0
4
3
2
1
0
4
3
2
1
0
BTIE
01h
rw–0
BTIE:
Basic timer interrupt enable
interrupt flag registers 1 and 2
7
Address
6
5
02h
NMIIFG
OFIFG
rw–0
rw–1
WDTIFG:
Set on watchdog timer overflow (in watchdog mode) or security key violation
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode
OFIFG:
Flag set on oscillator fault
NMIIFG:
Set via RST/NMI pin
7
Address
03h
6
5
4
3
BTIFG
rw–0
BTIFG:
10
Basic timer flag
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2
1
WDTIFG
rw–(0)
0
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
module enable registers 1 and 2
Address
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
04h
Address
05h
Legend: rw:
rw–0,1:
rw–(0,1):
Bit Can Be Read and Written
Bit Can Be Read and Written. It Is Reset or Set by PUC.
Bit Can Be Read and Written. It Is Reset or Set by POR.
SFR Bit Not Present in Device
memory organization
MSP430FG4250
MSP430FG4260
MSP430FG4270
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
16KB
0FFFFh − 0FFE0h
0FFFFh − 0C000h
24KB
0FFFFh − 0FFE0h
0FFFFh − 0A000h
32KB
0FFFFh − 0FFE0h
0FFFFh − 08000h
Information memory
Size
Flash
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
Boot memory
Size
ROM
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
Size
256 Byte
02FFh − 0200h
256 Byte
02FFh − 0200h
256 Byte
02FFh − 0200h
16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
RAM
Peripherals
bootstrap loader (BSL)
The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access
to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the
features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap
Loader, literature number SLAA089.
BSL Function
DL Package Pins
RGZ Package Pins
Data Transmit
28 - P1.0
22 - P1.0
Data Receive
27 - P1.1
21 - P1.1
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11
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and two segments of information memory (A and B) of
128 bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A and B can be erased individually, or as a group with segments 0 to n.
Segments A and B are also called information memory.
D New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
16KB
24KB
32KB
0FFFFh
0FFFFh
0FFFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
Segment 1
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
Segment 2
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0C400h
0C3FFh
0A400h
0A3FFh
08400h
083FFh
0C200h
0C1FFh
0A200h
0A1FFh
08200h
081FFh
0C000h
010FFh
0A000h
010FFh
08000h
010FFh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01000h
01000h
01000h
Segment 0
w/ Interrupt Vectors
Main
Memory
Segment n-1
Segment n
Segment A
Information
Memory
Segment B
12
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MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide, literature
number SLAU056.
oscillator and system clock
The clock system in the MSP430FG42x0 family of devices is supported by the FLL+ module, which includes
support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a
high-frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low
system cost and low-power consumption. The FLL+ features digital frequency locked loop (FLL) hardware that,
in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch
crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 μs. The
FLL+ module provides the following clock signals:
D
D
D
D
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal
Main clock (MCLK), the system clock used by the CPU
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8
brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on
and power-off. The CPU begins code execution after the brownout circuit releases the device reset. However,
VCC may not have ramped to VCC(min) at that time. The user must ensure the default FLL+ settings are not
changed until VCC reaches VCC(min).
digital I/O
There are four 8-bit I/O ports implemented—ports P1, P2, P5, and P6:
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
Read/write access to port-control registers is supported by all instructions.
Basic Timer1
Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers
can be read and written by software. Basic Timer1 can be used to generate periodic interrupts.
LCD driver with regulated charge pump
The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2−MUX, 3−MUX, and 4−MUX LCDs are supported by this peripheral.
The module can provide a LCD voltage independent of the supply voltage via an integrated charge pump.
Furthermore, it is possible to control the level of the LCD voltage and thus contrast in software.
watchdog timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
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13
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number
DL
RGZ
Device Input
Signal
Module
Input Name
23 - P1.5
17 - P1.5
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
23 - P1.5
17 - P1.5
TACLK
INCLK
28 - P1.0
22 - P1.0
TA0
CCI0A
27 - P1.1
21 - P1.1
TA0
CCI0B
DVSS
GND
DVCC
VCC
26 - P1.2
20 - P1.2
TA1
CCI1A
26 - P1.2
20 - P1.2
TA1
CCI1B
DVSS
GND
25 - P1.3
19 - P1.3
DVCC
VCC
TA2
CCI2A
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
Module
Block
Module Output
Signal
Timer
NA
CCR0
CCR1
CCR2
Output Pin Number
DL
RGZ
28 - P1.0
22 - P1.0
26 - P1.2
20 - P1.2
25 - P1.3
19 - P1.3
TA0
TA1
TA2
SD16_A
The SD16_A module supports 16-bit analog-to-digital conversions. The module implements a 16-bit
sigma-delta core and reference generator. In addition to external analog inputs, an internal VCC sense and
temperature sensor are also available.
DAC12
The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8- or 12-bit mode.
14
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MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
operational amplifier (OA)
The MSP430FG42x0 has two configurable low-current general-purpose operational amplifiers. Each OA input
and output terminal is software-selectable and offers a flexible choice of connections for various applications.
The OAs primarily support front-end analog signal conditioning prior to analog-to-digital conversion.
OA Signal Connections
Input Pin Number
DL
RGZ
Device Input
Signal
Module
Input Name
22 - P1.6
16 - P1.6
OA0I0
OA0I0
17 - P6.4
11 - P6.4
OA0I1
OA0I1
18 - P6.5
12 - P6.5
OA0I2
OA0I2
14 - P6.1
8 - P6.1
OA0FB
OA0FB
24 - P1.4
18 - P1.4
OA1I0
OA1I0
19 - P6.6
13 - P6.6
OA1I1
OA1I1
20 - P6.7
14 - P6.7
OA1I2
OA1I2
16 - P6.1
10 - P6.1
OA1FB
OA1FB
POST OFFICE BOX 655303
Module
Block
OA0
OA1
Module Output
Signal
Output Pin Number
DL
RGZ
13 - P6.0
7 - P6.0
15 - P6.0
9 - P6.0
OA0O
OA1O
• DALLAS, TEXAS 75265
15
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog
Watchdog timer control
WDTCTL
0120h
Timer_A3
_
Capture/compare register 2
TACCR2
0176h
Capture/compare register 1
TACCR1
0174h
Capture/compare register 0
TACCR0
0172h
Timer_A register
TAR
0170h
Capture/compare control 2
TACCTL2
0166h
Capture/compare control 1
TACCTL1
0164h
Capture/compare control 0
TACCTL0
0162h
Timer_A control
TACTL
0160h
Timer_A interrupt vector
TAIV
012Eh
Flash control 3
FCTL3
012Ch
Flash control 2
FCTL2
012Ah
Flash control 1
FCTL1
0128h
DAC12_0 data
DAC12_0DAT
01C8h
Flash
DAC12
DAC12_0 control
DAC12_0CTL
01C0h
SD16_A
(see also
Peripherals With
Byte Access)
General control
Channel 0 control
Interrupt vector word register
Channel 0 conversion memory
SD16CTL
SD16CCTL0
SD16IV
SD16MEM0
0100h
0102h
0110h
0112h
OA/GND Switches
Switch control register
SWCTL
0CFh
OA1
Operational amplifier 1 control register 1
Operational amplifier 1 control register 0
OA1CTL1
OA1CTL0
0C3h
0C2h
OA0
Operational amplifier 0 control register 1
Operational amplifier 0 control register 0
OA0CTL1
OA0CTL0
0C1h
0C0h
SD16_A
(see also:
Peripherals with
Word Access)
Channel 0 input control
Analog enable
SD16INCTL0
SD16AE
0B0h
0B7h
LCD_A
LCD voltage control 1
LCD voltage control 0
LCD voltage port control 1
LCD voltage port control 0
LCD memory 20
:
LCD memory 16
LCD memory 15
:
LCD memory 1
LCD control and mode
LCDAVCTL1
LCDAVCTL0
LCDAPCTL1
LCDAPCTL0
LCDM20
:
LCDM16
LCDM15
:
LCDM1
LCDACTL
0AFh
0AEh
0ADh
0ACh
0A4h
:
0A0h
09Fh
:
091h
090h
PERIPHERALS WITH BYTE ACCESS
16
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MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
FLL+ Clock
FLL+ Control 1
FLL_CTL1
054h
FLL+ Control 0
FLL_CTL0
053h
System clock frequency control
SCFQCTL
052h
System clock frequency integrator
SCFI1
051h
System clock frequency integrator
SCFI0
050h
Basic Timer1
BT counter 2
BT counter 1
BT control
BTCNT2
BTCNT1
BTCTL
047h
046h
040h
Port P6
Port P6 selection
P6SEL
037h
Port P6 direction
P6DIR
036h
Port P6 output
P6OUT
035h
Port P6 input
P6IN
034h
Port P5 selection
P5SEL
033h
Port P5 direction
P5DIR
032h
Port P5 output
P5OUT
031h
Port P5 input
P5IN
030h
Port P2 selection
P2SEL
02Eh
Port P2 interrupt enable
P2IE
02Dh
Port P2 interrupt-edge select
P2IES
02Ch
Port P2 interrupt flag
P2IFG
02Bh
Port P2 direction
P2DIR
02Ah
Port P2 output
P2OUT
029h
Port P2 input
P2IN
028h
Port P1 selection
P1SEL
026h
Port P1 interrupt enable
P1IE
025h
Port P1 interrupt-edge select
P1IES
024h
Port P1 interrupt flag
P1IFG
023h
Port P1 direction
P1DIR
022h
Port P1 output
P1OUT
021h
Port P1 input
P1IN
020h
SFR module enable 2
ME2
005h
SFR module enable 1
ME1
004h
SFR interrupt flag 2
IFG2
003h
SFR interrupt flag 1
IFG1
002h
SFR interrupt enable 2
IE2
001h
SFR interrupt enable 1
IE1
000h
Port P5
Port P2
Port P1
Special
p
functions
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MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V
Voltage applied to any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature, Tstg: Unprogrammed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
Programmed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TDI/TCLK pin when blowing the JTAG fuse.
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage during program execution (see Note 1),
VCC (AVCC = DVCC = VCC)
1.8
3.6
V
Supply voltage during flash memory programming (see Note 1),
VCC (AVCC = DVCC = VCC)
2.5
3.6
V
0
0
V
−40
85
°C
450
8000
kHz
1000
8000
VCC = 1.8 V
DC
4.15
VCC = 3.6 V
DC
8
Supply voltage, VSS (AVSS = DVSS = VSS)
Operating free-air temperature, TA
LFXT1 crystal frequency, f(LFXT1)
(see Note 2)
LF selected,
XTS_FLL=0
Watch crystal
XT1 selected,
XTS_FLL=1
Ceramic resonator
XT1 selected,
XTS_FLL=1
Crystal
Processor frequency (signal MCLK),
MCLK) f(System)
32.768
MHz
NOTES: 1. It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can
be tolerated during power up and operation.
2. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
fSystem (MHz)
8 MHz
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Supply voltage range,
MSP430FG42x0, during
program execution
4.15 MHz
1.8
3
2.5
Supply Voltage − V
Supply voltage range, MSP430FG42x0,
during flash memory programming
3.6
Figure 1. Frequency vs Supply Voltage, Typical Characteristic
18
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MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AVCC + DVCC excluding external current
PARAMETER
TEST CONDITIONS
Active mode (see Note 1),
f(MCLK) = f(SMCLK) = 1 MHz,
f(ACLK) = 32,768 Hz
XTS=0, SELM=(0,1)
TA = −40°C
40°C to 85°C
I(LPM0)
Low power mode (LPM0)
Low-power
(see Note 1 and Note 4)
TA = −40°C
40°C to 85°C
I(LPM2)
Low-power mode (LPM2),
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32,768 Hz, SCG0 = 0
(see Note 2 and Note 4)
TA = −40°C
40°C to 85°C
I(AM)
I(LPM3)
Low-power mode (LPM3),
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32,768 Hz, SCG0 = 1
Basic Timer1 enabled,
enabled ACLK selected
LCD_A
LCD A enabled, LCDCPEN = 0
(static
mode,, fLCD = f(ACLK)/32),
(
),
(see Note 2, Note 3, and Note 4)
NOM
MAX
VCC = 2.2 V
250
370
VCC = 3 V
400
520
VCC = 2.2 V
55
70
VCC = 3 V
95
110
VCC = 2.2 V
11
14
VCC = 3 V
17
22
TA = −40°C
1.0
2.0
TA = 25°C
1.1
2.0
TA = 60°C
VCC = 2
2.2
2V
2.0
3.0
3.5
6.0
TA = −40°C
1.8
2.8
1.6
2.7
2.5
3.5
4.2
7.5
2.5
3.5
2.5
3.5
TA = 85°C
3.8
6.0
TA = −40°C
2.9
4.0
2.9
4.0
TA = 60°C
VCC = 3 V
I(LPM3)
I(LPM4)
TA = −40°C
TA = 25°C
TA = 25°C
VCC = 2.2 V
VCC = 3 V
TA = 85°C
4.4
7.5
TA = −40°C
0.1
0.5
TA = 25°C
0.1
0.5
TA = 60°C
Low-power mode (LPM4)
(LPM4),
f(MCLK) = 0 MHz, f(SMCLK) = 0 MHz,
f(ACLK) = 0 Hz, SCG0 = 1
(see
Note
Note
(
N
t 2 and
dN
t 4)
2V
VCC = 2
2.2
0.7
1.1
TA = 85°C
1.7
3.0
TA = −40°C
0.1
0.8
0.1
0.8
0.8
1.2
1.9
3.5
TA = 25°C
TA = 60°C
VCC = 3 V
TA = 85°C
NOTES: 1.
2.
3.
4.
μA
A
A
μA
TA = 85°C
TA = 25°C
UNIT
A
μA
TA = 85°C
Low-power mode (LPM3),
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32,768 Hz, SCG0 = 1
enabled ACLK selected
Basic Timer1 enabled,
LCD_A
LCD A enabled, LCDCPEN = 0
(4-mux
mode,, fLCD = f(ACLK)/32),
(
),
(see Note 2, Note 3, and Note 4)
MIN
μA
A
A
μA
μA
A
Timer_A is clocked by f(DCOCLK) = f(DCO) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The LPM3 currents are characterized with a Micro Crystal CC4V−T1A (9 pF) crystal and OSCCAPx = 01h.
Current for brownout included.
current consumption of active mode versus system frequency
I(AM) = I(AM) [1 MHz] × f(System) [MHz]
current consumption of active mode versus supply voltage
I(AM) = I(AM) [3 V] + 175 μA/V × (VCC – 3 V)
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19
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Schmitt-trigger inputs − Ports P1, P2, P5, and P6; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
PARAMETER
TEST CONDITIONS
VIT+
Positive going input threshold voltage
Positive-going
VIT−
Negative going input threshold voltage
Negative-going
Vhys
Input voltage hysteresis (VIT+ − VIT−)
MIN
TYP
MAX
VCC = 2.2 V
1.1
1.55
VCC = 3 V
1.5
1.98
VCC = 2.2 V
0.4
0.9
VCC = 3 V
0.9
1.3
VCC = 2.2 V
0.3
1.1
VCC = 3 V
0.5
1
UNIT
V
V
V
inputs Px.x, TAx
PARAMETER
TEST CONDITIONS
VCC
MIN
2.2 V
62
3V
50
2.2 V
62
3V
50
t(int)
External interrupt timing
Port P1, P2: P1.x to P2.x, external trigger signal
for the interrupt flag, (see Note 1)
t(cap)
Timer A capture timing
Timer_A
TA0
TA0, TA1
TA1, TA2
f(TAext)
Timer_A clock frequency
externally applied to pin
TACLK,
TACLK INCLK: t(H) = t(L)
f(TAint)
Timer A clock frequency
Timer_A
SMCLK or ACLK signal selected
TYP
MAX
UNIT
ns
ns
2.2 V
8
3V
10
2.2 V
8
3V
10
MHz
MHz
NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) parameters are met. It may be set even with trigger signals
shorter than t(int).
leakage current − ports P1, P2, P5, and P6 (see Note 1)
PARAMETER
Ilkg(Px.y)
Leakage
current
TEST CONDITIONS
Port Px
V(Px.y) (see Note 2)
MIN
TYP
VCC = 2.2 V/3 V
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as input.
20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
UNIT
±50
nA
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − ports P1, P2, P5, and P6
PARAMETER
VOH
VOL
High level output voltage
High-level
Low level output voltage
Low-level
TEST CONDITIONS
MIN
TYP
MAX
IOH(max) = −1.5 mA,
VCC = 2.2 V,
See Note 1
VCC−0.25
VCC
IOH(max) = −6 mA,
VCC = 2.2 V,
See Note 2
VCC−0.6
VCC
IOH(max) = −1.5 mA,
VCC = 3 V,
See Note 1
VCC−0.25
VCC
IOH(max) = −6 mA,
VCC = 3 V,
See Note 2
VCC−0.6
VCC
IOL(max) = 1.5 mA,
VCC = 2.2 V,
See Note 1
VSS
VSS+0.25
IOL(max) = 6 mA,
VCC = 2.2 V,
See Note 2
VSS
VSS+0.6
IOL(max) = 1.5 mA,
VCC = 3 V,
See Note 1
VSS
VSS+0.25
IOL(max) = 6 mA,
VCC = 3 V,
See Note 2
VSS
VSS+0.6
UNIT
V
V
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum
specified voltage drop.
2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the maximum
specified voltage drop.
output frequency
PARAMETER
TEST CONDITIONS
f(Px.y)
(x = 1, 2, 5, 6, 0 ≤ y ≤ 7)
CL = 20 pF,
IL = ±1.5 mA
f(MCLK)
P1.1/TA0/MCLK
CL = 20 pF
t(Xdc)
Duty cycle of output frequency
P1.1/TA0/MCLK,
CL = 20 pF,
VCC = 2.2 V / 3 V
POST OFFICE BOX 655303
VCC = 2.2 V / 3 V
f(MCLK) = f(XT1)
f(MCLK) = f(DCOCLK)
• DALLAS, TEXAS 75265
MIN
TYP
DC
40%
50%−
15 ns
MAX
UNIT
fSystem
MHz
fSystem
MHz
60%
50%
50%+
15 ns
21
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − ports P1, P2, P5, and P6 (continued)
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50
VCC = 2.2 V
P1.0
I OL − Typical Low-level Output Current − mA
I OL − Typical Low-level Output Current − mA
30
TA = −40°C
25
TA = 25°C
20
TA = 85°C
15
10
5
0
0.0
0.5
1.0
1.5
2.0
VCC = 3 V
P1.0
45
TA = −40°C
40
TA = 25°C
35
TA = 85°C
30
25
20
15
10
5
0
0.0
2.5
0.5
VOL − Low-Level Output Voltage − V
1.0
Figure 2
3.0
3.5
0
VCC = 2.2 V
P1.0
I OH− Typical High-level Output Current − mA
I OH− Typical High-level Output Current − mA
2.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
−5
−10
−15
TA = 85°C
TA = 25°C
−20
TA = −40°C
0.5
1.0
1.5
2.0
2.5
−5
VCC = 3 V
P1.0
−10
−15
−20
−25
−30
−35
TA = 85°C
TA = 25°C
−40
−45
−50
0.0
TA = −40°C
0.5
VOH − High-Level Output Voltage − V
1.0
1.5
Figure 5
POST OFFICE BOX 655303
2.0
2.5
3.0
VOH − High-Level Output Voltage − V
Figure 4
22
2.0
Figure 3
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
−25
0.0
1.5
VOL − Low-Level Output Voltage − V
• DALLAS, TEXAS 75265
3.5
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
wake-up LPM3
PARAMETER
TEST CONDITIONS
MIN
TYP
f = 1 MHz
td(LPM3)
f = 2 MHz
Delay time
MAX
UNIT
6
6
VCC = 2.2 V/3 V
f = 3 MHz
μs
6
RAM
PARAMETER
TEST CONDITIONS
VRAMh
MIN
CPU halted (see Note 1)
TYP
MAX
1.6
UNIT
V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
LCD_A
PARAMETER
TEST CONDITIONS
VCC(LCD)
Supply voltage
Charge pump enabled
(LCDCPEN = 1, VLCDx > 0000)
CLCD
Capacitor on LCDCAP (see Note 1)
Charge pump enabled
(LCDCPEN = 1, VLCDx > 0000)
ICC(LCD)
Average supply current (see Note 2)
VLCD(typ)=3V, LCDCPEN = 1,
VLCDx= 1000, all segments on
fLCD= fACLK/32
no LCD connected (see Note 3)
TA = 25°C
fLCD
LCD frequency
VLCD
RLCD
LCD voltage
LCD driver output impedance
VCC
2.2 V
MIN
2.2
4.7
TYP
MAX
3.6
μA
3.8
VLCDx = 0000
VCC
VLCDx = 0001
2.60
VLCDx = 0010
2.66
VLCDx = 0011
2.72
VLCDx = 0100
2.78
VLCDx = 0101
2.84
VLCDx = 0110
2.90
VLCDx = 0111
2.96
VLCDx = 1000
3.02
VLCDx = 1001
3.08
VLCDx = 1010
3.14
VLCDx = 1011
3.20
VLCDx = 1100
3.26
VLCDx = 1101
3.32
VLCDx = 1110
3.38
VLCDx = 1111
3.44
2.2 V
V
μF
1.1
VLCD = 3V, LCDCPEN = 1,
VLCDx = 1000, ILOAD = ±10 μA
UNIT
kHz
V
3.60
10
kΩ
NOTES: 1. Enabling the internal charge pump with an external capacitor smaller than the minimum specified might damage the device.
2. Refer to the supply current specifications I(LPM3) for additional current specifications with the LCD_A module active.
3. Connecting an actual display will increase the current consumption depending on the size of the LCD.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
POR/brownout reset (BOR) (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
td(BOR)
dVCC/dt ≤ 3 V/s (see Figure 6)
VCC(start)
V(B_IT−)
Vhys(B_IT−)
t(reset)
UNIT
2000
μs
0.7 × V(B_IT−)
dVCC/dt ≤ 3 V/s (see Figure 6 through Figure 8)
Brownout
(see Note 2)
MAX
dVCC/dt ≤ 3 V/s (see Figure 6)
70
Pulse length needed at RST/NMI pin to accepted reset internally,
VCC = 2.2 V/3 V
2
130
V
1.71
V
180
mV
μs
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level
V(B_IT−) + Vhys(B_IT−) is ≤ 1.8V.
2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT−) + Vhys(B_IT−). The default
FLL+ settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired
operating frequency. See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout.
typical characteristics
VCC
Vhys(B_IT−)
V(B_IT−)
VCC(start)
1
0
t d(BOR)
Figure 6. POR/Brownout Reset (BOR) vs Supply Voltage
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
typical characteristics (continued)
VCC
3V
2
VCC(drop)− V
VCC = 3 V
Typical Conditions
t pw
1.5
1
VCC(drop)
0.5
0
0.001
1
1000
1 ns
tpw − Pulse Width − μs
1 ns
tpw − Pulse Width − μs
Figure 7. V(CC)min Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
2
t pw
3V
VCC(drop)− V
VCC = 3 V
1.5
Typical Conditions
1
VCC(drop)
0.5
0
0.001
tf = tr
1
1000
tf
tr
tpw − Pulse Width − μs
tpw − Pulse Width − μs
Figure 8. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
DCO
PARAMETER
VCC
f(DCOCLK)
N(DCO)=01Eh, FN_8=FN_4=FN_3=FN_2=0, D = 2, DCOPLUS= 0,
fCrystal = 32.768 kHz
f(DCO=2)
FN 8 = FN
FN_8
FN_4
4 = FN
FN_3
3 = FN
FN_2
2=0
0, DCOPLUS = 1
f(DCO=27)
FN 8 = FN
FN_8
FN_4
4 = FN
FN_3
3 = FN
FN_2
2=0
0, DCOPLUS = 1
f(DCO=2)
FN 8 = FN
FN_8
FN_4
4 = FN
FN_3
3=0
0, FN
FN_2
2=1
1, DCOPLUS = 1
f(DCO=27)
FN 8 = FN
4 = FN
3=0
2=1
FN_8
FN_4
FN_3
0, FN
FN_2
1, DCOPLUS = 1
f(DCO=2)
FN 8 = FN
FN_8
FN_4
4=0
0, FN
FN_3
3=1
1, FN
FN_2
2 = xx, DCOPLUS = 1
f(DCO=27)
FN 8 = FN
FN_8
FN_4
4=0
0, FN
FN_3
3=1
1, FN
FN_2
2 = xx, DCOPLUS = 1
f(DCO=2)
FN 8 = 0
FN_8
0, FN
FN_4
4=1
1, FN
FN_3
3 = FN
FN_2
2 = xx, DCOPLUS = 1
f(DCO=27)
FN 8 = 0
FN_8
0, FN
FN_4
4=1
1, FN
FN_3
3 = FN
FN_2
2 = xx, DCOPLUS = 1
f(DCO=2)
FN 8 = 1
4 = FN
3 = FN
2 = xx, DCOPLUS = 1
FN_8
1, FN
FN_4
FN_3
FN_2
f(DCO=27)
FN 8 1
FN_8=
1, FN_4
FN 4 = FN
FN_3
3 = FN
FN_2
2 = xx, DCOPLUS = 1
Sn
Step size between adjacent DCO taps:
Sn = fDCO(Tap n+1) / fDCO(Tap n) (see Figure 10 for taps 21 to 27)
Dt
Temperature drift, N(DCO) = 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0,
D = 2, DCOPLUS = 0 (see Note 2)
DV
Drift with VCC variation, N(DCO) = 01Eh,
FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0
f
f
TEST CONDITIONS
f
(DCO)
f
(DCO3V)
MIN
2.2 V/3 V
TYP
1
UNIT
MHz
2.2 V
0.3
0.65
1.25
3V
0.3
0.7
1.3
2.2 V
2.5
5.6
10.5
3V
2.7
6.1
11.3
2.2 V
0.7
1.3
2.3
3V
0.8
1.5
2.5
2.2 V
5.7
10.8
18
3V
6.5
12.1
20
2.2 V
1.2
2
3
3V
1.3
2.2
3.5
2.2 V
9
15.5
25
3V
10.3
17.9
28.5
2.2 V
1.8
2.8
4.2
3V
2.1
3.4
5.2
2.2 V
13.5
21.5
33
3V
16
26.6
41
2.2 V
2.8
4.2
6.2
3V
4.2
6.3
9.2
2.2 V
21
32
46
3V
30
46
70
1 < TAP ≤ 20
1.06
1.11
TAP = 27
1.07
1.17
2.2 V
–0.2
–0.3
–0.4
3V
–0.2
–0.3
–0.4
0
5
15
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%/_C
%/V
(DCO)
(DCO205C)
1.0
1.0
0
1.8
2.4
3.0
3.6
VCC − V
−40
−20
0
20
40
60
Figure 9. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature
26
MAX
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
85
TA − °C
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
Sn - Stepsize Ratio between DCO Taps
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
1.17
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Max
1.11
1.07
1.06
Min
1
20
27
DCO Tap
Figure 10. DCO Tap Step Size
f(DCO)
Legend
Tolerance at Tap 27
DCO Frequency
Adjusted by Bits
29 to 25 in SCFI1 {N{DCO}}
Tolerance at Tap 2
Overlapping DCO Ranges:
Uninterrupted Frequency Range
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=x
FN_4=x
FN_8=1
Figure 11. Five Overlapping DCO Ranges Controlled by FN_x Bits
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
crystal oscillator, LFXT1 oscillator (see Notes 1 and 2)
PARAMETER
CXIN
CXOUT
Integrated input capacitance
(see Note 4)
Integrated output capacitance
(see Note 4)
TEST CONDITIONS
MIN
0
OSCCAPx = 1h, VCC = 2.2 V / 3 V
10
OSCCAPx = 2h, VCC = 2.2 V / 3 V
14
OSCCAPx = 3h, VCC = 2.2 V / 3 V
18
OSCCAPx = 0h, VCC = 2.2 V / 3 V
0
OSCCAPx = 1h, VCC = 2.2 V / 3 V
10
OSCCAPx = 2h, VCC = 2.2 V / 3 V
14
OSCCAPx = 3h, VCC = 2.2 V / 3 V
VIL
VIH
Input levels at XIN
TYP
OSCCAPx = 0h, VCC = 2.2 V / 3 V
VCC = 2
2.2
2 V/3 V (see Note 3)
MAX
UNIT
pF
pF
18
VSS
0.2×VCC
0.8×VCC
VCC
V
NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2 pF. The effective load capacitor for the crystal is
(CXIN × CXOUT) / (CXIN + CXOUT). This is independent of XTS_FLL.
2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed.
− Keep as short of a trace as possible between the ’FG42x0 and the crystal.
− Design a good ground plane around the oscillator pins.
− Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
− Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
− Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
− If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
− Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
3. Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or
resonator.
4. External capacitance is recommended for precision real-time clock applications, OSCCAPx = 0h.
28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SD16_A, power supply and recommended operating conditions
PARAMETER
AVCC
ISD16
fSD16
Analog supply
voltage
Analog supply
current including
internal reference
Analog front-end
input clock
frequency
TEST CONDITIONS
VCC
MIN
AVCC = DVCC
AVSS = DVSS = 0V
TYP
MAX
2.5
3.6
SD16LP = 0,
fSD16 = 1 MHz,
SD16OSR = 256
SD16BUFx = 00, GAIN: 1,2
650
950
SD16BUFx = 00, GAIN: 4,8,16
730
1100
SD16BUFx = 00, GAIN: 32
1050
1550
SD16LP = 1,
fSD16 = 0.5
0 5 MHz
MHz,
SD16OSR = 256
SD16BUFx = 00, GAIN: 1
620
930
700
1060
SD16LP = 0,
fSD16 = 1 MHz,
SD16OSR = 256
SD16BUFx = 01, GAIN: 1
850
SD16BUFx = 10, GAIN: 1
1130
SD16BUFx = 11, GAIN: 1
1130
3V
SD16BUFx = 00, GAIN: 32
SD16LP = 0 (Low power mode disabled)
0.03
1
0.03
0.5
UNIT
V
μA
A
1.1
3V
MHz
SD16LP = 1 (Low power mode enabled)
SD16_A, input range
PARAMETER
VID,FSR
VID
ZI
ZID
Differential full scale
input voltage range
Differential input
voltage range for
specified
performance
(see Note 1)
Input impedance
(one input pin
to AVSS)
Differential
Input impedance
(IN+ to IN−)
VI
Absolute input
voltage range
VIC
Common mode
Common-mode
input voltage range
TEST CONDITIONS
VCC
Bipolar mode, SD16UNI = 0
MIN
fSD16 = 1MHz,
SD16BUFx = 00
0
+VREF/2GAIN
fSD16 = 1MHz,
SD16BUFx = 01
fSD16 = 1MHz,
SD16BUFx = 00
fSD16 = 1MHz,
SD16BUFx > 00
SD16GAINx = 1
±500
SD16GAINx = 2
±250
SD16GAINx = 4
±125
SD16GAINx = 8
±62
SD16GAINx = 16
±31
SD16GAINx = 32
±15
SD16GAINx = 1
200
SD16GAINx = 32
3V
300
400
100
150
MΩ
kΩ
>10
SD16GAINx = 1
mV
kΩ
>10
SD16GAINx = 1
UNIT
mV
75
3V
SD16GAINx = 1
SD16GAINx = 32
MAX
+VREF/2GAIN
Unipolar mode, SD16UNI = 1
SD16REFON 1
SD16REFON=1
TYP
−VREF/2GAIN
MΩ
SD16BUFx = 00
AVSS − 0.1V
AVCC
SD16BUFx > 00
AVSS
AVCC −1.2V
SD16BUFx = 00
AVSS − 0.1V
AVCC
SD16BUFx > 00
AVSS
AVCC −1.2V
V
V
NOTES: 1. The analog input range depends on the reference voltage applied to VREF. If VREF is sourced externally, the full-scale range
is defined by VFSR+ = +(VREF/2)/GAIN and VFSR− = −(VREF/2)/GAIN. The analog input range should not exceed 80% of
VFSR+ or VFSR−.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SD16_A, performance (fSD16 = 30kHz, SD16REFON = 1, SD16BUFx = 01)
PARAMETER
TEST CONDITIONS
VCC
MIN
SD16GAINx = 1,Signal Amplitude = 500mV
SD16OSRx = 256
SINAD
Signal-to-noise +
distortion ratio
SD16GAINx = 1,Signal Amplitude = 500mV
SD16OSRx = 512
TYP
MAX
UNIT
84
fIN = 2.8Hz
84
3V
SD16GAINx = 1,Signal Amplitude = 500mV
SD16OSRx = 1024
dB
84
Nominal gain
SD16GAINx = 1, SD16OSRx = 1024
3V
dG/dT
Gain temperature
drift
SD16GAINx = 1, SD16OSRx = 1024 (see Note 1)
3V
dG/dVCC
Gain supply voltage
drift
SD16GAINx = 1, SD16OSRx = 1024, VCC = 2.5 V to 3.6 V
(see Note 2)
0.97
1.00
1.02
15
ppm/_C
0.35
%/V
NOTES: 1. Calculated using the box method: (MAX(−40...85_C) − MIN(−40...85_C))/MIN(−40...85_C)/(85C − (−40_C))
2. Calculated using the box method: (MAX(2.5...3.6V) − MIN(2.5...3.6V))/MIN(2.5...3.6V)/(3.6V − 2.5V)
SD16_A, performance (fSD16 = 1MHz, SD16OSRx = 256, SD16REFON = 1, SD16BUFx = 00)
PARAMETER
SINAD
Signal-to-noise
Signal
to noise +
distortion ratio
TEST CONDITIONS
VCC
83.5
85
SD16GAINx = 2,Signal Amplitude = 250mV
81.5
84
76
79.5
73
76.5
69
73
SD16GAINx = 4,Signal Amplitude = 125mV
SD16GAINx = 8,Signal Amplitude = 62mV
fIN = 50 Hz,
100 Hz
3V
SD16GAINx = 32,Signal Amplitude = 15mV
62
69
1.00
1.02
SD16GAINx = 2
1.90
1.96
2.02
3.76
3.86
3.96
7.36
7.62
7.84
SD16GAINx = 16
14.56
15.04
15.52
SD16GAINx = 32
27.20
28.35
29.76
3V
SD16GAINx = 8
Offset error
±0.2
dEOS/dT
Offset error
temperature
coefficient
CMRR
Common
mode
Common-mode
rejection ratio
AC PSRR
30
AC power supply
rejection ratio
3V
SD16GAINx = 32
SD16GAINx = 1
3V
SD16GAINx = 32
SD16GAINx = 1, Common-mode input signal:
VID = 500 mV, fIN = 50 Hz, 100 Hz
SD16GAINx = 32, Common-mode input signal:
VID = 16 mV, fIN = 50 Hz, 100 Hz
SD16GAINx = 1, VCC = 3 V ± 100 mV, fVCC = 50 Hz
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
dB
0.97
SD16GAINx = 1
EOS
MAX
SD16GAINx = 1
SD16GAINx = 4
Nominal gain
TYP
SD16GAINx = 1,Signal Amplitude = 500mV
SD16GAINx = 16,Signal Amplitude = 31mV
G
MIN
±1.5
±4
±20
±20
±100
%FSR
ppm
FSR/_C
>90
3V
dB
>75
3V
>80
dB
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SD16_A, temperature sensor
PARAMETER
TEST CONDITIONS
VCC
MIN
TCSensor
Sensor temperature
coefficient
1.18
VOffset,sensor
Sensor offset voltage
−100
VSensor
Sensor output
S
t t voltage
lt
(see Note 2)
Temperature sensor voltage at TA = 85°C
Temperature sensor voltage at TA = 25°C
3V
Temperature sensor voltage at TA = 0°C
TYP
1.32
MAX
UNIT
1.46
mV/K
100
mV
435
475
515
355
395
435
320
360
400
mV
NOTES: 1. The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor ( 273 + T [°C] ) + VOffset,sensor [mV]
2. Results based on characterization and/or production test, not TCSensor or VOffset,sensor.
SD16_A, built-in voltage reference
PARAMETER
TEST CONDITIONS
VCC
VREF
Internal reference
voltage
SD16REFON = 1, SD16VMIDON = 0
3V
IREF
Reference supply
current
SD16REFON = 1, SD16VMIDON = 0
3V
TC
Temperature coefficient
SD16REFON = 1, SD16VMIDON = 0
3V
CREF
VREF load capacitance
SD16REFON = 1, SD16VMIDON = 0 (see Note 1)
ILOAD
VREF(I) maximum load
current
SD16REFON = 1, SD16VMIDON = 0
3V
tON
Turn-on time
SD16REFON = 0−>1, SD16VMIDON = 0,
CREF = 100 nF
3V
DC PSR
DC power-supply
rejection, ΔVREF/ΔVCC
SD16REFON = 1, SD16VMIDON = 0, VCC = 2.5 V to 3.6 V
MIN
1.14
TYP
MAX
UNIT
1.20
1.26
V
175
260
μA
18
50
ppm/K
100
nF
±200
5
nA
ms
μV/V
100
NOTES: 1. There is no capacitance required on VREF. However, a capacitance of at least 100nF is recommended to reduce any reference
voltage noise.
SD16_A, reference output buffer
PARAMETER
TEST CONDITIONS
VCC
VREF,BUF
Reference buffer output
voltage
SD16REFON = 1, SD16VMIDON = 1
3V
1.2
IREF,BUF
Reference supply +
reference output buffer
quiescent current
SD16REFON = 1, SD16VMIDON = 1
3V
385
CREF(O)
Required load
capacitance on VREF
SD16REFON = 1, SD16VMIDON = 1
ILOAD,Max
Maximum load current
on VREF
SD16REFON = 1, SD16VMIDON = 1
3V
Maximum voltage
variation vs load current
|ILOAD| = 0 to 1 mA
3V
Turn-on time
SD16REFON = 0−>1, SD16VMIDON = 1,
CREF = 470 nF
3V
tON
MIN
TYP
MAX
UNIT
V
600
470
μA
nF
−15
±1
mA
+15
mV
μs
100
SD16_A, external reference input
PARAMETER
TEST CONDITIONS
VCC
VREF(I)
Input voltage range
SD16REFON = 0
3V
IREF(I)
Input current
SD16REFON = 0
3V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
1.0
TYP
1.25
MAX
UNIT
1.5
V
50
nA
31
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, supply specifications
PARAMETER
AVCC
Analog supply voltage
TEST CONDITIONS
VCC
AVCC = DVCC,
AVSS = DVSS = 0 V
Supply current
(see Notes 1 and 2)
DAC12AMPx = 2, DAC12IR=1,
DAC12_xDAT = 0800h, VREF,DAC12 = AVCC
DAC12AMPx = 5, DAC12IR = 1,
DAC12_xDAT = 0800h, VREF,DAC12 = AVCC
Power supply
rejection ratio
(see Notes 3 and 4)
DAC12_xDAT = 800h, VREF,DAC12 = 1.2V
ΔAVCC = 100 mV
MAX
UNIT
3.60
V
50
110
50
110
200
440
700
1500
μA
A
2 2V/3V
2.2V/3V
DAC12AMPx=7, DAC12IR = 1,
DAC12_xDAT = 0800h, VREF,DAC12 = AVCC
PSRR
TYP
2.20
DAC12AMPx = 2, DAC12IR=0,
DAC12_xDAT=0800h
IDD
MIN
2.7V
70
dB
NOTES: 1. No load at the output pin assuming that the control bits for the shared pins are set properly.
2. Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input
specifications.
3. PSRR = 20 × log{ΔAVCC/ΔVDAC12_xOUT}.
4. VREF is applied externally. The internal reference is not used.
32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (see Figure 12)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
Resolution
12-bit monotonic
INL
Integral nonlinearity
(see Note 1)
VREF,DAC12 = 1.2 V,
DAC12AMPx = 7, DAC12IR = 1
2.7 V
±2.0
±8.0
LSB
DNL
Differential nonlinearity
(see Note 1)
VREF,DAC12 = 1.2 V,
DAC12AMPx = 7, DAC12IR = 1
2.7 V
±0.4
±1.0
LSB
Offset voltage w/o
calibration
(see Notes 1, 2)
VREF,DAC12 = 1.2 V,
DAC12AMPx = 7, DAC12IR = 1
2.7 V
Offset voltage with
calibration
(see Notes 1, 2)
VREF,DAC12 = 1.2 V,
DAC12AMPx = 7, DAC12IR = 1
EO
dE(O)/dT
12
UNIT
Gain error (see Note 1)
dE(G)/dT
Gain temperature
coefficient (see Note 1)
tOffset_Cal
Time for offset calibration
(see Note 3)
±20
mV
±2.5
2.7 V
Offset error
temperature coefficient
(see Note 1)
EG
bits
±30
2.7 V
VREF,DAC12 = 1.2 V
μV/C
±3.50
2.7 V
2.7 V
% FSR
ppm of
FSR/°C
10
DAC12AMPx = 2
2.7 V
100
DAC12AMPx = 3, 5
2.7 V
32
DAC12AMPx = 4, 6, 7
2.7 V
6
ms
NOTES: 1. Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and
“b” of the first order equation: y = a + b*x. VDAC12_xOUT = EO + (1 + EG) * (VREF,DAC12/4095) * DAC12_xDAT, DAC12IR = 1.
2. The offset calibration works on the output operational amplifier. Offset calibration is triggered setting bit DAC12CALON.
3. The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with
DAC12AMPx = {0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during
calibration may effect accuracy and is not recommended.
DAC V OUT
DAC Output
VR+
RLoad =
Ideal transfer
function
AV CC
2
Offset Error
Positive
CLoad = 100pF
Negative
Gain Error
DAC Code
Figure 12. Linearity Test Load Conditions and Gain/Offset Definition
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (continued)
TYPICAL INL ERROR
vs
DIGITAL INPUT DATA
INL − Integral Nonlinearity Error − LSB
4
VCC = 2.2 V, VREF = 1.2V
DAC12AMPx = 7
DAC12IR = 1
3
2
1
0
−1
−2
−3
−4
0
512
1024
1536
2048
2560
3072
3584
4095
DAC12_xDAT − Digital Code
TYPICAL DNL ERROR
vs
DIGITAL INPUT DATA
DNL − Differential Nonlinearity Error − LSB
2.0
VCC = 2.2 V, VREF = 1.2V
DAC12AMPx = 7
DAC12IR = 1
1.5
1.0
0.5
0.0
−0.5
−1.0
−1.5
−2.0
0
512
1024
1536
2048
2560
DAC12_xDAT − Digital Code
34
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3072
3584
4095
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, output specifications
PARAMETER
TEST CONDITIONS
VCC
MIN
No load, VREF,DAC12 = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
VO
No load, VREF,DAC12 = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
Output voltage
range
(see Note 1,
Figure 15)
RLoad = 3 kΩ, VREF,DAC12 = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
Max DAC12
load capacitance
IL(DAC12)
Max DAC12
load current
0
0.005
AVCC−0.05
AVCC
Output
resistance
(see Figure 15)
0
0.1
AVCC−0.13
AVCC
2.2V/3V
RLoad = 3 kΩ,
VO/P(DAC12) > AVCC – 0.3 V
DAC12_xDAT = 0FFFh
UNIT
V
100
2.2V
−0.5
+0.5
3V
−1.0
+1.0
RLoad = 3 kΩ, VO/P(DAC12) < 0.3 V,
DAC12AMPx = 2, DAC12_xDAT = 0h
RO/P(DAC12)
MAX
2 2V/3V
2.2V/3V
RLoad = 3 kΩ, VREF,DAC12 = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
CL(DAC12)
TYP
2.2V/3V
RLoad = 3 kΩ,
0.3 V ≤ VO/P(DAC12) ≤ AVCC − 0.3 V
150
250
150
250
1
4
pF
mA
Ω
NOTES: 1. Data is valid after the offset calibration of the output amplifier.
ILoad
RO/P(DAC12_x)
Max
RLoad
AV CC
DAC12
2
O/P(DAC12_x)
CLoad= 100pF
Min
0.3
AV CC−0.3V
VOUT
AV CC
Figure 15. DAC12_x Output Resistance Tests
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
35
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
12-bit DAC, reference input specifications
PARAMETER
TEST CONDITIONS
VREF
Reference input
voltage range
Ri(VREF)
Reference input
resistance
NOTES: 1.
2.
3.
4.
VCC
MIN
DAC12IR=0 (see Notes 1 and 2)
2 2V/3V
2.2V/3V
DAC12IR=1 (see Notes 3 and 4)
DAC12IR=0
TYP
MAX
AVCC/3
AVCC+0.2
AVCC
AVCC+0.2
48
56
20
2 2V/3V
2.2V/3V
DAC12IR=1
UNIT
V
MΩ
40
kΩ
For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VREF = [AVCC − VE(O)] / [3*(1 + EG)].
For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VREF = [AVCC − VE(O)] / (1 + EG).
12-bit DAC, dynamic specifications, VREF,DAC12 = AVCC, DAC12IR = 1 (see Figure 16 and Figure 17)
PARAMETER
tON
TEST CONDITIONS
DAC12
on time
DAC12_xDAT = 800h,
ErrorV(O) < ±0.5 LSB
(see Note 1,Figure 16)
Settling time,
time
full scale
DAC12_xDAT
DAC12
xDAT =
80h→ F7Fh→ 80h
VCC
MIN
DAC12AMPx=0 → {2, 3, 4}
DAC12AMPx=0 → {5, 6}
2.2V/3V
DAC12AMPx=0 → 7
DAC12AMPx=2
tS(FS)
tS(C-C)
Settling time,
time
code to code
DAC12AMPx=3,5
2.2V/3V
DAC12AMPx=4,6,7
DAC12_xDAT =
3F8h→ 408h→ 3F8h
DAC12AMPx=2
BF8h→ C08h→ BF8h
DAC12AMPx=4,6,7
SR
Slew rate
DAC12AMPx=3,5
15
30
6
12
100
200
40
80
15
30
2.2V/3V
DAC12AMPx=4,6,7
0.05
0.12
0.35
0.7
1.5
2.7
2.2V/3V
DAC12AMPx=4,6,7
10
15
NOTES: 1. RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 16.
2. Slew rate applies to output voltage steps ≥ 200mV.
Conversion 1
VOUT
ILoad
RLoad = 3 kΩ
Glitch
Energy
Conversion 2
Conversion 3
+/− 1/2 LSB
AV CC
2
RO/P(DAC12.x)
+/− 1/2 LSB
CLoad = 100pF
tsettleLH
Figure 16. Settling Time and Glitch Energy Testing
36
POST OFFICE BOX 655303
μs
μs
μs
V/μs
10
DAC12AMPx=3,5
DAC Output
UNIT
1
DAC12AMPx=2
Glitch energy, full scale
120
2
2.2V/3V
DAC12AMPx=3,5
DAC12 xDAT =
DAC12_xDAT
80h→ F7Fh→ 80h
MAX
60
5
DAC12AMPx=2
DAC12 xDAT =
DAC12_xDAT
80h→ F7Fh→ 80h
TYP
• DALLAS, TEXAS 75265
tsettleHL
nV-ss
nV
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
Conversion 1
Conversion 2
Conversion 3
VOUT
90%
90%
10%
10%
tSRLH
tSRHL
Figure 17. Slew Rate Testing
12-bit DAC, dynamic specifications (continued) (TA = 25°C unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
BW−3dB
3 dB bandwidth,
b d idth
3-dB
VDC=1.5 V, VAC=0.1 VPP
(see Figure 18)
DAC12AMPx = {5, 6}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
MIN
TYP
MAX
UNIT
40
2.2V/3V
DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
180
kHz
550
NOTES: 1. RLOAD = 3 kΩ, CLOAD = 100 pF
ILoad
Ve REF+
RLoad = 3 kΩ
AV CC
DAC12_x
2
DACx
AC
CLoad = 100pF
DC
Figure 18. Test Conditions for 3-dB Bandwidth Specification
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
37
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
operational amplifier OA, supply specifications
PARAMETER
VCC
TEST CONDITIONS
Supply voltage
VCC
MIN
—
TYP
2.2
Fast Mode
ICC
Supply
S
l currentt
(see Note 1)
Medium Mode
2 2 V/3 V
2.2
Slow Mode
PSRR
Power supply rejection ratio
Non-inverting
MAX
2.2 V/3 V
UNIT
3.6
180
290
110
190
50
80
70
V
μA
A
dB
NOTES: 1. P6SEL.x = 1 or SD16AE.x = 1 for each corresponding pin when used in OA input or OA output mode.
operational amplifier OA, input/output specifications
PARAMETER
VI/P
IIkg
TEST CONDITIONS
Input voltage, I/P
Input leakage current, I/P
(see Notes 1 and 2)
VCC
—
TA = −40_C to 55_C
—
TA = 55_C to 85_C
MIN
TYP
−0.1
VCC−1.2
V
±0.5
5
nA
−20
±5
20
nA
50
80
fV(I/P) = 1 kHz
Slow Mode
Vn
Voltage noise density
density, I/P
140
—
Fast Mode
Medium Mode
50
fV(I/P) = 10 kHz
65
Offset voltage
voltage, I/P
see Note 3
2.2 V/3 V
Offset voltage drift
with supply, I/P
0.3V ≤ VIN ≤ VCC−0.3 V
ΔVCC≤ ± 10%, TA = 25°C
2.2 V/3 V
High level output voltage
High-level
voltage, O/P
VOL
Low level output voltage
Low-level
voltage, O/P
CMRR
Common-mode rejection ratio
±10
±1.5
2.2 V
VCC−0.2
VCC
Slow Mode,ISOURCE ≤ −150 μA
3V
VCC−0.1
VCC
Fast Mode, ISOURCE ≤ +500 μA
2.2 V
VSS
0.2
Slow Mode,ISOURCE ≤ +150 μA
3V
VSS
0.1
Non-inverting
2.2 V/3 V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
70
mV
μV/°C
Fast Mode, ISOURCE ≤ −500 μA
NOTES: 1. ESD damage can degrade input current leakage.
2. The input bias current is overridden by the input leakage current.
3. Characterized and calculated using the box method, not production tested.
38
±10
2 2 V/3 V
2.2
Offset temperature drift, I/P
VOH
nV/√Hz
30
Slow Mode
VIO
UNIT
−5
Fast Mode
Medium Mode
MAX
mV/V
V
V
dB
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
operational amplifier OA, dynamic specifications
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
Fast Mode
SR
Medium Mode
Slew rate
0.8
—
Slow Mode
UNIT
V/μs
0.3
Open-loop voltage gain
φm
MAX
1.2
—
100
dB
Phase margin
CL = 50 pF
—
60
deg
Gain margin
CL = 50 pF
—
20
dB
Gain-bandwidth product
(see Figure 19
and Figure 20)
Noninverting Fast Mode
Noninverting,
Mode, RL = 47kΩ,
47kΩ CL = 50pF
ten(on)
Enable time on
ton, noninverting, Gain = 1
ten(off)
Enable time off
GBW
22
2.2
Noninverting
300kΩ CL = 50pF
Noninverting, Medium Mode
Mode, RL =300kΩ,
2 2 V/3 V
2.2
14
1.4
Noninverting Slow Mode
300kΩ CL = 50pF
Noninverting,
Mode, RL =300kΩ,
2.2 V/3 V
10
20
μs
1
μs
2.2 V/3 V
TYPICAL PHASE vs FREQUENCY
TYPICAL OPEN-LOOP GAIN vs FREQUENCY
0
140
120
Fast Mode
100
−50
Fast Mode
80
Medium Mode
60
Phase − degrees
Gain − dB
MHz
05
0.5
40
20
Slow Mode
0
−100
Medium Mode
−150
−20
Slow Mode
−40
−200
−60
−80
0.001
0.01
0.1
1
10
100
Input Frequency − kHz
1000
−250
0.001
10000
0.01
0.1
1
10
100
Input Frequency − kHz
1000
10000
Figure 20
Figure 19
switches to ground
PARAMETER
VCC
TEST CONDITIONS
Supply voltage
VCC
MIN
TYP
2.5
Ilkg
Input leakage current
(see Note 1)
TA = −40_C to + 55_C
IIN
Input current
Input switched to Ground.
0
RON
On resistance
IIN=100 μA, TA=−40°C to 85°C
NOTES: 1. ESD damage can degrade input current leakage.
POST OFFICE BOX 655303
3.6
±1
TA = 55_C to 85_C
• DALLAS, TEXAS 75265
MAX
±10
UNIT
V
±50
nA
100
μA
10
Ω
39
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
flash memory
TEST
CONDITIONS
PARAMETER
VCC(PGM/
VCC
MIN
TYP
MAX
UNIT
Program and erase supply voltage
2.5
3.6
V
fFTG
Flash timing generator frequency
257
476
kHz
IPGM
Supply current from DVCC during program
2.5V/3.6V
3
5
mA
IERASE
Supply current from DVCC during erase
2.5V/3.6V
3
7
mA
tCPT
Cumulative program time
see Note 1
2.5V/3.6V
10
ms
tCMErase
Cumulative mass erase time
see Note 2
2.5V/3.6V
ERASE)
200
104
Program/erase endurance
TJ = 25°C
ms
105
tRetention
Data retention duration
tWord
Word or byte program time
35
tBlock, 0
Block program time for 1st byte or word
30
tBlock, 1-63
Block program time for each additional byte or word
tBlock, End
Block program end-sequence wait time
tMass Erase
Mass erase time
5297
tSeg Erase
Segment erase time
4819
cycles
100
years
21
see Note 3
tFTG
6
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64−byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To
achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met.
(A worst case minimum of 19 cycles are required).
3. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).
JTAG interface
TEST
CONDITIONS
PARAMETER
fTCK
TCK input frequency
see Note 1
RInternal
Internal pull-up resistance on TMS, TCK, TDI/TCLK
see Note 2
VCC
MIN
2.2 V
0
TYP
MAX
UNIT
5
MHz
3V
0
10
MHz
2.2 V/ 3 V
25
60
90
kΩ
MIN
TYP
MAX
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG fuse (see Note 1)
TEST
CONDITIONS
PARAMETER
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TDI/TCLK for fuse-blow: F versions
IFB
Supply current into TDI/TCLK during fuse blow
tFB
Time to blow fuse
TA = 25°C
VCC
2.5
6
UNIT
V
7
V
100
mA
1
ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
input/output schematics
Port P1 pin schematic: P1.0, P1.1, input/output with Schmitt trigger
Pad Logic
DV SS
DV SS
DV SS
P1DIR.x
0
Direction
0: Input
1: Output
1
P1OUT.x
0
Module X OUT
1
Bus
Keeper
P1SEL.x
P1.0/TA0
P1.1/TA0/MCLK
EN
P1IN.x
EN
Module X IN
D
P1IE.x
P1IRQ.x
EN
Q
Set
P1IFG.x
P1SEL.x
P1IES.x
Interrupt
Edge
Select
Note: x = 0,1
Port P1 (P1.0, P1.1) pin functions
PIN NAME (P1.X)
(P1 X)
P1.0/TA0
P1.1/TA0/MCLK
CONTROL BITS / SIGNALS
X
0
1
FUNCTION
P1DIR.x
P1SEL.x
0/1
0
Timer_A3.CCI0A
0
1
Timer_A3.TA0
1
1
0/1
0
Timer_A3.CCI0B
0
1
MCLK
1
1
P1.0† Input/Output
P1.1† Input/Output
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
POST OFFICE BOX 655303
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41
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
Port P1 pin schematic: P1.2, input/output with Schmitt trigger and analog functions
INCH=4
Pad Logic
0
AV SS
A4−
1
SD16AE.x
P1DIR.x
0
Direction
0: Input
1: Output
1
P1OUT.x
0
Module X OUT
1
P1.2/TA1/A4−
Bus
Keeper
P1SEL.x
EN
P1IN.x
EN
Module X IN
D
P1IE.x
P1IRQ.x
EN
Q
P1IFG.x
Set
Interrupt
Edge
Select
P1SEL.x
P1IES.x
Note: x = 2
Port P1 (P1.2) pin functions
(P1 X)
PIN NAME (P1.X)
P1.2/TA1/A4−
CONTROL BITS / SIGNALS
X
2
FUNCTION
P1.2† Input/Output
P1DIR.x
P1SEL.x
SD16AE.x
0/1
0
0
Timer_A3.CCI1A
0
1
0
Timer_A3.TA1
1
1
0
A4− (see Notes 3, 4)
X
X
1
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the SD16AE.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
4. Negative input to SD16_A (A4−) connected to VSS if corresponding SD16AE.x bit is cleared.
42
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
Port P1 pin schematic: P1.3, P1.5, P1.7, input/output with Schmitt trigger and analog functions
INCH=y
Pad Logic
Ay+
SD16AE.x
P1DIR.x
0
Direction
0: Input
1: Output
1
P1OUT.x
0
Module X OUT
1
Bus
Keeper
P1SEL.x
P1.3/TA2/A4+
P1.5/TACLK/ACLK/A3+
P1.7/A2+
EN
P1IN.x
EN
Module X IN
P1IRQ.x
D
P1IE.x
EN
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
Note: x = 3,5,7
y = 4,3,2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
43
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
Port P1 (P1.3, P1.5, P1.7) pin functions
(P1 X)
PIN NAME (P1.X)
P1.3/TA2/A4+
CONTROL BITS / SIGNALS
X
3
FUNCTION
P1.3† Input/Output
Timer_A3.CCI2A
P1.5/TACLK/ACLK/A3+
5
7
P1SEL.x
SD16AE.x
0/1
0
0
0
1
0
Timer_A3.TA2
1
1
0
A4+ (see Note 3)
X
X
1
P1.5† Input/Output
0/1
0
0
Timer_A3.TACLK/INCLK
0
1
0
ACLK
1
1
0
A3+ (see Note 3)
P1.7/A2+
P1DIR.x
P1.5† Input/Output
N/A
X
X
1
0/1
0
0
0
1
0
DVSS
1
1
0
A2+ (see Note 3)
X
X
1
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the SD16AE.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
44
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
Port P1 pin schematic: P1.4, input/output with Schmitt trigger and analog functions
INCH=3
Pad Logic
0
AV SS
A3−
1
SD16AE.x
DAC12OPS
P1DIR.x
0
Direction
0: Input
1: Output
1
P1OUT.x
0
DV SS
1
P1.4/A3−/OA1I0/DAC0
Bus
Keeper
P1SEL.x
EN
P1IN.x
DAC12OPS
P1IE.x
P1IRQ.x
DAC0
EN
Q
Set
P1IFG.x
Interrupt
Edge
Select
P1SEL.x
P1IES.x
+
OA1
−
Note: x = 4
Port P1 (P1.4) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
(P1 X)
X
P1.4/A3−/OA1I0/DAC0
4
FUNCTION
P1.4† Input/Output
P1DIR.x
P1SEL.x
SD16AE.x
OAPx (OA1)
DAC12OPS
0/1
0
0
XX
0
N/A
0
1
0
XX
0
DVSS
1
1
0
XX
0
A3− (see Notes 3, 4)
X
X
1
XX
0
OA1I0
X
X
1
00
0
DAC0 (see Note 5)
X
X
X
XX
1
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the SD16AE.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
4. Negative input to SD16_A (A3−) connected to AVSS if corresponding SD16AE.x bit is cleared.
5. Setting the DAC12OPS bit also disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
POST OFFICE BOX 655303
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45
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
Port P1 pin schematic: P1.6, input/output with Schmitt trigger and analog functions
INCH=2
Pad Logic
0
AV SS
A2−
1
SD16AE.x
P1DIR.x
0
Direction
0: Input
1: Output
1
P1OUT.x
DV SS
0
1
P1.6/A2−/OA0I0
Bus
Keeper
P1SEL.x
EN
P1IN.x
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
+
OA0/1
−
Set
Interrupt
Edge
Select
P1SEL.x
P1IES.x
Note: x = 6
Port P1 (P1.6) pin functions
(P1 X)
PIN NAME (P1.X)
P1.6/A2−/OA0I0
CONTROL BITS / SIGNALS
X
6
FUNCTION
P1DIR.x
P1SEL.x
SD16AE.x
OAPx (OA0)
OAPx (OA1)
0/1
0
0
XX
XX
N/A
0
1
0
XX
XX
DVSS
1
1
0
XX
XX
A2− (see Notes 3, 4)
X
X
1
XX
XX
X
X
1
00 or 01
XX
X
X
1
XX
01
P1.6† Input/Output
OA0I0 (see Note 5)
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the SD16AE.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
4. Negative input to SD16_A (A2−) connected to AVSS if corresponding SD16AE.x bit is cleared.
5. OA0I0 connected to pin if for OA0 the OAPx bits are cleared or set to 01, or if for OA1 the OAPx bits are set to 01.
46
POST OFFICE BOX 655303
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MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
Port P2 pin schematic: P2.0 to P2.1, input/output with Schmitt trigger, LCD and analog functions
Pad Logic
LCDS12
Segment Sy
P2DIR.x
0
Direction
0: Input
1: Output
1
P2OUT.x
DV SS
0
1
P2.0/S13/SW0C
P2.1/S12/SW1C
Bus
Keeper
P2SEL.x
EN
P2IN.x
P2IE.x
P2IRQ.x
SWCTL.SWCLT2 (SW0C)
SWCTL.SWCLT6 (SW1C)
EN
Q
Set
P2IFG.x
AV SS
Interrupt
Edge
Select
P2SEL.x
P2IES.x
Note: x = 0,1
y = 13,12
Port P2 (P2.0, P2.1) pin functions
PIN NAME (P2.X)
(P2 X)
P2.0/S13/SW0C
CONTROL BITS / SIGNALS
X
0
FUNCTION
P2.0† Input/Output
SW0C (see Notes 3, 4)
S13
P2.1/S12/SW1C
1
P2DIR.x
P2SEL.x
LCDS12
0/1
0
0
X
1
0
X
X
1
0/1
0
0
SW1C (see Notes 3, 4)
X
1
0
S12
X
X
1
P2.1† Input/Output
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the P2SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
4. The low impedance switch to ground is closed by setting the corresponding bits in SWCTL register.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
47
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
Port P2 pin schematic: P2.2 to P2.7, input/output with Schmitt trigger, LCD and analog functions
Pad Logic
LCDS4/8/12
Segment Sy
DV SS
P2DIR.x
0
Direction
0: Input
1: Output
1
P2OUT.x
DV SS
0
1
Bus
Keeper
P2SEL.x
EN
P2IN.x
P2IE.x
P2IRQ.x
EN
Q
P2IFG.x
P2SEL.x
P2IES.x
Set
Interrupt
Edge
Select
Note: x = 2 to 7
y = 11 to 6
48
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
P2.2/S11
P2.3/S10
P2.4/S9
P2.5/S8
P2.6/S7
P2.7/S6
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
Port P2 (P2.0 to P2.7) pin functions
(P2 X)
PIN NAME (P2.X)
P2.2/S11
CONTROL BITS / SIGNALS
X
2
FUNCTION
P2.2† Input/Output
N/A
P2.3/S10
3
4
5
6
7
1
0
1
1
0
X
1
P2.3† Input/Output
0/1
0
0
N/A
0
1
0
DVSS
1
1
0
P2.4† Input/Output
X
X
1
0/1
0
0
0
1
0
DVSS
1
1
0
S9
X
X
1
0/1
0
0
N/A
0
1
0
DVSS
1
1
0
P2.5† Input/Output
P2.6† Input/Output
N/A
P2.7/S6
0
0
X
S8
P2.6/S7
LCDS12
0
S11
N/A
P2.5/S8
P2SEL.x
0/1
DVSS
S10
P2.4/S9
P2DIR.x
X
X
1
0/1
0
0
0
1
0
DVSS
1
1
0
S7
X
X
1
0/1
0
0
N/A
0
1
0
DVSS
1
1
0
S6
X
X
1
P2.7† Input/Output
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
49
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
Port P5 pin schematic: P5.0, P5.1, P5.5 to P5.7, input/output with Schmitt trigger and LCD functions
Pad Logic
LCDS0/4
Segment Sy
DV SS
P5DIR.x
0
1
P5OUT.x
DV SS
P5SEL.x
Direction
0: Input
1: Output
0
1
Bus
Keeper
EN
P5IN.x
Note: x = 0,1,5,6,7
y = 1,0,2,3,4
50
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
P5.0/S1
P5.1/S0
P5.5/S2
P5.6/S3
P5.7/S4
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
Port P5 (P5.0, P5.1, P5.5, P5.6) pin functions
(P5 X)
PIN NAME (P5.X)
P5.0/S1
CONTROL BITS / SIGNALS
X
0
FUNCTION
P5.0† Input/Output
N/A
P5.1/S0
1
5
6
LCDS0
0
0
0
1
0
1
1
0
S1
X
X
1
P5.1† Input/Output
0/1
0
0
N/A
0
1
0
DVSS
1
1
0
P5.5† Input/Output
N/A
P5.6/S3
P5SEL.x
0/1
DVSS
S0
P5.5/S2
P5DIR.x
X
X
1
0/1
0
0
0
1
0
DVSS
1
1
0
S2
X
X
1
0/1
0
0
N/A
0
1
0
DVSS
1
1
0
S3
X
X
1
P5.6† Input/Output
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
Port P5 (P5.7) pin functions
(P5 X)
PIN NAME (P5.X)
P5.7/S4
CONTROL BITS / SIGNALS
X
7
FUNCTION
P5DIR.x
P5SEL.x
LCDS4
0/1
0
0
N/A
0
1
0
DVSS
1
1
0
S4
X
X
1
P5.7† Input/Output
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
POST OFFICE BOX 655303
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51
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
Port P5 pin schematic: P5.2 to P5.4, input/output with Schmitt trigger and LCD functions
Pad Logic
LCD Signal
DV SS
P5DIR.x
0
Direction
0: Input
1: Output
1
P5OUT.x
DV SS
0
1
Bus
Keeper
P5SEL.x
P5.2/COM1
P5.3/COM2
P5.4/COM3
EN
P5IN.x
Note: x = 2 to 4
Port P5 (P5.2 to P5.4) pin functions
(P5 X)
PIN NAME (P5.X)
CONTROL BITS / SIGNALS
X
P5.2/COM1
2
P5.3/COM2
3
FUNCTION
P5.2† Input/Output
COM1
P5.3† Input/Output
COM2
P5.4/COM3
4
P5.4† Input/Output
COM3
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
52
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
P5DIR.x
P5SEL.x
0/1
0
X
1
0/1
0
X
1
0/1
0
X
1
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
Port P6 pin schematic: P6.0, P6.2, input/output with Schmitt trigger and analog functions
INCH=0/1 #
Pad Logic
Ay+ #
P6DIR.x
0
Direction
0: Input
1: Output
1
P6OUT.x
DV SS
0
1
Bus
Keeper
P6SEL.x
P6.0/A0+/OA0O
P6.2/A1+/OA1O
EN
P6IN.x
Note: x = 0,2
y = 0,1
#Signal from or to SD16
+
OA0/1
−
Port P6 (P6.0, P6.2) pin functions
PIN NAME (P6.X)
(P6 X)
P6.0/A0+/OA0O
CONTROL BITS / SIGNALS
X
0
FUNCTION
P6.0† Input/Output
A0+/OA0O (see Note 3)
P6.2/A1+/OA1O
2
P6.2† Input/Output
A1+/OA1O (see Note 3)
P6DIR.x
P6SEL.x
0/1
0
X
1
0/1
0
X
1
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
53
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
Port P6 pin schematic: P6.1, P6.3, input/output with Schmitt trigger and analog functions
INCH=0/1 #
Pad Logic
Ay−#
P6DIR.x
0
Direction
0: Input
1: Output
1
P6OUT.x
DV SS
0
1
Bus
Keeper
P6SEL.x
P6.1/A0−/OA0FB
P6.3/A1−/OA1FB
EN
P6IN.x
Note: x = 1,3
y = 0,1
#Signal from or to SD16
+
OA0/1
−
Port P6 (P6.1, P6.3) pin functions
PIN NAME (P6.X)
(P6 X)
P6.1/A0−/OA0FB
CONTROL BITS / SIGNALS
X
1
FUNCTION
P6.1† Input/Output
A0−/OA0FB (see Note 3)
P6.3/A1−/OA1FB
3
P6.3† Input/Output
A1−/OA1FB (see Note 3)
†
P6DIR.x
P6SEL.x
0/1
0
X
1
0/1
0
X
1
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
54
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
Port P6 pin schematic: P6.4 to P6.7, input/output with Schmitt trigger and analog functions
P6DIR.x
Pad Logic
0
Direction
0: Input
1: Output
1
P6OUT.x
DV SS
0
1
Bus
Keeper
P6SEL.x
P6.4/OA0I1
P6.5/OA0I2
P6.6/OA1I1
P6.7/OA1I2
EN
P6IN.x
+
OA0/1
−
Note: x = 4 to 7
Port P6 (P6.4 to P6.7) pin functions
PIN NAME (P6.X)
(P6 X)
CONTROL BITS / SIGNALS
X
P6.4/OA0I1
4
P6.5/OA0I2
5
P6.6/OA1I1
P6.7/OA1I2
6
7
FUNCTION
P6DIR.x
P6SEL.x
0/1
0
OA0I1 (see Note 3)
X
1
P6.5† Input/Output
0/1
0
OA0I2 (see Note 3)
X
1
P6.6† Input/Output
0/1
0
OA1I1 (see Note 3)
X
1
P6.7† Input/Output
0/1
0
OA1I2 (see Note 3)
X
1
P6.4† Input/Output
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
55
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger or output
TDO
Controlled by JTAG
Controlled by JTAG
TDO/TDI
JTAG
Controlled
by JTAG
DVCC
TDI
Burn and Test
Fuse
TDI/TCLK
Test
and
Emulation
DVCC
TMS
Module
TMS
DVCC
TCK
TCK
RST/NMI
Tau ~ 50 ns
Brownout
TCK
56
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
G
D
U
S
G
D
U
S
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current (I(TF) ) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be
taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see
Figure 21). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition). The JTAG pins are terminated internally and therefore do not require external termination.
Time TMS Goes Low After POR
TMS
I(TF)
ITDI/TCLK
Figure 21. Fuse Check Mode Current
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
57
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
Data Sheet Revision History
Literature
Number
Summary
SLAS556
Product Preview data sheet release
SLAS556A
Production Data data sheet release
NOTE: Page and figure numbers refer to the respective document revision.
58
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
MSP430FG4250IDL
ACTIVE
SSOP
DL
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430FG4250
MSP430FG4250IDLR
ACTIVE
SSOP
DL
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430FG4250
MSP430FG4250IRGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430
FG4250
MSP430FG4250IRGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430
FG4250
MSP430FG4260IDL
ACTIVE
SSOP
DL
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430FG4260
MSP430FG4260IDLR
ACTIVE
SSOP
DL
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430FG4260
MSP430FG4260IRGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430
FG4260
MSP430FG4260IRGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430
FG4260
MSP430FG4270IDL
ACTIVE
SSOP
DL
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430FG4270
MSP430FG4270IDLR
ACTIVE
SSOP
DL
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430FG4270
MSP430FG4270IRGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430
FG4270
MSP430FG4270IRGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430
FG4270
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
MSP430FG4250IDLR
SSOP
DL
48
1000
330.0
32.4
11.35
16.2
3.1
16.0
32.0
Q1
MSP430FG4260IDLR
SSOP
DL
48
1000
330.0
32.4
11.35
16.2
3.1
16.0
32.0
Q1
MSP430FG4270IDLR
SSOP
DL
48
1000
330.0
32.4
11.35
16.2
3.1
16.0
32.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430FG4250IDLR
SSOP
DL
48
1000
367.0
367.0
55.0
MSP430FG4260IDLR
SSOP
DL
48
1000
367.0
367.0
55.0
MSP430FG4270IDLR
SSOP
DL
48
1000
367.0
367.0
55.0
Pack Materials-Page 2
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Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Texas Instruments:
MSP430FG4250IDLR MSP430FG4250IRGZR MSP430FG4260IDLR MSP430FG4260IRGZR
MSP430FG4270IRGZR MSP430FG4250IDL MSP430FG4250IRGZT MSP430FG4260IDL MSP430FG4260IRGZT
MSP430FG4270IRGZT MSP430FG4270IDLR MSP430FG4270IDL