ISL8103 ® Data Sheet February 15, 2006 Three-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers FN9246.0 Features • Integrated Multi-Phase Power Conversion - 1, 2, or 3 Phase Operation The ISL8103 is a three-phase PWM control IC with integrated MOSFET drivers. It provides a precision voltage regulation system for multiple applications including, but not limited to, high current low voltage point-of-load converters, embedded applications and other general purpose low voltage medium to high current applications.The integration of power MOSFET drivers into the controller IC marks a departure from the separate PWM controller and driver configuration of previous multi-phase product families. By reducing the number of external parts, this integration allows for a cost and space saving power management solution. • Precision Output Voltage Regulation - Differential Remote Voltage Sensing - ±0.8% System Accuracy Over Temperature (for REF=0.6V and 0.9V) - ±0.5% System Accuracy Over Temperature (for REF=1.2V and 1.5V) - Usable for Output Voltages not Exceeding 2.3V - Adjustable Reference-Voltage Offset • Precision Channel Current Sharing - Uses Loss-Less rDS(ON) Current Sampling Output voltage can be programmed using the on-chip DAC or an external precision reference. A two bit code programs the DAC reference to one of 4 possible values (0.6V, 0.9V, 1.2V and 1.5V). A unity gain, differential amplifier is provided for remote voltage sensing, compensating for any potential difference between remote and local grounds. The output voltage can also be offset through the use of single external resistor. An optional droop function is also implemented and can be disabled for applications having less stringent output voltage variation requirements or experiencing less severe step loads. • Optional Load Line (Droop) Programming - Uses Loss-Less Inductor DCR Current Sampling • Variable Gate-Drive Bias - 5V to 12V • Internal or External Reference Voltage Setting - On-Chip Adjustable Fixed DAC Reference voltage with 2-bit Logic Input Selects from Four Fixed Reference Voltages (0.6V, 0.9V, 1.2V, 1.5V) - Reference can be Changed Dynamically - Can use an External Voltage Reference A unique feature of the ISL8103 is the combined use of both DCR and rDS(ON) current sensing. Load line voltage positioning and overcurrent protection are accomplished through continuous inductor DCR current sensing, while rDS(ON) current sensing is used for accurate channel-current balance. Using both methods of current sampling utilizes the best advantages of each technique. • Overcurrent Protection Protection features of this controller IC include a set of sophisticated overvoltage and overcurrent protection. Overvoltage results in the converter turning the lower MOSFETs ON to clamp the rising output voltage and protect the load. An OVP output is also provided to drive an optional crowbar device. The overcurrent protection level is set through a single external resistor. Other protection features include protection against an open circuit on the remote sensing inputs. Combined, these features provide advanced protection for the output load. • Pb-Free Plus Anneal Available (RoHS Compliant) • Multi-tiered Overvoltage Protection - OVP Pin to Drive Optional Crowbar Device • Selectable Operation Frequency up to 1.5MHz per Phase • Digital Soft-Start • Capable of Start-up in a Pre-Biased Load Applications • High Current DDR/Chipset Core Voltage Regulators • High Current, Low Voltage DC/DC Converters • High Current, Low Voltage FPGA/ASIC DC/DC Converters Ordering Information PART NUMBER* PART MARKING TEMERATURE (°C) PACKAGE PKG. DWG. # ISL8103CRZ (Note) ISL8103CRZ 0 to 70 40 Ld 6x6 QFN (Pb-free) L40.6x6 ISL8103IRZ (Note) ISL8103IRZ -40 to 85 40 Ld 6x6 QFN (Pb-free) L40.6x6 ISL8103EVAL1 Evaluation Platform * Add “-T” suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL8103 Pinout REF0 REF1 OVP ENLL FS PGOOD LGATE1 PVCC1 ISEN1 UGATE1 ISL8103 (6x6 QFN) TOP VIEW 40 39 38 37 36 35 34 33 32 31 3PH 1 30 BOOT1 2PH 2 29 PHASE1 DAC 3 28 PHASE2 REF 4 27 UGATE2 OFST 5 26 BOOT2 VCC 6 25 ISEN2 COMP 7 24 PVCC2 FB 8 23 LGATE2 VDIFF 9 22 PHASE3 RGND 10 21 BOOT3 2 11 12 13 14 15 16 17 18 19 20 VSEN OCSET ICOMP DROOP ISUM IREF LGATE3 PVCC3 ISEN3 UGATE3 41 GND FN9246.0 February 15, 2006 ISL8103 Block Diagram ICOMP DROOP OCSET ISEN AMP PGOOD OVP 100µA ENLL 0.66V ISUM POWER-ON OC IREF VCC RESET PVCC1 RGND VSEN BOOT1 +1V UGATE1 SOFT-START AND x1 x1 GATE CONTROL LOGIC FAULT LOGIC SHOOTTHROUGH PROTECTION PHASE1 VDIFF LGATE1 UVP 0.2V FS OVP PVCC2 CLOCK AND SAWTOOTH GENERATOR OVP BOOT2 UGATE2 PWM1 ∑ GATE CONTROL LOGIC +150mV x 0.82 ∑ SHOOTTHROUGH PROTECTION PHASE2 PWM2 LGATE2 REF1 DAC ∑ REF0 PWM3 2PH CHANNEL DETECT 3PH DAC PVCC3 BOOT3 REF CHANNEL CURRENT BALANCE E/A FB 1 N COMP OFST ∑ UGATE3 GATE CONTROL LOGIC SHOOTTHROUGH PROTECTION OFFSET PHASE3 LGATE3 CHANNEL CURRENT SENSE ISEN1 3 ISEN2 ISEN3 GND FN9246.0 February 15, 2006 ISL8103 Typical Application - ISL8103 +12V VDIFF FB COMP PVCC1 BOOT1 VSEN +5V RGND UGATE1 3PH 2PH PHASE1 ISEN1 VCC LGATE1 OFST +12V FS PVCC2 BOOT2 DAC UGATE2 ISL8103 PHASE2 REF ISEN2 LOAD LGATE2 REF1 REF0 +12V +12V OVP PGOOD PVCC3 GND BOOT3 UGATE3 PHASE3 ENLL ISEN3 IREF DROOP LGATE3 OCSET ICOMP 4 ISUM FN9246.0 February 15, 2006 ISL8103 Absolute Maximum Ratings Thermal Information Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Supply Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +15V Absolute Boot Voltage, VBOOT . . . . . . . . GND - 0.3V to GND + 36V Phase Voltage, VPHASE . . . . . . . . GND - 0.3V to 15V (PVCC = 12) GND - 8V (<400ns, 20µJ) to 24V (<200ns, VBOOT-PHASE = 12V) Upper Gate Voltage, VUGATE . . . . VPHASE - 0.3V to VBOOT + 0.3V VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V Lower Gate Voltage, VLGATE. . . . . . . . GND - 0.3V to PVCC + 0.3V GND - 5V (<100ns Pulse Width, 2µJ) to PVCC+ 0.3V Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD Thermal Resistance θJA (°C/W) θJC (°C/W) QFN Package (Notes 1, 2) . . . . . . . . . . 32 3.5 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C Recommended Operating Conditions VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5% PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5% Ambient Temperature (ISL8103CRZ) . . . . . . . . . . . . . . 0°C to 70°C Ambient Temperature (ISL8103IRZ) . . . . . . . . . . . . . .-40°C to 85°C CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. NOTES: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS BIAS SUPPLY AND INTERNAL OSCILLATOR Input Bias Supply Current IVCC; ENLL = high - 15 20 mA Gate Drive Bias Current IPVCC; ENLL = high; all gate outputs open, Fsw = 250kHz - 0.8 2.00 mA VCC POR (Power-On Reset) Threshold VCC Rising 4.25 4.38 4.50 V VCC Falling 3.75 3.88 4.00 V PVCC Rising 4.25 4.38 4.50 V PVCC Falling 3.75 3.88 4.00 V - 1.50 - V - 66.6 - % ENLL Rising Threshold - 0.66 - V ENLL Hysteresis - 100 - mV COMP Falling 0.1 0.25 0.4 V System Accuracy (DAC = 0.6V, 0.9V) DROOP connected to IREF -0.8 - 0.8 % System Accuracy (DAC = 1.2V, 1.50V) DROOP connected to IREF -0.5 - 0.5 % DAC Input Low Voltage (REF0, REF1) - - 0.4 V DAC Input High Voltage (REF0, REF1) 0.8 - - V External Reference (Note 3) 0.6 1.75 V PVCC POR (Power-On Reset) Threshold Oscillator Ramp Amplitude (Note 3) VPP Maximum Duty Cycle (Note 3) CONTROL THRESHOLDS COMP Shutdown Threshold REFERENCE AND DAC OFS Sink Current Accuracy (Negative Offset) ROFS = 30kΩ from OFS to VCC 47.5 50.0 52.5 µA OFS Source Current Accuracy (Positive Offset) ROFS = 10kΩ from OFS to GND 47.5 50.0 52.5 µA 5 FN9246.0 February 15, 2006 ISL8103 Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ERROR AMPLIFIER DC Gain (Note 3) RL = 10K to ground - 96 - dB Gain-Bandwidth Product (Note 3) CL = 100pF, RL = 10K to ground - 20 - MHz Slew Rate (Note 3) CL = 100pF, Load = ±400µA - 8 - V/µs Maximum Output Voltage Load = 1mA 3.90 4.20 - V Minimum Output Voltage Load = -1mA - 0.85 1.0 V 49 55 60 µA Bandwidth (Note 3) - 20 - MHz Slew Rate (Note 3) - 8 - V/µs 93 100 107 µA REMOTE SENSE DIFFERENTIAL AMPLIFIER Input Bias Current (VSEN) (VSEN = 1.5V) OVERCURRENT PROTECTION OCSET Trip Current OCSET Accuracy OC comparator offset (OCSET and ISUM Difference) -5 0 5 mV ICOMP Offset ISEN amplifier offset -5 0 5 mV Undervoltage Threshold VSEN falling 80 82 84 %VID Undervoltage Hysteresis VSEN Rising - 3 - %VID 1.62 1.67 1.72 V PROTECTION Overvoltage Threshold while IC Disabled Overvoltage Threshold VSEN Rising DAC + 125mV DAC + 150mV DAC + 175mV V Overvoltage Hysteresis VSEN Falling - 50 - mV Open Sense-Line Protection Threshold IREF Rising and Falling VDIFF + 0.9V VDIFF + 1V VDIFF + 1.1V V OVP Output High Drive Voltage IOVP = 50mA, VCC = 5V 2.2 3.9 V SWITCHING TIME UGATE Rise Time (Note 3) tRUGATE; VPVCC = 12V, 3nF Load, 10% to 90% - 26 - ns LGATE Rise Time (Note 3) tRLGATE; VPVCC = 12V, 3nF Load, 10% to 90% - 18 - ns UGATE Fall Time (Note 3) tFUGATE; VPVCC = 12V, 3nF Load, 90% to 10% - 18 - ns LGATE Fall Time (Note 3) tFLGATE; VPVCC = 12V, 3nF Load, 90% to 10% - 12 - ns UGATE Turn-On Non-overlap (Note 3) tPDHUGATE; VPVCC = 12V, 3nF Load, Adaptive - 10 - ns LGATE Turn-On Non-overlap (Note 3) tPDHLGATE; VPVCC = 12V, 3nF Load, Adaptive - 10 - ns GATE DRIVE RESISTANCE (Note 3) Upper Drive Source Resistance VPVCC = 12V, 150mA Source Current 1.25 2.0 3.0 Ω Upper Drive Sink Resistance VPVCC = 12V, 150mA Sink Current 0.9 1.6 3.0 Ω Lower Drive Source Resistance VPVCC = 12V, 150mA Source Current 0.85 1.4 2.2 Ω Lower Drive Sink Resistance VPVCC = 12V, 150mA Sink Current 0.60 0.94 1.35 Ω Thermal Shutdown Setpoint (Note 3) - 160 - °C Thermal Recovery Setpoint (Note 3) - 100 - °C OVER TEMPERATURE SHUTDOWN NOTE: 3. Parameter magnitude guaranteed by design. Not 100% tested. 6 FN9246.0 February 15, 2006 ISL8103 Timing Diagram tPDHUGATE tRUGATE tFUGATE UGATE LGATE tFLGATE tRLGATE tPDHLGATE Simplified Power System Diagram +12VIN +5VIN Q1 CHANNEL1 Q2 2 REF0,REF1 DAC ENLL Q3 OVP PGOOD VOUT CHANNEL2 Q4 ISL8103 Q5 CHANNEL3 Q6 Functional Pin Description VCC (Pin 6) Bias supply for the IC’s small-signal circuitry. Connect this pin to a +5V supply and locally decouple using a quality 1.0µF ceramic capacitor. PVCC1, PVCC2, PVCC3 (Pins 33, 24, 18) Power supply pins for the corresponding channel MOSFET drive. These pins can be connected to any voltage from +5V to +12V, depending on the desired MOSFET gate drive level. Note that tying PVCC2 OR PVCC3 to GND has the same effect as tying 2PH or 3PH to GND for disabling the corresponding phase GND (Pin 41) Bias and reference ground for the IC. 7 ENLL (Pin 37) This pin is a threshold sensitive (approximately 0.66V) enable input for the controller. Held low, this pin disables controller operation. Pulled high, the pin enables the controller for operation. FS (Pin 36) A resistor, placed from FS to ground, will set the switching frequency. Refer to Equation 33 and Figure 23 for proper resistor calculation 3PH and 2PH (Pins 1, 2) These pins decide how many phases the controller will operate. Tying both pins to VCC allows for 3-phase operation. Tying the 3PH pin to GND causes the controller to operate in 2-phase mode, while connecting both 3PH and 2PH GND will allow for single phase operation. FN9246.0 February 15, 2006 ISL8103 REF0 and REF1 (Pins 40, 39) DAC (Pin 3) These pins make up the 2-bit input that selects the fixed DAC reference voltage. These pins respond to TTL logic thresholds. The ISL8103 decodes these inputs to establish one of four fixed reference voltages; see “Table 1” for correspondence between REF0 and REF1 inputs and reference voltage settings. The DAC pin is the direct output of the internal DAC. This pin is connected to the REF pin using a 1-5kΩ resistor. This pin can be left open if an external reference is used. These pins are internally pulled high, to approximately 1.2V, by 40µA (typically) internal current sources; the internal pullup current decreases to 0 as the REF0 and REF1 voltages approach the internal pull-up voltage. Both REF0 and REF1 pins are compatible with external pull-up voltages not exceeding the IC’s bias voltage (VCC). RGND and VSEN (Pins 10, 11) RGND and VSEN are inputs to the precision differential remote-sense amplifier and should be connected to the sense pins of the remote load. REF (Pin 4) The REF input pin is the positive input of the error amplifier. This pin can be connected to the DAC pin using a resistor (1-5kΩ) when the internal DAC voltage is used as the reference voltage. When an external voltage reference is used, it must be connected directly to the REF pin, while the DAC pin is left unconnected. The output voltage will be regulated to the voltage at the REF pin unless this voltage is greater than the voltage at the DAC pin. If an external reference is used at this pin, its magnitude cannot exceed 1.75V. A capacitor is used between the REF pin and ground to smooth the DAC voltage during soft-start. ICOMP, ISUM, and IREF (Pins 13, 15, 16) OFST (Pin 5) ISUM, IREF, and ICOMP are the DCR current sense amplifier’s negative input, positive input, and output respectively. For accurate DCR current sensing, connect a resistor from each channel’s phase node to ISUM and connect IREF to the summing point of the output inductors. A parallel R-C feedback circuit connected between ISUM and ICOMP will then create a voltage from IREF to ICOMP proportional to the voltage drop across the inductor DCR. This voltage is referred to as the droop voltage and is added to the differential remote-sense amplifier’s output. The OFST pin provides a means to program a DC current for generating an offset voltage across the resistor between FB and VDIFF. The offset current is generated via an external resistor and precision internal voltage references. The polarity of the offset is selected by connecting the resistor to GND or VCC. For no offset, the OFST pin should be left unconnected. OCSET (Pin 12) An optional 0.001-0.01µF ceramic capacitor can be placed from the IREF pin to the ISUM pin to help reduce common mode noise that might be introduced by the layout. This is the overcurrent set pin. Placing a resistor from OCSET to ICOMP, allows a 100µA current to flow out of this pin, producing a voltage reference. Internal circuitry compares the voltage at OCSET to the voltage at ISUM, and if ISUM ever exceeds OCSET, the overcurrent protection activates. DROOP (Pin 14) ISEN1, ISEN2 and ISEN3 (Pins 32, 25, 19) This pin enables or disables droop. Tie this pin to the ICOMP pin to enable droop. To disable droop, tie this pin to the IREF pin. These pins are used for balancing the channel currents by sensing the current through each channel’s lower MOSFET when it is conducting. Connect a resistor between the ISEN1, ISEN2, and ISEN3 pins and their respective phase node. This resistor sets a current proportional to the current in the lower MOSFET during its conduction interval. VDIFF (Pin 9) VDIFF is the output of the differential remote-sense amplifier. The voltage on this pin is equal to the difference between VSEN and RGND added to the difference between IREF and ICOMP. VDIFF therefore represents the VOUT voltage plus the droop voltage. FB and COMP (Pin 7, 8) The internal error amplifier’s inverting input and output respectively. FB is connected to VDIFF through an external R or R-C network depending on the desired type of compensation (Type II or III). COMP is tied back to FB through an external R-C network to compensate the regulator. PHASE1, PHASE2, and PHASE3 (Pins 29, 28, 22) Connect these pins to the sources of the upper MOSFETs. 8 UGATE1, UGATE2, and UGATE3 (Pins 31, 27, 20) Connect these pins to the upper MOSFETs’ gates. These pins are used to control the upper MOSFETs and are monitored for shoot-through prevention purposes. Maximum individual channel duty cycle is limited to 66%. BOOT1, BOOT2, and BOOT3 (Pins 30, 26, 21) These pins provide the bias voltage for the upper MOSFETs’ drives. Connect these pins to appropriately-chosen external bootstrap capacitors. Internal bootstrap diodes connected to the PVCC pins provide the necessary bootstrap charge. These pins are the return path for the upper MOSFETs’ drives. FN9246.0 February 15, 2006 ISL8103 LGATE1, LGATE2, and LGATE3 (Pins 34, 23, 17) These pins are used to control the lower MOSFETs and are monitored for shoot-through prevention purposes. Connect these pins to the lower MOSFETs’ gates. Do not use external series gate resistors as this might lead to shootthrough. PGOOD (Pin 35) PGOOD is used as an indication of the end of soft-start. It is an open-drain logic output that is low impedance until the soft-start is completed and VOUT is equal to the VID setting. Once in normal operation PGOOD indicates whether the output voltage is within specified overvoltage and undervoltage limits. If the output voltage exceeds these limits or a reset event occurs (such as an overcurrent event), PGOOD becomes high impedance again. The potential at this pin should not exceed that of the potential at VCC pin by more than a typical forward diode drop at any time. combine to form the AC ripple current and the DC load current. The ripple component has three times the ripple frequency of each individual channel current. Each PWM pulse is terminated 1/3 of a cycle after the PWM pulse of the previous phase. The peak-to-peak current for each phase is about 7A, and the dc components of the inductor currents combine to feed the load. IL1 + IL2 + IL3, 7A/DIV IL3, 7A/DIV PWM3, 5V/DIV IL2, 7A/DIV PWM2, 5V/DIV IL1, 7A/DIV OVP (Pin 38) Overvoltage protection pin. This pin pulls to VCC when an overvoltage condition is detected. Connect this pin to the gate of an SCR or MOSFET tied across VIN and ground to prevent damage to a load device. Operation Multi-Phase Power Conversion Modern low voltage DC/DC converter load current profiles have changed to the point that the advantages of multiphase power conversion are impossible to ignore. The technical challenges associated with producing a singlephase converter that is both cost-effective and thermally viable have forced a change to the cost-saving approach of multi-phase. The ISL8103 controller helps simplify implementation by integrating vital functions and requiring minimal output components. The block diagram on page 3 provides a top level view of multi-phase power conversion using the ISL8103 controller. Interleaving The switching of each channel in a multi-phase converter is timed to be symmetrically out of phase with each of the other channels. In a 3-phase converter, each channel switches 1/3 cycle after the previous channel and 1/3 cycle before the following channel. As a result, the three-phase converter has a combined ripple frequency three times greater than the ripple frequency of any one phase. In addition, the peak-topeak amplitude of the combined inductor currents is reduced in proportion to the number of phases (Equations 1 and 2). Increased ripple frequency and lower ripple amplitude mean that the designer can use less per-channel inductance and lower total output capacitance for any performance specification. Figure 1 illustrates the multiplicative effect on output ripple frequency. The three channel currents (IL1, IL2, and IL3) 9 PWM1, 5V/DIV FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS FOR 3-PHASE CONVERTER To understand the reduction of ripple current amplitude in the multi-phase circuit, examine the equation representing an individual channel peak-to-peak inductor current. ( V IN – V OUT ) ⋅ V OUT I PP = --------------------------------------------------------L ⋅ F SW ⋅ V IN (EQ. 1) In Equation 1, VIN and VOUT are the input and output voltages respectively, L is the single-channel inductor value, and FSW is the switching frequency. The output capacitors conduct the ripple component of the inductor current. In the case of multi-phase converters, the capacitor current is the sum of the ripple currents from each of the individual channels. Compare Equation 1 to the expression for the peak-to-peak current after the summation of N symmetrically phase-shifted inductor currents in Equation 2. Peak-to-peak ripple current decreases by an amount proportional to the number of channels. Output voltage ripple is a function of capacitance, capacitor equivalent series resistance (ESR), and inductor ripple current. Reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors. ( V IN – N ⋅ V OUT ) ⋅ V OUT I C, PP = ------------------------------------------------------------------L ⋅ F SW ⋅ V (EQ. 2) IN Another benefit of interleaving is to reduce input ripple current. Input capacitance is determined in part by the maximum input ripple current. Multi-phase topologies can improve overall system cost and size by lowering input ripple current and allowing the designer to reduce the cost of input capacitance. The example in Figure 2 illustrates input FN9246.0 February 15, 2006 ISL8103 currents from a three-phase converter combining to reduce the total input ripple current. The converter depicted in Figure 2 delivers 1.5V to a 36A load from a 12V input. The RMS input capacitor current is 6.1A. Compare this to a single-phase converter also stepping down 12V to 1.5V at 36A. The single-phase converter has a 13.3A RMS input capacitor current. The single-phase converter must use an input capacitor bank with twice the RMS current capacity as the equivalent threephase converter. INPUT-CAPACITOR CURRENT CHANNEL 3 INPUT CURRENT CHANNEL 2 INPUT CURRENT CHANNEL 1 INPUT CURRENT FIGURE 2. CHANNEL INPUT CURRENTS AND INPUTCAPACITOR RMS CURRENT FOR 3-PHASE CONVERTER Figures 24, 25 and 26 in the section entitled Input Capacitor Selection can be used to determine the input capacitor RMS current based on load current, duty cycle, and the number of channels. They are provided as aids in determining the optimal input capacitor solution. PWM Operation The timing of each converter leg is set by the number of active channels. The default channel setting for the ISL8103 is three. One switching cycle is defined as the time between the internal PWM1 pulse termination signals. The pulse termination signal is the internally generated clock signal that triggers the falling edge of PWM1. The cycle time of the pulse termination signal is the inverse of the switching frequency set by the resistor between the FS pin and ground. Each cycle begins when the clock signal commands PWM1 to go low. The PWM1 transition signals the internal channel 1 MOSFET driver to turn off the channel 1 upper MOSFET and turn on the channel 1 synchronous MOSFET. In the default channel configuration, the PWM2 pulse terminates 1/3 of a cycle after the PWM1 pulse. The PWM3 pulse terminates 1/3 of a cycle after PWM2. operation is selected. The 2PH and 3PH inputs can also be used to accomplish this function. Once a PWM pulse transitions low, it is held low for a minimum of 1/3 cycle. This forced off time is required to ensure an accurate current sample. Current sensing is described in the next section. After the forced off time expires, the PWM output is enabled. The PWM output state is driven by the position of the error amplifier output signal, VCOMP, minus the current correction signal relative to the sawtooth ramp as illustrated in Figure 3. When the modified VCOMP voltage crosses the sawtooth ramp, the PWM output transitions high. The internal MOSFET driver detects the change in state of the PWM signal and turns off the synchronous MOSFET and turns on the upper MOSFET. The PWM signal will remain high until the pulse termination signal marks the beginning of the next cycle by triggering the PWM signal low. Channel Current Balance One important benefit of multi-phase operation is the thermal advantage gained by distributing the dissipated heat over multiple devices and greater area. By doing this the designer avoids the complexity of driving parallel MOSFETs and the expense of using expensive heat sinks and exotic magnetic materials. In order to realize the thermal advantage, it is important that each channel in a multi-phase converter be controlled to carry about the same amount of current at any load level. To achieve this, the currents through each channel must be sampled every switching cycle. The sampled currents, In, from each active channel are summed together and divided by the number of active channels. The resulting cycle average current, IAVG, provides a measure of the total load current demand on the converter during each switching cycle. Channel current balance is achieved by comparing the sampled current of each channel to the cycle average current, and making the proper adjustment to each channel pulse width based on the error. Intersil’s patented currentbalance method is illustrated in Figure 3, with error correction for channel 1 represented. In the figure, the cycle average current, IAVG, is compared with the channel 1 sample, I1, to create an error signal IER. The filtered error signal modifies the pulse width commanded by VCOMP to correct any unbalance and force IER toward zero. The same method for error signal correction is applied to each active channel. If PVCC3 is left open or connected to ground, two channel operation is selected and the PWM2 pulse terminates 1/2 of a cycle after the PWM1 pulse terminates. If both PVCC3 and PVCC2 are left open or connected to ground, single channel 10 FN9246.0 February 15, 2006 ISL8103 + VCOMP + FILTER PWM1 - TO GATE CONTROL LOGIC each channel in the converter, but may not be active depending on the status of the PVCC3 and PVCC2 pins, as described in the PWM Operation section. SAWTOOTH SIGNAL f(s) VIN I3 IER IAVG - + Σ ÷N I In r DS ( ON ) SEN = I L x ------------------------R ISEN CHANNEL N UPPER MOSFET I2 IL SAMPLE & HOLD I1 ISEN(n) - NOTE: Channel 2 and 3 are optional. FIGURE 3. CHANNEL 1 PWM FUNCTION AND CURRENTBALANCE ADJUSTMENT The sampled current, at the end of the tSAMPLE, is proportional to the inductor current and is held until the next switching period sample. The sampled current is used only for channel current balance. IL I x r DS ( ON ) L CHANNEL N LOWER MOSFET ISL8103 INTERNAL CIRCUIT EXTERNAL CIRCUIT FIGURE 5. ISL8103 INTERNAL AND EXTERNAL CURRENTSENSING CIRCUITRY FOR CURRENT BALANCE The ISL8103 senses the channel load current by sampling the voltage across the lower MOSFET rDS(ON), as shown in Figure 5. A ground-referenced operational amplifier, internal to the ISL8103, is connected to the PHASE node through a resistor, RISEN. The voltage across RISEN is equivalent to the voltage drop across the rDS(ON) of the lower MOSFET while it is conducting. The resulting current into the ISEN pin is proportional to the channel current, IL. The ISEN current is sampled and held as described in the Current Sampling section. From Figure 5, the following equation for In is derived where IL is the channel current. r DS ( ON ) I n = I L ⋅ ---------------------R ISEN (EQ. 3) Output Voltage Setting PWM SWITCHING PERIOD ISEN SAMPLING PERIOD NEW SAMPLE CURRENT OLD SAMPLE CURRENT TIME FIGURE 4. SAMPLE AND HOLD TIMING The ISL8103 supports MOSFET rDS(ON) current sensing to sample each channel’s current for channel current balance. The internal circuitry, shown in Figure 5 represents channel n of an N-channel converter. This circuitry is repeated for 11 + Current Sampling In order to realize proper current balance, the currents in each channel must be sampled every switching cycle. This sampling occurs during the forced off-time, following a PWM transition low. During this time the current sense amplifier uses the ISEN inputs to reproduce a signal proportional to the inductor current, IL. This sensed current, ISEN, is simply a scaled version of the inductor current. The sample window opens exactly 1/6 of the switching period, tSW, after the PWM transitions low. The sample window then stays open the rest of the switching cycle until PWM transitions high again, as illustrated in Figure 4. RISEN + The ISL8103 uses a digital to analog converter (DAC) to generate a reference voltage based on the logic signals at the REF1, REF0 pins. The DAC decodes the 2-bit logic signals into one of the discrete voltages shown in Table 1. Each REF0 and REF1 pins are pulled up to an internal 1.2V voltage by weak current sources (40µA current, decreasing to 0 as the voltage at the REF0, REF1 pins varies from 0 to the internal 1.2V pull-up voltage). External pull-up resistors or active-high output stages can augment the pull-up current sources, up to a voltage of 5V. The DAC pin must be connected to REF pin through a 1-5kΩ resistor and a filter capacitor (0.022µF) is connected between REF and GND. The ISL8103 accommodates the use of external voltage reference connected to REF pin if a different output voltage is required. The DAC voltage must be set at least as high as the external reference. The error amp internal noninverting input is the lower of REF or (DAC +300mV). A third method for setting the output voltage is to use a resistor divider (RP1, RS1) from the output terminal (VOUT) FN9246.0 February 15, 2006 ISL8103 to VSEN pin to set the output voltage level as shown in Figure 6. This method is good for generating voltages up to 2.3V (with the REF voltage set to 1.5V). EXTERNAL CIRCUIT R2 C1 COMP For this case, the output voltage can be obtained as follows: DAC ( R S1 + R P1 ) −V -+ OUT = V REF ⋅ --------------------------------OFS – V DROOP R P1 REF (EQ. 4) It is recommended to choose resistor values of less than 500Ω for RS1 and RP1 resistors in order to get better output voltage DC accuracy. TABLE 1. ISL8103 DAC VOLTAGE SELECTION TABLE REF1 REF0 VDAC 0 0 0.600V 0 1 0.900V 1 0 1.200V 1 1 1.500V + FB R1 + VOFS - - IOFS RS1 VOUT VCOMP ERROR AMPLIFIER VDIFF VSEN + RP1 + + RGND - - In order to regulate the output voltage to a specified level, the ISL8103 uses the integrating compensation network shown in Figure 6. This compensation network insures that the steady state error in the output voltage is limited only to the error in the reference voltage (output of the DAC or the external voltage reference) and offset errors in the OFS current source, remote sense and error amplifiers. Intersil specifies the guaranteed tolerance of the ISL8103 to include the combined tolerances of each of these elements, except when an external reference or voltage divider is used, then the tolerances of these components has to be taken into account. The ISL8103 incorporates an internal differential remotesense amplifier in the feedback path. The amplifier removes the voltage error encountered when measuring the output voltage relative to the controller ground reference point, resulting in a more accurate means of sensing output voltage. Connect the microprocessor sense pins to the noninverting input, VSEN, and inverting input, RGND, of the remote-sense amplifier. The droop voltage, VDROOP, also feeds into the remote-sense amplifier. The remote-sense output, VDIFF, is therefore equal to the sum of the output voltage, VOUT, and the droop voltage. VDIFF is connected to the inverting input of the error amplifier through an external resistor. The output of the error amplifier, VCOMP, is compared to the sawtooth waveform to generate the PWM signals. The PWM signals control the timing of the Internal MOSFET drivers and regulate the converter output so that the voltage at FB is equal to the voltage at REF. This will regulate the output voltage to be equal to Equation 5. The internal and external circuitry that controls voltage regulation is illustrated in Figure 6. 12 VID DAC CREF Voltage Regulation V OUT = V REF ± V OFST – V DROOP ISL8103 INTERNAL CIRCUIT (EQ. 5) VDROOP + CSUM DROOP DIFFERENTIAL REMOTE-SENSE AMPLIFIER IREF ICOMP + ISENSE AMP - ISUM FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE REGULATION WITH OFFSET ADJUSTMENT Load-Line (Droop) Regulation In some high current applications, a requirement on a precisely controlled output impedance is imposed. This dependence of output voltage on load current is often termed “droop” or “load line” regulation. The Droop is an optional feature in the ISL8103. It can be enabled by connecting ICOMP pin to DROOP pin as shown in Figure 6. To disable it, connect the DROOP pin to IREF pin. As shown in Figure 6, a voltage, VDROOP, proportional to the total current in all active channels, IOUT, feeds into the differential remote-sense amplifier. The resulting voltage at the output of the remote-sense amplifier is the sum of the output voltage and the droop voltage. As Equation 4 shows, feeding this voltage into the compensation network causes the regulator to adjust the output voltage so that it’s equal to the reference voltage minus the droop voltage. The droop voltage, VDROOP, is created by sensing the current through the output inductors. This is accomplished by using a continuous DCR current sensing method. Inductor windings have a characteristic distributed resistance or DCR (Direct Current Resistance). For simplicity, the inductor DCR is considered as a separate FN9246.0 February 15, 2006 ISL8103 lumped quantity, as shown in Figure 7. The channel current, IL, flowing through the inductor, passes through the DCR. Equation 6 shows the s-domain equivalent voltage, VL, across the inductor. (EQ. 6) V L ( s ) = I L ⋅ ( s ⋅ L + DCR ) The inductor DCR is important because the voltage dropped across it is proportional to the channel current. By using a simple R-C network and a current sense amplifier, as shown in Figure 7, the voltage drop across all of the inductors DCRs can be extracted. The output of the current sense amplifier, VDROOP, can be shown to be proportional to the channel currents IL1, IL2, and IL3, shown in Equation 7. (EQ. 7) s ⋅ L + 1 ------------R DCR COMP V ( s ) = -------------------------------------------------------------------------- ⋅ ----------------------- ⋅ ( I + I + I ) ⋅ DCR DROOP L1 L2 L3 (s ⋅ R ⋅C + 1) R COMP COMP S If the R-C network components are selected such that the R-C time constant matches the inductor L/DCR time constant, then VDROOP is equal to the sum of the voltage drops across the individual DCRs, multiplied by a gain. As Equation 8 shows, VDROOP is therefore proportional to the total output current, IOUT. R COMP V DROOP = --------------------- ⋅ I OUT ⋅ DCR RS VL(s) L1 PHASE1 - + (EQ. 8) Output Voltage Offset Programming The ISL8103 allows the designer to accurately adjust the offset voltage by connecting a resistor, ROFS, from the OFS pin to VCC or GND. When ROFS is connected between OFS and VCC, the voltage across it is regulated to 1.5V. This causes a proportional current (IOFS) to flow into the OFS pin and out of the FB pin. If ROFS is connected to ground, the voltage across it is regulated to 0.5V, and IOFS flows into the FB pin and out of the OFS pin. The offset current flowing through the resistor between VDIFF and FB will generate the desired offset voltage which is equal to the product (IOFS x R1). These functions are shown in Figures 8 and 9. VDIFF + VOFS - R1 VREF E/A IOUT DCR INDUCTOR RS By simply adjusting the value of RS, the load line can be set to any level, giving the converter the right amount of droop at all load currents. It may also be necessary to compensate for any changes in DCR due to temperature. These changes cause the load line to be skewed, and cause the R-C time constant to not match the L/DCR time constant. If this becomes a problem a simple negative temperature coefficient resistor network can be used in the place of RCOMP to compensate for the rise in DCR due to temperature. FB VOUT IOFS I L1 COUT L2 PHASE2 DCR INDUCTOR I RS L2 - ISUM - + OFS ICOMP CCOMP RCOMP GND DROOP VDROOP + ISL8103 ROFS IREF CSUM - 1.5V + + 0.5V GND VCC FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE PROGRAMMING (Optional) ISL8103 FIGURE 7. DCR SENSING CONFIGURATION 13 FN9246.0 February 15, 2006 ISL8103 UGATE voltages during a PWM falling edge and the subsequent UGATE turn-off. If either the UGATE falls to less than 1.75V above the PHASE or the PHASE falls to less than +0.8V, the LGATE is released to turn on. VDIFF VOFS + R1 VREF Internal Bootstrap Device E/A FB All three integrated drivers feature an internal bootstrap schottky diode. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. The bootstrap function is also designed to prevent the bootstrap capacitor from overcharging due to the large negative swing at the PHASE node. This reduces voltage stress on the boot to phase pins. IOFS VCC - ROFS + OFS - ISL8103 1.5V + 0.5V GND VCC FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE PROGRAMMING Q GATE C BOOT_CAP ≥ -------------------------------------∆V BOOT_CAP (EQ. 11) Q G1 • PVCC Q GATE = -------------------------------- • N Q1 V GS1 Once the desired output offset voltage has been determined, use the following formulas to set ROFS: For Positive Offset (connect ROFS to GND): 0.5 ⋅ R 1 R OFS = -------------------------V OFFSET The bootstrap capacitor must have a maximum voltage rating above PVCC + 5V and its capacitance value can be chosen from the following equation: (EQ. 9) where QG1 is the amount of gate charge per upper MOSFET at VGS1 gate-source voltage and NQ1 is the number of control MOSFETs. The ∆VBOOT_CAP term is defined as the allowable droop in the rail of the upper gate drive. Figure 10 shows the boot capacitor ripple voltage as a function of boot capacitor value and total upper MOSFET gate charge. For Negative Offset (connect ROFS to VCC): 1.6 1.5 ⋅ R 1 R OFS = -------------------------V OFFSET (EQ. 10) 1.4 Advanced Adaptive Zero Shoot-Through Deadtime Control (Patent Pending) During turn-off of the lower MOSFET, the PHASE voltage is monitored until it reaches a -0.3V/+0.8V trip point for a forward/reverse current, at which time the UGATE is released to rise. An auto-zero comparator is used to correct the rDS(ON) drop in the phase voltage preventing false detection of the -0.3V phase level during rDS(ON) conduction period. In the case of zero current, the UGATE is released after 35ns delay of the LGATE dropping below 0.5V. During the phase detection, the disturbance of LGATE falling transition on the PHASE node is blanked out to prevent falsely tripping. Once the PHASE is high, the advanced adaptive shoot-through circuitry monitors the PHASE and 14 CBOOT_CAP (µF) The integrated drivers incorporate a unique adaptive deadtime control technique to minimize deadtime, resulting in high efficiency from the reduced freewheeling time of the lower MOSFET body-diode conduction, and to prevent the upper and lower MOSFETs from conducting simultaneously. This is accomplished by ensuring either rising gate turns on its MOSFET with minimum and sufficient delay after the other has turned off. 1.2 1. 0.8 0.6 QGATE = 100nC 0.4 50nC 0.2 20nC 0.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 ∆VBOOT_CAP (V) FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE Gate Drive Voltage Versatility The ISL8103 provides the user flexibility in choosing the gate drive voltage for efficiency optimization. The controller ties the upper and lower drive rails together. Simply applying a voltage from 5V up to 12V on PVCC sets both gate drive rail voltages simultaneously. FN9246.0 February 15, 2006 ISL8103 Initialization threshold. Hysteresis between the rising and falling thresholds assure that once enabled, the ISL8103 will not inadvertently turn off unless the PVCC bias voltage drops substantially (see Electrical Specifications). Prior to initialization, proper conditions must exist on the ENLL, VCC, PVCC and the REF0 and REF1 pins. When the conditions are met, the controller begins soft-start. Once the output voltage is within the proper window of operation, the controller asserts PGOOD. When each of these conditions is true, the controller immediately begins the soft-start sequence. Enable and Disable Soft-Start While in shutdown mode, the PWM outputs are held in a high-impedance state to assure the drivers remain off. The following input conditions must be met before the ISL8103 is released from shutdown mode. During soft-start, the DAC voltage ramps linearly from zero to the programmed level. The PWM signals remain in the high-impedance state until the controller detects that the ramping DAC level has reached the output-voltage level. This protects the system against the large, negative inductor currents that would otherwise occur when starting with a preexisting charge on the output as the controller attempted to regulate to zero volts at the beginning of the soft-start cycle. The Output soft-start time, TSS, begins with a delay period equal to 64 switching cycles after the ENLL has exceeded its POR level, followed by a linear ramp with a rate determined by the switching period, 1/Fsw. 1. The bias voltage applied at VCC must reach the internal power-on reset (POR) rising threshold. Once this threshold is reached, proper operation of all aspects of the ISL8103 is guaranteed. Hysteresis between the rising and falling thresholds assure that once enabled, the ISL8103 will not inadvertently turn off unless the bias voltage drops substantially (see Electrical Specifications). ISL8103 INTERNAL CIRCUIT EXTERNAL CIRCUIT PVCC1 +12V ENABLE COMPARATOR 10.7kΩ ENLL + - (EQ. 12) For example, a regulator with 450kHz switching frequency having REF voltage set to 1.2V has TSS equal to 3.55ms. VCC POR CIRCUIT 64 + DAC ⋅ 1280 T SS = -------------------------------------------F SW 1.40kΩ 0.66V SOFT-START AND FAULT LOGIC FIGURE 11. POWER SEQUENCING USING THRESHOLDSENSITIVE ENABLE (ENLL) FUNCTION 2. The voltage on ENLL must be above 0.66V. The EN input allows for power sequencing between the controller bias voltage and another voltage rail. The enable comparator holds the ISL8103 in shutdown until the voltage at ENLL rises above 0.66V. The enable comparator has 100mV of hysteresis to prevent bounce. A 100mV offset exists on the remote-sense amplifier at the beginning of soft-start and ramps to zero during the first 640 cycles of soft-start (704 cycles following enable). This prevents the large inrush current that would otherwise occur should the output voltage start out with a slight negative bias. The ISL8103 also has the ability to start up into a precharged output as shown in Figure 12, without causing any unnecessary disturbance. The FB pin is monitored during soft-start, and should it be higher than the equivalent internal ramping reference voltage, the output drives hold both MOSFETs off. Once the internal ramping reference exceeds the FB pin potential, the output drives are enabled, allowing the output to ramp from the pre-charged level to the final level dictated by the reference setting. Should the output be pre-charged to a level exceeding the reference setting, the output drives are enabled at the end of the soft-start period, leading to an abrupt correction in the output voltage down to the “reference set” level. 3. The driver bias voltage applied at the PVCC pins must reach the internal power-on reset (POR) rising threshold. In order for the ISL8103 to begin operation, PVCC1 is the only pin that is required to have a voltage applied that exceeds POR. However, for 2 or 3-phase operation PVCC2 and PVCC3 must also exceed the POR 15 FN9246.0 February 15, 2006 ISL8103 One common power good indicator is provided for linking to external system monitors. The schematic in Figure 13 outlines the interaction between the fault monitors and the power good signal OUTPUT PRECHARGED ABOVE DAC LEVEL OUTPUT PRECHARGED BELOW DAC LEVEL Power Good Signal GND> VOUT (0.5V/DIV) GND> ENLL (5V/DIV) T1 T2 T3 FIGURE 12. SOFT-START WAVEFORMS FOR ISL8103-BASED MULTI-PHASE CONVERTER Fault Monitoring and Protection The ISL8103 actively monitors output voltage and current to detect fault conditions. Fault monitors trigger protective measures to prevent damage to the load. ICOMP - VOCSET + OCSET + ISEN VDROOP ISUM 100µA + +1V - + OC + VDIFF The undervoltage threshold is set at 82% of the REF voltage. When the output voltage (VSEN-RGND) is below the undervoltage threshold, PGOOD gets pulled low. No other action is taken by the controller. PGOOD will return high if the output voltage rises above 85% of the REF voltage. The ISL8103 constantly monitors the difference between the VSEN and RGND voltages to detect if an overvoltage event occurs. During soft-start, while the DAC/REF is ramping up, the overvoltage trip level is the higher of REF plus 150mV or a fixed voltage, VOVP. The fixed voltage, VOVP, is 1.67V. Upon successful soft-start, the overvoltage trip level is only REF plus 150mV. OVP releases 50mV below its trip point if it was “REF plus 150mV” that tripped it, and releases 100mV below its trip point if it was the fixed voltage, VOVP, that tripped it. Actions are taken by the ISL8103 to protect the load when an overvoltage condition occurs, until the output voltage falls back within set limits. ROCSET IREF - Undervoltage Detection Overvoltage Protection * Connect DROOP to IREF to disable the Droop feature. DROOP* The power good pin (PGOOD) is an open-drain logic output that transitions high when the converter is operating after soft-start. PGOOD pulls low during shutdown and releases high after a successful soft-start. PGOOD transitions low when an undervoltage, overvoltage, or overcurrent condition is detected or when the controller is disabled by a reset from ENLL or POR. If after an undervoltage or overvoltage event occurs the output returns to within under and overvoltage limits, PGOOD will return high. - At the inception of an overvoltage event, all LGATE signals are commanded high, and the PGOOD signal is driven low. This causes the controller to turn on the lower MOSFETs and pull the output voltage below a level that might cause damage to the load. The LGATE outputs remain high until VDIFF falls to within the overvoltage limits explained above. The ISL8103 will continue to protect the load in this fashion as long as the overvoltage condition recurs. DAC + 150mV SOFT-START, FAULT AND CONTROL LOGIC VOVP OV VSEN + + PGOOD x1 - - RGND Pre-POR Overvoltage Protection UV + 0.82 x DAC Once an overvoltage condition ends the ISL8103 continues normal operation and PGOOD returns high. ISL8103 INTERNAL CIRCUITRY FIGURE 13. POWER GOOD AND PROTECTION CIRCUITRY 16 Prior to PVCC and VCC exceeding their POR levels, the ISL8103 is designed to protect the load from any overvoltage events that may occur. This is accomplished by means of an internal 10kΩ resistor tied from PHASE to LGATE, which turns on the lower MOSFET to control the output voltage until the overvoltage event ceases or the input power supply cuts off. For complete protection, the low side MOSFET FN9246.0 February 15, 2006 ISL8103 should have a gate threshold well below the maximum voltage rating of the load/microprocessor. In the event that during normal operation the PVCC or VCC voltage falls back below the POR threshold, the pre-POR overvoltage protection circuitry reactivates to protect from any more pre-POR overvoltage events. Open Sense Line Protection OUTPUT CURRENT 0A In the case that either of the remote sense lines, VSEN or GND, become open, the ISL8103 is designed to detect this and shut down the controller. This event is detected by monitoring the voltage on the IREF pin, which is a local version of VOUT sensed at the outputs of the inductors. If VSEN or RGND become opened, VDIFF falls, causing the duty cycle to increase and the output voltage on IREF to increase. If the voltage on IREF exceeds “VDIFF+1V”, the controller will shut down. Once the voltage on IREF falls below “VDIFF+1V”, the ISL8103 will restart at the beginning of soft-start. Overcurrent Protection The ISL8103 detects overcurrent events by comparing the droop voltage, VDROOP, to the OCSET voltage, VOCSET, as shown in Figure 13. The droop voltage, set by the external current sensing circuitry, is proportional to the output current as shown in Equation 8. A constant 100µA flows through ROCSET, creating the OCSET voltage. When the droop voltage exceeds the OCSET voltage, the overcurrent protection circuitry activates. Since the droop voltage is proportional to the output current, the overcurrent trip level, IMAX, can be set by selecting the proper value for ROCSET, as shown in Equation 13. I MAX ⋅ R COMP ⋅ DCR R OCSET = --------------------------------------------------------100µA ⋅ R S (EQ. 13) Once the output current exceeds the overcurrent trip level, VDROOP will exceed VOCSET, and a comparator will trigger the converter to begin overcurrent protection procedures. At the beginning of overcurrent shutdown, the controller turns off both upper and lower MOSFETs. The system remains in this state for a period of 4096 switching cycles. If the controller is still enabled at the end of this wait period, it will attempt a soft-start (as shown in Figure 14). If the fault remains, the trip-retry cycles will continue indefinitely until either the controller is disabled or the fault is cleared. Note that the energy delivered during trip-retry cycling is much less than during full-load operation, so there is no thermal hazard. 17 OUTPUT VOLTAGE 0V FIGURE 14. OVERCURRENT BEHAVIOR IN HICCUP MODE General Design Guide This design guide is intended to provide a high-level explanation of the steps necessary to create a multi-phase power converter. It is assumed that the reader is familiar with many of the basic skills and techniques referenced below. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for many applications. Power Stages The first step in designing a multi-phase converter is to determine the number of phases. This determination depends heavily on the cost analysis which in turn depends on system constraints that differ from one design to the next. Principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board, whether through-hole components are permitted, the total board space available for power-supply circuitry, and the maximum amount of load current. Generally speaking, the most economical solutions are those in which each phase handles between 25 and 30A. All surface-mount designs will tend toward the lower end of this current range. If through-hole MOSFETs and inductors can be used, higher per-phase currents are possible. In cases where board space is the limiting constraint, current can be pushed as high as 40A per phase, but these designs require heat sinks and forced air to cool the MOSFETs, inductors and heatdissipating surfaces. MOSFETs The choice of MOSFETs depends on the current each MOSFET will be required to conduct, the switching frequency, the capability of the MOSFETs to dissipate heat, and the availability and nature of heat sinking and air flow. FN9246.0 February 15, 2006 ISL8103 LOWER MOSFET POWER CALCULATION The calculation for the approximate power loss in the lower MOSFET can be simplified, since virtually all of the loss in the lower MOSFET is due to current conducted through the channel resistance (rDS(ON)). In Equation 14, IM is the maximum continuous output current, IPP is the peak-to-peak inductor current (see Equation 1), and d is the duty cycle (VOUT/VIN). I L, 2PP ⋅ ( 1 – d ) I M 2 · P LOW, 1 = r DS ( ON ) ⋅ ----- ⋅ ( 1 – d ) + ------------------------------------12 N (EQ. 14) An additional term can be added to the lower-MOSFET loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lower-MOSFET body diode. This term is dependent on the diode forward voltage at IM, VD(ON), the switching frequency, FSW, and the length of dead times, td1 and td2, at the beginning and the end of the lower-MOSFET conduction interval respectively. I M I PP I M I PP - + --------- ⋅ t d1 + ----- – - ⋅ t d2 P LOW, 2 = V D ( ON ) ⋅ F SW ⋅ ----N N -------2 2 (EQ. 15) The total maximum power dissipated in each lower MOSFET is approximated by the summation of PLOW,1 and PLOW,2. UPPER MOSFET POWER CALCULATION In addition to rDS(ON) losses, a large portion of the upperMOSFET losses are due to currents conducted across the input voltage (VIN) during switching. Since a substantially higher portion of the upper-MOSFET losses are dependent on switching frequency, the power calculation is more complex. Upper MOSFET losses can be divided into separate components involving the upper-MOSFET switching times, the lower-MOSFET body-diode reverserecovery charge, Qrr, and the upper MOSFET rDS(ON) conduction loss. When the upper MOSFET turns off, the lower MOSFET does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. Once the lower MOSFET begins conducting, the current in the upper MOSFET falls to zero as the current in the lower MOSFET ramps up to assume the full inductor current. In Equation 16, the required time for this commutation is t1 and the approximated associated power loss is PUP,1. I M I PP t 1 P UP,1 ≈ V IN ⋅ ----- ⋅ ---- ⋅ F SW N- + -------2 2 18 (EQ. 16) At turn on, the upper MOSFET begins to conduct and this transition occurs over a time t2. In Equation 17, the approximate power loss is PUP,2. I M I PP t 2 P UP, 2 ≈ V IN ⋅ ----- ⋅ ---- ⋅ F SW N- – -------2 2 (EQ. 17) A third component involves the lower MOSFET reverserecovery charge, Qrr. Since the inductor current has fully commutated to the upper MOSFET before the lowerMOSFET body diode can recover all of Qrr, it is conducted through the upper MOSFET across VIN. The power dissipated as a result is PUP,3. P UP,3 = V IN ⋅ Q rr ⋅ F SW (EQ. 18) Finally, the resistive part of the upper MOSFET is given in Equation 19 as PUP,4. 2 I PP2 I M P UP,4 ≈ r DS ( ON ) ⋅ ----- ⋅ d + ---------12 N (EQ. 19) The total power dissipated by the upper MOSFET at full load can now be approximated as the summation of the results from Equations 16, 17, 18 and 19. Since the power equations depend on MOSFET parameters, choosing the correct MOSFETs can be an iterative process involving repetitive solutions to the loss equations for different MOSFETs and different switching frequencies. Package Power Dissipation When choosing MOSFETs it is important to consider the amount of power being dissipated in the integrated drivers located in the controller. Since there are a total of three drivers in the controller package, the total power dissipated by all three drivers must be less than the maximum allowable power dissipation for the QFN package. Calculating the power dissipation in the drivers for a desired application is critical to ensure safe operation. Exceeding the maximum allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of 125°C. The maximum allowable IC power dissipation for the 6x6 QFN package is approximately 4W at room temperature. See Layout Considerations paragraph for thermal transfer improvement suggestions. When designing the ISL8103 into an application, it is recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected MOSFETs. The total gate drive power losses, PQg_TOT, due to the gate charge of MOSFETs and the integrated driver’s internal circuitry and their corresponding average driver current can be estimated with Equations 20 and 21, respectively. FN9246.0 February 15, 2006 ISL8103 P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q ⋅ VCC (EQ. 20) 3 P Qg_Q1 = --- ⋅ Q G1 ⋅ PVCC ⋅ F SW ⋅ N Q1 ⋅ N PHASE 2 P Qg_Q2 = Q G2 ⋅ PVCC ⋅ F SW ⋅ N Q2 ⋅ N PHASE P DR = P DR_UP + P DR_LOW + P BOOT + ( I Q • VCC ) (EQ. 21) 3 I DR = --- • Q G1 • N + Q G2 • N Q2 • N PHASE • F SW + I Q 2 Q1 In Equations 20 and 21, PQg_Q1 is the total upper gate drive power loss and PQg_Q2 is the total lower gate drive power loss; the gate charge (QG1 and QG2) is defined at the particular gate to source drive voltage PVCC in the corresponding MOSFET data sheet; IQ is the driver total quiescent current with no load at both drive outputs; NQ1 and NQ2 are the number of upper and lower MOSFETs per phase, respectively; NPHASE is the number of active phases. The IQ*VCC product is the quiescent power of the controller without capacitive load and is typically 75mW at 300kHz. PVCC BOOT D CGD RHI1 G UGATE RLO1 RG1 and RG2) and the internal gate resistors (RGI1 and RGI2) of the MOSFETs. Figures 15 and 16 show the typical upper and lower gate drives turn-on transition path. The total power dissipation in the controller itself, PDR, can be roughly estimated as: CDS RGI1 CGS Q1 S PHASE FIGURE 15. TYPICAL UPPER-GATE DRIVE TURN-ON PATH (EQ. 22) P Qg_Q1 P BOOT = --------------------3 R LO1 R HI1 P Qg_Q1 P DR_UP = -------------------------------------+ --------------------------------------- • --------------------3 R + R R + R HI1 EXT1 LO1 EXT1 R LO2 R HI2 P Qg_Q2 + --------------------------------------- • --------------------P DR_LOW = -------------------------------------2 R + R R + R HI2 EXT2 LO2 EXT2 R GI1 R EXT1 = R G1 + ------------N Q1 R GI2 R EXT2 = R G2 + ------------N Q2 Current Balancing Component Selection The ISL8103 senses the channel load current by sampling the voltage across the lower MOSFET rDS(ON), as shown in Figure 17. The ISEN pins are denoted ISEN1, ISEN2, and ISEN3. The resistors connected between these pins and the respective phase nodes determine the gains in the channel current balance loop. Select values for these resistors based on the room temperature rDS(ON) of the lower MOSFETs; the full load operating current, IFL; and the number of phases, N using Equation 23. r DS ( ON ) R ISEN = ----------------------- ⋅ 50 ⋅ 10 – 6 I FL -------N (EQ. 23) VIN PVCC D CHANNEL N UPPER MOSFET CGD RHI2 RLO2 IL G LGATE RG2 CDS RGI2 ISEN(n) CGS Q2 RISEN S ISL8103 FIGURE 16. TYPICAL LOWER-GATE DRIVE TURN-ON PATH The total gate drive power losses are dissipated among the resistive components along the transition path and in the bootstrap diode. The portion of the total power dissipated in the controller itself is the power dissipated in the upper drive path resistance, PDR_UP, the lower drive path resistance, PDR_UP, and in the boot strap diode, PBOOT. The rest of the power will be dissipated by the external gate resistors (RG1 19 I L x r DS ( ON ) + CHANNEL N LOWER MOSFET FIGURE 17. ISL8103 INTERNAL AND EXTERNAL CURRENTSENSING CIRCUITRY In certain circumstances, it may be necessary to adjust the value of one or more ISEN resistors. When the components of one or more channels are inhibited from effectively FN9246.0 February 15, 2006 ISL8103 dissipating their heat so that the affected channels run hotter than desired, choose new, smaller values of RISEN for the affected phases (see the section entitled Channel Current Balance). Choose RISEN,2 in proportion to the desired decrease in temperature rise in order to cause proportionally less current to flow in the hotter phase. ∆T 2 R ISEN ,2 = R ISEN ⋅ ---------∆T 1 (EQ. 24) In Equation 24, make sure that ∆T2 is the desired temperature rise above the ambient temperature, and ∆T1 is the measured temperature rise above the ambient temperature. While a single adjustment according to Equation 24 is usually sufficient, it may occasionally be necessary to adjust RISEN two or more times to achieve optimal thermal balance between all channels. Load Line Regulation Component Selection (DCR Current Sensing) For accurate load line regulation, the ISL8103 senses the total output current by detecting the voltage across the output inductor DCR of each channel (As described in the Load Line Regulation section). As Figure 7 illustrates, an R-C network is required to accurately sense the inductor DCR voltage and convert this information into a droop voltage, which is proportional to the total output current. Choosing the components for this current sense network is a two step process. First, RCOMP and CCOMP must be chosen so that the time constant of this RCOMP-CCOMP network matches the time constant of the inductor L/DCR. Then the resistor RS must be chosen to set the current sense network gain, obtaining the desired full load droop voltage. Follow the steps below to choose the component values for this R-C network. 1. Choose an arbitrary value for CCOMP. The recommended value is 0.01µF. 2. Plug the inductor L and DCR component values, and the values for CCOMP chosen in steps 1, into Equation 25 to calculate the value for RCOMP. L R COMP = --------------------------------------DCR ⋅ C COMP (EQ. 25) 3. Use the new value for RCOMP obtained from Equation 25, as well as the desired full load current, IFL, full load droop voltage, VDROOP, and inductor DCR in Equation 26 to calculate the value for RS. I FL R S = ------------------------- ⋅ R COMP ⋅ DCR V DROOP (EQ. 26) Due to errors in the inductance or DCR it may be necessary to adjust the value of RCOMP to match the time constants correctly. The effects of time constant mismatch can be seen in the form of droop overshoot or undershoot during the initial load transient spike, as shown in Figure 18. Follow the 20 steps below to ensure the R-C and inductor L/DCR time constants are matched accurately. 1. Capture a transient event with the oscilloscope set to about L/DCR/2 (sec/div). For example, with L = 1µH and DCR = 1mΩ, set the oscilloscope to 500µs/div. 2. Record ∆V1 and ∆V2 as shown in Figure 18. 3. Select a new value, RCOMP,2, for the time constant resistor based on the original value, RCOMP,1, using the following equation. ∆V 1 R COMP, 2 = R COMP, 1 ⋅ ---------∆V (EQ. 27) 2 4. Replace RCOMP with the new value and check to see that the error is corrected. Repeat the procedure if necessary. After choosing a new value for RCOMP, it will most likely be necessary to adjust the value of RS to obtain the desired full load droop voltage. Use Equation 26 to obtain the new value for RS. ∆V2 ∆V1 VOUT ITRAN ∆I FIGURE 18. TIME CONSTANT MISMATCH BEHAVIOR Compensation The two opposing goals of compensating the voltage regulator are stability and speed. Depending on whether the regulator employs the optional load-line regulation as described in “Load-Line Regulation”, there are two distinct methods for achieving these goals. Compensating the Load-Line Regulated Converter The load-line regulated converter behaves in a similar manner to a peak current mode controller because the two poles at the output filter L-C resonant frequency split with the introduction of current information into the control loop. The final location of these poles is determined by the system function, the gain of the current signal, and the value of the compensation components, R2 and C1. FN9246.0 February 15, 2006 ISL8103 In Equations 28, L is the per-channel filter inductance divided by the number of active channels; C is the sum total of all output capacitors; ESR is the equivalent series resistance of the bulk output filter capacitance; and VPP is the peak-to-peak sawtooth signal amplitude as described in the Electrical Specifications. C2 (Optional) R2 C1 COMP FB ISL8103 R1 VDIFF FIGURE 19. COMPENSATION CONFIGURATION FOR LOAD-LINE REGULATED ISL8103 CIRCUIT Since the system poles and zero are affected by the values of the components that are meant to compensate them, the solution to the system equation becomes fairly complicated. Fortunately, there is a simple approximation that comes very close to an optimal solution. Treating the system as though it were a voltage-mode regulator, by compensating the L-C poles and the ESR zero of the voltage mode approximation, yields a solution that is always stable with very close to ideal transient performance. The feedback resistor, R1, has already been chosen as outlined in Load-Line Regulation Resistor. Select a target bandwidth for the compensated system, F0. The target bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the perchannel switching frequency. The values of the compensation components depend on the relationships of F0 to the L-C double pole frequency and the ESR zero frequency. For each of the following three, there is a separate set of equations for the compensation components. Case 1: 1 --------------------------- > F 0 2π ⋅ L ⋅ C The ISL8103 multi-phase converter operating without load line regulation behaves in a similar manner to a voltagemode controller. This section highlights the design consideration for a voltage-mode controller requiring external compensation. To address a broad range of applications, a type-3 feedback network is recommended (see Figure 20). C2 R2 2 V OSC ⋅ ( 2π ) 2 ⋅ F 0 ⋅ L ⋅ C R 2 = R 1 ⋅ ---------------------------------------------------------------0.66 ⋅ V IN 0.66 ⋅ V IN C 1 = ------------------------------------------------------------------------------2 2 ( 2π ) ⋅ F 0 ⋅ V OSC ⋅ R 1 ⋅ L ⋅ C 1 F 0 > --------------------------------2π ⋅ C ⋅ ESR 2π ⋅ F 0 ⋅ V OSC ⋅ L R 2 = R 1 ⋅ ----------------------------------------------0.66 ⋅ V IN ⋅ ESR 0.66 ⋅ V IN ⋅ ESR ⋅ C C 2 = -------------------------------------------------------------2π ⋅ V OSC ⋅ R 1 ⋅ F 0 ⋅ L C1 COMP FB R1 VDIFF ISL8103 FIGURE 20. COMPENSATION CONFIGURATION FOR NON-LOAD-LINE REGULATED ISL8103 CIRCUIT 1 1 --------------------------- ≤ F 0 < -------------------------------2π ⋅ C ⋅ ESR 2π ⋅ L ⋅ C 21 Compensating the Converter operating without Load-Line Regulation R3 0.66 ⋅ V IN C 1 = -----------------------------------------------2π ⋅ V OSC ⋅ R 1 ⋅ f 0 Case 3: The optional capacitor C2, is sometimes needed to bypass noise away from the PWM comparator (see Figure 19). Keep a position available for C2, and be prepared to install a high frequency capacitor of between 22pF and 150pF in case any leading edge jitter problem is noted. C3 2π ⋅ F 0 ⋅ V OSC ⋅ L ⋅ C R 2 = R 1 ⋅ -----------------------------------------------------------0.66 ⋅ V IN Case 2: Once selected, the compensation values in Equations 28 assure a stable converter with reasonable transient performance. In most cases, transient performance can be improved by making adjustments to R2. Slowly increase the value of R2 while observing the transient performance on an oscilloscope until no further improvement is noted. Normally, C1 will not need adjustment. Keep the value of C1 from Equations 28 unless some performance issue is noted. (EQ. 28) Figure 21 highlights the voltage-mode control loop for a synchronous-rectified buck converter, applicable, with a small number of adjustments, to the multi-phase ISL8103 circuit. The output voltage (VOUT) is regulated to the reference voltage, VREF, level. The error amplifier output (COMP pin voltage) is compared with the oscillator (OSC) modified sawtooth wave to provide a pulse-width modulated wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (L and C). The output filter capacitor bank’s equivalent series resistance is represented by the series resistor E. FN9246.0 February 15, 2006 ISL8103 1. Select a value for R1 (1kΩ to 5kΩ, typically). Calculate value for R2 for desired converter bandwidth (F0). C2 COMP R2 C3 R3 C1 V OSC ⋅ R 1 ⋅ F 0 R 2 = -------------------------------------------d MAX ⋅ V IN ⋅ F LC If setting the output voltage to be equal to the reference set voltage as shown in Figure 21, the design procedure can be followed as presented. However, when setting the output voltage via a resistor divider placed at the input of the differential amplifier (as shown in Figure 6), in order to compensate for the attenuation introduced by the resistor divider, the obtained R2 value needs be multiplied by a factor of (RP+RS)/RP. The remainder of the calculations remain unchanged, as long as the compensated R2 value is used. E/A FB + R1 VREF VDIFF - RGND + VSEN VOUT OSCILLATOR VIN VOSC PWM CIRCUIT UGATE HALF-BRIDGE DRIVE L 1 C 1 = ----------------------------------------------2π ⋅ R 2 ⋅ 0.5 ⋅ F LC DCR PHASE LGATE ISL8103 C ESR EXTERNAL CIRCUIT FIGURE 21. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN The modulator transfer function is the small-signal transfer function of VOUT /VCOMP. This function is dominated by a DC gain, given by dMAXVIN /VOSC , and shaped by the output filter, with a double pole break frequency at FLC and a zero at FCE . For the purpose of this analysis, L and DCR represent the individual channel inductance and its DCR divided by 3 (equivalent parallel value of the three output inductors), while C and ESR represents the total output capacitance and its equivalent series resistance. 1 F LC = --------------------------2π ⋅ L ⋅ C 1 F CE = --------------------------------2π ⋅ C ⋅ ESR The compensation network consists of the error amplifier (internal to the ISL8103) and the external R1-R3, C1-C3 components. The goal of the compensation network is to provide a closed loop transfer function with high 0dB crossing frequency (F0; typically 0.1 to 0.3 of FSW) and adequate phase margin (better than 45 degrees). Phase margin is the difference between the closed loop phase at F0dB and 180°. The equations that follow relate the compensation network’s poles, zeros and gain to the components (R1 , R2 , R3 , C1 , C2 , and C3) in Figure 20 and 21. Use the following guidelines for locating the poles and zeros of the compensation network: 22 2. Calculate C1 such that FZ1 is placed at a fraction of the FLC, at 0.1 to 0.75 of FLC (to adjust, change the 0.5 factor to desired number). The higher the quality factor of the output filter and/or the higher the ratio FCE/FLC, the lower the FZ1 frequency (to maximize phase boost at FLC). 3. Calculate C2 such that FP1 is placed at FCE. C1 C 2 = ------------------------------------------------------2π ⋅ R 2 ⋅ C 1 ⋅ F CE – 1 4. Calculate R3 such that FZ2 is placed at FLC. Calculate C3 such that FP2 is placed below FSW (typically, 0.5 to 1.0 times FSW). FSW represents the per-channel switching frequency. Change the numerical factor to reflect desired placement of this pole. Placement of FP2 lower in frequency helps reduce the gain of the compensation network at high frequency, in turn reducing the HF ripple component at the COMP pin and minimizing resultant duty cycle jitter. R1 R 3 = --------------------F SW ------------ – 1 F LC 1 C 3 = ------------------------------------------------2π ⋅ R 3 ⋅ 0.7 ⋅ F SW It is recommended a mathematical model is used to plot the loop response. Check the loop gain against the error amplifier’s open-loop gain. Verify phase margin results and adjust as necessary. The following equations describe the frequency response of the modulator (GMOD), feedback compensation (GFB) and closed-loop response (GCL): d MAX ⋅ V IN 1 + s ( f ) ⋅ ESR ⋅ C G MOD ( f ) = ------------------------------ ⋅ ----------------------------------------------------------------------------------------------------------2 V OSC 1 + s ( f ) ⋅ ( ESR + DCR ) ⋅ C + s ( f ) ⋅ L ⋅ C 1 + s ( f ) ⋅ R2 ⋅ C1 G FB ( f ) = ---------------------------------------------------- ⋅ s ( f ) ⋅ R1 ⋅ ( C1 + C2 ) 1 + s ( f ) ⋅ ( R1 + R3 ) ⋅ C3 ⋅ ------------------------------------------------------------------------------------------------------------------------ C1 ⋅ C2 ( 1 + s ( f ) ⋅ R 3 ⋅ C 3 ) ⋅ 1 + s ( f ) ⋅ R 2 ⋅ --------------------- C 1 + C 2 G CL ( f ) = G MOD ( f ) ⋅ G FB ( f ) where, s ( f ) = 2π ⋅ f ⋅ j FN9246.0 February 15, 2006 ISL8103 COMPENSATION BREAK FREQUENCY EQUATIONS 1 F Z1 = ------------------------------2π ⋅ R 2 ⋅ C 1 1 F P1 = --------------------------------------------C1 ⋅ C2 2π ⋅ R 2 ⋅ --------------------C1 + C2 1 F Z2 = ------------------------------------------------2π ⋅ ( R 1 + R 3 ) ⋅ C 3 1 F P2 = ------------------------------2π ⋅ R 3 ⋅ C 3 Figure 22 shows an asymptotic plot of the DC/DC converter’s gain vs. frequency. The actual Modulator Gain has a high gain peak dependent on the quality factor (Q) of the output filter, which is not shown. Using the above guidelines should yield a compensation gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 against the capabilities of the error amplifier. The closed loop gain, GCL, is constructed on the log-log graph of Figure 22 by adding the modulator gain, GMOD (in dB), to the feedback compensation gain, GFB (in dB). This is equivalent to multiplying the modulator transfer function and the compensation transfer function and then plotting the resulting gain. FP1 FP2 GAIN FZ1 FZ2 MODULATOR GAIN COMPENSATION GAIN CLOSED LOOP GAIN OPEN LOOP E/A GAIN transient response. The output capacitors must supply or sink load current while the current in the output inductors increases or decreases to meet the demand. In high-speed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. Output filter design begins with minimizing the cost of this part of the circuit. The critical load parameters in choosing the output capacitors are the maximum size of the load step, ∆I, the load-current slew rate, di/dt, and the maximum allowable output-voltage deviation under transient loading, ∆VMAX. Capacitors are characterized according to their capacitance, ESR, and ESL (equivalent series inductance). At the beginning of the load transient, the output capacitors supply all of the transient current. The output voltage will initially deviate by an amount approximated by the voltage drop across the ESL. As the load current increases, the voltage drop across the ESR increases linearly until the load current reaches its final value. The capacitors selected must have sufficiently low ESL and ESR so that the total outputvoltage deviation is less than the allowable maximum. Neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount di ∆V ≈ ( ESL ) ⋅ ----- + ( ESR ) ⋅ ∆I dt R2 20 log -------- R1 d MAX ⋅ V IN 20 log --------------------------------V OSC 0 The filter capacitor must have sufficiently low ESL and ESR so that ∆V < ∆VMAX. GFB LOG GCL GMOD LOG FLC FCE F0 FREQUENCY FIGURE 22. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN A stable control loop has a gain crossing with close to a -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin. The mathematical model presented makes a number of approximations and is generally not accurate at frequencies approaching or exceeding half the switching frequency. When designing compensation networks, select target crossover frequencies in the range of 10% to 30% of the per-channel switching frequency, FSW. Output Filter Design The output inductors and the output capacitor bank together to form a low-pass filter responsible for smoothing the pulsating voltage at the phase nodes. The output filter also must provide the transient energy until the regulator can respond. Because it has a low bandwidth compared to the switching frequency, the output filter limits the system 23 (EQ. 29) Most capacitor solutions rely on a mixture of high frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. Minimizing the ESL of the high-frequency capacitors allows them to support the output voltage as the current increases. Minimizing the ESR of the bulk capacitors allows them to supply the increased current with less output voltage deviation. The ESR of the bulk capacitors also creates the majority of the output-voltage ripple. As the bulk capacitors sink and source the inductor ac ripple current (see Interleaving and Equation 2), a voltage develops across the bulk capacitor ESR equal to IC,PP (ESR). Thus, once the output capacitors are selected, the maximum allowable ripple voltage, VPP(MAX), determines the lower limit on the inductance. V – N ⋅ V OUT ⋅ V OUT IN L ≥ ( ESR ) ⋅ -------------------------------------------------------------------F SW ⋅ V IN ⋅ V PP( MAX ) (EQ. 30) Since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. The output inductors must be capable of assuming the entire load current before the output voltage decreases more than ∆VMAX. This places an upper limit on inductance. FN9246.0 February 15, 2006 ISL8103 2 ⋅ N ⋅ C ⋅ VO L ≤ --------------------------------- ⋅ ∆V MAX – ( ∆I ⋅ ESR ) ( ∆I ) 2 ( 1.25 ) ⋅ N ⋅ C L ≤ ---------------------------------- ⋅ ∆V MAX – ( ∆I ⋅ ESR ) ⋅ V IN – V O ( ∆I ) 2 (EQ. 31) (EQ. 32) handle the AC component of the current drawn by the upper MOSFETs which is related to duty cycle and the number of active phases. 0.3 INPUT-CAPACITOR CURRENT (IRMS/IO) Equation 31 gives the upper limit on L for the cases when the trailing edge of the current transient causes a greater output-voltage deviation than the leading edge. Equation 32 addresses the leading edge. Normally, the trailing edge dictates the selection of L because duty cycles are usually less than 50%. Nevertheless, both inequalities should be evaluated, and L should be selected based on the lower of the two results. In each equation, L is the per-channel inductance, C is the total output capacitance, and N is the number of active channels. There are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upper MOSFET loss calculation. These effects are outlined in MOSFETs, and they establish the upper limit for the switching frequency. The lower limit is established by the requirement for fast transient response and small outputvoltage ripple as outlined in Output Filter Design. Choose the lowest switching frequency that allows the regulator to meet the transient-response requirements. Switching frequency is determined by the selection of the frequency-setting resistor, RFS. Figure 23 and Equation 33 are provided to assist in selecting the correct value for RFS R FS = 10 [10.61 – 1.035 ⋅ log ( F ] SW ) (EQ. 33) IL,PP = 0.5 IO IL,PP = 0.25 IO IL,PP = 0.75 IO 0.2 0.1 0 Switching Frequency IL,PP = 0 0 0.2 0.4 0.6 0.8 1.0 DUTY CYCLE (VIN/VO) FIGURE 24. NORMALIZED INPUT-CAPACITOR RMS CURRENT FOR 3-PHASE CONVERTER For a three-phase design, use Figure 24 to determine the input-capacitor RMS current requirement set by the duty cycle, maximum sustained output current (IO), and the ratio of the peak-to-peak inductor current (IL,PP) to IO. Select a bulk capacitor with a ripple current rating which will minimize the total number of input capacitors required to support the RMS current calculated. The voltage rating of the capacitors should also be at least 1.25 times greater than the maximum input voltage. Figures 25 and 26 provide the same input RMS current information for two-phase and single-phase designs respectively. Use the same approach for selecting the bulk capacitor type and number. RFS VALUE (kΩ) 200 100 50 20 10 100k 1M 500k 200k SWITCHING FREQUENCY (Hz) 2M FIGURE 23. RFS vs SWITCHING FREQUENCY Input Capacitor Selection INPUT-CAPACITOR CURRENT (IRMS/IO) 0.3 0.2 0.1 IL,PP = 0 IL,PP = 0.5 IO IL,PP = 0.75 IO 0 0 0.2 0.4 0.6 0.8 1.0 DUTY CYCLE (VIN/VO) FIGURE 25. NORMALIZED INPUT-CAPACITOR RMS CURRENT FOR 2-PHASE CONVERTER The input capacitors are responsible for sourcing the AC component of the input current flowing into the upper MOSFETs. Their RMS current capacity must be sufficient to 24 FN9246.0 February 15, 2006 ISL8103 MOSFETs using short, high current pulses, it is important to size them as large and as short as possible to reduce their overall impedance and inductance. Extra care should be given to the LGATE traces in particular since keeping the impedance and inductance of these traces helps to significantly reduce the possibility of shoot-through. Equidistant placement of the controller to the three power trains also helps to keep these traces equally short (equal impedances, resulting in similar driving of both sets of MOSFETs). INPUT-CAPACITOR CURRENT (IRMS/IO) 0.6 0.4 0.2 IL,PP = 0 IL,PP = 0.5 IO IL,PP = 0.75 IO 0 0 0.2 0.4 0.6 0.8 1.0 DUTY CYCLE (VIN/VO) FIGURE 26. NORMALIZED INPUT-CAPACITOR RMS CURRENT FOR SINGLE-PHASE CONVERTER Low ESL, high-frequency ceramic capacitors are needed in addition to the input bulk capacitors to suppress leading and falling edge voltage spikes. The spikes result from the high current slew rate produced by the upper MOSFET turn on and off. Place them as close as possible to each upper MOSFET drain to minimize board parasitics and maximize suppression. Layout Considerations MOSFETs switch very fast and efficiently. The speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit and lead to device overvoltage stress. Careful component layout and printed circuit design minimizes the voltage spikes in the converter. Consider, as an example, the turnoff transition of the upper PWM MOSFET. Prior to turnoff, the upper MOSFET was carrying channel current. During the turnoff, current stops flowing in the upper MOSFET and is picked up by the lower MOSFET. Any inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. There are two sets of critical components in a DC/DC converter using a ISL8103 controller. The power components are the most critical because they switch large amounts of energy. Next are small signal components that connect to sensitive nodes or supply critical bypassing current and signal coupling. The power components should be placed first. Locate the input capacitors close to the power switches. Minimize the length of the connections between the input capacitors, CIN, and the power switches. Locate the output inductors and output capacitors between the MOSFETs and the load. Locate the high-frequency decoupling capacitors (ceramic) as close as practicable to the decoupling target, making use of the shortest connection paths to any internal planes, such as vias to GND immediately next, or even onto the capacitor solder pad. The critical small components include the bypass capacitors for VCC and PVCC. Locate the bypass capacitors, CBP, close to the device. It is especially important to locate the components associated with the feedback circuit close to their respective controller pins, since they belong to a highimpedance circuit loop, sensitive to EMI pick-up. It is also important to place current sense components close to their respective pins on the ISL8103, including the RISEN resistors, RS, RCOMP, CCOMP. For proper current sharing route three separate symmetrical as possible traces from the corresponding phase node for each RISEN. A multi-layer printed circuit board is recommended. Figure 27 shows the connections of the critical components for the converter. Note that capacitors CxxIN and CxxOUT could each represent numerous physical capacitors. Dedicate one solid layer, usually the one underneath the component side of the board, for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Keep the metal runs from the PHASE terminal to inductor LOUT short. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the phase nodes. Use the remaining printed circuit layers for small signal wiring. The wiring traces from the IC to the MOSFETs’ gates and sources should be sized to carry at least one ampere of current (0.02” to 0.05”). It is important to have a symmetrical layout, preferably with the controller equidistantly located from the three power trains it controls. Equally important are the gate drive lines (UGATE, LGATE, PHASE): since they drive the power train 25 FN9246.0 February 15, 2006 ISL8103 LOCATE CLOSE TO IC (MINIMIZE CONNECTION PATH) R1 KEY HEAVY TRACE ON CIRCUIT PLANE LAYER C2 ISLAND ON POWER PLANE LAYER C1 VDIFF +12V R2 ISLAND ON CIRCUIT PLANE LAYER CHF01 FB COMP VIA CONNECTION TO GROUND PLANE PVCC1 CBIN1 CHF1 BOOT1 +5V LOCATE NEAR SWITCHING TRANSISTORS; (MINIMIZE CONNECTION PATH) CBOOT1 VSEN RGND UGATE1 3PH 2PH PHASE1 LOUT1 ISEN1 VCC RISEN1 CHF0 LGATE1 ROFST OFST +12V CHF02 FS PVCC2 CHF2 RFS CBIN2 BOOT2 CBOOT2 DAC ISL8103 RREF UGATE2 PHASE2 REF CREF LOUT2 ISEN2 CBOUT (CHFOUT) RISEN2 LOAD LGATE2 REF1 REF0 +12V CHF03 OVP PGOOD CBIN3 LOCATE NEAR LOAD; (MINIMIZE CONNECTION PATH) PVCC3 CHF3 +12V BOOT3 GND CBOOT3 UGATE3 PHASE3 ENLL LOUT3 ISEN3 IREF RISEN3 DROOP LGATE3 OCSET ICOMP ISUM RS RCOMP RS RS ROCSET CCOMP CSUM FIGURE 27. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS 26 FN9246.0 February 15, 2006 ISL8103 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) 2X 9 MILLIMETERS D/2 D1 D1/2 2X N 6 INDEX AREA 40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VJJD-2 ISSUE C) 0.15 C A D A L40.6x6 0.15 C B SYMBOL MIN NOMINAL MAX NOTES A 0.80 0.90 1.00 - A1 - - 0.05 - A2 - - 1.00 A3 1 2 3 E1/2 E/2 E1 b D2 0.15 C B 0.15 C A B TOP VIEW A C 0.08 C SEATING PLANE A1 A3 SIDE VIEW 9 5 NX b 0.10 M C A B 4X P D2 (DATUM B) 8 7 NX k D2 2 N 4X P - 4.10 9 4.25 6.00 BSC - 5.75 BSC 9 3.95 4.10 4.25 (Ne-1)Xe REF. E2 - k 0.25 - - - L 0.30 0.40 0.50 8 L1 - - 0.15 10 N 40 2 Nd 10 3 Ne 10 3 P - - 0.60 9 θ - - 12 9 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 7 N e 8 2. N is the number of terminals. E2/2 NX L 8 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 9 CORNER OPTION 4X (Nd-1)Xe REF. 7, 8 0.50 BSC Rev. 1 10/02 2 3 6 INDEX AREA 7, 8 E 1 (DATUM A) 5, 8 5.75 BSC 3.95 e / / 0.10 C 0.30 E1 E2 A2 0 4X 0.23 9 6.00 BSC D1 9 2X 2X 0.18 D E 9 0.20 REF 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. BOTTOM VIEW 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. A1 NX b 5 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. C L SECTION "C-C" L1 10 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. C L L L1 e 10 L e C C TERMINAL TIP FOR ODD TERMINAL/SIDE 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm. FOR EVEN TERMINAL/SIDE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 27 FN9246.0 February 15, 2006