AD ADV7330 Multiformat 11-bit triple dac video encoder Datasheet

Multiformat 11-Bit
Triple DAC Video Encoder
ADV7330
FEATURES
High Definition Input Formats
8-Bit or 16-Bit (4:2:2) Parallel YCrCb Compliant with:
SMPTE 293M (525p)
BTA T-1004 EDTV2 525p
ITU-R BT.1358 (525p/625p)
ITU-R BT.1362 (525p/625p)
SMPTE 274M (1080i) at 30 Hz and 25 Hz
SMPTE 296M (720p)
Other High Definition Formats Using Async
Timing Mode
High Definition Output Formats
YPrPb Progressive Scan (EIA-770.1, EIA-770.2)
YPrPb HDTV (EIA 770.3)
RGB, RGBHV
CGMS-A (720p/1080i)
Macrovision® Rev 1.1 (525p/625p)
CGMS-A (525p)
Standard Definition Input Formats
CCIR-656 4:2:2 8-Bit or 16-Bit Parallel Input
Standard Definition Output Formats
Composite NTSC M/N
Composite PAL M/N/B/D/G/H/I, PAL-60
SMPTE 170M NTSC Compatible Composite Video
ITU-R BT.470 PAL Compatible Composite Video
S-Video (Y/C)
EuroScart RGB
Component YPrPb (Betacam, MII, SMPTE/EBU N10)
Macrovision Rev 7.1.L1
CGMS/WSS
Closed Captioning
GENERAL FEATURES
Programmable DAC Gain Control
Sync Outputs in All Modes
On-Board Voltage Reference
Three 11-Bit Precision Video DACs
2-Wire Serial I2C® Interface, Open Drain Configuration
Dual I/O Supply 2.5 V/3.3 V Operation
Analog and Digital Supply 2.5 V
On-Board PLL
64-Lead LQFP Package
Lead (Pb) Free Product
APPLICATIONS
SD/PS DVD Recorders/Players
SD/Prog Scan/HDTV Display Devices
SD/HDTV Set Top Boxes
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
STANDARD DEFINITION
CONTROL BLOCK
COLOR CONTROL
BRIGHTNESS
DNR
GAMMA
PROGRAMMABLE FILTERS
SD TEST PATTERN
Y7–Y0
C7–C0
D
E
M
U
X
PROGRAMMABLE
RGB MATRIX
HIGH DEFINITION
CONTROL BLOCK
ADV7330
O
V
E
R
S
A
M
P
L
I
N
G
11-BIT
DAC
11-BIT
DAC
11-BIT
DAC
HD TEST PATTERN
HSYNC_I/P
VSYNC_I/P
BLANK_I/P
CLKIN
TIMING
GENERATOR
COLOR CONTROL
ADAPTIVE FILTER CTRL
SHARPNESS FILTER
PLL
I2C
INTERFACE
GENERAL DESCRIPTION
The ADV®7330 is a high speed, digital-to-analog encoder on a
single monolithic chip. It includes three high speed video D/A
converters with TTL compatible inputs.
The ADV7330 has separate 8-bit or 16-bit input ports that
accept data in high definition or standard definition video
format. For all standards, external horizontal, vertical, and
blanking signals or EAV/SAV timing codes control the insertion of appropriate synchronization signals into the digital
data stream and therefore the output signal.
Purchase of licensed I2C components of Analog Devices or one of its
sublicensed Associated Companies conveys a license for the purchaser under
the Philips I2C Patent Rights to use these components in an I2C system,
provided that the system conforms to the I2C Standard Specification as
defined by Philips.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2004 Analog Devices, Inc. All rights reserved.
ADV7330
DETAILED FEATURES
High Definition Programmable Features (720p/1080i)
2 Oversampling (148.5 MHz)
Internal Test Pattern Generator
(Color Hatch, Black Bar, Flat Field/Frame)
Fully Programmable YCrCb to RGB Matrix
Gamma Correction
Programmable Adaptive Filter Control
Programmable Sharpness Filter Control
CGMS-A (720p/1080i)
Programmable Features (525p/625p)
8 Oversampling
Internal Test Pattern Generator
(Color Hatch, Black Bar, Flat Frame)
Individual Y and PrPb Output Delay
Gamma Correction
Programmable Adaptive Filter Control
Fully Programmable YCrCb to RGB/Matrix
Undershoot Limiter
Macrovision Rev 1.1 (525p/625p)
CGMS-A (525p)
Standard Definition Programmable Features
16 Oversampling
Internal Test Pattern Generator
(Colorbars, Black Bar)
Controlled Edge Rates for Sync, Active Video
Individual Y and PrPb Output Delay
Gamma Correction
Digital Noise Reduction (DNR)
Multiple Chroma and Luma Filters
Luma-SSAF™ Filter with Programmable
Gain/Attenuation
PrPb SSAF™
Separate Pedestal Control on Component and
Composite/S-Video Outputs
VCR FF/RW Sync Mode
Macrovision Rev 7.1.L1
CGMS/WSS
Closed Captioning
Standards Directly Supported
Resolution
Frame
Rate (Hz)
Clk
Input (MHz)
Standard
720 480
720 576
720 483
720 480
720 576
1280 720
1920 1080
1920 1080
29.97
25
59.94
59.94
50
60
30
25
27
27
27
27
27
74.25
74.25
74.25
ITU-R BT.656
ITU-R BT.656
SMPTE 293M
BTA T-1004
ITU-R BT.1362
SMPTE 296M
SMPTE 274M
SMPTE 274M*
Other standards are supported in Async Timing Mode.
*SMPTE 274M-1998: System No. 6
DETAILED FUNCTIONAL BLOCK DIAGRAM
Y
DEINTERCR
LEAVE
TEST
PATTERN
CB
HSYNC
VSYNC
BLANK
SHARPNESS
AND
ADAPTIVE
FILTER
CONTROL
Y COLOR
CR COLOR
CB COLOR
PS 8
HDTV 2
4:2:2
TO
4:4:4
DAC
DAC
TIMING
GENERATOR
CLOCK
CONTROL
AND PLL
U
UV SSAF
V
DAC
RGB
MATRIX
SD 16
CLKIN
CB
DEINTERLEAVE CR
SD/PS/HD
PIXEL INPUT
TEST
PATTERN
DNR
GAMMA
COLOR
CONTROL
SYNC
INSERTION
Y
–2–
LUMA
AND
CHROMA
FILTERS
2 OVERSAMPLING
FSC
MODULATION
CGMS
WSS
REV. B
ADV7330
TABLE OF CONTENTS
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
DETAILED FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
DETAILED FUNCTIONAL BLOCK DIAGRAM . . . . . . . 2
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
DYNAMIC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . 5
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 6
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 11
THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . 11
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 12
MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 13
REGISTER ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Subaddress Register (SR7–SR0) . . . . . . . . . . . . . . . . . . . 14
INPUT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . 27
Standard Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Progressive Scan or HDTV Mode . . . . . . . . . . . . . . . . . . 27
Progressive Scan at 27 MHz (Dual Edge) or 54 MHz . . . 27
OUTPUT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . 28
TIMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
HD Async Timing Mode . . . . . . . . . . . . . . . . . . . . . . . . . 29
HD Timing Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SD Real-Time Control, Subcarrier Reset, Timing Reset . 31
Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SD VCR FF/RW Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Vertical Blanking Interval . . . . . . . . . . . . . . . . . . . . . . . . . 33
SD Subcarrier Frequency Registers . . . . . . . . . . . . . . . . . 33
Square Pixel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
FILTER SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
HD Sinc Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SD Internal Filter Response . . . . . . . . . . . . . . . . . . . . . . . 35
Typical Performance Characteristics . . . . . . . . . . . . . . . . . . 36
COLOR CONTROLS AND RGB MATRIX . . . . . . . . . . . 40
HD Y Level, Cr Level, Cb Level . . . . . . . . . . . . . . . . . . . 40
HD RGB Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
SD Luma and Color Control . . . . . . . . . . . . . . . . . . . . . . 40
SD Hue Adjust Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
SD Brightness Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
SD Brightness Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Double Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
PROGRAMMABLE DAC GAIN CONTROL . . . . . . . . . . 42
Gamma Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
REV. B
HD SHARPNESS FILTER CONTROL AND
ADAPTIVE FILTER CONTROL . . . . . . . . . . . . . . . . . . .
HD Sharpness Filter Mode . . . . . . . . . . . . . . . . . . . . . . .
HD Adaptive Filter Mode . . . . . . . . . . . . . . . . . . . . . . . .
HD Sharpness Filter and Adaptive Filter Application
Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADAPTIVE FILTER CONTROL APPLICATION . . . . . .
SD Digital Noise Reduction . . . . . . . . . . . . . . . . . . . . . . .
Coring Gain Border . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Coring Gain Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DNR Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Border Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Size Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DNR Input Select Control . . . . . . . . . . . . . . . . . . . . . . . .
DNR Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Offset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SD ACTIVE VIDEO EDGE . . . . . . . . . . . . . . . . . . . . . . . .
SAV/EAV STEP EDGE CONTROL . . . . . . . . . . . . . . . . .
BOARD DESIGN AND LAYOUT CONSIDERATIONS .
DAC Termination and Layout Considerations . . . . . . . .
VIDEO OUTPUT BUFFER AND OPTIONAL
OUTPUT FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PC BOARD LAYOUT CONSIDERATIONS . . . . . . . . . .
Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . .
Analog Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX 1—COPY GENERATION
MANAGEMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . .
HD CGMS Data Registers 2–0 . . . . . . . . . . . . . . . . . . . .
SD CGMS Data Registers 2–0 . . . . . . . . . . . . . . . . . . . . .
HD CGMS Data Registers . . . . . . . . . . . . . . . . . . . . . . .
Function of CGMS Bits . . . . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX 2—SD WIDE SCREEN SIGNALING . . . . . .
APPENDIX 3—SD CLOSED CAPTIONING . . . . . . . . . .
APPENDIX 4—TEST PATTERNS . . . . . . . . . . . . . . . . . .
APPENDIX 5—SD TIMING MODES . . . . . . . . . . . . . . .
Mode 0 (CCIR-656)—Slave Option . . . . . . . . . . . . . . . .
Mode 0 (CCIR-656)—Master Option . . . . . . . . . . . . . . .
Mode 1—Slave Option . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 1—Master Option . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 2—Slave Option . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 2—Master Option . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 3—Master/Slave Option . . . . . . . . . . . . . . . . . . . . .
APPENDIX 6—HD TIMING . . . . . . . . . . . . . . . . . . . . . .
APPENDIX 7—VIDEO OUTPUT LEVELS . . . . . . . . . . .
HD YPrPb Output Levels . . . . . . . . . . . . . . . . . . . . . . . .
RGB Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
YPrPb Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX 8—VIDEO STANDARDS . . . . . . . . . . . . . . .
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . .
–3–
44
44
44
45
46
47
47
47
47
47
48
48
48
48
48
48
50
50
50
51
51
52
52
53
53
53
53
53
55
56
57
60
60
61
62
63
64
65
66
67
68
68
69
70
74
76
ADV7330–SPECIFICATIONS
Parameter
Min
(VAA = 2.375 V to 2.625 V, VDD = 2.375 V to 2.625 V; VDD_IO = 2.375 V to 3.6 V,
VREF = 1.235 V, RSET = 3040 , RLOAD = 300 . All specifications TMIN to TMAX
(0C to 70C), unless otherwise noted.)
Typ
Max
Unit
Conditions
1
STATIC PERFORMANCE
(With No Oversampling Ratio)
Resolution
Integral Nonlinearity
Differential Nonlinearity2, +ve
Differential Nonlinearity2, –ve
DIGITAL OUTPUTS
Output Low Voltage, VOL
Output High Voltage, VOH
Three-State Leakage Current
Three-State Output Capacitance
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Leakage Current
Input Capacitance, CIN
ANALOG OUTPUTS
Full-scale Output Current
Output Current Range
DAC to DAC Matching
Output Compliance Range, VOC
Output Capacitance, COUT
VOLTAGE REFERENCE
Internal Reference Range, VREF
External Reference Range, VREF
VREF Current4
POWER REQUIREMENTS
Normal Power Mode
IDD5
IDD_IO
IAA7, 8
Sleep Mode
IDD
IAA
IDD_IO
Power Supply Rejection Ratio
11
1.5
0.5
1.0
Bits
LSB
LSB
LSB
0.4 [0.4]3
3
2.4 [2.0]
± 1.0
2
2
0.8
3
2
4.1
4.1
0
1.15
1.15
4.33
4.33
1.0
1.0
7
4.6
4.6
1.4
V
V
µA
pF
V
V
µA
pF
VIN = 2.4 V
mA
mA
%
V
pF
1.235
1.235
± 10
1.3
1.3
V
V
µA
170
110
95
1.0
24
1906
mA
mA
mA
mA
mA
28
ISINK = 3.2 mA
ISOURCE = 400 µA
VIN = 0.4 V, 2.4 V
200
10
250
µA
µA
µA
0.01
%/%
SD (16×)
PS (8×)
HDTV (2×)
NOTES
1
Oversampling disabled. Static DAC performance will be improved with increased oversampling ratios.
2
DNL measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value; for –ve DNL,
the actual step value lies below the ideal step value.
3
Value in brackets for V DD_IO = 2.375 V to 2.75 V.
4
External current required to overdrive internal V REF.
5
IDD, the circuit current, is the continuous current required to drive the digital core.
6
Guaranteed maximum by characterization.
7
IAA is the total current required to supply all DACs including the V REF circuitry and the PLL circuitry.
8
All DACs on.
Specifications subject to change without notice.
–4–
REV. B
ADV7330
DYNAMIC SPECIFICATIONS
Parameter
PROGRESSIVE SCAN MODE
Luma Bandwidth
Chroma Bandwidth
SNR
HDTV MODE
Luma Bandwidth
Chroma Bandwidth
STANDARD DEFINITION MODE
Hue Accuracy
Color Saturation Accuracy
Chroma Nonlinear Gain
Chroma Nonlinear Phase
Chroma/Luma Intermodulation
Chroma/Luma Gain Inequality
Chroma/Luma Delay Inequality
Luminance Nonlinearity
Chroma AM Noise
Chroma PM Noise
Differential Gain
Differential Phase
SNR
(VAA = 2.375 V to 2.625 V, VDD = 2.375 V to 2.625 V; VDD_IO = 2.375 V to 3.6 V, VREF = 1.235 V,
RSET = 3040 , RLOAD = 300 . All specifications TMIN to TMAX (0C to 70C), unless otherwise noted.)
Min
Typ
Max
Unit
Conditions
12.5
5.8
65.6
72
MHz
MHz
dB
dB
Luma ramp unweighted
Flat field full bandwidth
30
13.75
MHz
MHz
0.4
0.4
1.2
–0.2
0
97.0
–1.1
0.5
84
75.2
0.20
0.15
59.1
77.7
Degrees
%
±%
± Degrees
±%
±%
ns
±%
dB
dB
%
Degrees
dB
dB
Specifications subject to change without notice.
REV. B
–5–
Referenced to 40 IRE
NTSC
NTSC
Luma ramp
Flat field full bandwidth
ADV7330
(VAA = 2.375 V to 2.625 V, VDD = 2.375 V to 2.625 V; VDD_IO = 2.375 V to 3.6 V, VREF = 1.235 V,
SET = 3040 , RLOAD = 300 . All specifications TMIN to TMAX (0C to 70C), unless otherwise noted.)
TIMING SPECIFICATIONS R
Parameter
Min
Typ
Max
Unit
400
kHz
µs
µs
µs
µs
ns
ns
ns
µs
ns
Conditions
1
MPU PORT
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
RESET Low Time
0
0.6
1.3
0.6
0.6
100
300
300
0.6
100
ANALOG OUTPUTS
Analog Output Delay2
Output Skew
CLOCK CONTROL AND PIXEL PORT3
fCLK
fCLK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t111
Data Hold Time, t121
SD Output Access Time, t13
SD Output Hold Time, t14
HD Output Access Time, t13
HD Output Hold Time, t14
PIPELINE DELAY4
7
1
After this period, the first clock is generated
Relevant for repeated start condition
ns
ns
27
MHz
Progressive scan mode
MHz
HDTV mode/async mode
% of one clk cycle
% of one clk cycle
ns
ns
ns
ns
ns
ns
81
40
40
2.0
2.0
15
5.0
14
5.0
63
76
35
41
36
clk cycles
clk cycles
clk cycles
clk cycles
clk cycles
SD (2×, 16×)
SD component mode (16×)
PS (1×)
PS (8×)
HD (2×, 1×)
NOTES
1
Guaranteed by characterization.
2
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of the DAC output full-scale transition.
3
Data: C [9:0]; Y [9:0], S[9:0].
Control: HSYNC_I/P, VSYNC_I/P, BLANK_I/P, HSYNC_O/P, VSYNC_O/P, BLANK_O/P.
4
SD, PS = 27 MHz, HD = 74.25 MHz.
Specifications subject to change without notice.
–6–
REV. B
ADV7330
CLKIN
t9
CONTROL
INPUTS
t12
t10
HSYNC_I/P
VSYNC_I/P
BLANK_I/P
Y7–Y0
Y0
Y1
Y2
Y3
Y4
Y5
C7–C0
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
t11
CONTROL
OUTPUTS
t13
HSYNC_O/P
VSYNC_O/P
BLANK_O/P
t14
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
Figure 1. HD/PS 4:2:2 Input Mode (HD: Input Mode 010) (PS: Input Mode 001)
CLKIN
t9
CONTROL
INPUTS
t10
HSYNC_I/P
VSYNC_I/P
BLANK_I/P
Y7–Y0
Cb0
Y0
Cr0
Y1
t12
Crxxx
Yxxx
t12
t11
t11
t13
CONTROL
OUTPUTS
HSYNC_O/P
VSYNC_O/P
BLANK_O/P
t14
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
Figure 2. PS 4:2:2 1× 8-Bit Interleaved at 27 MHz Hsync/Vsync Input Mode (Input Mode 100)
REV. B
–7–
ADV7330
CLKIN
t9
3FF
Y7–Y0
t10
00
00
XY
t12
Cb0*
Y0
Cr0
Y1
t12
t11
t11
t13
CONTROL
OUTPUTS
HSYNC_O/P
VSYNC_O/P
BLANK_O/P
t14
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
*Y0, Cb, SEQUENCE AS PER SUBADDRESS 01h BIT 1
Figure 3. PS 4:2:2 1× 8-Bit Interleaved at 27 MHz EAV/SAV Input Mode (Input Mode 100)
CLKIN
t9
CONTROL
INPUTS
Cb0
Y7–Y0
Y0
Cr2
Y1
t12
t11
CONTROL
OUTPUTS
t10
HSYNC_I/P
VSYNC_I/P
BLANK_I/P
Cbxxx
Cbxxx
t13
t14
HSYNC_O/P
VSYNC_O/P
BLANK_O/P
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
Figure 4. PS 4:2:2 1× 8-Bit Interleaved at 54 MHz Hsync/Vsync I/P Mode (Input Mode 011)
CLKIN
t9
Y7–Y0
3FF
t10
00
00
XY
Y0
Cr0
Y1
t13
t12
t11
Cb0
t14
CONTROL
OUTPUTS
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
Figure 5. PS 4:2:2 1× 8-Bit Interleaved at 54 MHz EAV/SAV Input Mode (Input Mode 011)
–8–
REV. B
ADV7330
CLKIN
CONTROL
INPUTS
t12
t10
t9
HSYNC_I/P
VSYNC_I/P
BLANK_I/P
IN SLAVE MODE
Cb
Y7–Y0
Y
Y
Cr
Cb
t13
t11
CONTROL
OUTPUTS
Y
HSYNC_O/P
VSYNC_O/P
BLANK_O/P
IN MASTER/SLAVE
MODE
t14
Figure 6. 8-Bit SD Pixel Input Mode (Input Mode 000)
CLKIN
t9
CONTROL
INPUTS
t12
t10
HSYNC_I/P
VSYNC_I/P
BLANK_I/P
IN SLAVE MODE
Y7–Y0
Y0
Y1
Y2
Y3
C7–C0
Cb0
Cr0
Cb2
Cr2
t13
t11
CONTROL
OUTPUTS
HSYNC_O/P
VSYNC_O/P
BLANK_O/P
IN MASTER/SLAVE
MODE
t14
Figure 7. 16-Bit SD Pixel Input Mode (Input Mode 000)
HSYNC_I/P
VSYNC_I/P
A
BLANK_I/P
Y7–Y0
Y0
Y1
Y2
Y3
C7–C0
Cb0
Cr0
Cr1
Cb1
B
A = 16 CLK CYCLES FOR 525p
A = 12 CLK CYCLES FOR 626p
A = 44 CLK CYCLES FOR 1080i @ 30Hz, 25Hz
A = 70 CLK CYCLES FOR 720p
AS RECOMMENDED BY STANDARD
B (MIN) = 122 CLK CYCLES FOR 525p
B (MIN) = 132 CLK CYCLES FOR 625p
B (MIN) = 236 CLK CYCLES FOR 1080i @ 30Hz, 25Hz
B (MIN) = 300 CLK CYCLES FOR 720p
Figure 8. HD 4:2:2 Input Timing Diagram
REV. B
–9–
ADV7330
HSYNC_I/P
VSYNC_I/P
A
BLANK_I/P
Y7–Y0
Cb
Y
Cr
Y
Cr
Y
B
A = 32 CLK CYCLES FOR 525p
A = 24 CLK CYCLES FOR 626p
AS RECOMMENDED BY STANDARD
B (MIN) = 244 CLK CYCLES FOR 525p
B (MIN) = 264 CLK CYCLES FOR 625p
Figure 9. PS 4:2:2, 1 × 8-Bit Interleaved Input Timing Diagram
HSYNC_I/P
VSYNC_I/P
PAL = 24 CLK CYCLES
NTSC = 32 CLK CYCLES
BLANK_I/P
Y7–Y0
Cb
Y
*SELECTED BY ADDRESS 44h BIT 7
PAL = 264 CLK CYCLES
NTSC = 244 CLK CYCLES
Figure 10. SD Timing Input for Timing Mode 1
t3
t5
t3
SDA
t1
t6
SCLK
t2
t4
t7
t8
Figure 11. MPU Port Timing Diagram
–10–
REV. B
ADV7330
ABSOLUTE MAXIMUM RATINGS 1, 2
THERMAL CHARACTERISTICS
VAA to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.0 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.0 V
VDD_IO to GND_IO . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
Digital Input Voltage to DGND . . . . –0.3 V to VDD_IO + 0.3 V
VAA to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
DGND to GND_IO . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
AGND to GND_IO . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Ambient Operating Temperature (TA) . . . . . . . . 0°C to 70°C
Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C
Infrared Reflow Soldering (20 secs) . . . . . . . . . . . . . . . . 260°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational section
of this specification is not implied. Exposure to absolute maximum ratings for
extended periods may affect device reliability.
2
Analog output short circuit to any power supply or common can be of an indefinite
duration.
␪JC = 11°C/W
␪JA = 47°C/W
The ADV7330 is a Pb-free, environmentally friendly product. It is
manufactured using the most up-to-date materials and processes.
The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications, and is able
to withstand surface-mount soldering at up to 255°C (± 5°C).
In addition, it is backward compatible with conventional SnPb
soldering processes. This means that the electroplated Sn coating
can be soldered with Sn/Pb solder pastes at conventional reflow
temperatures of 220°C to 235°C.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADV7330KST
0°C to 70°C
Low Profile Quad Flat Package
ST-64-2
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADV7330 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. B
–11–
ADV7330
VSYNC_O/P
HSYNC_O/P
TEST4
TEST5
TEST6
TEST7
TEST8
VDD
DGND
TEST9
TEST10
TEST11
TEST12
TEST13
TEST14
GND_IO
PIN CONFIGURATION
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
BLANK_O/P
47
TEST16
TEST1 3
46
VREF
Y0 4
45
TEST15
Y1 5
44
NC
Y2 6
43
NC
VDD_IO 1
TEST0 2
PIN 1
IDENTIFIER
Y3 7
ADV7330
42
NC
Y4 8
TOP VIEW
(Not to Scale)
41
VAA
40
AGND
VDD 10
39
DAC A
DGND 11
38
DAC B
Y6 12
37
DAC C
Y7 13
36
COMP
TEST2 14
35
RSET
TEST3 15
34
EXT_LF
C0 16
33
RESET
Y5 9
CLKIN
RTC_SCR_TR
C7
C6
C5
C4
C3
BLANK_I/P
VSYNC_I/P
HSYNC_I/P
NC = NO CONNECT
SCLK
SDA
ALSB
I2C
C2
C1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIN FUNCTION DESCRIPTIONS
Pin Number
Mnemonic
I/O
Function
11, 57
DGND
G
Digital Ground.
2, 3, 14, 15,
51–55, 58–63
TEST0–TEST14
I
Not used, tie to DGND.
40
AGND
G
Analog Ground.
32
CLKIN
I
Pixel Clock Input for HD (74.25 MHz Only, PS (27 MHz), SD (27 MHz)).
36
COMP
O
Compensation Pin for DACs. Connect 0.1 µF capacitor from COMP pin to VAA.
39
DAC A
O
CVBS/GREEN/Y Analog Output.
38
DAC B
O
Chroma/BLUE/Pb Analog Output.
37
DAC C
O
Luma/RED/Pr Analog Output.
25
BLANK_I/P
I
Video Blanking Control Signal. For HD and PS, this input is active high. For SD
input, this input is active low.
23
HSYNC_I/P
I
Video Horizontal Sync Control Signal.
24
VSYNC_I/P
I
Video Vertical Sync Control Signal.
4–9, 12, 13
Y7–Y0
I
SD or Progressive Scan/HDTV Input Port for Y Data. Input port for interleaved
progressive scan data. The LSB is set up on Pin Y0.
16–18, 26–30
C7–C0
I
8-Bit SD/Progressive Scan/HDTV Input Port. The LSB is set up on Pin C0.
33
RESET
I
This input resets the on-chip timing generator and sets the ADV7330 into the default
register setting. Reset is an active low signal.
35
RSET
I
A 3040 Ω resistor must be connected from this pin to AGND and is used to control
the amplitudes of the DAC outputs.
22
SCLK
I
I2C Port Serial Interface Clock Input.
21
SDA
I/O
I2C Port Serial Data Input/Output.
20
ALSB
I
TTL Address Input. This signal sets up the LSB of the I2C address. When this pin is
tied low, the I2C filter is activated, which reduces noise on the I2C interface.
1
VDD_IO
P
Power Supply for Digital Inputs and Outputs.
–12–
REV. B
ADV7330
PIN FUNCTION DESCRIPTIONS (continued)
Pin Number
Mnemonic
I/O
Function
10, 56
VDD
P
Digital Power Supply.
41
VAA
P
Analog Power Supply.
45, 47
TEST15, TEST16 O
Not used, do not connect.
34
EXT_LF
I
External Loop Filter for the Internal PLL.
31
RTC_SCR_TR
I
Multifunctional Input: Real-Time Control (RTC) Input, Timing Reset Input,
Subcarrier Reset Input.
48
BLANK_O/P
O
Video Blanking Control Signal. For HD and PS, this input is active high. For SD input,
this output is active low.
50
HSYNC_O/P
O
Video Horizontal Sync Control Signal.
49
VSYNC_O/P
O
Video Vertical Sync Control Signal.
I
This input pin must be tied high (VDD_IO) for the ADV7330 to interface over the I2C port.
2
19
IC
64
GND_IO
Digital Input/Output Ground.
42–44
NC
No Connect.
46
VREF
I/O
Optional External Voltage Reference Input for DACs or Voltage Reference Output
(1.235 V).
TERMINOLOGY
SD
HD
PS
Standard definition video, conforming to ITU-R
BT.601/656.
High definition video, such as progressive scan or HDTV.
Progressive scan video, conforming to SMPTE 293M,
ITU-R BT.1358, BTA T-1004EDTC2, BTA1362
MPU PORT DESCRIPTION
The ADV7330 supports a 2-wire serial (I2C compatible) microprocessor bus driving multiple peripherals. This bus operates
in an Open Drain configuration. Two inputs, serial data
(SDA) and serial clock (SCL), carry information between any
devices connected to the bus. Each slave device is recognized by a
unique address. The ADV7330 has four possible slave addresses for both read and write operations. These are unique
addresses for each device and are illustrated in Figure 12. The
LSB sets either a read or write operation. Logic 1 corresponds to
a read operation, while Logic 0 corresponds to a write operation.
A1 is set by setting the ALSB pin of the ADV7330 to Logic 0
or Logic 1. When ALSB is set to 1, there is greater input bandwidth on the I2C lines, which allows high speed data transfers
on this bus. When ALSB is set to 0, there is reduced input
bandwidth on the I2C lines, which means that pulses of less
than 50 ns will not pass into the I2C internal controller. This
mode is recommended for noisy systems.
1
1
0
1
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
0
1
WRITE
READ
Figure 12. ADV7330 Slave Address = D4h
REV. B
HDTV
High definition television video, conforming to SMPTE
274M or SMPTE 296M.
YCrCb SD, PS, or HD component digital video.
YPrPb SD, PS, or HD component analog video.
To control the various devices on the bus, the following protocol must be followed. First the master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDA, while SCL remains high. This indicates that an address/
data stream will follow. All peripherals respond to the start
condition and shift the next eight bits (7-bit address + R/W bit).
The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling
the data line low during the ninth clock pulse. This is known as
an acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition is
when the device monitors the SDA and SCL lines waiting for the
start condition and the correct transmitted address. The R/W
bit determines the direction of the data.
A Logic 0 on the LSB of the first byte means that the master
will write information to the peripheral. A Logic 1 on the LSB
of the first byte means that the master will read information
from the peripheral.
The ADV7330 acts as a standard slave device on the bus. The
data on the SDA pin is eight bits long, supporting the 7-bit
addresses plus the R/W bit. It interprets the first byte as the device
address and the second byte as the starting subaddress. There
is a subaddress auto-increment facility. This allows data to be
written to or read from registers in ascending subaddress
sequence, starting at any valid subaddress. A data transfer is
always terminated by a stop condition. The user can also access
any unique subaddress register on a one-by-one basis without
having to update all the registers.
–13–
ADV7330
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCL high period, the
user should issue only one start condition, one stop condition,
or a single stop condition followed by a single start condition.
If an invalid subaddress is issued by the user, the ADV7330 will
not issue an acknowledge and will return to the idle condition.
If in auto-increment mode the user exceeds the highest subaddress,
the following action will be taken:
1. In read mode, the highest subaddress register contents will
continue to be output until the master device issues a no
acknowledge. This indicates the end of a read. A no acknowledge condition is when the SDA line is not pulled low on the
ninth pulse.
2. In write mode, the data for the invalid byte will not be loaded
into any subaddress register, a no acknowledge will be issued
by the ADV7330, and the part will return to the idle condition.
Before writing to the subcarrier frequency registers, it is a requirement that the ADV7330 reset at least once after power-up.
last subcarrier frequency register byte has been received by
the ADV7330.
Figure 13 illustrates an example of data transfer for a write
sequence and the start and stop conditions. Figure 14 shows
bus write and read sequences.
REGISTER ACCESS
The MPU can write to or read from all of the registers of the
ADV7330 except the subaddress registers that are write-only
registers. The subaddress register determines which register the
next read or write operation accesses. All communications with
the part go through the bus start with an access to the subaddress
register. Then a read/write operation is performed from/to the
target address, which then increments to the next address until
a stop command on the bus is performed.
Register Programming
The following tables describe the functionality of each register.
All registers can be read from as well as written to, unless otherwise stated.
Subaddress Register (SR7–SR0)
The communications register is an 8-bit write-only register. After
the part has been accessed over the bus and a read/write operation
is selected, the subaddress is set up. The subaddress register
determines to/from which register the operation takes place.
The four subcarrier frequency registers must be updated starting
with subcarrier frequency register 0 through subcarrier frequency
register 3. The subcarrier frequency will not update until the
SDATA
SCLOCK
S
1–7
9
8
START ADRR R/W ACK
1–7
8
9
SUBADDRESS ACK
1–7
8
DATA
9
P
ACK
STOP
Figure 13. Bus Data Transfer
WRITE
SEQUENCE
S
SLAVE ADDR
A(S)
SUBADDR
A(S)
DATA
LSB = 0
READ
SEQUENCE
S
SLAVE ADDR A(S)
S = START BIT
P = STOP BIT
A(S)
DATA
A(S) P
LSB = 1
SUBADDR
A(S) S SLAVE ADDR
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S)
DATA
A(M)
DATA
A(M)
P
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
Figure 14. Write and Read Sequence
–14–
REV. B
ADV7330
SR7–
SR0
Register
Bit Description
00h
Power Mode
Sleep Mode. With this control
enabled, the current consumption is
reduced to µA level. All DACs and the
2
internal PLL cct are disabled. I C
registers can be read from and written
to in sleep mode.
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
1
1
0
1
DAC A. Power On/Off.
0
1
x
x
Sleep Mode On
PLL On
Reserved
x
BTA T-1004 or BT 1362
Compatibility.
0
1
Clock Edge
0
1
Reserved
Reserved
Input Mode
REV. B
FCh
PLL Off
DAC C Off
DAC C On
DAC B Off
DAC B On
DAC A Off
DAC A On
0
1
DAC B. Power On/Off.
Reserved
Sleep Mode Off
0
DAC C. Power On/Off.
Input Mode
Register Reset
Values (Shaded)
0
PLL and Oversampling Control. This
control allows the internal PLL cct to
be powered down and the oversampling to be switched off.
01h
Register Setting
Disabled
Enabled
Cb Clocked on Rising
Edge
Y Clocked on Rising Edge
Only for PS dualedge clk mode
Only for PS
interleaved input at
27 MHz
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
SD Input
PS Input
HDTV Input
PS 54 MHz Input
PS 27 MHz Input
Reserved
Reserved
1
1
1
Reserved
0
–15–
38h
ADV7330
SR7–
SR0
Register
Bit Description
02h
Mode Register 0
Reserved
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Test Pattern Black Bar
Bit
2
Bit
1
Bit
0
Register Setting
Reset Values
0
0
Zero must be written
to these bits
20h
Disabled
Enabled
Disable
Programmable RGB
Matrix
Enable Programmable
RGB Martix
11h, Bit 2 must
also be enabled
0
1
RGB Matrix
0
1
Sync on RGB1
0
1
RGB/YUV Output
0
1
SD Sync
HD Sync
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0
1
RGB Matrix 0
RGB Matrix 1
RGB Matrix 2
RGB Matrix 3
RGB Matrix 4
RGB Matrix 5
RGB Matrix 6
2
DAC A,B,C Output Level
Positive Gain to DAC Output Voltage
Negative Gain to DAC Output Voltage
0Ch
0Dh
0Eh
0Fh
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1
0
…
1
0
0
1
0
…
1
x
x
x
x
x
x
x
0
0
0
x
x
x
x
x
x
x
0
0
0
x
x
x
x
x
x
0
0
0
x
x
x
x
x
x
0
0
0
x
x
x
x
x
x
0
0
0
x
x
x
x
x
x
0
0
0
x
x
x
x
x
x
0
0
1
0
0
1
1
1
0
1
1
1
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
Reserved
Reserved
Reserved
Reserved
No Sync
Sync on all RGB
Outputs
RGB component
Outputs
YUV component
Outputs
No Sync Output
Output SD Syncs on
HSYNC_O/P,
VSYNC_O/P,
BLANK_O/P
No Sync Output
Output HD Syncs on
HSYNC_O/P,
VSYNC_O/P,
BLANK_O/P
LSB for GY
LSB for RV
LSB for BU
LSB for GV
LSB for GU
Bit 9–2 for GY
Bit 9–2 for GU
Bit 9–2 for GV
Bit 9–2 for BU
Bit 9–2 for RV
Reserved
0%
0.018%
0.036%
……
7.382%
7.5%
–7.5%
–7.382%
–7.364%
…….
–0.018%
03h
F0h
4Eh
0Eh
24h
92h
7Ch
00h
00h
00h
00h
00h
NOTES
1
For more detail, refer to Appendix 7.
2
For more detail on the programmable output levels, refer to the Programmable DAC Gain Control section.
–16–
REV. B
ADV7330
SR7–
SR0
Register
Bit Description
10h
HD Mode
Register 1
HD Output Standard
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
HD Input Control Signals
HD 625p
0
0
1
1
1
0
1
HD 720p
HD Mode
Register 2
EIA770.2 Output
0
1
1
0
1
1
EIA770.1 Output
Output levels for Full Input
Range
Reserved
HSYNC, VSYNC, BLANK
EAV/SAV codes
Async Timing Mode
Reserved
525p
625p
1080i
720p
BLANK Active High
BLANK Active Low
Macrovision Off
0
1
0
1
0
HD Pixel Data Valid
0
1
0
HD Test Pattern Enable
0
1
HD Test Pattern Hatch/Field
0
1
HD VBI Open
0
1
HD Undershoot Limiter
HD Sharpness Filter
REV. B
0
0
1
1
0
1
0
1
0
1
–17–
00h
0
1
11h
Reset
Values
0
0
1
HD BLANK Polarity
HD Macrovision for 525p/625p
0
Register Setting
Macrovision On
Pixel Data Valid Off
Pixel Data Valid On
Reserved
HD Test Pattern Off
HD Test Pattern On
Hatch
Field/Frame
Disabled
Enabled
Disabled
–11 IRE
–6 IRE
–1.5 IRE
Disabled
Enabled
00h
ADV7330
SR7–
SR0
Register
Bit Description
12h
HD Mode Register 3
HD Y Delay with respect to falling
edge of HSYNC
Bit
7
Bit
6
HD Color Delay with respect to
falling edge of HSYNC
HD CGMS
HD Mode Register 4
Bit
4
Bit
3
0
0
0
0
0
0
1
0
1
1
0
1
0
1
0
Bit
2
Bit
1
Bit
0
Register Setting
Reset
Values
0 Clk Cycle
1 Clk Cycle
2 Clk Cycles
3 Clk Cycles
4 Clk Cycles
0 Clk Cycle
00h
0
0
0
0
0
0
1
0
1
1
0
1
0
1
0
0
1
HD CGMS CRC
13h
Bit
5
0
1
0
HD Cr/Cb Sequence
1
Reserved
Reserved
Sinc Filter on DAC A, B, C
0
0
0
1
Reserved
HD Chroma SSAF
Reserved
HD Double Buffering
14h
HD Mode Register 5
0
0
1
Disabled
x
0
0
1080i Frame Rate
0
Reserved
HD Vsync/Field Input
1
0
0
1
HD Mode Register 6
0
Field Input
1
Vsync Input
Update Field/Line Counter
Field/Line Counter Free Running
0
Reserved
0
HD RGB Input
1
HD Sync on PrPb
0
1
HD Color DAC Swap
0
1
HD Gamma Curve A/B
0
1
HD Gamma Curve Enable
HD Adaptive Filter Enable
00h
0 must be written to these bits.
0
0
0
1
HD Adaptive Filter Mode
Enabled
A low-high-low transition resets the
internal HD timing counters.
30 Hz/2200 Total Samples/Line
25 Hz/2640 Total Samples/Line
1
15h
4Ch
Cr after Falling Edge of HSYNC
0 must be written to this bit.
0 must be written to this bit.
Disabled
Enabled
0 must be written to this bit.
Disabled
Enabled
1
0
1
HD Timing Reset
Lines/Frame
1 Clk Cycle
2 Clk Cycles
3 Clk Cycles
4 Clk Cycles
Disabled
Enabled
Disabled
Enabled
Cb after Falling Edge of HSYNC
0
1
0
1
0 must be written to this bit.
00h
Disabled
Enabled
Disabled
Enabled
DAC E = Pr; DAC F = Pb
DAC E = Pb; DAC F = Pr
Gamma Curve A
Gamma Curve B
Disabled
Enabled
Mode A
Mode B
Disabled
Enabled
NOTES
1
When set to 0, the line and field counters automatically wrap around at the end of the field/frame of the standard selected. When set to 1, the field/line counters are
free running and wrap around when external sync signals indicate so.
–18–
REV. B
ADV7330
SR7–
SR0
Register
Bit Description
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
HD Y Level
HD Cr Level 1
HD Cb Level1
1
HD Sharpness Filter
Gain
HD CGMS Data 0
HD CGMS Data 1
HD CGMS Data 2
HD Gamma A
HD Gamma A
HD Gamma A
HD Gamma A
HD Gamma A
HD Gamma A
HD Gamma A
HD Gamma A
HD Gamma A
HD Gamma A
HD Gamma B
HD Gamma B
HD Gamma B
HD Gamma B
HD Gamma B
HD Gamma B
HD Gamma B
HD Gamma B
HD Gamma B
HD Gamma B
Bit 6 Bit 5
Bit 4 Bit 3
Bit 2 Bit 1
Bit 0 Register
Setting
Reset
Values
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Y Color Value
Cr Color Value
Cb Color Value
0
0
..
0
1
..
1
0
0
..
1
0
..
1
0
0
..
1
0
..
1
0
1
..
1
0
..
1
C19
C11
C3
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
C18
C10
C2
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
C17
C9
C1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
C16
C8
C0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Gain A = 0
Gain A = +1
……
Gain A = +7
Gain A = –8
……
Gain A = –1
Gain B = 0
Gain B = +1
…….
Gain B = +7
Gain B = –8
……..
Gain B = –1
CGMS 19–16
CGMS 15–8
CGMS 7–0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
A0h
80h
80h
00h
00h
00h
00h
00h
00h
00h
00h
HD CGMS Data Bits
HD CGMS Data Bits
HD CGMS Data Bits
HD Gamma Curve A Data Points
HD Gamma Curve A Data Points
HD Gamma Curve A Data Points
HD Gamma Curve A Data Points
HD Gamma Curve A Data Points
HD Gamma Curve A Data Points
HD Gamma Curve A Data Points
HD Gamma Curve A Data Points
HD Gamma Curve A Data Points
HD Gamma Curve A Data Points
HD Gamma Curve B Data Points
HD Gamma Curve B Data Points
HD Gamma Curve B Data Points
HD Gamma Curve B Data Points
HD Gamma Curve B Data Points
HD Gamma Curve B Data Points
HD Gamma Curve B Data Points
HD Gamma Curve B Data Points
HD Gamma Curve B Data Points
HD Gamma Curve B Data Points
0
0
..
0
1
..
1
0
C15
C7
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
..
1
0
..
1
0
C14
C6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
NOTES
1
For the internal test pattern only.
REV. B
x
x
x
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
HD Sharpness Filter Gain Value A
HD Sharpness Filter Gain Value B
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
Bit 7
–19–
0
0
..
1
0
..
1
0
C13
C5
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1
..
1
0
..
1
0
C12
C4
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
ADV7330
SR7SR0
Register
Bit Description
38h
HD Adaptive Filter
Gain 1
HD Adaptive Filter Gain 1
Value A
HD Adaptive Filter Gain 1
Value B
39h
HD Adaptive Filter
Gain 2
HD Adaptive Filter
Gain 3
3Ch
3Dh
HD Adaptive Filter
Threshold A
HD Adaptive Filter
Threshold B
HD Adaptive Filter
Threshold C
0
1
..
1
0
..
1
x
x
x
x
x
x
x
x
x
x
x
x
x
Threshold B
00h
x
x
x
x
x
x
x
x
Threshold C
00h
0
0
..
0
1
..
1
0
0
..
1
0
..
1
0
0
..
1
0
..
1
HD Adaptive Filter Threshold A
Value
HD Adaptive Filter Threshold B
Value
HD Adaptive Filter Threshold C
Value
–20–
0
1
..
1
0
..
1
0
0
..
0
1
..
1
0
0
..
1
0
..
1
0
0
..
1
0
..
1
0
1
..
1
0
..
1
0
0
..
0
1
..
1
0
0
..
1
0
..
1
0
0
..
1
0
..
1
0
1
..
1
0
..
1
0
1
..
1
0
..
1
0
1
..
1
0
..
1
HD Adaptive Filter Gain 3
Value A
HD Adaptive Filter Gain 3
Value B
3Bh
0
0
..
1
0
..
1
x
0
0
..
1
0
..
1
0
0
..
1
0
..
1
00h
0
0
..
1
0
..
1
x
0
0
..
1
0
..
1
0
0
..
1
0
..
1
Reset
Values
0
0
..
0
1
..
1
x
0
0
..
0
1
..
1
0
0
..
0
1
..
1
Register
Setting
Gain A = 0
Gain A = +1
……
Gain A = +7
Gain A = –8
……
Gain A = –1
Gain B = 0
Gain B = +1
…….
Gain B = +7
Gain B = –8
……..
Gain B = –1
Gain A = 0
Gain A = +1
……
Gain A = +7
Gain A = –8
……
Gain A = –1
Gain B = 0
Gain B = +1
…….
Gain B = +7
Gain B = –8
……..
Gain B = –1
Gain A = 0
Gain A = +1
……
Gain A = +7
Gain A = –8
……
Gain A = –1
Gain B = 0
Gain B = +1
…….
Gain B = +7
Gain B = –8
……..
Gain B = –1
Threshold A
HD Adaptive Filter Gain 2
Value A
HD Adaptive Filter Gain 2
Value B
3Ah
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
00h
00h
00h
REV. B
ADV7330
SR7–
SR0
Register
Bit Description
3Eh
Reserved
3Fh
Reserved
40h
SD Mode Register 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
00h
00h
SD Standard
SD Luma Filter
SD Chroma Filter
41h
42h
0
0
NTSC
0
1
PAL B, D, G, H, I
1
0
PAL M
1
1
0
0
LPF NTSC
0
0
1
LPF PAL
0
1
0
Notch NTSC
0
1
1
Notch PAL
1
0
0
SSAF Luma
1
0
1
Luma CIF
1
1
0
Luma QCIF
1
1
1
Reserved
0
0
0
1.3 MHz
0
0
1
0.65 MHz
0
1
0
1.0 MHz
0
1
1
2.0 MHz
1
0
0
Reserved
1
0
1
Chroma CIF
1
1
0
Chroma QCIF
1
1
1
3.0 MHz
00h
SD PrPb SSAF
SD DAC Output 1
SD DAC Output 2
SD Pedestal
SD Square Pixel
SD VCR FF/RW Sync
SD Pixel Data Valid
SD SAV/EAV Step Edge Control
0
Disabled
1
Enabled
0
Refer to the Output Configuration
1
section
0
Refer to the Output Configuration
1
section
0
Disabled
1
Enabled
0
Disabled
1
Enabled
0
Disabled
1
Enabled
0
Disabled
1
Enabled
0
SD Mode Register 2
Enabled
SD Pedestal YPrPb Output
SD Output Levels Y
SD Output Levels PrPb
SD VBI Open
SD CC Field Control
Reserved
REV. B
08h
Disabled
1
43h
00h
PAL N
0
Reserved
SD Mode Register 1
Reset
Values
0
No Pedestal on YPrPb
1
7.5 IRE Pedestal on YPrPb
0
Y = 700 mV/300 mV
1
Y = 714 mV/286 mV
0
0
700 mV p-p (PAL); 1000 mV p-p (NTSC)
0
1
700 mV p-p
1
0
1000 mV p-p
1
1
648 mV p-p
0
Disabled
1
Enabled
0
0
CC Disabled
0
1
CC on Odd Field Only
1
0
CC on Even Field Only
1
1
CC on Both Fields
0
Reserved
–21–
00h
ADV7330
SR7–
SR0
Register
Bit Description
44h
SD Mode Register 3
SD VSYNC-3H
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
0
1
SD RTC/TR/SCR*
0
0
1
1
SD Active Video Length
0
1
SD Burst
0
1
SD Color Bars
0
1
0
1
45h
46h
47h
Reserved
Reserved
SD Mode Register 4
SD PrPb Scale
0
1
SD Y Scale
SD Mode Register 5
0
0
0
0
0
1
SD Input Format
0
1
Reserved
SD Digital Noise Reduction
0
0
1
SD Gamma Control
49h
SD Mode Register 6
0
1
0
1
SD Undershoot Limiter
0
0
1
1
Reserved
SD Black Burst Output on DAC Luma
0
0
1
SD Chroma Delay
Reserved
Reserved
0
1
0
1
0
1
Reserved
SD Double Buffering
SD Gamma Curve
0 must be written to this bit.
Disabled
Enabled
8-Bit Input
16-Bit Input
0 must be written to this bit.
Disabled
Enabled
Disabled
Enabled
Gamma Curve A
Gamma Curve B
Disabled
–11 IRE
–6 IRE
–1.5 IRE
0
1
SD Luma SSAF Gain
48h
0
0
1
SD Brightness
Reserved
Reserved
Reserved
Reserved
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
0 must be written to this bit.
0 must be written to this bit.
0 must be written to this bit.
0 must be written to this bit.
0
1
SD Hue Adjust
0
0
1
1
0
0
0
1
0
1
00h
Genlock Disabled
Subcarrier Reset
Timing Reset
RTC Enabled
720 Pixels
710 (NTSC)/702 (PAL)
Chroma Enabled
Chroma Disabled
Enabled
Disabled
Disabled
Enabled
DAC B = Luma
DAC C = Chroma
DAC B = Chroma
DAC C = Luma
0
1
SD Chroma
SD DAC Swap
0
1
0
1
Disabled
VSYNC = 2.5 Lines (PAL)
VSYNC = 3 Lines (NTSC)
Reset
Values
00h
00h
00h
00h
0 must be written to this bit.
Disabled
Enabled
Disabled
4 Clk Cycles
8 Clk Cycles
Reserved
0 must be written to this bit.
0 must be written to this bit.
*See Figure 23, RTC Timing and Connections.
–22–
REV. B
ADV7330
SR7–
SR0
Register
Bit Description
4Ah
SD Timing Register 0
SD Slave/Master Mode
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SD Timing Mode
SD BLANK Input
Register Setting
Reset Values
0
Slave Mode
08h
1
Master Mode
0
0
Mode 0
0
1
Mode 1
1
0
Mode 2
1
1
Mode 3
0
Enabled
1
SD Luma Delay
4Bh
SD Timing Register 1
SD Min. Luma Value
0
SD Timing Reset
1
0
x
Disabled
0
0
No Delay
0
1
2 Clk Cycles
1
0
4 Clk Cycles
1
1
6 Clk Cycles
– 40 IRE
0
0
0
0
SD HSYNC Width
SD HSYNC to VSYNC Delay
0
0
– 7.5 IRE
A low-high-low transition will reset the
internal SD timing counters.
0
0
TA = 1 Clk Cycle
0
1
TA = 4 Clk Cycles
1
0
TA = 16 Clk Cycles
1
1
TA = 128 Clk Cycles
0
0
TB = 0 Clk Cycle
0
1
TB = 4 Clk Cycles
1
0
TB = 8 Clk Cycles
1
1
TB = 18 Clk Cycles
SD HSYNC to VSYNC Rising
Edge Delay (Mode 1 Only)
x
0
TC = TB
x
1
TC = TB + 32 µs
VSYNC Width (Mode 2 Only)
0
0
1 Clk Cycle
0
1
4 Clk Cycles
1
0
16 Clk Cycles
1
1
128 Clk Cycles
HSYNC to Pixel Data Adjust
00h
0
0
0 Clk Cycles
0
1
1 Clk Cycle
1
0
2 Clk Cycles
1
1
3 Clk Cycles
4Ch
SD FSC Register 0
x
x
x
x
x
x
x
x
Subcarrier Frequency Bit 7–0
16h
4Dh
SD FSC Register 1
x
x
x
x
x
x
x
x
Subcarrier Frequency Bit 15–8
7Ch
4Eh
SD FSC Register 2
x
x
x
x
x
x
x
x
Subcarrier Frequency Bit 23–16
F0h
4Fh
SD FSC Register 3
x
x
x
x
x
x
x
x
Subcarrier Frequency Bit 31–24
21h
50h
SD FSC Phase
x
x
x
x
x
x
x
x
Subcarrier Phase Bit 9–2
00h
51h
SD Closed Captioning
Extended Data on Even Fields
x
x
x
x
x
x
x
x
Extended Data Bit 7–0
00h
52h
SD Closed Captioning
Extended Data on Even Fields
x
x
x
x
x
x
x
x
Extended Data Bit 15–8
00h
53h
SD Closed Captioning
Data on Odd Fields
x
x
x
x
x
x
x
x
Data Bit 7–0
00h
54h
SD Closed Captioning
Data on Odd Fields
x
x
x
x
x
x
x
x
00h
55h
SD Pedestal Register 0
Pedestal on Odd Fields
17
16
15
14
13
12
11
10
Data Bit 15–8
Setting any of these bits to 1
56h
SD Pedestal Register 1
Pedestal on Odd Fields
25
24
23
22
21
20
19
18
will disable pedestal on the
00h
57h
SD Pedestal Register 2
Pedestal on Even Fields
17
16
15
14
13
12
11
10
line number indicated by the
00h
58h
SD Pedestal Register 3
Pedestal on Even Fields
25
24
23
22
21
20
19
18
bit settings.
00h
LINE 1
HSYNC
LINE 313
tA
tC
tB
VSYNC
Figure 15. Timing Register 1 in PAL Mode
REV. B
–23–
LINE 314
00h
ADV7330
SR7– Register
SR0
59h
Bit Description
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
SD CGMS/WSS 0 SD CGMS Data
SD CGMS CRC
SD CGMS/WSS 1 SD CGMS/WSS Data
5Bh
5Ch
SD CGMS/WSS 2 SD CGMS/WSS Data
SD LSB Register SD LSB for Y Scale Value
SD LSB for U Scale Value
SD LSB for V Scale Value
SD LSB for FSC Phase
SD Y Scale
SD Y Scale Value
R
SD iV Scale
SD V Scale Value
R
SD iU Scale
SD U Scale Value
R
i
SD Hue Register SD Hue Adjust Value
SD Brightness/
SD Brightness Value
WSS
SD Blank WSS Data
5Dh
5Eh
5Fh
60h
61h
62h
SD Luma SSAF
SD Luma SSAF Gain/Attenuation
63h
SD DNR 0
Coring Gain Border
Coring Gain Data
64h
SD DNR 1
17
16
0
1
0
1
15
7
x
x
x
x
x
0
1
0
0
0
0
0
0
0
0
0
0
0
1
13
12
11
10
9
8
5
4
3
2
1
x
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
1
1
1
1
0
0
1
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
0
1
0
1
0
1
0
0
0
…
1
1
0
0
…
1
1
0
0
…
1
1
0
1
…
0
1
14
6
0
0
0
0
1
1
1
1
0
DNR Threshold
Border Area
Block Size Control
18
0
1
SD CGMS on Even Fields
5Ah
19
0
1
SD CGMS on Odd Fields
SD WSS
Bit 0 Register Setting
0
0
1
1
0
0
1
1
0
0
0
…
1
1
0
1
0
1
0
1
0
1
0
0
0
…
1
1
0
1
0
1
–24–
CGMS data bits C19-C16
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
CGMS Data Bits C13–C8 or
WSS Data Bits C13–C8
CGMS Data Bits C15–C14
CGMS/WSS Data Bits C7–C0
SD Y Scale Bit 1–0
SD U Scale Bit 1–0
SD V Scale Bit 1–0
Subcarrier Phase Bits 1–0
SD Y Scale Bit 7–2
SD V Scale Bit 7–2
SD U Scale Bit 7–2
SD Hue Adjust Bit 7–0
SD Brightness Bit 6–0
Disabled
Enabled
–4 dB
0 dB
4 dB
No Gain
+1/16 (–1/8)
+2/16 (–2/8)
+3/16 (–3/8)
+4/16 (–4/8)
+5/16 (–5/8)
+6/16 (–6/8)
+7/16 (–7/8)
+8/16 (–1)
No Gain
+1/16 (–1/8)
+2/16 (–2/8)
+3/16 (–3/8)
+4/16 (–4/8)
+5/16 (–5/8)
+6/16 (–6/8)
+7/16 (–7/8)
+8/16 (–1)
0
1
…
62
63
2 Pixels
4 Pixels
8 Pixels
16 Pixels
Reset Values
00h
00h
00h
00h
00h
00h
00h
00h
00h
Line 23
00h
00h
In DNR
modes the
values in the
parentheses apply.
00h
REV. B
ADV7330
SR7–
SR0
Register
Bit Description
65h
SD DNR 2
DNR Input Select
Bit
7
Bit
6
Bit
5
DNR Mode
DNR Block Offset
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7C
REV. B
SD Gamma A
SD Gamma A
SD Gamma A
SD Gamma A
SD Gamma A
SD Gamma A
SD Gamma A
SD Gamma A
SD Gamma A
SD Gamma A
SD Gamma B
SD Gamma B
SD Gamma B
SD Gamma B
SD Gamma B
SD Gamma B
SD Gamma B
SD Gamma B
SD Gamma B
SD Gamma B
SD Brightness Detect
Field Count Register
SD Gamma Curve A Data Points
SD Gamma Curve A Data Points
SD Gamma Curve A Data Points
SD Gamma Curve A Data Points
SD Gamma Curve A Data Points
SD Gamma Curve A Data Points
SD Gamma Curve A Data Points
SD Gamma Curve A Data Points
SD Gamma Curve A Data Points
SD Gamma Curve A Data Points
SD Gamma Curve B Data Points
SD Gamma Curve B Data Points
SD Gamma Curve B Data Points
SD Gamma Curve B Data Points
SD Gamma Curve B Data Points
SD Gamma Curve B Data Points
SD Gamma Curve B Data Points
SD Gamma Curve B Data Points
SD Gamma Curve B Data Points
SD Gamma Curve B Data Points
SD Brightness Value
Field Count
Reserved
Reserved
Reserved
Revision Code
0
0
…
1
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
…
1
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
…
1
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Bit
4
0
1
0
1
…
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Bit
3
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
x
x
Reserved
Bit
2
Bit
1
Bit
0
Register Setting
Reset
Values
0
0
0
1
0
1
1
0
1
0
1
0
00h
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Filter A
Filter B
Filter C
Filter D
DNR Mode
DNR Sharpness Mode
0 Pixel Offset
1 Pixel Offset
…
14 Pixel Offset
15 Pixel Offset
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
Read-Only
x
x
x
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Read-Only
0 must be written to this bit.
0 must be written to this bit.
0 must be written to this bit.
Read-Only
00h
–25–
ADV7330
SR7–
SR0
Register
7Dh
7Eh
7Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
Reserved
Reserved
Reserved
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Bit Description
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit Register Setting
0
Reset
Values
MV Control Bits
MV Control Bits
MV Control Bits
MV Control Bits
MV Control Bits
MV Control Bits
MV Control Bits
MV Control Bits
MV Control Bits
MV Control Bits
MV Control Bits
MV Control Bits
MV Control Bits
MV Control Bits
MV Control Bits
MV Control Bits
MV Control Bits
MV Control Bits
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
0
0
0
0
0
0
0
–26–
00h
00h
00h
00h
00h
00h
00h
0 must be written to these bits.
REV. B
ADV7330
INPUT CONFIGURATION
Progressive Scan at 27 MHz (Dual Edge) or 54 MHz
Address(01h): Input Mode 100 or 111, Respectively
Note that the ADV7330 defaults to progressive scan 54 MHz
mode on power-up. Address(01h): Input Mode = 011
Standard Definition
Address(01h): Input Mode = 000
The 8-bit multiplexed input data is input on Pins Y7–Y0, with Y0
being the LSB. Input standards supported are ITU-R BT.601/656.
In 16-bit input mode the Y pixel data is input on Pins Y7–Y0
and CrCb data on Pins C7–C0.
YCrCb progressive scan data can be input at 27 MHz or 54 MHz.
The input data is interleaved onto a single 8-bit bus and is input
on Pins Y7–Y0. When a 27 MHz clock is supplied, the data is
clocked in on the rising and falling edge of the input clock and
CLOCK EDGE [Address 01h, Bit 1] must be set accordingly.
The following figures show the possible conditions.
Input sync signals are optional and are input on the VSYNC_I/P,
HSYNC_I/P, and BLANK_I/P pins.
CLKIN
Y7–Y0
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
ADV7330
VSYNC_I/P
HSYNC_I/P
BLANK_I/P
3
MPEG2
DECODER
27MHz
Figure 18a. Cb Data on Rising Edge—Clock Edge
Address 01h Bit 1 Should be Set to 0
CLKIN
CLKIN
8
YCrCb
Y[7:0]
Y7–Y0
3FF
00
00
XY
Y0
Cb0
Y1
Cr0
Figure 16. SD Input Mode
Figure 18b. Y Data on Rising Edge—Clock Edge
Address 01h Bit 1 Should be Set to 1
Progressive Scan or HDTV Mode
Address(01h): Input Mode 001 or 010, Respectively
YCrCb progressive scan, HDTV, or any other HD YCrCb data
can be input in 4:2:2. In 4:2:2 input mode, the Y data is input
on Pins Y7–Y0 and the CrCb data on Pins C7–C0.
With a 54 MHz clock, the data is latched on every rising edge.
CLKIN
If the YCrCb data does not conform to SMPTE 293M (525p),
ITU-R BT.1358M (625p), SMPTE 274M (1080i), SMPTE
296M (720p), or BTA T-1004/1362, the async timing mode
must be used.
PIXEL INPUT
DATA
YCrCb
CbCr
8
Y
8
3
XY
CLKIN
Cb0
Y0
Cr0
27MHz OR 54MHz
ADV7330
CLKIN
C[7:0]
YCrCb 8
Y[7:0]
INTERLACED
TO
PROGRESSIVE
VSYNC_I/P
HSYNC_I/P
BLANK_I/P
Figure 17. Progressive Scan Input Mode
REV. B
00
MPEG2
DECODER
ADV7330
YCrCb
INTERLACED
TO
PROGRESSIVE
00
Y1
Figure 18c. Input Sequence in PS Bit Interleaved
Mode (EAV/SAV)
MPEG2
DECODER
27MHz
3FF
3
Y[7:0]
VSYNC_I/P
HSYNC_I/P
BLANK_I/P
Figure 19. 1 8-Bit PS at 27 MHz or 54 MHz
–27–
ADV7330
Table I provides an overview of possible input configurations.
Table I. Input Configurations
Input
Format
Total Bits
ITU-R
BT.656
PS
HDTV
Input
Video
Input
Pins
Subaddress
Register
Setting
01h
48h
01h
48h
00h
00h
00h
08h
40h
40h
30h
40h
10h
40h
20h
40h
8
4:2:2
YCrCb
Y7–Y0
16
4:2:2
Y
YCrCb
Y7–Y0
C7–C0
8 (27 MHz clock)
4:2:2
YCrCb
Y7–Y0
8 (54 MHz clock)
4:2:2
YCrCb
Y7–Y0
16
4:2:2
Y
CrCb
Y7–Y0
C7–C0
10h
13h
10h
13h
01h
13h
16
4:2:2
Y
CrCb
Y7–Y0
C7–C0
01h
13h
OUTPUT CONFIGURATION
Tables II and III show which output signals are assigned to the DACs when according control bits are set.
Table II. Output Configuration in SD Mode
RGB/YPrPb Output SD DAC Output 1
02h, Bit 5
42h, Bit 2
SD DAC Output 1 SD DAC Swap
42h, Bit 1
44h, Bit 7
DAC A
DAC B
DAC C
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
G
G
CVBS
CVBS
CVBS
CVBS
G
G
Y
Y
CVBS
CVBS
CVBS
CVBS
Y
Y
B
B
Luma
Chroma
B
B
Luma
Chroma
Pb
Pb
Luma
Chroma
Pb
Pb
Luma
Chroma
R
R
Chroma
Luma
R
R
Chroma
Luma
Pr
Pr
Chroma
Luma
Pr
Pr
Chroma
Luma
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Table III. Output Configuration in HD/PS Mode
HD Input
Format
RGB/YPrPb Output HD Color Swap
02h, Bit 5
15h, Bit 3
DAC A DAC B DAC C
YCrCb 4:2:2
YCrCb 4:2:2
YCrCb 4:2:2
YCrCb 4:2:2
1
1
0
0
0
1
0
1
–28–
Y
Y
G
G
Pb
Pr
B
R
Pr
Pb
R
B
REV. B
ADV7330
TIMING MODES
HD Async Timing Mode
[Subaddress 10h, Bit 3,2]
For any input data that does not conform to the standards selectable in input mode, Subaddress 10h, asynchronous timing mode
can be used to interface to the ADV7330. Timing control signals
for Hsync, Vsync, and Blank have to be programmed by the user.
Macrovision and programmable oversampling rates are not available in async timing mode. In async mode, the PLL must be
turned off [Subaddress 01h, Bit 1 = 1].
Figures 20a and 20b show an example of how to program
the ADV7330 to accept a different high definition standard
other than SMPTE 293M, SMPTE 274M, SMPTE 296M, or
ITU-R BT.1358.
The following truth table must be followed when programming
the control signals in async timing mode.
For standards that do not require a tri-sync level, BLANK_I/P
must be tied low at all times.
CLK
HSYNC_I/P
VSYNC_I/P
PROGRAMMABLE
INPUT TIMING
BLANK_I/P
SET ADDRESS 10h,
BIT 6 TO 1
ACTIVE VIDEO
HORIZONTAL SYNC
ANALOG
OUTPUT
81
66
a
66
b
243
c
1920
e
d
Figure 20a. Async Timing Mode—Programming Input Control Signals for SMPTE 295M Compatibility
CLK
HSYNC_I/P
VSYNC_I/P
0
BLANK_I/P
SET ADDRESS 10h,
BIT 6 TO 1
1
ACTIVE VIDEO
HORIZONTAL SYNC
ANALOG OUTPUT
a
b
c
d
Figure 20b. Async Timing Mode—Programming Input Control Signals for Bilevel Sync Signals
REV. B
–29–
e
ADV7330
Table IV. Async Timing Mode Truth Table
HSYNC_I/P
VSYNC_I/P
BLANK_I/P*
1→0
0
0→1
1
1
0
0→1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0
0→1
1→0
Reference in
Figures 20a and 20b
50% point of falling edge of tri-level horizontal sync signal
25% point of rising edge of tri-level horizontal sync signal
50% point of falling edge of tri-level horizontal sync signal
50% start of active video
50% end of active video
a
b
c
d
e
*When async timing mode is enabled, BLANK_I/P (Pin 25) becomes an active high input.
BLANK_I/P is set to active low at Address 10h, Bit 6.
HD Timing Reset
[Address 14h, Bit 0]
A timing reset is achieved in setting the HD timing reset control
bit at Address 14h from 0 to 1. In this state, the horizontal and
vertical counters will remain reset. When this bit is set back to
0, the internal counters will commence counting again. PLL must
be powered off by this mode.
The minimum time the pin has to be held high is one clock cycle,
otherwise this reset signal might not be recognized. This timing
reset applies to the HD timing counters only.
–30–
REV. B
ADV7330
SD Real-Time Control, Subcarrier Reset, Timing Reset
[Subaddress 44h, Bit 2,1]
This reset signal will have to be held high for a minimum of one
clock cycle.
Together with the RTC_SCR_TR pin and SD Mode Register 3
[Address 44h, Bit 1,2], the ADV7330 can be used in timing
reset mode, subcarrier phase reset mode, or RTC mode.
Since the field counter is not reset, it is recommended that the
reset signal be applied in Field 7 [PAL] or Field 3 [NTSC]. The
reset of the phase will then occur on the next field, i.e., Field 1
being lined up correctly with the internal counters. The field count
register at Address 7Bh can be used to identify the number of
the active field.
A timing reset is achieved in a low-to-high transition on the
RTC_SCR_TR pin (Pin 31). In this state, the horizontal and
vertical counters will remain reset. On releasing this pin (set
to low), the internal counters will commence counting again,
the field count will start on Field 1, and the subcarrier phase
will also be reset.
In RTC mode, the ADV7330 can be used to lock to an external
video source. The real-time control mode allows the ADV7330
to automatically alter the subcarrier frequency to compensate for
line length variations. When the part is connected to a device that
outputs a digital data stream in the RTC format (such as an
ADV7183A video decoder, see Figure 23), the part will automatically change to the compensated subcarrier frequency on a
line by line basis. This digital data stream is 67 bits wide and the
subcarrier is contained in Bits 0 to 21. Each bit is two clock cycles
long. 00h should be written into all four subcarrier frequency
registers when this mode is used.
The minimum time the pin has to be held high is one clock cycle;
otherwise, this reset signal might not be recognized. This timing
reset applies to the SD timing counters only.
In subcarrier phase reset, a low-to-high transition on the
RTC_SCR_TR pin (Pin 31) will reset the subcarrier phase to
zero on the field following the subcarrier phase reset when the
SD RTC/TR/SCR control bits at Address 44h are set to 01.
DISPLAY
307
START OF FIELD 4 OR 8
310
FSC PHASE = FIELD 4 OR 8
313
320
NO TIMING RESET APPLIED
DISPLAY
START OF FIELD 1
307
1
2
3
4
FSC PHASE = FIELD 1
5
6
7
21
TIMING RESET PULSE
TIMING RESET APPLIED
Figure 21. Timing Reset Timing Diagram
DISPLAY
307
310
START OF FIELD 4 OR 8
FSC PHASE = FIELD 4 OR 8
313
320
NO FSC RESET APPLIED
DISPLAY
307
310
START OF FIELD 4 OR 8
313
FSC PHASE = FIELD 1
320
FSC RESET PULSE
FSC RESET APPLIED
Figure 22. Subcarrier Reset Timing Diagram
REV. B
–31–
ADV7330
Reset Sequence
A reset is activated with a high-to-low transition on the RESET pin
(Pin 33) according to the Timing Specifications. The ADV7330
will revert to the default output configuration.
Figure 24 illustrates the RESET sequence timing.
SD VCR FF/RW Sync
[Subaddress 42h, Bit 5]
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW sync control bit can be used for
nonstandard input video, i.e., in fast forward or rewind modes.
In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct
number of lines/fields are reached. In rewind mode, this sync
signal usually occurs after the total number of lines/fields are
reached. Conventionally this means that the output video will
have corrupted field signals, one generated by the incoming video
and one generated when the internal lines/field counters reach
the end of a field.
When the VCR FF/RW sync control is enabled [Subaddress 42h,
Bit 5], the lines/field counters are updated according to the
incoming vsync signal, and the analog output matches the incoming
vsync signal.
This control is available in all slave timing modes except
Slave Mode 0.
ADV7330
CLKIN
DAC A
LCC1
COMPOSITE VIDEO
e.g., VCR OR CABLE
RTC_SCR_TR
GLL
ADV7183A
DAC B
DAC C
VIDEO
P17–P10
DECODER
Y7–Y0
14 BITS
4 BITS
H/L TRANSITION
SUBCARRIER RESERVED
COUNT START
PHASE
LOW
128
13
0
21
SEQUENCE
BIT2
FSC PLL INCREMENT1
RESET
BIT3
RESERVED
0
RTC
TIME SLOT: 01
14
6768
19
VALID INVALID
SAMPLE SAMPLE
8/LINE
LOCKED
CLOCK
5 BITS
RESERVED
NOTES
1F
SC PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7330, FSC DSS REGISTER IS FSC PLL INCREMENTS BITS 21:0 PLUS
BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY
REGISTERS OF THE ADV7330.
2SEQUENCE BIT.
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED.
NTSC: 0 = NO CHANGE.
3RESET BIT. RESET ADV7330 DSS.
Figure 23. RTC Timing and Connections
RESET
DACs
A, B, C
XXXXXX
DIGITAL TIMING
XXXXXX
OFF
DIGITAL TIMING SIGNALS SUPPRESSED
VALID VIDEO
TIMING ACTIVE
PIXEL DATA
VALID
Figure 24. RESET Timing Sequence
–32–
REV. B
ADV7330
Vertical Blanking Interval
SD Subcarrier Frequency Registers
[Subaddress 4Ch–4Fh]
The ADV7330 accepts input data that contains VBI data (such
as CGMS, WSS, VITS) in SD and HD modes.
Four 8-bit wide registers are used to set up the subcarrier
frequency. The value of these registers is calculated using the
following equation:
For SMPTE 293M (525p) standards, VBI data can be inserted
on Lines 13 to 42 of each frame, or Lines 6 to 43 for the
ITU-R BT.1358 [625p] standard.
Subcarrier Frequency Register =
For SD NTSC, this data can be present on Lines 10 to 20; in PAL,
on Lines 7 to 22.
For example, NTSC mode,
If VBI is disabled [Address 11h, Bit 4 for HD; Address 43h,
Bit 4 for SD], VBI data is not present at the output and the entire
VBI is blanked. These control bits are valid in all master and
slave modes.
In Slave Mode 0, if VBI is enabled, the blanking bit in the
EAV/SAV code is overwritten; it is possible to use VBI in this
timing mode as well.
In Slave Mode 1 or 2, the BLANK control bit must be set to
enabled [Address 4Ah, Bit 3] to allow VBI data to pass through
the ADV7330; otherwise, the ADV7330 automatically blanks
the VBI to standard.
If CGMS is enabled and VBI disabled, the CGMS data will
nevertheless be available at the output.
# Subcarrier FrequencyValue in one video line
× 232
#27 MHz clk cycles in one video line
 227.5 
32
Subcarrier FrequencyValue = 
 × 2 = 569408542
 1716 
Subcarrier Register Value = 21F07C1Eh
SD FSC Register 0: 1Eh
SD FSC Register 1: 7Ch
SD FSC Register 2: F0h
SD FSC Register 3: 21h
Refer to the MPU Port Description section for details on how to
access the subcarrier frequency registers.
Square Pixel Timing
[Register 42h, Bit 4]
In square pixel mode, the timing diagrams in Figures 25 and
26 apply.
ANALOG
VIDEO
EAV CODE
INPUT PIXELS
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
PAL SYSTEM
(625 LINES/50Hz)
C
F 0 0 X 8 1 8 1
Y
Y
r
F 0 0 Y 0 0 0 0
4 CLOCK
SAV CODE
0 F F A A A
0 F F B B B
C
C
8 1 8 1 F 0 0 X C Y C Y C
Y r Y b
b
0 0 0 0 F 0 0 Y b
r
ANCILLARY DATA
(HANC)
4 CLOCK
272 CLOCK
1280 CLOCK
4 CLOCK
4 CLOCK
344 CLOCK
1536 CLOCK
START OF ACTIVE
VIDEO LINE
END OF ACTIVE
VIDEO LINE
Figure 25. EAV/SAV Embedded Timing
HSYNC
FIELD
PAL = 44 CLOCK CYCLES
NTSC = 44 CLOCK CYCLES
BLANK
PIXEL
DATA
Cb
PAL = 136 CLOCK CYCLES
NTSC = 208 CLOCK CYCLES
Figure 26. Active Pixel Timing
REV. B
–33–
Y
Cr
Y
ADV7330
FILTER SECTION
HD Sinc Filter
Table V shows an overview of the programmable filters available
on the ADV7330.
0.5
0.4
Table V. Selectable Filters of the ADV7330
0.3
Subaddress
0.2
SD Luma LPF NTSC
SD Luma LPF PAL
SD Luma Notch NTSC
SD Luma Notch PAL
SD Luma SSAF
SD Luma CIF
SD Luma QCIF
SD Chroma 0.65 MHz
SD Chroma 1.0 MHz
SD Chroma 1.3 MHz
SD Chroma 2.0 MHz
SD Chroma 3.0 MHz
SD Chroma CIF
SD Chroma QCIF
SD UV SSAF
HD Chroma Input
HD Sinc Filter
HD Chroma SSAF
40h
40h
40h
40h
40h
40h
40h
40h
40h
40h
40h
40h
40h
40h
42h
13h
13h
13h
0.1
GAIN (dB)
Filter
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
5
10
15
20
FREQUENCY (MHz)
25
30
Filter 27. HD Sinc Filter Enabled
0.5
0.4
0.3
GAIN (dB)
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
5
10
15
20
FREQUENCY (MHz)
25
30
Figure 28. HD Sinc Filter Disabled
–34–
REV. B
ADV7330
SD Internal Filter Response
[Subaddress 40h; Subaddress 42, Bit 0]
Table VI. Internal Filter Specifications
The Y filter supports several different frequency responses including two low-pass responses, two notch responses, an extended
(SSAF) response with or without gain boost/attenuation, a CIF
response, and a QCIF response. The UV filter supports several
different frequency responses including six low-pass responses,
a CIF response, and a QCIF response, as can be seen in the
typical performance characteristics graphs on the following pages.
If SD SSAF gain is enabled, there is the option of 12 responses in
the range of –4 dB to +4 dB [Subaddress 47, Bit 4]. The desired
response can be chosen by the user by programming the correct
value via the I2C [Subaddress 62h]. The variation of frequency
responses can be seen in the typical performance characteristics
graphs on the following pages.
In addition to the chroma filters listed in Table VI, the ADV7330
contains an SSAF filter specifically designed for and applicable
to the color difference component outputs, U and V.
This filter has a cutoff frequency of about 2.7 MHz and –40 dB
at 3.8 MHz, as can be seen in Figure 29. This filter can be
controlled with Address 42h, Bit 0.
If this filter is disabled, the selectable chroma filters shown in
Table VI can be used for the CVBS or chroma signal.
Filter
Pass-Band Ripple 3 dB Bandwidth
(dB)1
(MHz)2
Luma LPF NTSC
Luma LPF PAL
Luma Notch NTSC
Luma Notch PAL
Luma SSAF
Luma CIF
Luma QCIF
Chroma 0.65 MHz
Chroma 1.0 MHz
Chroma 1.3 MHz
Chroma 2.0 MHz
Chroma 3.0 MHz
Chroma CIF
Chroma QCIF
0.16
0.1
0.09
0.1
0.04
0.127
Monotonic
Monotonic
Monotonic
0.09
0.048
Monotonic
Monotonic
Monotonic
4.24
4.81
2.3/4.9/6.6
3.1/5.6/6.4
6.45
3.02
1.5
0.65
1
1.395
2.2
3.2
0.65
0.5
NOTES
1
Pass-band ripple refers to the maximum fluctuations from the 0 dB response in
the pass band, measured in (dB). The pass band is defined to have 0 (Hz) to
fc (Hz) frequency limits for a low-pass filter, 0 (Hz) to f1 (Hz) and f2 (Hz) to
infinity for a notch filter, where fc, f1, f2 are the –3 dB points.
2
3 dB bandwidth refers to the –3 dB cutoff frequency.
EXTENDED UV FILTER MODE
0
GAIN (dB)
–10
–20
–30
–40
–50
–60
0
1
2
3
4
5
FREQUENCY (MHz)
Figure 29. UV SSAF Filter
REV. B
–35–
6
ADV7330–Typical Performance Characteristics
PROG SCAN Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4
Y PASS BAND IN PS OVERSAMPLING MODE
1.0
0
0.5
–10
0
–0.5
–30
GAIN (dB)
GAIN (dB)
–20
–40
–1.0
–1.5
–50
–60
–2.0
–70
–2.5
–80
0
20
40
60
80 100 120 140
FREQUENCY (MHz)
160
180
–3.0
200
TPC 1. PS—UV (8 × Oversampling Filter (Linear))
0
2
–10
–10
–20
–20
–30
–30
–40
–50
–60
–60
–70
–70
40
60
80 100 120 140
FREQUENCY (MHz)
160
180
–80
200
TPC 2. PS—UV (8 × Oversampling Filter (SSAF))
0
20
–10
–10
–20
–20
–30
–30
–40
–50
–60
–60
–70
–70
40
60
80 100 120 140
FREQUENCY (MHz)
160
120
140
–40
–50
20
60
80
100
FREQUENCY (MHz)
Y RESPONSE IN HDTV OVERSAMPLING MODE
0
GAIN (dB)
GAIN (dB)
Y RESPONSE IN PS OVERSAMPLING MODE
0
40
TPC 5. HDTV—UV (2 × Oversampling Filter)
0
–80
12
–40
–50
20
10
Pr/Pb RESPONSE IN HDTV OVERSAMPLING MODE
0
GAIN (dB)
GAIN (dB)
PROG SCAN Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4
0
6
8
FREQUENCY (MHz)
TPC 4. PS—Y (8 × Oversampling Filter (Pass Band))
0
–80
4
180
–80
200
TPC 3. PS—Y (8 × Oversampling Filter)
0
20
40
60
80
100
FREQUENCY (MHz)
120
140
TPC 6. HDTV—Y (2 × Oversampling Filter)
–36–
REV. B
0
0
–10
–10
–20
–20
MAGNITUDE (dB)
MAGNITUDE (dB)
ADV7330
–30
–40
–30
–40
–50
–50
–60
–60
–70
–70
0
2
4
6
8
FREQUENCY (MHz)
10
12
0
TPC 7. Luma NTSC Low-Pass Filter
2
4
6
8
FREQUENCY (MHz)
10
12
TPC 10. Luma PAL Notch Filter
0
–10
–10
–20
–20
GAIN (dB)
MAGNITUDE (dB)
Y RESPONSE IN SD OVERSAMPLING MODE
0
–30
–40
–30
–40
–50
–50
–60
–60
–70
–70
0
2
4
6
8
FREQUENCY (MHz)
10
–80
12
0
0
0
–10
–10
–20
–20
MAGNITUDE (dB)
MAGNITUDE (dB)
40
60
80 100 120 140
FREQUENCY (MHz)
160
180
200
TPC 11. Y-16 × Oversampling Filter
TPC 8. Luma PAL Low-Pass Filter
–30
–40
–30
–40
–50
–50
–60
–60
–70
–70
0
2
4
6
8
FREQUENCY (MHz)
10
12
0
TPC 9. Luma NTSC Notch Filter
REV. B
20
2
4
6
8
FREQUENCY (MHz)
10
TPC 12. Luma SSAF Filter up to 12 MHz
–37–
12
ADV7330
4
0
2
–10
MAGNITUDE (dB)
MAGNITUDE (dB)
0
–2
–4
–6
–20
–30
–40
–50
–8
–60
–10
–70
–12
0
1
2
3
4
5
6
0
7
2
4
6
8
10
12
10
12
10
12
FREQUENCY (MHz)
FREQUENCY (MHz)
TPC 13. Luma SSAF Filter—Programmable Responses
TPC 16. Luma CIF LP Filter
5
4
–10
3
–20
MAGNITUDE (dB)
MAGNITUDE (dB)
0
2
1
–30
–40
–50
0
–60
–70
–1
0
1
2
3
4
5
6
0
7
2
4
6
8
FREQUENCY (MHz)
FREQUENCY (MHz)
TPC 14. Luma SSAF Filter—Programmable Gain
TPC 17. Luma QCIF LP Filter
1
0
–10
–1
–20
MAGNITUDE (dB)
MAGNITUDE (dB)
0
–2
–3
–30
–40
–50
–4
–60
–70
–5
0
1
2
3
4
5
6
0
7
FREQUENCY (MHz)
2
4
6
8
FREQUENCY (MHz)
TPC 15. Luma SSAF Filter—Programmable Attenuation
TPC 18. Chroma 3.0 MHz LP Filter
–38–
REV. B
0
0
–10
–10
–20
–20
MAGNITUDE (dB)
MAGNITUDE (dB)
ADV7330
–30
–40
–30
–40
–50
–50
–60
–60
–70
–70
0
2
4
6
8
10
12
0
2
4
FREQUENCY (MHz)
0
0
–10
–10
–20
–20
–30
–40
10
12
–30
–40
–50
–50
–60
–60
–70
–70
0
2
4
6
8
10
12
0
2
4
FREQUENCY (MHz)
6
8
10
12
10
12
FREQUENCY (MHz)
TPC 20. Chroma 1.3 MHz LP Filter
TPC 23. Chroma CIF LP Filter
0
0
–10
–10
–20
–20
MAGNITUDE (dB)
MAGNITUDE (dB)
8
TPC 22. Chroma 0.65 MHz LP Filter
MAGNITUDE (dB)
MAGNITUDE (dB)
TPC 19. Chroma 2.0 MHz LP Filter
–30
–40
–30
–40
–50
–50
–60
–60
–70
–70
0
2
4
6
8
10
12
0
FREQUENCY (MHz)
2
4
6
8
FREQUENCY (MHz)
TPC 21. Chroma 1.0 MHz LP Filter
REV. B
6
FREQUENCY (MHz)
TPC 24. Chroma QCIF LP Filter
–39–
ADV7330
COLOR CONTROLS AND RGB MATRIX
Programming the RGB Matrix
HD Y Level, Cr Level, Cb Level
[Subaddress 16h–18h]
The RGB matrix should be enabled [Address 02h, Bit 3], the
output should be set to RGB [Address 02h, Bit 5], Sync on PrPb
should be disabled [Address 15h, Bit 2], and Sync on RGB is
optional [Address 02h, Bit 4].
Three 8-bit wide registers at Addresses 16h, 17h, 18h are used to
program the output color of the internal HD test pattern generator, whether it is the lines of the cross hatch pattern or the uniform
field test pattern. They are not functional as color controls on
external pixel data input. For this purpose, the RGB matrix is used.
The standard used for the values for Y and the color difference
signals to obtain white, black, and the saturated primary and
complementary colors conforms to the ITU-R BT.601-4 standard.
Table VII shows sample color values to be programmed into the
color registers when output standard selection is set to EIA 770.2.
Table VII. Sample Color Values for EIA770.2 Output
Standard Selection
Sample
Color
Y Value
CR Value
CB Value
White
Black
Red
Green
Blue
Yellow
Cyan
Magenta
235 (EB)
16 (10)
81 (51)
145 (91)
41 (29)
210 (D2)
170 (AA)
106 (6A)
128 (80)
128(80)
240 (F0)
34 (22)
110 (6E)
146 (92)
16 (10)
222 (DE)
128 (80)
128 (80)
90 (5A)
54 (36)
240 (F0)
16 (10)
166 (A6)
202 (CA)
GY at addresses 03h and 05h controls the output levels on the
green signal, BU at 04h and 08h the blue signal output levels, and
RV at 04h and 09h the red output levels. To control YPrPb output
levels, YPrPb output should be enabled [Address 02h, Bit 5].
In this case, GY [Address 05h; Address 03, Bit 0–1] is used for
the Y output, RV [Address 09h; Address 04, Bit 0–1] is used for
the Pr output, and BU [Address 08h; Address 04h, Bit 2–3] is
used for the Pb output.
If RGB output is selected, the RGB matrix scaler uses the
following equations:
G = GY × Y + GU × Pb + GV × Pr
B = GY × Y + BU × Pb
R = GY × Y + RV × Pr
If YPrPb output is selected, the following equations are used:
Y = GY × Y
U = BU × Pb
V = RV × Pr
On power-up, the RGB matrix is programmed with default values.
Table VIII. RGB Matrix Default Values
HD RGB Matrix
[Subaddress 03h–09h]
When the programmable RGB matrix is disabled [Address 02h,
Bit 3], the internal RGB matrix takes care of all YCrCb to YPrPb
or RGB scaling according to the input standard programmed
into the device.
When the programmable RGB matrix is enabled, the color
components are converted according to the 1080i standard
[SMPTE 274M]:
Y ' = 0.2126 R' + 0.7152 G' + 0.0722 B'
CB' = [ 0.5 / (1 − 0.0722 )] ( B' −Y ' )
CR' = [ 0.5 / (1 − 0.2126 )] ( R' −Y ' )
This is reflected in the preprogrammed values for GY = 138Bh,
GU = 93h, GV = 3B, BU = 248h, RV = 1F0.
If another input standard is used, the scale values for GY, GU,
GV, BU, and RV have to be adjusted according to this input
standard. The user must consider that the color component conversion might use different scale values. For example, SMPTE
293M uses the following conversion:
Y ' = 0.299 R' + 0.587 G' + 0.114 B'
CB' = [ 0.5 / (1 − 0.114 )] ( B' −Y ' )
CR' = [ 0.5 / (1 − 0.299 )] ( R' −Y ' )
The programmable RGB matrix can be used to control the HD
output levels in cases where the video output does not confirm
to standards due to altering the DAC output stages such as
termination resistors. The programmable RGB matrix is used
for external HD data and is not functional when the HD test
pattern is enabled.
Address
Default
03h
04h
05h
06h
07h
08h
09h
03h
F0h
4Eh
0Eh
24h
92h
7Ch
When the programmable RGB matrix is not enabled, the
ADV7330 automatically scales YCrCb inputs to all standards
supported by this part.
SD Luma and Color Control
[Subaddresses 5Ch, 5Dh, 5Eh, 5Fh]
SD Y SCALE, SD Cr SCALE, and SD Cb SCALE are 10-bit
wide control registers to scale the Y, U, and V output levels.
Each of these registers represents the value required to scale the
U or V level from 0.0 to 2.0, and the Y level from 0.0 to 1.5 of
its initial level. The value of these 10 bits is calculated using the
following equation:
Y , U , or V Scalar Value = Scale Factor × 512
For example:
Scale factor = 1.18
Y, U, or V Scalar Value = 1.18 × 512 = 665.6
Y, U, or V Scalar Value = 665 (rounded to the nearest integer)
Y, U, or V Scalar Value = 1010 0110 01b
Address 5Ch, SD LSB Register = 15h
Address 5Dh, SD Y Scale Register = A6h
Address 5Eh, SD V Scale Register = A6h
Address 5Fh, SD U Scale Register = A6h
–40–
REV. B
ADV7330
Standard: PAL.
To add –7 IRE brightness level, write 72h to Address 61h,
SD brightness.
SD Hue Adjust Value
[Subaddress 60h]
The hue adjust value is used to adjust the hue on the composite
and chroma outputs.
These eight bits represent the value required to vary the hue of
the video data, i.e., the variance in phase of the subcarrier during
active video with respect to the phase of the subcarrier during
the colorburst. The ADV7330 provides a range of ± 22.5° increments of 0.17578125°. For normal operation (zero adjustment),
this register is set to 80h. FFh and 00h represent the upper and
lower limits (respectively) of adjustment attainable.
(Hue Adjust) [°] = 0.17578125° × (HCRd–128), for positive
hue adjust value.
For example, to adjust the hue by +4°, write 97h to the hue
adjust value register:
4



 + 128 = 105d* = 97h
 0.17578125 
[ IREValue × 2.015631] =
[7 × 2.015631] = [14.109417] = 0001110b
[0001110]into twos complement = [1110010]B = 72h
Table IX. Brightness Control Values*
Setup
Level in
NTSC with
Pedestal
Setup
Level in
NTSC No
Pedestal
Setup
Level in
PAL
SD
Brightness
22.5 IRE
15 IRE
7.5 IRE
0 IRE
15 IRE
7.5 IRE
0 IRE
–7.5 IRE
15 IRE
7.5 IRE
0 IRE
–7.5 IRE
1Eh
0Fh
00h
71h
*rounded to the nearest integer
*Values in the range of 3Fh to 44h might result in an invalid output signal.
To adjust the hue by –4°, write 69h to the hue adjust value
register:
SD Brightness Detect
[Subaddress 7Ah]
The ADV7330 allows monitoring of the brightness level of the
incoming video data. Brightness detect is a read-only register.
−4



 + 128 = 105d* = 69h
 0.17578125 
Double Buffering
[Subaddress 13h, Bit 7; Subaddress 48h, Bit 2]
*rounded to the nearest integer
SD Brightness Control
[Subaddress 61h]
The brightness is controlled by adding a programmable setup
level onto the scaled Y data. This brightness level may be added
onto the scaled Y data. For NTSC with pedestal, the setup can
vary from 0 IRE to 22.5 IRE. For NTSC without pedestal and
PAL, the setup can vary from –7.5 IRE to +15 IRE.
The brightness control register is an 8-bit wide register. Seven
bits of this 8-bit register are used to control the brightness level.
This brightness level can be a positive or negative value.
For example:
Standard: NTSC with pedestal.
To add +20 IRE brightness level, write 28h to Address 61h, SD
brightness.
Double-buffered registers are updated once per field on the
falling edge of the VSYNC signal. Double buffering improves
the overall performance since modifications to register settings
will not be made during active video, but take effect on the start
of the active video.
Double buffering can be activated on the following HD registers:
HD Gamma A and Gamma B curves, and HD CGMS registers.
Double buffering can be activated on the following SD registers:
SD Gamma A and Gamma B curves, SD Y scale, SD U scale,
SD V scale, SD brightness, SD closed captioning, and
SD Macrovision Bits 5–0.
[SD BrightnessValue] H =
[ IREValue × 2.015631]H =
[20 × 2.015631]H = [ 40.31262 ]H = 28 H
NTSC WITHOUT PEDESTAL
+7.5 IRE
100 IRE
0 IRE
–7.5 IRE
NO SETUP
VALUE ADDED
POSITIVE SETUP
VALUE ADDED
NEGATIVE SETUP
VALUE ADDED
Figure 30. Examples of Brightness Control Values
REV. B
–41–
ADV7330
PROGRAMMABLE DAC GAIN CONTROL
DACs A, B, and C are controlled by Reg 0B. The I2C control
registers will adjust the output signal gain up or down from its
absolute level.
CASE A
700mV
GAIN PROGRAMMED IN DAC OUTPUT LEVEL
REGISTERS, SUBADDRESS 0Ah, 0Bh
In Case B, the video output signal is reduced. The absolute level
of the sync tip and blanking level both decrease with respect to
the reference video output signal. The overall gain of the signal is
reduced from the reference signal.
The range of this feature is specified for ± 7.5% of the nominal
output from the DACs. For example, if the output current of
the DAC is 4.33 mA, the DAC tune feature can change this
output current from 4.008 mA (–7.5%) to 4.658 mA (+7.5%).
The reset value of the vid_out_ctrl registers is 00h → nominal
DAC output current. Table X is an example of how the output
current of the DACs varies for a nominal 4.33 mA output current.
Table X.
300mV
CASE B
700mV
NEGATIVE GAIN PROGRAMMED IN
DAC OUTPUT LEVEL REGISTERS,
SUBADDRESS 0Ah, 0Bh
300mV
Figure 31. Programmable DAC Gain—Positive
and Negative Gain
Register 0Ah or 0Bh
DAC
Current
(mA)
% Gain
0100 0000 (40h)
0011 1111 (3Fh)
0011 1110 (3Eh)
...
...
0000 0010 (02h)
0000 0001 (01h)
0000 0000 (00h)
4.658
4.653
4.648
...
...
4.43
4.38
4.33
7.5000
7.3820
7.3640
...
...
0.0360
0.0180
0.0000
1111 1111 (FFh)
1111 1110 (FEh)
...
...
1100 0010 (C2h)
1100 0001 (C1h)
1100 0000 (C0h)
4.25
4.23
...
...
4.018
4.013
4.008
–0.0180
–0.0360
...
...
–7.3640
–7.3820
–7.5000
(I2C Reset Value,
Nominal)
In Case A, the video output signal is gained. The absolute level
of the sync tip and blanking level both increase with respect to
the reference video output signal. The overall gain of the signal
is increased from the reference signal.
–42–
REV. B
ADV7330
For the length of 16 to 240, the gamma correction curve has to
be calculated as follows:
Gamma Correction
[Subaddress 24h–37h for HD, Subaddress 66h–79h for SD]
Gamma correction is available for SD and HD video. For each
standard there are 20 8-bit wide registers. They are used to
program the gamma correction curves A and B. HD gamma
curve A is programmed at Addresses 24h–2Dh, HD gamma
curve B at 2Eh–37h. SD gamma curve A is programmed at
Addresses 66h–6Fh, SD gamma curve B at Addresses 70h–79h.
y=x
where:
y = gamma corrected output
x = linear input signal
= gamma power factor
Generally, gamma correction is applied to compensate for the
nonlinear relationship between signal input and brightness level
output (as perceived on the CRT). It can also be applied
wherever nonlinear processing is used.
To program the gamma correction registers, the seven values for
y have to be calculated using the following formula:
 x (n −16 ) 
yn = 
 × (240 − 16) + 16
 (240 − 16) 
Gamma correction uses the function
(
SignalOUT = Signal IN
)
where:
where = gamma power factor.
x(n–16) = Value for x along x-axis at points
Gamma correction is performed on the luma data only. The user
has the choice to use two different curves, curve A or curve B.
At any one time, only one of these curves can be used. The
response of the curve is programmed at 10 predefined locations.
In changing the values at these locations, the gamma curve can
be modified. Between these points, linear interpolation is used
to generate intermediate values. Considering the curve to have a
total length of 256 points, the 10 locations are at 24, 32, 48, 64,
80, 96, 128, 160, 192, 224. Locations 0, 16, 240, and 255 are
fixed and cannot be changed.
n = 24, 32, 48, 64, 80, 96, 128, 160, 192 or 224
For example:
y24 = [(8 / 224)0.5 × 224] + 16 = 58*
y32 = [16 / 224)0.5 × 224] + 16 = 76*
y48 = [(32 / 224)0.5 × 224] + 16 = 101*
y64 = [(48 / 224)0.5 × 224] + 16 =120*
y80 = [(64 / 224)0.5 × 224] + 16 =136*
y96 = [(80 / 224)0.5 × 224] + 16 = 150*
y128 = [(112 / 224)0.5 × 224] + 16 = 174*
y160 = [(144 / 224)0.5 × 224] + 16 = 195*
y192 = [(176 / 224)0.5 × 224] + 16 = 214*
y224 = [(208 / 224)0.5 × 224] + 16 = 232*
GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT
300
250
*rounded to the nearest integer
SIGNAL OUTPUT
The gamma curves in Figure 32 and 33 are examples only; any
user defined curve is acceptable in the range of 16–240.
200
0.5
150
100
SIGNAL INPUT
50
0
GAMMA CORRECTION BLOCK TO A RAMP INPUT FOR
VARIOUS GAMMA VALUES
300
GAMMA CORRECTED AMPLITUDE
GAMMA CORRECTED AMPLITUDE
yn = Value for y along the y-axis, which has to be written into
the gamma correction register
0
50
100
150
LOCATION
200
250
Figure 32. Signal Input (Ramp) and Signal Output
for Gamma 0.5
250
0.3
200
0.5
150
T
PU
100
AL
IN
1.5
N
G
SI
1.8
50
0
0
50
100
150
LOCATION
200
250
Figure 33. Signal Input (Ramp) and Selectable
Gamma Output Curves
REV. B
–43–
ADV7330
The derivative of the incoming signal is compared to the three
programmable threshold values: HD adaptive filter threshold
A, B, C. The recommended threshold range is from 16–235,
although any value in the range of 0–255 can be used.
HD SHARPNESS FILTER CONTROL AND ADAPTIVE
FILTER CONTROL
[Subaddress 20h, 38h–3Dh]
There are three filter modes available on the ADV7330: sharpness filter mode and two adaptive filter modes.
The edges can then be attenuated with the settings in HD adaptive
filter gain 1, 2, 3 registers and HD sharpness filter gain register.
According to the settings of the HD adaptive filter mode control, there are two Adaptive Filter modes available:
HD Sharpness Filter Mode
To enhance or attenuate the Y signal in the frequency ranges
shown in the figures below, the following register settings must
be used: HD sharpness filter must be enabled and HD adaptive
filter enable must be set to disabled.
To select one of the 256 individual responses, the according gain
values for each filter, which range from –8 to +7 , must be programmed into the HD sharpness filter gain register at Address 20h.
HD Adaptive Filter Mode
The HD adaptive filter threshold A, B, C registers, the HD
adaptive filter gain 1, 2, 3 registers, and the HD sharpness filter
gain register are used in Adaptive Filter mode. To activate the
adaptive filter control, HD sharpness filter must be enabled and
HD adaptive filter gain must be enabled.
2. Mode B is used when adaptive filter gain is set to 1. In this
mode a cascade of Filter A and Filter B is used. Both settings
for Gain A and Gain B in the HD sharpness filter gain,
HD adaptive filter gain 1, 2, 3 become active when needed.
SHARPNESS AND ADAPTIVE FILTER CONTROL BLOCK
1.5
1.4
1.3
1.3
1.2
1.2
1.1
1.0
0.9
1.1
1.0
0.9
0.8
0.8
0.7
0.7
0.6
0.6
0.5
1.6
MAGNITUDE RESPONSE (Linear Scale)
1.4
MAGNITUDE
INPUT
SIGNAL:
STEP
MAGNITUDE
1.5
1. Mode A is used when adaptive filter mode is set to 0. In this
case, Filter B (LPF) will be used in the adaptive filter block.
Also, only the programmed values for Gain B in the HD
sharpness filter gain, HD adaptive filter gain 1, 2, 3 are
applied when needed. The Gain A values are fixed and cannot
be changed.
0.5
1.5
1.4
1.3
1.2
1.1
1.0
FREQUENCY (MHz)
FREQUENCY (MHz)
FILTER A RESPONSE (Gain Ka)
FILTER B RESPONSE (Gain Kb)
0
2
4
6
8
10
FREQUENCY (MHz)
12
FREQUENCY RESPONSE IN SHARPNESS
FILTER MODE WITH Ka = 3 AND Kb = 7
Figure 34. Sharpness and Adaptive Filter Control Block
–44–
REV. B
ADV7330
The effect of the sharpness filter can also be seen when using
the internally generated cross hatch pattern.
HD Sharpness Filter and Adaptive Filter Application Examples
HD Sharpness Filter Application
The HD sharpness filter can be used to enhance or attenuate
the Y video output signal. The following register settings were
used to achieve the results shown in the figures below. Input
data was generated by an external signal source.
Table XII.
Table XI.
Address
Register
Setting
00h
01h
02h
10h
11h
20h
20h
20h
20h
20h
20h
FCh
10h
20h
00h
81h
00h
08h
04h
40h
80h
22h
Reference in
Figure 35
Address
Register Setting
00h
01h
02h
10h
11h
20h
FCh
10h
20h
00h
85h
99h
In toggling the sharpness filter enable bit [Address 11h, Bit 8],
it can be seen that the line contours of the crosshatch pattern
change their sharpness.
a
b
c
d
e
f
d
a
R2
1
e
b
R4
R1
f
c
1
R2
CH1 500mV
REF A
500mV 4.00s
1
M 4.00s
9.99978ms
CH1
ALL FIELDS
CH1 500mV
REF A
500mV 4.00s
1
M 4.00s
9.99978ms
CH1
ALL FIELDS
Figure 35. HD Sharpness Filter Control with Different Gain Settings for HS Sharpness Filter Gain Value
REV. B
–45–
ADV7330
ADAPTIVE FILTER CONTROL APPLICATION
Figures 36 and 37 show a typical signal to be processed by the
adaptive filter control block.
When changing the adaptive filter mode to Mode B [Address 15h,
Bit 6], the following output can be obtained:
: 674mV
@: 446mV
: 332ns
@: 12.8ms
: 692mV
@: 446mV
: 332ns
@: 12.8ms
Figure 38. Output Signal from Adaptive Filter Control
Figure 36. Input Signal to Adaptive Filter Control
: 692mV
@: 446mV
: 332ns
@: 12.8ms
The adaptive filter control can also be demonstrated using the
internally generated crosshatch test pattern and toggling the
adaptive filter control bit [Address 15h, Bit 7].
Table XIV.
Figure 37. Output Signal After Adaptive Filter Control
The following register settings were used to obtain the results
shown in Figure 37, i.e., to remove the ringing on the Y signal.
Input data was generated by an external signal source.
Address
Register Setting
00h
01h
02h
10h
11h
15h
20h
38h
39h
3Ah
3Bh
3Ch
3Dh
FCh
10h
20h
00h
85h
80h
00h
ACh
9Ah
88h
28h
3Fh
64h
Table XIII.
Address
Register Setting
00h
01h
02h
10h
11h
15h
20h
38h
39h
3Ah
3Bh
3Ch
3Dh
FCh
10h
20h
00h
81h
80h
00h
ACh
9Ah
88h
28h
3Fh
64h
All other registers are set as normal.
–46–
REV. B
ADV7330
SD Digital Noise Reduction
[Subaddress 63h, 64h, 65h]
DNR is applied to the Y data only. A filter block selects the high
frequency, low amplitude components of the incoming signal
[DNR input select]. The absolute value of the filter output is
compared to a programmable threshold value ['DNR threshold
control]. There are two DNR modes available: DNR mode and
DNR sharpness mode.
In DNR mode, if the absolute value of the filter output is smaller
than the threshold, it is assumed to be noise. A programmable
amount [coring gain border, coring gain data] of this noise
signal will be subtracted from the original signal.
In DNR sharpness mode, if the absolute value of the filter output
is less than the programmed threshold, it is assumed to be noise,
as before. Otherwise, if the level exceeds the threshold now being
identified as a valid signal, a fraction of the signal [coring gain
border, coring gain data] will be added to the original signal in
order to boost high frequency components and to sharpen the
video image.
In MPEG systems, it is common to process the video information
in blocks of 8 pixels × 8 pixels for MPEG2 systems, or 16 pixels
× 16 pixels for MPEG1 systems [block size control]. DNR can be
applied to the resulting block transition areas, which are known
to contain noise. Generally, the block transition area contains
two pixels. It is possible to define this area to contain four pixels
[border area].
DNR MODE
DNR CONTROL
It is also possible to compensate for variable block positioning or
differences in YCrCb pixel timing with the use of the DNR
block offset.
The digital noise reduction registers are three 8-bit wide registers.
They are used to control the DNR processing.
Coring Gain Border [Address 63h, Bits 3–0]
These four bits are assigned to the gain factor applied to
border areas.
In DNR mode, the range of gain values is 0 to 1 in increments
of 1/8. This factor is applied to the DNR filter output, which
lies below the set threshold range. The result is then subtracted
from the original signal.
In DNR sharpness mode, the range of gain values is 0 to 0.5 in
increments of 1/16. This factor is applied to the DNR filter
output, which lies above the threshold range. The result is added
to the original signal.
Coring Gain Data [Address 63h, Bits 7–4]
These four bits are assigned to the gain factor applied to the
luma data inside the MPEG pixel block.
In DNR mode, the range of gain values is 0 to 1 in increments
of 1/8. This factor is applied to the DNR filter output, which
lies below the set threshold range. The result is then subtracted
from the original signal.
In DNR sharpness mode, the range of gain values is 0 to 0.5 in
increments of 1/16. This factor is applied to the DNR filter
output, which lies above the threshold range. The result is
added to the original signal.
BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET
APPLY DATA
CORING GAIN
APPLY BORDER
CORING GAIN
GAIN
NOISE
SIGNAL PATH
CORING GAIN DATA
CORING GAIN BORDER
OXXXXXXOOXXXXXXO
OXXXXXXOOXXXXXXO
INPUT FILTER
BLOCK
FILTER
OUTPUT
< THRESHOLD?
Y DATA
INPUT
FILTER OUTPUT
> THRESHOLD
SUBTRACT SIGNAL
IN THRESHOLD
RANGE FROM
ORIGINAL SIGNAL
DNR OUT
DNR Threshold [Address 64h, Bits 5–0]
These six bits are used to define the threshold value in the range
of 0 to 63. The range is an absolute value.
Border Area [Address 64h, Bit 6]
DNR CONTROL
In setting this bit to a Logic 1, the block transition area can be
defined to consist of four pixels. If this bit is set to a Logic 0,
the border transition area consists of two pixels, where one pixel
refers to two clock cycles at 27 MHz.
BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET
GAIN
NOISE
SIGNAL PATH
CORING GAIN DATA
CORING GAIN BORDER
720485 PIXELS
(NTSC)
INPUT FILTER
BLOCK
Y DATA
INPUT
OXXXXXXOOXXXXXXO
Figure 40. DNR Block Offset Control
–
+
MAIN SIGNAL PATH
DNR
SHARPNESS
MODE
DNR27 – DNR24 = 01H
OFFSET CAUSED
BY VARIATIONS IN
INPUT TIMING
FILTER
OUTPUT
> THRESHOLD?
FILTER OUTPUT
< THRESHOLD
2 PIXEL
BORDER DATA
ADD SIGNAL
ABOVE THRESHOLD
RANGE FROM
ORIGINAL SIGNAL
+
+
DNR OUT
MAIN SIGNAL PATH
88 PIXEL BLOCK
Figure 39. DNR Block Diagram
88 PIXEL BLOCK
Figure 41. DNR Border Area
REV. B
–47–
ADV7330
Block Size Control [Address 64h, Bit 7]
This bit is used to select the size of the data blocks to be processed.
Setting the block size control function to a Logic 1 defines a
16 pixel × 16 pixel data block and a Logic 0 defines an 8 pixel ×
8 pixel data block, where one pixel refers to two clock cycles at
27 MHz.
DNR Input Select Control [Address 65h, Bit 2–0]
Three bits are assigned to select the filter that is applied to the
incoming Y data. The signal that lies in the pass band of the
selected filter is the signal that will be DNR processed. Figure 42
shows the filter responses selectable with this control.
1.0
FILTER D
MAGNITUDE
0.8
In DNR mode, it is possible to subtract a fraction of the signal
that lies below the set threshold, assumed to be noise, from the
original signal. The threshold is set in DNR Register 1.
When DNR sharpness mode is enabled, it is possible to add a
fraction of the signal that lies above the set threshold to the
original signal, since this data is assumed to be valid data and
not noise. The overall effect is that the signal will be boosted
(similar to using Extended SSAF filter).
Block Offset Control [Address 65h, Bits 7–4]
Four bits are assigned to this control, which allows a shift of the
data block of 15 pixels maximum. Consider the coring gain
positions fixed. The block offset shifts the data in steps of one
pixel such that the border coring gain factors can be applied at the
same position regardless of variations in input timing of the data.
SD ACTIVE VIDEO EDGE
[Subaddress 42h, Bit 7]
FILTER C
When the active video edge is enabled, the first three pixels and
the last three pixels of the active video on the luma channel are
scaled in such a way that maximum transitions on these pixels
are not possible. The scaling factors are ×1/8, ×1/2, and ×7/8.
All other active video passes through unprocessed.
0.6
0.4
FILTER B
0.2
FILTER A
0
0
1
2
3
4
FREQUENCY (Hz)
SAV/EAV STEP EDGE CONTROL
5
6
Figure 42. DNR Input Select
DNR Mode Control [Address 65h, Bit 4]
This bit controls the DNR mode selected. A Logic 0 selects
DNR mode, a Logic 1 selects DNR sharpness mode.
The ADV7330 has the capability of controlling fast rising and
falling signals at the start and end of active video to minimize
ringing.
An algorithm monitors SAV and EAV and governs when the
edges are too fast. The result will be reduced ringing at the start
and end of active video for fast transitions.
Subaddress 42h, Bit 7 = 1 enables this feature.
DNR works on the principle of defining low amplitude, high
frequency signals as probable noise and subtracting this noise
from the original signal.
LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
DISABLED
100 IRE
LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
ENABLED
100 IRE
87.5 IRE
50 IRE
0 IRE
12.5 IRE
0 IRE
Figure 43. Example for Active Video Edge Functionality
–48–
REV. B
ADV7330
VOLTS
IRE:FLT
100
0.5
50
0
0
F2
L135
–50
0
2
4
6
8
10
12
Figure 44. Address 42h, Bit 7 = 0
VOLTS
IRE:FLT
100
0.5
50
0
0
F2
L135
–50
–2
0
2
4
6
8
Figure 45. Address 42h, Bit 7 = 1
REV. B
–49–
10
12
ADV7330
Table XVI shows possible output rates from the ADV7330.
BOARD DESIGN AND LAYOUT CONSIDERATIONS
DAC Termination and Layout Considerations
Table XVI.
The ADV7330 contains an on-board voltage reference. The VREF
pin is normally terminated to VAA through a 0.1 µF capacitor
when the internal VREF is used. Alternatively, the ADV7330 can
be used with an external VREF (AD1580).
Input Mode
Address 01h, Bit 6–4
PLL
Output
Address 00h, Bit 1 Rate
The RSET resistors connected between the RSET pin and AGND
are used to control the full-scale output current and therefore
the DAC voltage output levels. For full-scale output, RSET must
have a value of 3040 Ω. The RSET values should not be changed.
RLOAD has a value of 300 Ω for full-scale output.
SD
Off
On
27 MHz (2×)
216 MHz (16×)
PS
Off
On
27 MHz (1×)
216 MHz (8×)
HDTV
Off
On
74.25 MHz (1×)
148.5 MHz (2×)
VIDEO OUTPUT BUFFER AND OPTIONAL
OUTPUT FILTER
Output buffering on all three DACs is necessary in order to
drive output devices, such as SD or HD monitors.
10H
DAC
OUTPUT
Analog Devices produces a range of suitable op amps for this
application, such as the AD8061. More information on line
driver buffering circuits is given in the relevant op amp data sheets.
3
600
22pF
75
600
1
BNC
OUTPUT
4
An optional analog reconstruction low-pass filter (LPF) may be
required as an anti-imaging filter if the ADV7330 is connected
to a device that requires this filtering.
560
560
Figure 46. Example for Output Filter for SD,
16 × Oversampling
The filter specifications vary with the application.
Table XV. External Filter Requirements
CIRCUIT FREQUENCY RESPONSE
0
Cutoff
Frequency Attenuation
Application Oversampling (MHz)
–50 dB @ (MHz)
24n
–30
–10
MAGNITUDE (dB)
–20
2×
16×
1×
8×
1×
2×
>6.5
>6.5
>12.5
>12.5
>30
>30
20.5
209.5
14.5
203.5
44.25
118.5
18n
15n
–120
–40
PHASE (Deg)
–50
GROUP DELAY (sec)
–60
12n
–150
9n
–180
6n
–210
–70
–80
1M
21n
–60
–90
–30
GAIN (dB)
SD
SD
PS
PS
HDTV
HDTV
0
10M
100M
FREQUENCY (Hz)
3n
–240
0
1G
Figure 47. Filter Plot for Output Filter for SD,
16 × Oversampling
–50–
REV. B
ADV7330
PC BOARD LAYOUT CONSIDERATIONS
4.7H
DAC
OUTPUT
3
6.8pF
600
75
600
6.8pF
The ADV7330 is optimally designed for low noise performance,
both radiated and conducted noise. To complement the excellent
noise performance of the ADV7330, it is imperative that great
care be given to the PC board layout.
BNC
OUTPUT
1
4
560
The layout should be optimized for lowest noise on the ADV7330
power and ground lines. This can be achieved by shielding the
digital inputs and providing good decoupling. The lead length
between groups of VAA and AGND, VDD and DGND, and
VDD_IO and GND_IO pins should be kept as short as possible to
minimized inductive ringing.
560
Figure 48. Example Output Filter for PS,
8 × Oversampling
DAC OUTPUT
3
1
300
75
470nH
3
33pF
4
220nH
BNC OUTPUT
75
82pF
1
4
500
500
There should be a separate analog ground plane and a separate
digital ground plane.
Figure 49. Example Output Filter for HDTV,
2 × Oversampling
0
CIRCUIT FREQUENCY RESPONSE
480
18n
400
–10
MAGNITUDE (dB)
16n
320
–20
14n
240
GAIN (dB)
–30
–40
GROUP DELAY (Sec)
PHASE (Deg) 160
12n
10n
–50
80
–60
0
–70
–80
–80
–160
8n
6n
4n
–90
1M
2n
–240
0
1G
10M
100M
FREQUENCY (Hz)
Figure 50. Filter Plot for Output Filter for PS,
8 × Oversampling
0
480
MAGNITUDE (dB)
360
–10
240
GAIN (dB)
–20
GROUP DELAY (Sec)
PHASE (Deg)
120
–40
0
–50
–120
–60
1M
10M
100M
FREQUENCY (Hz)
Power planes should encompass a digital power plane and an
analog power plane. The analog power plane should contain the
DACs and all associated circuitry, VREF circuitry. The digital
power plane should contain all logic circuitry.
The analog and digital power planes should be individually connected to the common power plane at one single point through a
suitable filtering device, such as a ferrite bead.
DAC output traces on a PCB should be treated as transmission
lines. It is recommended that the DACs be placed as close as
possible to the output connector, with the analog output traces
being as short as possible (less than 3 inches). The DAC termination resistors should be placed as close as possible to the
DAC outputs and should overlay the PCB’s ground plane. As
well as minimizing reflections, short analog output traces will
reduce noise pickup due to neighboring digital circuitry.
To avoid crosstalk between the DAC outputs, it is recommended
to leave as much space as possible between the tracks of the
individual DAC output pins. The addition of ground tracks
between outputs is also recommended.
Supply Decoupling
CIRCUIT FREQUENCY RESPONSE
–30
It is recommended that a 4-layer printed circuit board is used
with power and ground planes separating the layer of the signal
carrying traces of the components and solder-side layer. Component placement should be carefully considered in order to
separate noisy circuits, such as crystal clocks, high speed logic
circuitry, and analog circuitry.
18n
15n
12n
9n
6n
Noise on the analog power plane can be further reduced by the
use of decoupling capacitors.
Optimum performance is achieved by the use of 10 nF and 0.1 µF
ceramic capacitors. Each group of VAA, VDD, or VDD_IO pins
should be individually decoupled to ground. This should be
done by placing the capacitors as close as possible to the device
with the capacitor leads as short as possible, thus minimizing
lead inductance.
A 1 µF tantalum capacitor is recommended across the VAA supply
in addition to 10 nF ceramic capacitor. See Figure 52.
3n
–240 0
1G
Figure 51. Example for Output Filter HDTV,
2 × Oversampling
REV. B
–51–
ADV7330
Digital Signal Interconnect
Analog Signal Interconnect
The digital signal lines should be isolated as much as possible
from the analog outputs and other analog circuitry. Digital
signal lines should not overlay the analog power plane.
The ADV7330 should be located as close as possible to the
output connectors, thus minimizing noise pickup and reflections
due to impedance mismatch.
Due to the high clock rates used, long clock lines to the ADV7330
should be avoided to minimize noise pickup.
For optimum performance, the analog outputs should each be
source and load terminated, as shown in Figure 52. The
termination resistors should be as close as possible to the
ADV7330 to minimize reflections.
Any active pull-up termination resistors for the digital inputs
should be connected to the digital power plane and not the analog
power plane.
For optimum performance, it is recommended that all decoupling
and external components relating to ADV7330 be located on the
same side of the PCB and as close as possible to the ADV7330.
Any unused inputs should be tied to ground.
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
VAA
+
VDD_IO
10nF
1F
10nF
0.1F
10nF
0.1F
VAA
VDD
0.1F
10, 56
VDD_IO
5k
36
41
COMP
VAA
1
VDD VDD_IO
VAA
19
I2C
50
HSYNC_O/P
ADV7330
49
VSYNC_O/P
48
BLANK_O/P
1.1k
VREF 46
RECOMMENDED EXTERNAL
AD1580 FOR OPTIMUM
PERFORMANCE
100nF
C0–C7
UNUSED
INPUTS
SHOULD BE
GROUNDED
CVBS/GREEN/Y
DAC A 39
300
Y0–Y7
LUMA/BLUE/Pb
DAC B 38
VAA
4.7k
4.7F
23
HSYNC_I/P
24
VSYNC_I/P
25
BLANK_I/P
33
RESET
32
CLKIN
300
300
+
VAA
SCLK 22
SDA 21
820pF
34
EXT_LF
GND_ IO AGND DGND
64
100
VDD_IO
VDD_IO
5k
5k
I2C BUS
100
VDD_IO
ALSB 20
680
3.9nF
CHROMA/RED/Pr
DAC C 37
5k
RSET 35
3040
40
2, 11, 14, 15,
51–55, 57–63
SELECTION HERE
DETERMINES
DEVICE ADDRESS
Figure 52. ADV7330 Circuit Layout
–52–
REV. B
ADV7330
APPENDIX 1—COPY GENERATION
MANAGEMENT SYSTEM
HD CGMS Data Registers 2–0
[Subaddress 21h, 22h, 23h]
CGMS CRC Functionality
HD CGMS is available in 525p mode only, conforming to
‘CGMS-A EIA-J CPR1204-1, Transfer Method of Video ID
Information Using Vertical Blanking Interval (525p system),
March 1998’, and IEC61880, 1998, Video systems (525/60) —
video and accompanied data using the vertical blanking intervalanalog interface.
When HD CGMS is enabled [Subaddress 12h, Bit 6 = 1], CGMS
data is inserted on Line 41. The HD CGMS data registers are
to be found at address 21h, 22h, 23h.
SD CGMS Data Registers 2–0
[Subaddress 59h, 5Ah, 5Bh]
The ADV7330 supports copy generation management system
(CGMS) conforming to the standard. CGMS data is transmitted
on Line 20 of the odd fields and Line 283 of even fields. Bits
C/W05 and C/W06 control whether or not CGMS data is output
on odd and even fields. CGMS data can be transmitted only
when the ADV7330 is configured in NTSC mode. The CGMS
data is 20 bits long; the function of each of these bits is as shown
below. The CGMS data is preceded by a reference pulse of the
same amplitude and duration as a CGMS bit; see Figure 54.
If SD CGMS CRC [Address 59h, Bit 4] or PS/HD CGMS CRC
[Subaddress 12h, Bit 7] is set to Logic 1, the last six bits,
C19–C14, which comprise the 6-bit CRC check sequence, are
calculated automatically on the ADV7330 based on the lower
14 bits (C0–C13) of the data in the data registers and output
with the remaining 14 bits to form the complete 20 bits of the
CGMS data. The calculation of the CRC sequence is based on
the polynomial x6 + x + 1 with a preset value of 111111. If SD
CGMS CRC [Address 59h, Bit 4] or PS/HD CGMS CRC
[Subaddress 12h, Bit 7] is set to Logic 0, all 20 bits (C0–C19)
are output directly from the CGMS registers (no CRC calculated, must be calculated by the user).
Function of CGMS Bits
Word 0–6 bits; Word 1–4 bits; Word 2–6 bits; CRC 6 bits;
CRC polynomial = x6 + x + 1 (preset to 111111).
Table XVII.
Bit
Function
WORD0
B1
B2
B3
Aspect ratio
Display format
Undefined
HD CGMS Data Registers
[Subaddress 12h, Bit 6]
WORD0
B4, B5, B6
The ADV7330 supports copy generation management system
(CGMS) in HDTV mode (720p and 1080i) in accordance to
EIAJ CPR-1204-2. The HD CGMS data registers are to be found
at Addresses 21h, 22h, and 23h.
WORD1
B7, B8, B9, B10
720p System
CGMS data is applied to Line 24 of the luminance vertical
blanking interval.
0
4:3
Normal
Identification information about video and
other signals (e.g., audio)
Identification signal incidental to Word 0
WORD2
B11, B12, B13, B14 Identification signal and information
incidental to Word 0
1080i System
CGMS data is applied to Line 19 and also on Line 582 of the
luminance vertical blanking interval.
REV. B
1
16:9
Letterbox
–53–
ADV7330
CRC SEQUENCE
+700mV
REF
70% 10%
BIT1 BIT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BIT20
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV
–300mV
21.2s 0.22s
22T
5.8s 0.15s
6T
T = 1/(fH 33) = 963ns
fH = HORIZONTAL SCAN FREQUENCY
T 30ns
Figure 53. PS CGMS Waveform
+100 IRE
CRC SEQUENCE
REF
+70 IRE
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0 IRE
–40 IRE
49.1s 0.5s
11.2s
2.235s 20ns
Figure 54. SD CGMS Waveform
CRC SEQUENCE
+700mV
REF
70% 10%
BIT1 BIT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BIT20
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV
–300mV
T 30ns
17.2s 160ns
22 T
4T
3.128s 90ns
T = 1/(fH 1650/58) = 781.93ns
fH = HORIZONTAL SCAN FREQUENCY
1H
Figure 55. HDTV 720p CGMS Waveform
CRC SEQUENCE
+700mV
REF
70% 10%
BIT1 BIT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BIT20
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV
–300mV
T 30ns
4T
4.15s 60ns
22.84s 210ns
22 T
T = 1/(fH 2200/77) = 1.038s
fH = HORIZONTAL SCAN FREQUENCY
1H
Figure 56. HDTV 1080i CGMS Waveform
–54–
REV. B
ADV7330
APPENDIX 2—SD WIDE SCREEN SIGNALING
[Subaddress 59h, 5Ah, 5Bh]
The ADV7330 supports wide screen signaling (WSS) conforming to the standard. WSS data is transmitted on Line 23. WSS
data can be transmitted only when the ADV7330 is configured
in PAL mode. The WSS data is 14 bits long, and the function
of each of these bits is shown in Table XVII. The WSS data is
preceded by a run-in sequence and a start code (see Figure 57).
If SD WSS [Address 59h, Bit 7] is set to Logic 1, it enables the
WSS data to be transmitted on Line 23. The latter portion of
Line 23 (42.5 µs from the falling edge of HSYNC) is available
for the insertion of video.
It is possible to blank the WSS portion of Line 23 with
Subaddress 61h, Bit 7.
Table XVIII. Function of WSS Bits
Bit
Description
Bit
Description
Bit 0–Bit 2
Aspect Ratio/Format/Position
Bit 3
Odd Parity Check of Bit 0 to Bit 2
B6
0
1
No Helper
Modulated Helper
B7
Reserved
B0, B1,
0 0
1 0
0 1
B2
0
0
0
B3
1
0
0
Aspect Ratio
4:3
14:9
14:9
Format
Full Format
Letterbox
Letterbox
Position
N/A
Center
Top
1
0
1
0
1
0
1
1
1
1
1
0
1
1
0
16:9
16:9
>16:9
14:9
16:9
Letterbox
Letterbox
Letterbox
Full Format
N/A
Center
Top
Center
Center
N/A
1
0
0
1
1
B4
0
1
Camera Mode
Film Mode
B5
0
1
Standard Coding
Motion Adaptive Color Plus
B9
0
1
0
1
B10
0
0
1
1
No Open Subtitles
Subtitles in Active Image Area
Subtitles out of Active Image Area
Reserved
B11
0
1
No Surround Sound Information
Surround Sound Mode
B12
Reserved
B13
Reserved
500mV
RUN-IN
SEQUENCE
START
CODE
W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13
11.0s
38.4s
42.5s
Figure 57. WSS Waveform Diagram
REV. B
–55–
ACTIVE
VIDEO
ADV7330
FCC Code of Federal Regulations (CFR) 47 section 15.119
and EIA608 describe the closed captioning information for
Lines 21 and 284.
APPENDIX 3—SD CLOSED CAPTIONING
[Subaddress 51h–54h]
The ADV7330 supports closed captioning conforming to the
standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active
line time of Line 21 of the odd fields and Line 284 of even fields.
Closed captioning consists of a 7-cycle sinusoidal burst that is
frequency and phase locked to the caption data. After the clock
run-in signal, the blanking level is held for two data bits and is
followed by a Logic 1 start bit. Sixteen bits of data follow the
start bit. These consist of two 8-bit bytes, seven data bits and
one odd parity bit. The data for these bytes is stored in the SD
closed captioning registers (Address 53h–54h).
The ADV7330 also supports the extended closed captioning
operation, which is active during even fields and is encoded on
Scan Line 284. The data for this operation is stored in the SD
closed captioning registers (Address 51h–52h).
All clock run-in signals and timing to support closed captioning
on Lines 21 and 284 are generated automatically by the ADV7330.
All pixel inputs are ignored during Lines 21 and 284 if closed
captioning is enabled.
10.5s 0.25s
The ADV7330 uses a single buffering method. This means that
the closed captioning buffer is only one byte deep; therefore
there will be no frame delay in outputting the closed captioning
data unlike other 2-byte deep buffering systems. The data must
be loaded one line before (Line 20 or Line 283) it is output on
Lines 21 and 284. A typical implementation of this method is to
use VSYNC to interrupt a microprocessor, which in turn will load
the new data (two bytes) every field. If no new data is required
for transmission, 0s must be inserted in both data registers; this
is called nulling. It is also important to load control codes, all of
which are double bytes on Line 21 or a TV will not recognize
them. If there is a message like “Hello World” that has an odd
number of characters, it is important to pad it out to even in
order to get “end of caption” 2-byte control code to land in the
same field.
12.91s
7 CYCLES OF
0.5035MHz
CLOCK RUN-IN
TWO 7-BIT + PARITY
ASCII CHARACTERS
(DATA)
S
T
A
R
T
50 IRE
P
A
R
I
T
Y
D0–D6
D0–D6
BYTE 0
P
A
R
I
T
Y
BYTE 1
40 IRE
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = FSC = 3.579545MHz
AMPLITUDE = 40 IRE
10.003s
27.382s
33.764s
Figure 58. Closed Captioning Waveform, NTSC
–56–
REV. B
ADV7330
APPENDIX 4—TEST PATTERNS
The ADV7330 can generate SD and HD test patterns.
T
T
2
2
CH2 200mV
M 10.0s
A CH2
30.6000s
T
CH2 100mV
1.20V
M 10.0s
CH2
1.82600ms
T
EVEN
Figure 62. PAL Black Bar (–21 mV, 0 mV, +3.5 mV,
+7 mV, +10.5 mV, +14 mV, +18 mV, +23 mV)
Figure 59. NTSC Color Bars
T
T
2
2
CH2 200mV
M 10.0s
A CH2
30.6000s
T
1.21V
CH2 200mV
Figure 60. PA0L Color Bars
EVEN
Figure 63. 525p Hatch Pattern
T
T
2
2
CH2 100mV
M 10.0s
CH2
1.82380ms
T
EVEN
CH2 200mV
Figure 61. NTSC Black Bar (–21 mV, 0 mV, +3.5 mV,
+7 mV, +10.5 mV, +14 mV, +18 mV, +23 mV)
REV. B
M 4.0s
CH2
1.82944ms
T
M 4.0s
CH2
1.84208ms
T
Figure 64. 625p Hatch Pattern
–57–
EVEN
ADV7330
T
T
2
2
CH2 200mV
M 4.0s
CH2
1.82872ms
T
EVEN
CH2 100mV
Figure 65. 525p Field Pattern
M 4.0s
CH2
1.82936ms
T
EVEN
Figure 67. 525p Black Bar (–35 mV, 0 mV, +7 mV,
+14 mV, +21 mV, +28 mV, +35 mV)
T
T
2
2
CH2 200mV
M 4.0s
CH2
1.84176ms
T
EVEN
CH2 100mV
Figure 66. 625p Field Pattern
M 4.0s
CH2
1.84176ms
T
EVEN
Figure 68. 625p Black Bar (–35 mV, 0 mV, +7 mV,
+14 mV, +21 mV, +28 mV, +35 mV)
–58–
REV. B
ADV7330
The following register settings are used to generate a SD NTSC
CVBS output on DAC A:
Subaddress
Register
Setting
00h
40h
42h
44h
4Ah
10h
10h
40h
40h
08h
For PAL black bar pattern output on DAC A, the same settings
are used except that subaddress = 40h and register setting = 11h.
The following register settings are used to generate a 525p hatch
pattern on DAC A:
All other registers are set to normal/default.
For PAL CVBS output on DAC A, the same settings are used
except that subaddress = 40h and register setting = 11h.
The following register settings are used to generate an SD NTSC
black bar pattern output on DAC A:
Subaddress
Register
Setting
00h
02h
40h
42h
44h
4Ah
10h
04h
10h
40h
40h
08h
Register
Setting
00h
01h
10h
11h
16h
17h
18h
10h
10h
40h
05h
A0h
80h
80h
All other registers are set to normal/default.
For 625p hatch pattern on DAC A, the same register settings
are used except that subaddress = 10h and register setting = 50h.
For a 525p black bar pattern output on DAC A, the same settings
are used as above except that subaddress = 02h and register
setting = 24h.
For 625p black bar pattern output on DAC A, the same settings
are used as above except that subaddress = 02h and register
setting = 24h; and subaddress = 10h and register setting = 50h.
All other registers are set to normal/default.
REV. B
Subaddress
–59–
ADV7330
APPENDIX 5—SD TIMING MODES
[Subaddress 4Ah]
Mode 0 (CCIR-656)—Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7330 is controlled by the SAV (start active video) and
EAV (end active video) time codes in the pixel data. All timing
information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and
after each line during active picture and retrace. VSYNC_O/P,
HSYNC_O/P, and BLANK_O/P (if not used) pins should be
tied high during this mode. Blank output is available.
ANALOG
VIDEO
EAV CODE
INPUT PIXELS
C
F 0 0 X 8 1 8 1
Y
Y
r
F 0 0 Y 0 0 0 0
4 CLOCK
SAV CODE
0 F F A A A
0 F F B B B
C
C
8 1 8 1 F 0 0 X C Y C Y C
Y r Y b
b
0 0 0 0 F 0 0 Y b
r
ANCILLARY DATA
(HANC)
1440 CLOCK
4 CLOCK
4 CLOCK
PAL SYSTEM
(625 LINES/50Hz)
4 CLOCK
268 CLOCK
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
280 CLOCK
1440 CLOCK
START OF ACTIVE
VIDEO LINE
END OF ACTIVE
VIDEO LINE
Figure 69. SD Slave Mode 0
–60–
REV. B
ADV7330
Mode 0 (CCIR-656)—Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7330 generates H, V, and F signals required for the SAV
(start active video) and EAV (end active video) time codes in
the CCIR656 standard. The H bit is output on HSYNC_O/P,
the V bit is output on BLANK_O/P, and the F bit is output
on VSYNC_O/P pin.
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
1
2
3
4
6
5
7
8
9
10
11
20
21
22
H
V
EVEN FIELD
F
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
260
261
262
263
264
265
266
267
268
269
270
271
272
273
283
274
284
285
H
V
F
ODD FIELD
EVEN FIELD
Figure 70. SD Master Mode 0 (NTSC)
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
5
6
7
21
22
23
H
V
EVEN FIELD
F
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
317
318
319
H
V
F
ODD FIELD
EVEN FIELD
Figure 71. SD Master Mode 0 (PAL)
REV. B
–61–
320
334
335
336
ADV7330
ANALOG
VIDEO
H
F
V
Figure 72. SD Master Mode 0, Data Transitions
Mode 1—Slave Option
(Timing Register 0 TR0 = X X X X X 0 1 0)
In this mode, the ADV7330 accepts horizontal SYNC and odd/
even field signals. A transition of the field input when HSYNC_I/P
is low indicates a new frame i.e., vertical retrace. The BLANK_I/P
signal is optional. When the BLANK_I/P input is disabled, the
ADV7330 automatically blanks all normally blank lines as per
CCIR-624. HSYNC is applied to the HSYNC_I/P pin, BLANK
to the BLANK_I/P pin, and Field to the VSYNC_I/P pin.
DISPLAY
DISPLAY
522
523
VERTICAL BLANK
524
525
1
2
3
4
6
5
7
8
9
10
11
20
21
22
HSYNC_I/P
BLANK_I/P
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
260
261
VERTICAL BLANK
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
HSYNC_I/P
BLANK_I/P
FIELD
ODD FIELD
EVEN FIELD
Figure 73. SD Slave Mode 1 (NTSC)
–62–
REV. B
ADV7330
Mode 1—Master Option
(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode, the ADV7330 can generate horizontal sync and
odd/even field signals. A transition of the field output when
HSYNC_O/P is low indicates a new frame i.e., vertical retrace.
The blank signal is optional. Pixel data is latched on the rising
clock edge following the timing signal transitions. HSYNC is
output on the HSYNC_O/P pin, BLANK on the BLANK_O/P
pin, and Field on the VSYNC_O/P pin.
DISPLAY
DISPLAY
622
VERTICAL BLANK
623
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC_O/P
BLANK_O/P
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
317
318
319
320
334
335
HSYNC_O/P
BLANK_O/P
ODD FIELD
FIELD
EVEN FIELD
Figure 74. SD Slave Mode 1 (PAL)
HSYNC_O/P
FIELD
PAL = 12 CLOCK/2
NTSC = 16 CLOCK/2
BLANK_O/P
PIXEL
DATA
Cb
Y
PAL = 132 CLOCK/2
NTSC = 122 CLOCK/2
Figure 75. SD Timing Mode 1—Odd/Even Field Transitions Master/Slave
REV. B
–63–
Cr
Y
336
ADV7330
Mode 2—Slave Option
(Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode, the ADV7330 accepts horizontal and vertical
sync signals. A coincident low transition of both HSYNC_I/P
and VSYNC_I/P inputs indicates the start of an odd field. A
VSYNC_I/P low transition when HSYNC_I/P is high indicates
the start of an even field. The blank signal is optional. When the
blank input is disabled, the ADV7330 automatically blanks all
normally blank lines as per CCIR-624. HSYNC is input on the
HSYNC_I/P pin, BLANK on the BLANK_I/P pin, and VSYNC
on the VSYNC_I/P pin.
DISPLAY
522
DISPLAY
VERTICAL BLANK
523
524
525
1
2
3
4
6
5
7
8
10
9
20
11
21
22
HSYNC_I/P
BLANK_I/P
VSYNC_I/P
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
260
261
262
263
264
265
266
267
268
269
270
271
272
273
283
274
285
284
HSYNC_I/P
BLANK_I/P
VSYNC_I/P
EVEN FIELD
ODD FIELD
Figure 76. SD Slave Mode 2 (NTSC)
DISPLAY
622
623
DISPLAY
VERTICAL BLANK
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC_I/P
BLANK_I/P
VSYNC_I/P
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
309
310
VERTICAL BLANK
311
312
313
314
315
316
317
318
319
320
334
335
336
HSYNC_I/P
BLANK_I/P
VSYNC_I/P
ODD FIELD
EVEN FIELD
Figure 77. SD Slave Mode 2 (PAL)
–64–
REV. B
ADV7330
Mode 2—Master Option
(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode, the ADV7330 can generate horizontal and vertical
sync signals. A coincident low transition of both HSYNC_O/P
and VSYNC_O/P outputs indicates the start of an odd field.
A VSYNC_O/P low transition when HSYNC_O/P is high
indicates the start of an even field. HSYNC is output on the
HSYNC_O/P pin, BLANK on the BLANK_O/P pin, and VSYNC
on the VSYNC_O/P pin.
HSYNC_O/P
VSYNC_O/P
BLANK_O/P
PAL = 12 CLOCK/2
NTSC = 16 CLOCK/2
PIXEL
DATA
Cb
Y
PAL = 132 CLOCK/2
NTSC = 122 CLOCK/2
Figure 78. SD Timing Mode 2—Even to Odd Field Transition Master/Slave
HSYNC_O/P
VSYNC_O/P
BLANK_O/P
PAL = 864 CLOCK/2
NTSC = 858 CLOCK/2
PAL = 12 CLOCK/2
NTSC = 16 CLOCK/2
PIXEL
DATA
Cb
Y
Cr
Y
Cb
PAL = 132 CLOCK/2
NTSC = 122 CLOCK/2
Figure 79. SD Timing Mode 2—Odd to Even Field Transition Master/Slave
REV. B
–65–
Cr
Y
ADV7330
Mode 3—Master/Slave Option
(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode, the ADV7330 accepts or generates horizontal
sync and odd/even field signals. A transition of the field input
when HSYNC_I/P is high indicates a new frame, i.e., vertical
retrace. The BLANK_I/P signal is optional. When the BLANK_I/P
input is disabled, the ADV7330 automatically blanks all
normally blank lines as per CCIR-624. HSYNC is interfaced on
HSYNC_I/P, BLANK on BLANK_I/P, VSYNC on VSYNC_I/P.
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
1
2
3
4
6
5
7
8
9
10
11
20
21
22
HSYNC_I/P
BLANK_I/P
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
260
261
DISPLAY
VERTICAL BLANK
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
HSYNC_I/P
BLANK_I/P
FIELD
ODD FIELD
EVEN FIELD
Figure 80. SD Timing Mode 3 (NTSC)
–66–
REV. B
ADV7330
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
6
5
7
21
22
23
HSYNC_I/P
BLANK_I/P
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
318
317
319
320
334
335
HSYNC_I/P
BLANK_I/P
FIELD
EVEN FIELD
ODD FIELD
Figure 81. SD Timing Mode 3 (PAL)
APPENDIX 6—HD TIMING
DISPLAY
FIELD 1
VERTICAL BLANKING INTERVAL
1124
1125
1
2
3
4
5
6
7
8
20
21
22
560
VSYNC_I/P
HSYNC_I/P
DISPLAY
VERTICAL BLANKING INTERVAL
FIELD 2
561
562
563
564
565
566
567
568
569
570
583
VSYNC_I/P
HSYNC_I/P
Figure 82. 1080i Hsync and Vsync Input Timing
REV. B
–67–
584
585
1123
336
ADV7330
APPENDIX 7—VIDEO OUTPUT LEVELS
HD YPrPb Output Levels
INPUT CODE
EIA-770.2, STANDARD FOR Y
OUTPUT VOLTAGE
INPUT CODE
940
EIA-770.3, STANDARD FOR Y
OUTPUT VOLTAGE
940
CTV V
CTV V
700mV
700mV
64
64
300mV
300mV
EIA-770.2, STANDARD FOR Pr/Pb
EIA-770.3, STANDARD FOR Pr/Pb
OUTPUT VOLTAGE
OUTPUT VOLTAGE
960
960
600mV
512
CTV V
512
700mV
CTV V
700mV
64
64
Figure 85. EIA 770.3 Standard Output Signals
(1080i, 720p)
Figure 83. EIA 770.2 Standard Output Signals
(525p/625p)
INPUT CODE
EIA-770.1, STANDARD FOR Y
INPUT CODE
OUTPUT VOLTAGE
782mV
Y–OUTPUT LEVELS FOR
FULL I/P SELECTION
OUTPUT VOLTAGE
1023
940
CTV V
CTV V
700mV
714mV
64
300mV
64
286mV
EIA-770.1, STANDARD FOR Pr/Pb
INPUT CODE
OUTPUT VOLTAGE
Pr/Pb–OUTPUT LEVELS FOR
FULL I/P SELECTION
OUTPUT VOLTAGE
1023
960
CTV V
512
CTV V
700mV
700mV
64
300mV
64
Figure 84. EIA 770.1 Standard Output Signals
(525p/625p)
Figure 86. Output Levels for Full I/P Selection
–68–
REV. B
ADV7330
RGB Output Levels
700mV
550mV
700mV
300mV
300mV
700mV
550mV
300mV
700mV
550mV
700mV
550mV
300mV
700mV
550mV
300mV
300mV
Figure 87. HD RGB Output Levels
700mV
Figure 89. SD RGB Output Levels—RGB Sync Disabled
550mV
700mV
300mV
300mV
0mV
0mV
700mV
550mV
300mV
300mV
0mV
0mV
700mV
550mV
300mV
300mV
0mV
0mV
Figure 88. HD RGB Output Levels—RGB Sync Enabled
REV. B
550mV
550mV
700mV
550mV
700mV
550mV
Figure 90. SD RGB Output Levels—RGB Sync Enabled
–69–
ADV7330
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
332mV
YELLOW
WHITE
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
YPrPb Output Levels
2150mV
280mV
2000mV
220mV
1260mV
1000mV
160mV
900mV
110mV
60mV
140mV
BLACK
BLUE
RED
GREEN
CYAN
WHITE
280mV
YELLOW
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
332mV
MAGENTA
Figure 94. U Levels—PAL
Figure 91. U Levels—NTSC
220mV
160mV
110mV
300mV
60mV
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
WHITE
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
2150mV
2000mV
YELLOW
Figure 95. Y Levels—NTSC
Figure 92. U Levels—PAL
1260mV
1000mV
900mV
300mV
140mV
Figure 96. Y Levels—PAL
Figure 93. U Levels—NTSC
–70–
REV. B
ADV7330
VOLTS
IRE:FLT
100
0.5
50
0
0
–50
0
F1
L76
20
10
30
40
50
60
s
APL = 44.5%
525 LINE NTSC
SLOW CLAMP TO 0.00V AT 6.77s
PRECISION MODE OFF
SYNCHRONOUS
SYNC = A
FRAMES SELECTED 1 2
Figure 97. NTSC Color Bars 75%
VOLTS
0.4
IRE:FLT
50
0.2
0
0
–0.2
–50
–0.4
F1
L76
0
10
NOISE REDUCTION: 15.05dB
APL NEEDS SYNC-SOURCE!
525 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00V AT 6.72s
20
30
s
40
60
PRECISION MODE OFF
SYNCHRONOUS
SYNC = B
FRAMES SELECTED 1 2
Figure 98. NTSC Chroma
REV. B
50
–71–
ADV7330
VOLTS
IRE:FLT
0.6
0.4
50
0
0.2
0
0
–0.2
F2
L238
10
20
30
s
NOISE REDUCTION: 15.05dB
APL = 44.3%
525 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00V AT 6.72s
40
50
60
PRECISION MODE OFF
SYNCHRONOUS
SYNC = SOURCE
FRAMES SELECTED 1 2
Figure 99. NTSC Luma
VOLTS
0.6
0.4
0.2
0
–0.2
L608
0
10
20
NOISE REDUCTION: 0.00dB
APL = 39.1%
625 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00V AT 6.72s
30
40
50
60
s
PRECISION MODE OFF
SYNCHRONOUS
SOUND-IN-SYNC OFF
FRAMES SELECTED 1 2 3 4
Figure 100. PAL Color Bars 75%
–72–
REV. B
ADV7330
0.5
0
–0.5
10
20
30
s
APL NEEDS SYNC = SOURCE
625 LINE PAL, NO FILTERING
SLOW CLAMP TO 0.00V AT 6.72s
40
50
60
NO BUNCH SIGNAL
PRECISION MODE OFF
SYNCHRONOUS
SOUND-IN-SYNC OFF
FRAMES SELECTED 1
Figure 101. PAL Chroma
VOLTS
0.5
0
L575
0
10
APL NEEDS SYNC = SOURCE
625 LINE PAL, NO FILTERING
SLOW CLAMP TO 0.00V AT 6.72s
20
30
40
50
60
70
s
NO BUNCH SIGNAL
PRECISION MODE OFF
SYNCHRONOUS
SOUND-IN-SYNC OFF
FRAMES SELECTED 1
Figure 102. PAL Luma
REV. B
–73–
ADV7330
APPENDIX 8—VIDEO STANDARDS
0HDATUM
SMPTE274M
ANALOG WAVEFORM
DIGITAL HORIZONTAL BLANKING
*1
4T
272T
4T
1920T
EAV CODE
ANCILLARY DATA
(OPTIONAL) OR BLANKING CODE
SAV CODE
DIGITAL
ACTIVE LINE
F
F
INPUT PIXELS
0
0
0 F
0 V
H*
4 CLOCK
SAMPLE NUMBER
2112
C
0 F C
0 V b Y r
H*
F 0
F 0
C
Y
r
4 CLOCK
0
2199
2116 2156
44
188
192
2111
*FVH = FVH AND PARITY BITS
SAV/EAV: LINE 1–562: F = 0
SAV/EAV: LINE 563–1125: F = 1
SAV/EAV: LINE 1–20; 561–583; 1124–1125: V = 1
SAV/EAV: LINE 21–560; 584–1123: V = 0
FOR A FIELD RATE OF 30Hz: 40 SAMPLES
FOR A FIELD RATE OF 25Hz: 480 SAMPLES
Figure 103. EAV/SAV Input Data Timing Diagram—SMPTE 274M
SMPTE293M
ANALOG WAVEFORM
ANCILLARY DATA
(OPTIONAL)
EAV CODE
F
F
INPUT PIXELS
0
0
0
0
F
V
H*
F
F
4 CLOCK
SAMPLE NUMBER
719
DIGITAL
ACTIVE LINE
SAV CODE
0
0
F
0
V
0
H*
C
C
b Y r
C
Y r
Y
4 CLOCK
723 736
0HDATUM
799
853
857
0
719
DIGITAL HORIZONTAL BLANKING
*FVH = FVH AND PARITY BITS
SAV: LINE 43–525 = 200H
SAV: LINE 1–42 = 2AC
EAV: LINE 43–525 = 274H
EAV: LINE 1–42 = 2D8
Figure 104. EAV/SAV Input Data Timing Diagram—SMPTE 293M
–74–
REV. B
ADV7330
ACTIVE
VIDEO
522
523
ACTIVE
VIDEO
VERTICAL BLANK
524
525
1
2
5
6
7
8
9
12
13
14
15
16
42
43
44
Figure 105. SMPTE 293M (525p)
ACTIVE
VIDEO
622
623
ACTIVE
VIDEO
VERTICAL BLANK
624
625
1
2
4
5
6
7
8
9
10
11
12
13
43
44
45
Figure 106. ITU-R BT.1358 (625p)
DISPLAY
VERTICAL BLANKING INTERVAL
747
748
749
750
1
2
3
4
5
6
7
8
25
26
27
744
745
Figure 107. SMPTE 296M (720p)
DISPLAY
VERTICAL BLANKING INTERVAL
FIELD 1
1124
1125
1
2
3
4
5
6
7
8
20
21
22
560
DISPLAY
VERTICAL BLANKING INTERVAL
FIELD 2
561
562
563
564
565
566
567
568
569
570
Figure 108. SMPTE 274M (1080i)
REV. B
–75–
583
584
585
1123
ADV7330
OUTLINE DIMENSIONS
64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
0.75
0.60
0.45
12.00 BSC
SQ
1.60
MAX
64
49
1
48
SEATING
PLANE
PIN 1
10.00
BSC SQ
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.15
0.05
10ⴗ
6ⴗ
2ⴗ
SEATING
PLANE
0.20
0.09
C03750–0–7/04(B)
Dimensions shown in millimeters
VIEW A
7ⴗ
3.5ⴗ
0ⴗ
0.08 MAX
COPLANARITY
16
33
32
17
0.50
BSC
VIEW A
ROTATED 90ⴗ CCW
0.27
0.22
0.17
COMPLIANT TO JEDEC STANDARDS MS-026BCD
Revision History
Location
Page
7/04—Data sheet changed from REV. A to REV. B.
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Changes to PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5/04—Data sheet changed from REV. 0 to REV. A.
Changes to Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Change to Mode Register 0, SD Sync and HD Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Removed Footnote 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Change to HD Mode Register 5, Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Removed Footnote 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Change to Register 43h, Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Change to Figure 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Change to Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Changes to Figures 105 and 106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
–76–
REV. B