AMC1204 SBAS512A – APRIL 2011 – REVISED APRIL 2011 www.ti.com 20MHz, Second-Order, Isolated Delta-Sigma Modulator for Current-Shunt Measurement Check for Samples: AMC1204 FEATURES DESCRIPTION • The AMC1204 is a 1-bit digital output, isolated delta-sigma (ΔΣ) modulator that can be clocked at up to 20MHz. The digital isolation of the modulator output is provided by a silicon dioxide (SiO2) barrier that is highly resistant to magnetic interference. This barrier has been certified to provide basic galvanic isolation of up to 4000VPEAK according to UL1577, IEC60747-5-2, and CSA standards or specifications. 1 2 • • • • • • • ±250mV Input Voltage Range Optimized for Shunt Resistors Certified Digital Isolation: – CSA, IEC60747-5-2, and UL1577 Approved – Isolation Voltage: 4000VPEAK – Working Voltage: 1200VPEAK – Transient Immunity: 15kV/µs Long Isolation Barrier Lifetime (see Application Report SLLA197) High Electromagnetic Field Immunity (see Application Note SLLA181A) Outstanding AC Performance: – SNR: 84dB (min) – THD: –80dB (max) Excellent DC Precision: – INL: ±8LSB (max) – Gain Error: ±2% (max) External Clock Input for Easier Synchronization Fully Specified Over the Extended Industrial Temperature Range The AMC1204 provides a single-chip solution for measuring the small signal of a shunt resistor across an isolated barrier. These types of resistors are typically used to sense currents in motor control inverters, green energy generation systems, and other industrial applications. The AMC1204 differential inputs easily connect to the shunt resistor or other low-level signal sources. An internal reference eliminates the need for external components. When used with an appropriate external digital filter, an effective number of bits (ENOB) of 14 is achieved at a data rate of 78kSPS. A 5V analog supply (AVDD) is used by the modulator while the isolated digital interface operates from a 3V, 3.3V, or 5V supply (DVDD). The AMC1204 is available in an SO-16 (DW) package and is specified from –40°C to +105°C. APPLICATIONS • Shunt Resistor Based Current Sensing in: – Motor Control – Green Energy – Inverter Applications – Uninterruptible Power Supplies AVDD DS Modulator 2.5V Ref AGND Isolation Barrier VINP VINN DVDD DATA CLKIN DGND 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated AMC1204 SBAS512A – APRIL 2011 – REVISED APRIL 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder on www.ti.com. FAMILY OVERVIEW PART NUMBER MODULATOR CLOCK (MHz) DIGITAL SUPPLY CLOCK SOURCE INL (LSB) GAIN ERROR (%) THD (dB) AMC1203 10 5V Internal ±9 ±2 –84.5 AMC1203B 10 5V Internal ±6 ±1 –88 AMC1204 20 3V, 3.3V, or 5V External ±8 ±2 –80 ABSOLUTE MAXIMUM RATINGS (1) Over the operating ambient temperature range, unless otherwise noted. AMC1204 PARAMETER Supply voltage, AVDD to AGND or DVDD to DGND MIN MAX UNIT –0.3 +6 V V Analog input voltage at VINP, VINN AGND – 0.5 AVDD + 0.5 Digital input voltage at CLKIN DGND – 0.3 DVDD + 0.3 V –10 +10 mA Input current to any pin except supply pins +150 °C –40 +125 °C Human body model (HBM) JEDEC standard 22, test method A114-C.01 –3000 +3000 V Charged device model (CDM) JEDEC standard 22, test method C101 –1500 +1500 V Machine model (MM) JEDEC standard 22, test method A115A –200 +200 V Maximum virtual junction temperature, TJ Operating ambient temperature range, TOA Electrostatic discharge (ESD), all pins (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. THERMAL INFORMATION AMC1204 THERMAL METRIC (1) DW UNITS 16 PINS θJA Junction-to-ambient thermal resistance 78.5 θJCtop Junction-to-case (top) thermal resistance 41.3 θJB Junction-to-board thermal resistance 50.2 ψJT Junction-to-top characterization parameter 11.5 ψJB Junction-to-board characterization parameter 41.2 θJCbot Junction-to-case (bottom) thermal resistance n/a (1) 2 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): AMC1204 AMC1204 SBAS512A – APRIL 2011 – REVISED APRIL 2011 www.ti.com REGULATORY INFORMATION VDE/IEC CSA UL Certified according to IEC 60747-5-2 Approved under CSA component acceptance notice Recognized under 1577 component recognition program File number: 40016131 File number: 2350550 File number: E181974 IEC SAFETY LIMITING VALUES Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output (I/O) circuitry. A failure of the I/O circuitry can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. The safety-limiting constraint is the operating virtual junction temperature range specified in the Absolute Maximum Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determine the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages and is conservative. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. PARAMETER IS Safety input, output, or supply current TC Maximum case temperature TEST CONDITIONS MIN TYP MAX θJA = +78.5°C/W, VI = 5.5V, TJ = +150°C, TA = +25°C UNIT 10 mA +150 °C IEC 61000-4-5 RATINGS PARAMETER VIOSM Surge immunity TEST CONDITIONS 1.2/50μs voltage surge and 8/20μs current surge VALUE UNIT ±4000 V IEC 60664-1 RATINGS PARAMETER TEST CONDITIONS SPECIFICATION Basic isolation group Material group II Installation classification Rated mains voltage ≤ 150VRMS I-IV Rated mains voltage < 300VRMS I-IV Rated mains voltage < 400VRMS I-III Rated mains voltage < 600VRMS I-III Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): AMC1204 3 AMC1204 SBAS512A – APRIL 2011 – REVISED APRIL 2011 www.ti.com ISOLATION CHARACTERISTICS VALUE UNIT VIORM Maximum working insulation voltage per IEC PARAMETER TEST CONDITIONS 1200 VPEAK VPD(t) Partial discharge test voltage per IEC t = 1s (100% production test), partial discharge < 5pC 2250 VPEAK VIOTM Transient overvoltage t = 60s (qualification test) 4000 VPEAK t = 1s (100% production test) 4000 VPEAK RS Isolation resistance VIO = 500V at TS > 109 Ω PD Pollution degree 2 Degrees ISOLATOR CHARACTERISTICS (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT L(I01) Minimum air gap (clearance) Shortest terminal to terminal distance through air L(I02) Minimum external tracking (creepage) Shortest terminal to terminal distance across the package surface CTI Tracking resistance (comparative tracking index) DIN IEC 60112/VDE 0303 part 1 ≥ 175 V Minimum internal gap (internal clearance) Distance through the insulation 0.014 mm RIO Isolation resistance 7.9 mm 7.9 mm Input to output, VIO = 500V, all pins on each side of the barrier tied together to create a two-terminal device, TA < +85°C > 1012 Ω Input to output, VIO = 500V, +100°C ≤ TA < TA max > 1011 Ω CIO Barrier capacitance input to output VI = 0.8VPP at 1MHz 1.2 pF CI Input capacitance to ground VI = 0.8VPP at 1MHz 3 pF (1) 4 Creepage and clearance requirements should be applied according to the specific equipment isolation standards of a specific application. Care should be taken to maintain the creepage and clearance distance of the board design to ensure that the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal according to the measurement techniques shown in the Isolation Glossary section. Techniques such as inserting grooves and/or ribs on the PCB are used to help increase these specifications. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): AMC1204 AMC1204 SBAS512A – APRIL 2011 – REVISED APRIL 2011 www.ti.com ELECTRICAL CHARACTERISTICS All minimum/maximum specifications at TA = –40°C to +105°C, AVDD = 4.5V to 5.5V, DVDD = 2.7V to 5.5V, VINP = –250mV to +250mV, VINN = 0V, and sinc3 filter with OSR = 256, unless otherwise noted. Typical values are at TA = +25°C, AVDD = 5V, and DVDD = 3.3V. AMC1204 PARAMETER TA TEST CONDITIONS MIN TYP –40 Specified ambient temperature range MAX UNIT +105 °C RESOLUTION Resolution 16 Bits DC ACCURACY TA = –40°C to +85°C –8 ±2 8 LSB TA = –40°C to +105°C -16 ±5 16 LSB 1 LSB INL Integral linearity error (1) DNL Differential nonlinearity –1 VOS Offset error (2) –1 ±0.1 1 TCVOS Offset error thermal drift –3.5 ±1 3.5 GERR Gain error (2) –2 ±0.5 2 TCGERR Gain error thermal drift PSRR Power-supply rejection ratio mV μV/°C % ±30 ppm/°C 79 dB ANALOG INPUTS FSR Full-scale differential voltage input range VINP – VINN Specified FSR VCM Operating common-mode signal (3) CI Input capacitance to AGND CID Differential input capacitance RID Differential input resistance IIL Input leakage current CMTI Common-mode transient immunity CMRR Common-mode rejection ratio ±320 mV –250 250 AGND AVDD VINP or VINN mV V 7 pF 3.5 pF 12.5 kΩ VINP – VINN = ±250mV –10 10 VINP – VINN = ±320mV -50 50 15 μA μA kV/μs VIN from 0V to 5V at 0Hz 108 dB VIN from 0V to 5V at 100kHz 114 dB EXTERNAL CLOCK tCLKIN Clock period fCLKIN Input clock frequency DutyCLKIN Duty cycle 45.5 50 200 ns 5 20 22 MHz 5MHz ≤ fCLKIN < 20MHz 40 50 60 % 20MHz ≤ fCLKIN ≤ 22MHz 45 50 55 % fIN = 1kHz, TA = –40°C to +85°C 78 87 dB fIN = 1kHz, TA = –40°C to +105°C 70 87 dB fIN = 1kHz, TA = –40°C to +85°C 84 88 dB fIN = 1kHz, TA = –40°C to +105°C 83 88 AC ACCURACY SINAD SNR Signal-to-noise + distortion Signal-to-noise ratio THD Total harmonic distortion SFDR Spurious-free dynamic range dB fIN = 1kHz, TA = –40°C to +85°C –96 –80 dB fIN = 1kHz, TA = –40°C to +105°C -96 -70 dB fIN = 1kHz, TA = –40°C to +85°C 82 96 dB fIN = 1kHz, TA = –40°C to +105°C 72 96 dB DIGITAL INPUTS (3) IIN Input current CIN Input capacitance VIN = DVDD to DGND –10 10 5 CMOS logic family μA pF CMOS with Schmitt-trigger VIH High-level input voltage DVDD = 4.5V to 5.5V 0.7DVDD DVDD + 0.3 V VIL Low-level input voltage DVDD = 4.5V to 5.5V –0.3 0.3DVDD V (1) (2) (3) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as number of LSBs or as a percent of the specified 560mV input range. Maximum values, including temperature drift, are ensured over the full specified temperature range. Ensured by design. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): AMC1204 5 AMC1204 SBAS512A – APRIL 2011 – REVISED APRIL 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All minimum/maximum specifications at TA = –40°C to +105°C, AVDD = 4.5V to 5.5V, DVDD = 2.7V to 5.5V, VINP = –250mV to +250mV, VINN = 0V, and sinc3 filter with OSR = 256, unless otherwise noted. Typical values are at TA = +25°C, AVDD = 5V, and DVDD = 3.3V. AMC1204 PARAMETER TEST CONDITIONS MIN LVCMOS logic family TYP MAX UNIT LVCMOS VIH High-level input voltage DVDD = 2.7V to 3.6V 2 DVDD + 0.3 V VIL Low-level input voltage DVDD = 2.7V to 3.6V –0.3 0.8 V DIGITAL OUTPUTS (3) COUT Output capacitance CLOAD Load capacitance 5 CMOS logic family High-level output voltage DVDD = 4.5V, IOH = –100µA VOL Low-level output voltage DVDD = 4.5V, IOL = +100µA 4.4 VOL Low-level output voltage V 0.5 LVCMOS logic family High-level output voltage V CMOS VOH VOH V 30 V LVCMOS IOH = 20µA DVDD – 0.1 V IOH = –4mA, 2.7V ≤ DVDD ≤ 3.6V DVDD – 0.4 V IOH = –4mA, 4.5V ≤ DVDD ≤ 5.5V DVDD – 0.8 V IOL = 20µA 0.1 V IOL = 4mA 0.4 V V POWER SUPPLY AVDD High-side supply voltage 4.5 5 5.5 DVDD Controller-side supply voltage 2.7 3.3 5.5 V IAVDD High-side supply current 11 16 mA IDVDD Controller-side supply current 2.7V ≤ DVDD ≤ 3.6V 2 4 mA 4.5V ≤ DVDD ≤ 5.5V 2.8 5 mA PD Power dissipation 61.6 102.4 mW 6 4.5V ≤ AVDD ≤ 5.5V AVDD = 5.5V, DVDD = 3.6V Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): AMC1204 AMC1204 SBAS512A – APRIL 2011 – REVISED APRIL 2011 www.ti.com PIN CONFIGURATION DW PACKAGE TSSOP-16 (TOP VIEW) AVDD 1 16 DGND VINP 2 15 NC VINN 3 14 DVDD AGND 4 13 CLKIN (1) 5 12 NC NC 6 11 DATA NC 7 10 NC AGND 8 9 NC DGND (1) NC = no internal connection. PIN DESCRIPTIONS PIN NAME PIN# FUNCTION DESCRIPTION AVDD 1 Power VINP 2 Analog input Noninverting analog input Inverting analog input High-side power supply VINN 3 Analog input AGND 4, 8 (1) Power High-side ground DGND 9, 16 Power Controller-side ground DATA 11 CLKIN 13 Digital input DVDD 14 Power NC 5, 6, 7, 10, 12, 15 — (1) Digital output Modulator data output Modulator clock input Controller-side power supply No internal connection; can be tied to any potential or left unconnected Both pins are connected internally via a low-impedance path; thus, only one of the pins must be tied to the ground plane. TIMING INFORMATION tCLK tHIGH CLKIN tLOW tD DATA Figure 1. Modulator Output Timing TIMING CHARACTERISTICS FOR Figure 1 Over recommended ranges of supply voltage and operating free-air temperature, unless otherwise noted. PARAMETER MIN TYP MAX UNIT 45.5 50 200 ns CLKIN clock high time 20 25 120 ns tLOW CLKIN clock low time 20 25 120 ns tD Delayed falling edge of CLKIN to DATA valid 15 ns tCLK CLKIN clock period tHIGH 2 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): AMC1204 7 AMC1204 SBAS512A – APRIL 2011 – REVISED APRIL 2011 www.ti.com TYPICAL CHARACTERISTICS At AVDD = 5V, DVDD = 3.3V, VINP = –250mV to +250mV, VINN = 0V, and sinc3 filter with OSR = 256, unless otherwise noted. INTEGRAL NONLINEARITY vs INPUT SIGNAL AMPLITUDE INTEGRAL NONLINEARITY vs TEMPERATURE 8 7 5 INL (LSB) INL (LSB) 6 4 3 2 1 0 −250 −200 −150 −100 −50 0 50 100 Input Signal Amplitude (mV) 150 200 250 16 14 12 10 8 6 4 2 0 −2 −4 −6 −8 −10 −12 −14 −16 −40 −25 −10 5 Figure 2. 0.8 0.8 0.6 0.6 0.4 0.4 Offset Error (mV) Offset Error (mV) 1 0.2 0 −0.2 −0.4 0 −0.2 −0.4 −0.6 −0.8 −0.8 5 AVDD (V) −1 −40 −25 −10 5.5 5 Figure 4. 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0 95 110 125 −0.2 −0.4 0.2 0 −0.2 −0.4 −0.6 −0.6 −0.8 −0.8 20 25 −1 40 Figure 6. 8 80 OFFSET ERROR vs CLOCK DUTY CYCLE 1 Offset Error (mV) Offset Error (mV) OFFSET ERROR vs CLOCK FREQUENCY 15 Clock Freuency (MHz) 20 35 50 65 Temperature (°C) Figure 5. 1 10 110 125 0.2 −0.6 5 95 OFFSET ERROR vs TEMPERATURE 1 −1 80 Figure 3. OFFSET ERROR vs ANALOG SUPPLY VOLTAGE −1 4.5 20 35 50 65 Temperature (°C) 45 50 Clock Duty Cycle (%) 55 60 Figure 7. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): AMC1204 AMC1204 SBAS512A – APRIL 2011 – REVISED APRIL 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At AVDD = 5V, DVDD = 3.3V, VINP = –250mV to +250mV, VINN = 0V, and sinc3 filter with OSR = 256, unless otherwise noted. GAIN ERROR vs TEMPERATURE 2 1.5 1.5 1 1 Gain Error (%) Gain Error (%) GAIN ERROR vs ANALOG SUPPLY VOLTAGE 2 0.5 0 −0.5 0.5 0 −0.5 −1 −1 −1.5 −1.5 −2 4.5 5 AVDD (V) −2 −40 −25 −10 5.5 5 Figure 8. 1.5 1.5 1 1 0.5 0 −0.5 110 125 0.5 0 −0.5 −1 −1 −1.5 −1.5 10 95 GAIN ERROR vs CLOCK DUTY CYCLE 2 Gain Error (%) Gain Error (%) GAIN ERROR vs CLOCK FREQUENCY 5 80 Figure 9. 2 −2 20 35 50 65 Temperature (°C) 15 20 Clock Frequency (MHz) −2 25 40 45 50 Clock Duty Cycle (%) 55 Figure 10. Figure 11. POWER-SUPPLY REJECTION RATIO vs FREQUENCY COMMON-MODE REJECTION RATIO vs INPUT SIGNAL FREQUENCY 100 60 140 130 Unfiltered sinc3, OSR = 256 90 CMRR (dB) PSRR (dB) 120 80 110 100 70 90 60 0.1 1 10 100 80 0.1 Frequency (kHz) Figure 12. 1 10 100 Input Signal Frequency (kHz) 1000 Figure 13. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): AMC1204 9 AMC1204 SBAS512A – APRIL 2011 – REVISED APRIL 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At AVDD = 5V, DVDD = 3.3V, VINP = –250mV to +250mV, VINN = 0V, and sinc3 filter with OSR = 256, unless otherwise noted. SINAD AND SNR vs ANALOG SUPPLY VOLTAGE SINAD AND SNR vs TEMPERATURE 100 100 SINAD SNR 90 SINAD and SNR (dB) SINAD and SNR (dB) SINAD SNR 80 70 60 4.5 5 AVDD (V) 90 80 70 60 −40 −25 −10 5.5 5 Figure 14. 20 35 50 65 Temperature (°C) 80 95 110 125 Figure 15. SINAD AND SNR vs INPUT SIGNAL FREQUENCY SINAD AND SNR vs INPUT SIGNAL AMPLITUDE 100 100 SINAD SNR SINAD SNR 90 SINAD and SNR (dB) SINAD & SNR (dB) 80 90 80 70 70 60 50 40 30 20 10 60 0.1 1 10 Input Signal Frequency (kHz) 0 0.1 100 1 10 100 Input Signal Amplitude (mVpp) Figure 16. Figure 17. SINAD AND SNR vs CLOCK FREQUENCY SINAD AND SNR vs CLOCK DUTY CYCLE 100 100 SINAD SNR 90 SINADand SNR (dB) SINAD and SNR (dB) SINAD SNR 80 70 60 5 10 15 20 Clock Frequency (MHz) 25 90 80 70 60 40 Figure 18. 10 1000 45 50 Clock Duty Cycle (%) 55 60 Figure 19. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): AMC1204 AMC1204 SBAS512A – APRIL 2011 – REVISED APRIL 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At AVDD = 5V, DVDD = 3.3V, VINP = –250mV to +250mV, VINN = 0V, and sinc3 filter with OSR = 256, unless otherwise noted. TOTAL HARMONIC DISTORTION vs TEMPERATURE −60 −60 −70 −70 −80 −80 THD (dB) THD (dB) TOTAL HARMONIC DISTORTION vs ANALOG SUPPLY VOLTAGE −90 −90 −100 −100 −110 −110 −120 4.5 5 AVDD (V) −120 −40 −25 −10 5.5 5 20 35 50 65 Temperature (°C) 80 95 Figure 20. Figure 21. TOTAL HARMONIC DISTORTION vs INPUT SIGNAL FREQUENCY TOTAL HARMONIC DISTORTION vs INPUT SIGNAL AMPLITUDE −60 110 125 0 −10 −70 −20 −30 −40 THD (dB) THD (dB) −80 −90 −50 −60 −70 −100 −80 −110 −100 −90 −110 1 10 Input Signal Frequency (kHz) −120 0.1 100 Figure 23. TOTAL HARMONIC DISTORTION vs CLOCK FREQUENCY TOTAL HARMONIC DISTORTION vs CLOCK DUTY CYCLE −60 −60 −70 −70 −80 −80 −90 −100 −110 −110 5 10 15 20 Clock Frequency (MHz) 25 1000 −90 −100 −120 1 10 100 Input Signal Amplitude (mVpp) Figure 22. THD (dB) THD (dB) −120 0.1 −120 40 Figure 24. 45 50 Clock Duty Cycle (%) 55 60 Figure 25. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): AMC1204 11 AMC1204 SBAS512A – APRIL 2011 – REVISED APRIL 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At AVDD = 5V, DVDD = 3.3V, VINP = –250mV to +250mV, VINN = 0V, and sinc3 filter with OSR = 256, unless otherwise noted. SPURIOUS-FREE DYNAMIC RANGE vs TEMPERATURE 120 120 110 110 100 100 SFDR (dB) SFDR (dB) SPURIOUS-FREE DYNAMIC RANGE vs ANALOG SUPPLY VOLTAGE 90 90 80 80 70 70 60 4.5 5 AVDD (V) 60 −40 −25 −10 5.5 5 20 35 50 65 Temperature (°C) 80 95 Figure 26. Figure 27. SPURIOUS-FREE DYNAMIC RANGE vs INPUT SUGNAL FREQUENCY SPURIOUS-FREE DYNAMIC RANGE vs INPUT SIGNAL AMPLITUDE 120 110 125 120 110 110 100 90 80 SFDR (dB) SFDR (dB) 100 90 80 70 60 50 40 30 70 20 10 1 10 Input Signal Frequency (kHz) 0 0.1 100 Figure 29. SPURIOUS-FREE DYNAMIC RANGE vs CLOCK FREQUENCY SPURIOUS-FREE DYNAMIC RANGE vs CLOCK DUTY CYCLE 120 120 110 110 100 100 90 80 70 70 5 10 15 20 Clock Frequency (MHz) 25 60 40 Figure 30. 12 1000 90 80 60 1 10 100 Input Signal Amplitude (mVpp) Figure 28. SFDR (dB) SFDR (dB) 60 0.1 45 50 Clock Duty Cycle (%) 55 60 Figure 31. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): AMC1204 AMC1204 SBAS512A – APRIL 2011 – REVISED APRIL 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At AVDD = 5V, DVDD = 3.3V, VINP = –250mV to +250mV, VINN = 0V, and sinc3 filter with OSR = 256, unless otherwise noted. FREQUENCY SPECTRUM (4096 point FFT, fIN = 5kHz, 056VPP) 0 0 -20 -20 -40 -40 Magnitude (dB) Magnitude (dB) FREQUENCY SPECTRUM (4096 point FFT, fIN = 1kHz, 056VPP) -60 -80 -60 -80 -100 -100 -120 -120 -140 -140 0 5 10 15 20 25 30 35 40 0 15 20 25 Figure 32. Figure 33. 16 14 14 12 12 10 10 8 6 35 6 4 2 2 0 −40 −25 −10 5.5 5 20 35 50 65 Temperature (°C) 80 95 Figure 34. Figure 35. ANALOG SUPPLY CURRENT vs CLOCK FREQUENCY DIGITAL SUPPLY CURRENT vs DIGITAL SUPPLY VOLTAGE (3V) 16 14 14 12 12 IDVDD (mA) 16 10 8 6 8 6 4 2 2 5 10 15 20 Clock Frequency (MHz) 25 110 125 10 4 0 40 8 4 5 AVDD (V) 30 ANALOG SUPPLY CURRENT vs TEMPERATURE 16 IAVDD (mV) IAVDD (mA) IAVDD (mA) 10 Frequency (kHz) ANALOG SUPPLY CURRENT vs ANALOG SUPPLY VOLTAGE 0 4.5 5 Frequency (kHz) 0 2.7 3 3.3 3.6 DVDD (V) Figure 36. Figure 37. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): AMC1204 13 AMC1204 SBAS512A – APRIL 2011 – REVISED APRIL 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At AVDD = 5V, DVDD = 3.3V, VINP = –250mV to +250mV, VINN = 0V, and sinc3 filter with OSR = 256, unless otherwise noted. DIGITAL SUPPLY CURRENT vs TEMPERATURE 16 16 14 14 12 12 IDVDD (mA) IDVDD (mA) DIGITAL SUPPLY CURRENT vs DIGITAL SUPPLY VOLTAGE (5V) 10 8 6 10 8 6 4 4 2 2 0 4.5 5 DVDD (V) DVDD = 3.3V DVDD = 5V 0 −40 −25 −10 5.5 5 20 35 50 65 Temperature (°C) Figure 38. 80 95 110 125 Figure 39. DIGITAL SUPPLY CURRENT vs CLOCK FREQUENCY 16 DVDD = 3.3V DVDD = 5V 14 IDVDD (mA) 12 10 8 6 4 2 0 5 10 15 20 Clock Frequency (MHz) 25 Figure 40. 14 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): AMC1204 AMC1204 SBAS512A – APRIL 2011 – REVISED APRIL 2011 www.ti.com GENERAL DESCRIPTION The AMC1204 is a single-channel, second-order, delta-sigma (ΔΣ) modulator designed for medium- to high-resolution analog-to-digital conversions. The isolated output of the converter (DATA) provides a stream of digital ones and zeros. The time average of this serial output is proportional to the analog input voltage. Figure 41 shows a detailed block diagram of the AMC1204. The analog input range is tailored to directly accommodate a voltage drop across a shunt resistor used for current sensing. The SiO2-based capacitive isolation barrier supports a high level of magnetic field immunity as described in the application report ISO72x Digital Isolator Magnetic-Field Immunity (SLLA181A, available for download at www.ti.com). The external clock input simplifies the synchronization of multiple current sense channels on system level. The extended frequency range of up to 20MHz supports higher performance levels compared to the other solutions available on the market. Isolation Barrier 2nd-Order DS Modulator VINN + Interface Circuit VINP VREF + 3-State Output Buffer DATA - POR + Buffer VREF 2.5V VREF CLKIN + - Figure 41. Detailed Block Diagram Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): AMC1204 15 AMC1204 SBAS512A – APRIL 2011 – REVISED APRIL 2011 www.ti.com THEORY OF OPERATION The differential analog input of the AMC1204 is implemented with a switched-capacitor circuit. This switched-capacitor circuit implements a second-order modulator stage that digitizes the input signal into a 1-bit output stream. The externally-provided clock source at the CLKIN pin is used by the capacitor circuit and the modulator and should be in the range of 5MHz to 22MHz. The analog input signal is continuously sampled by the modulator and compared to an internal voltage reference. A digital stream, accurately representing the analog input voltage over time, appears at the output of the converter at the DATA pin. ANALOG INPUT The AMC1204 measures the differential input signal VIN = (VINP – VINN) against the internal reference of 2.5V using internal capacitors that are continuously charged and discharged. Figure 42 shows the simplified schematic of the ADC input circuitry; the right side of Figure 42 illustrates the input circuitry with the capacitors and switches replaced by an equivalent circuit. In Figure 42, the S1 switches close during the input sampling phase. With the S1 switches closed, CDIFF charges to the voltage difference across VINP and VINN. For the discharge phase, both S1 switches open first and then both S2 switches close. CDIFF discharges approximately to AGND + 0.8V during this phase. This two-phase sample/discharge cycle repeats with a period of tCLKIN = 1/fCLKIN. fCLKIN is the operating frequency of the modulator. The capacitors CIP and CIN are of parasitic nature and caused by bonding wires and the internal ESD protection structure. AVDD AGND AGND CIP = 3pF 3pF 200W VINP S1 S2 Equivalent Circuit AGND + 0.8V VINP REFF = 12.5kW CDIFF = 4pF S1 VINN 200W S2 VINN AGND + 0.8V 3pF CIN = 3pF AGND AGND REFF = 1 fCLKIN ´ CDIFF AGND (fCLKIN = 20MHz) Figure 42. Equivalent Analog Input Circuit The input impedance becomes a consideration in designs with high input signal source impedance. This high impedance may cause degradation in gain, linearity, and THD. The importance of this effect, however, depends on the desired system performance. This input stage provides the mechanism to achieve low system noise, high common-mode rejection (105dB), and excellent power-supply rejection. There are two restrictions on the analog input signals VINP and VINN. First, if the input voltage exceeds the range AGND – 0.5V to AVDD + 0.3V, the input current must be limited to 10mA because the input protection diodes on the front end of the converter begin to turn on. In addition, the linearity and the noise performance of the device are ensured only when the differential analog input voltage remains within ±250mV. 16 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): AMC1204 AMC1204 SBAS512A – APRIL 2011 – REVISED APRIL 2011 www.ti.com MODULATOR The modulator topology of the AMC1204 is fundamentally a second-order, switched-capacitor, ΔΣ modulator, such as the one conceptualized in Figure 43. The analog input voltage (X(t)) and the output of the 1-bit digital-to-analog converter (DAC) are differentiated, providing an analog voltage (X2) at the input of the first integrator or modulator stage. The output of the first integrator is further differentiated with the DAC output; the resulting voltage (X3) feeds the input of the second integrator stage. When the value of the integrated signal (X4) at the output of the second stage equals the comparator reference voltage, the output of the comparator switches from high to low, or vice versa, depending on its previous state. In this case, the 1-bit DAC responds on the next clock pulse by changing its analog output voltage (X6), causing the integrators to progress in the opposite direction, while forcing the value of the integrator output to track the average of the input. fCLK X(t) X2 X3 Integrator 1 Integrator 2 X4 DATA fS VREF Comparator X6 DAC Figure 43. Block Diagram of a Second-Order Modulator The modulator shifts the quantization noise to high frequencies, as shown in Figure 44; therefore, a low-pass digital filter should be used at the output of the device to increase the overall performance. This filter is also used to convert from the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). A digital signal processor (DSP), microcontroller (µC), or field programmable gate array (FPGA) can be used to implement the filter. Another option is to use a suitable application-specific device such as the AMC1210, a four-channel digital sinc-filter. 0 Magnitude (dB) -20 -40 -60 -80 -100 -120 -140 10 100 1k 10k 100k 1G 10G Frequency (Hz) Figure 44. Quantization Noise Shaping Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): AMC1204 17 AMC1204 SBAS512A – APRIL 2011 – REVISED APRIL 2011 www.ti.com DIGITAL OUTPUT A differential input signal of 0V ideally produces a stream of ones and zeros that are high 50% of the time and low 50% of the time. A differential input of +250mV produces a stream of ones and zeros that are high 78.1% of the time. A differential input of –250mV produces a stream of ones and zeros that are high 21.9% of the time. This is also the specified linear input range of the modulator with the performance as specified in this data sheet. The range between 250mV and 320mV (absolute values) is the non-linear range of the modulator. The output of the modulator clipps with a stream of only zeros with an input less than or equal to –320mV or with a stream of only ones with an input greater than or equal to 320mV. The input voltage versus the output modulator signal is shown in Figure 45. The system clock of the AMC1204 is typically 20MHz and is provided externally at the CLKIN pin. The data are synchronously provided at 20MHz at the DATA output pin. The data are changing at the falling edge of CLKIN; for more details see the Timing Information section. Modulator Output +FS (Analog Input) -FS (Analog Input) Analog Input Figure 45. Analog Input versus AMC1204 Modulator Output FILTER USAGE The modulator generates a bit stream that is processed by a digital filter to obtain a digital word similar to a conversion result of a conventional analog-to-digital converter (ADC). A very simple filter, built with minimal effort and hardware, is a sinc3-type filter, as shown in Equation 1: 3 H(z) = 1 - z-OSR 1 - z-1 (1) This filter provides the best output performance at the lowest hardware size (count of digital gates). For an oversampling rate (OSR) in the range of 16 to 256, this filter is a good choice. All the characterization in this document is also done with a sinc3 filter with OSR = 256 and an output word width of 16 bits. 18 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): AMC1204 AMC1204 SBAS512A – APRIL 2011 – REVISED APRIL 2011 www.ti.com In a sinc3 filter response (shown in Figure 46 and Figure 47), the location of the first notch occurs at the frequency of output data rate fDATA = fCLK/OSR. The –3dB point is located at half the Nyquist frequency or fDATA/4. For some applications, it may be necessary to use another filter type with different frequency response. Performance can be improved, for example, by using a cascaded filter structure. The first decimation stage could be built of a sinc3 filter with a low OSR and the second stage using a high-order filter. 0 30k fDATA = 20MHz/64 = 312.5kHz -3dB: 81.9kHz OSR = 64 -10 Output Code Gain (dB) -20 -30 -40 -50 fMOD = 20MHz OSR = 64 FSR = 32768 ENOB = 12 Bits Settling Time = 3 ´ 1/fDATA = 9.6ms 25k 20k 15k 10k -60 5k -70 0 -80 0 200 400 600 800 1000 Frequency (kHz) 1200 1400 1600 Figure 46. Frequency Response of the Sinc3 Filter 0 5 10 15 20 25 30 Number of Output Clocks 35 40 Figure 47. Pole Response of the Sinc3 Filter The effective number of bits (ENOB) is often used to compare the performance of ADCs and ΔΣ modulators. Figure 48 illustrates the ENOB of the AMC1204 with different oversampling ratios. In this data sheet, this number is calculated from SNR using Equation 2: SNR = 1.76dB + 6.02dB ´ ENOB (2) In motor control applications, a very fast response time for overcurrent detection is required. The time for fully settling the filter depends on its order; that is, a sinc3 filter requires three data clocks for full settling (with fDATA = fCLK/OSR). Therefore, for overcurrent protection, filter types other than sinc3 might be a better choice; an alternative is the sinc2 filter. Figure 49 compares the settling times of different filter orders with sincfast being a modified sinc2 filter with behavior as shown in Equation 3. 2 1 - z-OSR (1 + z-2OSR) 1 - z-1 H(z) = (3) 16 16 sinc3 14 14 12 sinc2 ENOB (Bits) ENOB (Bits) 12 sincfast sinc3 sincfast 10 8 6 sinc 1 10 sinc2 8 6 sinc 4 4 2 2 0 1 0 1 10 100 1000 0 1 OSR Figure 48. Measured Effective Number of Bits versus Oversampling Ratio 2 3 4 5 6 7 8 9 Settling Time (ms) 10 11 12 13 Figure 49. Measured Effective Number of Bits versus Settling Time Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): AMC1204 19 AMC1204 SBAS512A – APRIL 2011 – REVISED APRIL 2011 www.ti.com An example code for an implementation of a sinc3 filter in an FPGA follows. For more information, see the application note Combining ADS1202 with FPGA Digital Filter for Current Measurement in Motor Control Applications (SBAA094), available for download at www.ti.com. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FLT is port(RESN, MOUT, MCLK, CNR : in std_logic; CN5 : out std_logic_vector(23 downto 0)); end FLT; architecture RTL of FLT is signal DN0, DN1, DN3, DN5 : std_logic_vector(23 downto 0); signal CN1, CN2, CN3, CN4 : std_logic_vector(23 downto 0); signal DELTA1 : std_logic_vector(23 downto 0); begin process(MCLK, RESn) begin if RESn = '0' then DELTA1 <= (others => '0'); elsif MCLK'event and MCLK = '1' then if MOUT = '1' then DELTA1 <= DELTA1 + 1; end if; end if; end process; process(RESN, MCLK) begin if RESN = '0' then CN1 <= (others => '0'); CN2 <= (others => '0'); elsif MCLK'event and MCLK = '1' then CN1 <= CN1 + DELTA1; CN2 <= CN2 + CN1; end if; end process; process(RESN, CNR) begin if RESN = '0' then DN0 <= (others => DN1 <= (others => DN3 <= (others => DN5 <= (others => elsif CNR'event and DN0 <= CN2; DN1 <= DN0; DN3 <= CN3; DN5 <= CN4; end if; end process; '0'); '0'); '0'); '0'); CNR = '1' then CN3 <= DN0 - DN1; CN4 <= CN3 - DN3; CN5 <= CN4 - DN5; end RTL; 20 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): AMC1204 AMC1204 SBAS512A – APRIL 2011 – REVISED APRIL 2011 www.ti.com APPLICATION INFORMATION A typical operation of the AMC1204 in a motor control application is shown in Figure 50. Measurement of the motor phase current is done via the shunt resistor RSHUNT (in this case, a two-terminal shunt). For better performance, the differential signal is filtered using RC filters (components R2, R3, and C2). Optionally, C3 and C4 can be used to reduce charge dumping from the inputs. In this case, care should be taken when choosing the quality of these capacitors—mismatch in values of these capacitors leads to a common-mode error at the input of the modulator. The high-side power supply for the AMC1204 (AVDD) is derived from the power supply of the upper gate driver. For lowest cost, a zener diode can be used to limit the voltage to 5V ±10%. A decoupling capacitor of 0.1µF is recommended for filtering this power-supply path. This capacitor (C1 in Figure 50) should be placed as close as possible to the AVDD pin for best performance. If better filtering is required, an additional 1µF to 10µF capacitor can be used. The floating ground reference AGND is derived from the end of the shunt resistor, which is connected to the negative input of the AMC1204 (VINN). If a four-terminal shunt is used, the inputs of AMC1204 are connected to the inner leads, while AGND is connected to one of the outer leads of the shunt. Both digital signals, CLKIN and DATA, can be directly connected to a digital filter (for example, the AMC1210); see Figure 51. HV+ Floating Power Supply Gated Drive Circuit Isolation Barrier R1 AMC1204 D1 5.1V R3 12W RSHUNT To Load Power Supply AVDD DVDD VINP DATA VINN CLKIN AGND DGND C1(1) 0.1mF R2 12W C2 330pF C3 10pF (optional) C4 10pF (optional) Gated Drive Circuit HV- (1) Place C1 close to the AMC1204. Figure 50. Typical Application Diagram Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): AMC1204 21 AMC1204 SBAS512A – APRIL 2011 – REVISED APRIL 2011 www.ti.com Figure 51 shows an example of two AMC1204s and one ADS1209 (a dual-channel, 10MHz, non-isolated modulator) connected to an AMC1210, building the entire analog front-end of a resolver-based motor control application. For detailed information on the ADS1209 and AMC1210, visit the respective device product folders at www.ti.com. Resolver AMC1210 Control Module PWM1 Signal Generator PWM2 Filter Module 1 Comparator Filter IN1 CLK1 ADS1209 IN2 Sinc Filter/ Integrator Input Control CLK RST Interrupt Unit INT ACK Time Measurement Filter Module 2 CLK2 Current Shunt Resistor Current Shunt Resistor IN3 AMC1204 CLK3 IN4 AMC1204 CLK4 Register Map Interface Module Filter Module 3 CS ALE RD WR M0 M1 AD0 AD7 Filter Module 4 Figure 51. Example of a Resolver-Based Motor Control Analog Front-End 22 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): AMC1204 AMC1204 SBAS512A – APRIL 2011 – REVISED APRIL 2011 www.ti.com A layout recommendation showing the critical placement of the decoupling capacitor on the high-side and placement of the other components required by the AMC1204 is presented in Figure 52. Top View Clearance Area Keep Free of Any Conductive Materials To Shunt 12W SMD 0603 330pF SMD 12W 0603 SMD 0603 0.1mF SMD 1206 AVDD DGND VINP NC VINN DVDD AGND LEGEND AMC1204 CLKIN NC NC NC DATA NC NC AGND DGND 0.1mF SMD 0603 From AMC1210 To AMC1210 Top layer; copper pour and traces High-Side Area Controller-Side Area Via Figure 52. Recommended Layout Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): AMC1204 23 AMC1204 SBAS512A – APRIL 2011 – REVISED APRIL 2011 www.ti.com ISOLATION GLOSSARY Creepage Distance: The shortest path between two conductive input to output leads measured along the surface of the insulation. The shortest distance path is found around the end of the package body. Clearance: The shortest distance between two conductive input to output leads measured through air (line of sight). Input-to-Output Barrier Capacitance: The total capacitance between all input terminals connected together, and all output terminals connected together. Input-to-Output Barrier Resistance: The total resistance between all input terminals connected together, and all output terminals connected together. Primary Circuit: An internal circuit directly connected to an external supply mains or other equivalent source that supplies the primary circuit electric power. Secondary Circuit: A circuit with no direct connection to primary power that derives its power from a separate isolated source. Comparative Tracking Index (CTI): CTI is an index used for electrical insulating materials. It is defined as the numerical value of the voltage that causes failure by tracking during standard testing. Tracking is the process that produces a partially conducting path of localized deterioration on or through the surface of an insulating material as a result of the action of electric discharges on or close to an insulation surface. The higher CTI value of the insulating material, the smaller the minimum creepage distance. Generally, insulation breakdown occurs either through the material, over its surface, or both. Surface failure may arise from flashover or from the progressive degradation of the insulation surface by small localized sparks. Such sparks are the result of the breaking of a surface film of conducting contaminant on the insulation. The resulting break in the leakage current produces an overvoltage at the site of the discontinuity, and an electric spark is generated. These sparks often cause carbonization on insulation material and lead to a carbon track between points of different potential. This process is known as tracking. Insulation: Operational insulation—Insulation needed for the correct operation of the equipment. Basic insulation—Insulation to provide basic protection against electric shock. Supplementary insulation—Independent insulation applied in addition to basic insulation in order to ensure protection against electric shock in the event of a failure of the basic insulation. Double insulation—Insulation comprising both basic and supplementary insulation. Reinforced insulation—A single insulation system that provides a degree of protection against electric shock equivalent to double insulation. 24 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): AMC1204 AMC1204 SBAS512A – APRIL 2011 – REVISED APRIL 2011 www.ti.com Pollution Degree: Pollution Degree 1—No pollution, or only dry, nonconductive pollution occurs. The pollution has no influence on device performance. Pollution Degree 2—Normally, only nonconductive pollution occurs. However, a temporary conductivity caused by condensation is to be expected. Pollution Degree 3—Conductive pollution, or dry nonconductive pollution that becomes conductive because of condensation, occurs. Condensation is to be expected. Pollution Degree 4—Continuous conductivity occurs as a result of conductive dust, rain, or other wet conditions. Installation Category: Overvoltage Category—This section is directed at insulation coordination by identifying the transient overvoltages that may occur, and by assigning four different levels as indicated in IEC 60664. 1. Signal Level: Special equipment or parts of equipment. 2. Local Level: Portable equipment, etc. 3. Distribution Level: Fixed installation. 4. Primary Supply Level: Overhead lines, cable systems. Each category should be subject to smaller transients than the previous category. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): AMC1204 25 AMC1204 SBAS512A – APRIL 2011 – REVISED APRIL 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (April 2011) to Revision A Page • Changed Analog input voltage at VINP, VINN parameter maximum specification in Absolute Maximum Ratings table ..... 2 • Changed Safety input, output, or supply current parameter maximum specification in IEC Safety Limiting Values table ...................................................................................................................................................................................... 3 • Updated Figure 3 .................................................................................................................................................................. 8 • Updated Figure 22 .............................................................................................................................................................. 11 • Updated Figure 28 .............................................................................................................................................................. 12 26 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): AMC1204 PACKAGE OPTION ADDENDUM www.ti.com 5-May-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) AMC1204DW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR AMC1204DWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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