OPA 2130 OPA 130 OPA 130 OPA OPA OPA130 OPA2130 OPA4130 4130 2130 OPA 4130 SBOS053A – MAY 1998 – REVISED MARCH 2006 Low Power, Precision FET-INPUT OPERATIONAL AMPLIFIERS FEATURES OPA130 ● LOW QUIESCENT CURRENT: 530µA/amp ● LOW OFFSET VOLTAGE: 1mV max ● HIGH OPEN-LOOP GAIN: 120dB min ● HIGH CMRR: 90dB min Offset Trim 1 8 NC –In 2 7 V+ +In 3 6 Output V– 4 5 Offset Trim 8 V+ 7 Out B 6 –In B 5 +In B ● FET INPUT: IB = 20pA max ● EXCELLENT BANDWIDTH: 1MHz DIP-8, SO-8 ● WIDE SUPPLY RANGE: ±2.25 to ±18V ● SINGLE, DUAL, AND QUAD VERSIONS OPA2130 DESCRIPTION Out A 1 –In A 2 +In A 3 V– 4 The OPA130 series of FET-input op amps combine precision dc performance with low quiescent current. Single, dual, and quad versions have identical specifications for maximum design flexibility. They are ideal for general-purpose, portable, and battery operated applications, especially with high source impedance. OPA130 op amps are easy to use and free from phase inversion and overload problems often found in common FET-input op amps. Input cascode circuitry provides excellent common-mode rejection and maintains low input bias current over its wide input voltage range. OPA130 series op amps are stable in unity gain and provide excellent dynamic behavior over a wide range of load conditions, including high load capacitance. Dual and quad designs feature completely independent circuitry for lowest crosstalk and freedom from interaction, even when overdriven or overloaded. Single and dual versions are available in DIP-8 and SO-8 surface-mount packages. Quad is available in DIP-14 and SO-14 surface-mount packages. All are specified for –40°C to +85°C operation. A B DIP-8, SO-8 OPA4130 Out A 1 –In A 2 A 14 Out D 13 –In D D +In A 3 12 +In D V+ 4 11 V– +In B 5 10 +In C B C –In B 6 9 –In C Out B 7 8 Out C DIP-14, SO-14 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 1998-2006, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) Supply Voltage, V+ to V– .................................................................... 36V Input Voltage ..................................................... (V–) –0.7V to (V+) +0.7V Output Short-Circuit(2) .............................................................. Continuous Operating Temperature .................................................. –40°C to +125°C Storage Temperature ..................................................... –40°C to +125°C Junction Temperature ...................................................................... 150°C NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. (2) Short-circuit to ground, one amplifier per package. PACKAGE/ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. 2 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. OPA130, OPA2130, OPA4130 www.ti.com SBOS053A ELECTRICAL CHARACTERISTICS At TA = +25°C, VS = ±15V, and RL = 10kΩ, unless otherwise noted. OPA130PA, UA OPA2130PA, UA OPA4130PA, UA PARAMETER OFFSET VOLTAGE Input Offset Voltage vs Temperature(1) vs Power Supply Channel Separation (dual and quad) CONDITION MIN Operating Temperature Range VS = ±2.25V to ±18V INPUT BIAS CURRENT(2) Input Bias Current vs Temperature Input Offset Current VCM = 0V VCM = 0V VCM = –13V to +13V INPUT IMPEDANCE Differential Common-Mode VCM = –13V to +13V OPEN-LOOP GAIN Open-loop Voltage Gain FREQUENCY RESPONSE Gain-Bandwidth Product Slew Rate Settling Time: 0.1% 0.01% Overload Recovery Time Total Harmonic Distortion + Noise VO = –13.8V to +13V RL = 2kΩ, VO = –13V to +12V (V+)–2 (V–)+2 90 120 120 G = 1, 10V Step, CL = 100pF G = 1, 10V Step, CL = 100pF G = 1, VIN = ±15V 1kHz, G = 1, VO = 3.5Vrms OUTPUT Voltage Output, Positive Negative Positive Negative Short-Circuit Current Capacitive Load Drive (Stable Operation) POWER SUPPLY Specified Operating Voltage Operating Voltage Range Quiescent Current (per amplifier) RL = 2kΩ RL = 2kΩ (V+)–2 (V–)+1.2 (V+)–3 (V–)+2 ±2.25 IO = 0 TEMPERATURE RANGE Operating Range Storage Thermal Resistance, θJA DIP-8 SO-8 Surface-Mount DIP-14 SO-14 Surface-Mount MAX UNITS ±0.2 ±2 2 0.3 ±1 ±10 20 mV µV/°C µV/V µV/V +5 ±20 See Typical Characteristics ±2 ±20 NOISE Input Voltage Noise Noise Density, f = 10Hz f = 100Hz f = 1kHz f = 10kHz Current Noise Density, f = 1kHz INPUT VOLTAGE RANGE Common-Mode Voltage Range, Positive Negative Common-Mode Rejection TYP pA pA 30 18 16 16 4 nV/√Hz nV/√Hz nV/√Hz nV/√Hz fA/√Hz (V+)–1.5 (V–)+1.2 105 V V dB 1013 || 1 1013 || 3 Ω || pF Ω || pF 135 135 dB dB 1 2 5.5 7 2 0.0003 MHz V/µs µs µs µs % (V+)–1.5 (V–)+1 (V+)–2.5 (V–)+1.5 ±18 10 V V V V mA nF ±15 ±530 –40 –40 100 150 80 110 ±18 ±650 V V µA +85 +125 °C °C °C/W °C/W °C/W °C/W NOTES: (1) Ensured by wafer test. (2) High-speed test at TJ = 25°C. OPA130, OPA2130, OPA4130 SBOS053A www.ti.com 3 TYPICAL CHARACTERISTICS At TA = +25°C, VS = ±15V, and RL = 10kΩ, unless otherwise noted. POWER SUPPLY AND COMMON-MODE REJECTION vs FREQUENCY OPEN-LOOP GAIN/PHASE vs FREQUENCY 0 120 80 φ –90 60 40 –135 PSR, CMR (dB) –45 CL = 100pF Phase Shift (°) Voltage Gain (dB) 100 20 G 0 –180 –20 1 10 100 1k 10k 100k 1M 120 110 100 90 80 70 60 50 40 30 20 10 0 –PSR CMR +PSR 10 10M 100 1k Frequency (Hz) 10 10 Channel Separation (dB) Voltage Noise 160 Current Noise (fA/√Hz) Voltage Noise (nV/√Hz) 100 100 140 120 100 Current Noise 1 1 1k 10k 100k RL = 10kΩ 10 100 1k 10k 100k Frequency (Hz) Frequency (Hz) INPUT BIAS AND INPUT OFFSET CURRENT vs TEMPERATURE INPUT BIAS CURRENT vs INPUT COMMON-MODE VOLTAGE 10 10k 1k VCM = 0V 100 IB IOS 10 1 5 0.1 0 0.01 –75 –50 –25 0 25 50 75 100 –15 125 –10 –5 0 5 10 15 Common-Mode Voltage (V) Ambient Temperature (°C) 4 Dual and quad devices. G = 1, all channels. Quad measured channel A to D or B to C—other combinations yield improved rejection. 80 1M Input Bias Current (pA) Input Bias and Input Offset Current (pA) 100 1M CHANNEL SEPARATION vs FREQUENCY 1k 1k 10 100k Frequency (Hz) INPUT VOLTAGE AND CURRENT NOISE SPECTRAL DENSITY vs FREQUENCY 1 10k OPA130, OPA2130, OPA4130 www.ti.com SBOS053A TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = ±15V, and RL = 10kΩ, unless otherwise noted. Quiescent Current Per Amp (mA) AOL, CMR, PSR (dB) 140 130 Open-Loop Gain 120 PSR 110 CMR 0.65 40 0.60 35 IQ 0.55 30 – ISC 0.50 25 0.45 20 + ISC 0.40 15 0.35 100 –75 –50 –25 0 25 50 75 100 10 –75 125 –50 –25 0 25 50 75 Ambient Temperature (°C) Temperature (°C) OFFSET VOLTAGE PRODUCTION DISTRIBUTION OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION 15 Short-Circuit Current (mA) QUIESCENT CURRENT AND SHORT-CIRCUIT CURRENT vs TEMPERATURE AOL, CMR, PSR vs TEMPERATURE 100 125 20 Percent of Amplifiers (%) Percent of Amplifiers (%) 18 10 5 16 14 12 10 8 6 4 2 0 Offset Voltage (µV) Offset Voltage Drift (µV/°C) TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY MAXIMUM OUTPUT VOLTAGE vs FREQUENCY 0.1 8.00 7.50 7.00 6.50 6.00 5.50 5.00 4.50 4.00 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 700 600 500 400 300 200 0 100 –100 –200 –300 –400 –500 –600 –700 0 30 Output Voltage (Vp-p) THD + Noise (%) 25 0.01 G = +10 0.001 RL = 10kΩ RL = 2kΩ G = +1 VS = ±15V 15 10 VS = ±2.25V 0 1k 10k 10k 100k Frequency (Hz) 100k 1M Frequency (Hz) OPA130, OPA2130, OPA4130 SBOS053A VS = ±5V 5 0.0001 100 Maximum output voltage without slew-rate induced distortion 20 www.ti.com 5 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = ±15V, and RL = 10kΩ, unless otherwise noted. SMALL-SIGNAL STEP RESPONSE G = 1, CL = 1000pF 50mV/div 50mV/div SMALL-SIGNAL STEP RESPONSE G =1, CL = 100pF 5µs/div 500ns/div LARGE-SIGNAL STEP RESPONSE G = 1, CL = 100pF SETTLING TIME vs GAIN 100 5V/div Settling Time (µs) 0.01% 10 0.1% 1 5µs/div ±1 ±10 ±100 Gain (V/V) SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE OUTPUT VOLTAGE SWING vs OUTPUT CURRENT 15 80 –55°C 12 11 60 +125°C +25°C 10 –10 –11 +125°C +85°C –12 –13 ±5 ±10 ±15 40 30 G = –1 G = ±5 10 –15 0 50 20 +25°C –55°C –14 0 10pF ±20 Output Current (mA) 6 G = +1 70 13 Overshoot (%) Output Voltage Swing (V) 14 100pF 1nF 10nF 100nF Load Capacitance (F) OPA130, OPA2130, OPA4130 www.ti.com SBOS053A APPLICATIONS INFORMATION V+ Trim Range: ±5mV typ OPA130 series op amps are unity-gain stable and suitable for a wide range of general-purpose applications. Power supply pins should be bypassed with 10nF ceramic capacitors or larger. OPA130 op amps are free from unexpected output phasereversal common with FET op amps. Many FET-input op amps exhibit phase-reversal of the output when the input common-mode voltage range is exceeded. This can occur in voltage-follower circuits, causing serious problems in control loop applications. OPA130 series op amps are free from this undesirable behavior. All circuitry is completely independent in dual and quad versions, assuring normal behavior when one amplifier in a package is overdriven or short-circuited. 10nF 100kΩ 7 1 2 5 3 10nF OPA130 4 6 OPA130 single op amp only. Use offset adjust pins only to null offset voltage of op amp—see text. V– FIGURE 1. OPA130 Offset Voltage Trim Circuit. INPUT BIAS CURRENT OPERATING VOLTAGE OPA130 series op amps operate with power supplies from ±2.25V to ±18V with excellent performance. Although specifications are production tested with ±15V supplies, most behavior remains unchanged throughout the full operating voltage range. Parameters which vary significantly with operating voltage are shown in the typical performance curves. The input bias current is approximately 5pA at room temperature and increases with temperature as shown in the Typical Characteristic curve Input Bias Current vs Temperature. Input stage cascode circuitry assures that the input bias current remains virtually unchanged throughout the full input common-mode range of the OPA130. See the Typical Characteristic curve Input Bias Current vs Common-Mode Voltage. OFFSET VOLTAGE TRIM Offset voltage of OPA130 series amplifiers is laser trimmed and usually requires no user adjustment. The OPA130 (single op amp version) provides offset voltage trim connections on pins 1 and 5. Offset voltage can be adjusted by connecting a potentiometer as shown in Figure 1. This adjustment should be used only to null the offset of the op amp, not to adjust system offset or offset produced by the signal source. Nulling offset that is not produced by the amplifier will change the offset voltage drift behavior of the op amp. OPA130, OPA2130, OPA4130 SBOS053A www.ti.com 7 PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) OPA130PA OBSOLETE PDIP P 8 TBD Call TI OPA130UA ACTIVE SOIC D 8 100 Pb-Free (RoHS) CU NIPDAU Call TI Level-3-260C-168 HR OPA130UA/2K5 ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR OPA130UA/2K5E4 ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR OPA130UAE4 ACTIVE SOIC D 8 100 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR OPA2130PA OBSOLETE PDIP P 8 TBD Call TI OPA2130UA ACTIVE SOIC D 8 100 Pb-Free (RoHS) CU NIPDAU Call TI Level-3-260C-168 HR OPA2130UA/2K5 ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR OPA2130UA/2K5E4 ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR OPA2130UAE4 ACTIVE SOIC D 8 100 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR OPA4130PA OBSOLETE PDIP N 14 TBD Call TI OPA4130UA ACTIVE SOIC D 14 58 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR OPA4130UA/2K5 ACTIVE SOIC D 14 2500 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR OPA4130UA/2K5E4 ACTIVE SOIC D 14 2500 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR OPA4130UAE4 ACTIVE SOIC D 14 58 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2007 accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant OPA130UA/2K5 D 8 SITE 41 330 12 6.9 5.4 2.0 8 12 Q1 OPA2130UA/2K5 D 8 SITE 41 330 12 6.9 5.4 2.0 8 12 Q1 OPA4130UA/2K5 D 14 SITE 41 330 16 6.5 9.5 2.1 8 16 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) OPA130UA/2K5 D 8 SITE 41 346.0 346.0 29.0 OPA2130UA/2K5 D 8 SITE 41 346.0 346.0 29.0 OPA4130UA/2K5 D 14 SITE 41 346.0 346.0 33.0 Pack Materials-Page 2 MECHANICAL DATA MPDI001A – JANUARY 1995 – REVISED JUNE 1999 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 0.400 (10,60) 0.355 (9,02) 8 5 0.260 (6,60) 0.240 (6,10) 1 4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gage Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.430 (10,92) MAX 0.010 (0,25) M 4040082/D 05/98 NOTES: A. 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