LINER LTC1590IN Dual serial 12-bit multiplying dac Datasheet

LTC1590
Dual Serial 12-Bit
Multiplying DAC
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DESCRIPTION
FEATURES
■
■
■
■
■
■
■
■
DNL and INL Over Temperature: ±0.5LSB Max
Gain Error: ± 1LSB Max
Low Supply Current: 10µA Max
4-Quadrant Multiplication
Power-On Reset
Asynchronous Clear Input
Daisy-Chain 3-Wire Serial Interface
16-Pin Narrow SO and PDIP Packages
The LTC®1590 is a dual, serial input 12-bit multiplying
digital-to-analog converter (DAC). It includes two current
output multiplying CMOS DACs and an easy SPI compatible serial interface with daisy-chain output. An asynchronous CLR pin sets both DACs to zero scale.
Excellent accuracy, stability and versatility are combined
with the smallest package available for a dual 12-bit
multiplying DAC.
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APPLICATIONS
■
■
■
Process Control and Industrial Automation
Software Controlled Gain Adjustment
Digitally Controlled Filter and Power Supplies
Automatic Test Equipment
, LTC and LT are registered trademarks of Linear Technology Corporation.
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■
Parts are available in 16-pin PDIP and narrow SO packages and are specified over the commercial and industrial
temperature ranges.
Integral Nonlinearity Over
Temperature DAC A
TYPICAL APPLICATION
1.0
Dual 12-Bit 2-Quadrant Multiplying DAC
VIN A
±10V
VIN B
±10V
9
1
16
VCC
2
15V
Daisy-Chained Control Outputs
33pF
13 DIN
VREF B RFB B
14 CLK
0.5
OUT1 B 3
–
OUT2 B 4
11 CS/LD
24-BIT
SHIFT
REG
AND
LATCH
0
–0.5
LT ®1112
DAC B
µP
INL (LSB)
5V
THREE
SUPERIMPOSED
CURVES
TA = –40°C,
25°C, 85°C
–1.0
VOUT B
±10V
+
0
Integral Nonlinearity Over
Temperature DAC B
8
VREF A RFB A
33pF
OUT1 A 6
1.0
–
VOUT A
±10V
DAC A
OUT2 A 5
+
THREE
SUPERIMPOSED
CURVES
TA = –40°C,
25°C, 85°C
0.5
5V
DGND
10
AGND
7
LTC1590
–15V
LTC1590 • TA01
INL (LSB)
12 DOUT
CLR
15
512 1024 1536 2048 2560 3072 3584 4095
DIGITAL INPUT CODE LTC1590 • TA02
0
–0.5
–1.0
0
512 1024 1536 2048 2560 3072 3584 4095
DIGITAL INPUT CODE LTC1590 • TA03
1
LTC1590
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VCC to AGND ............................................... – 0.5V to 7V
VCC to DGND .............................................. – 0.5V to 7V
AGND to DGND ............................................. VCC + 0.5V
DGND to AGND ..............................................VCC + 0.5V
VREF to AGND ........................................................ ±25V
RFB to AGND .......................................................... ±25V
Digital Inputs to DGND ................... – 0.5V to VCC + 0.5V
VOUT1, VOUT2 to AGND .................... – 0.5V to VCC + 0.5V
Maximum Junction Temperature .......................... 150°C
Operating Temperature Range
LTC1590C................................................ 0°C to 70°C
LTC1590I ............................................ – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
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ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
VREF B 1
16 VCC
RFB B 2
15 CLR
OUT1 B 3
14 CLK
OUT2 B 4
13 DIN
OUT2 A 5
12 DOUT
OUT1 A 6
11 CS/LD
AGND 7
10 DGND
RFB A 8
9
N PACKAGE
16-LEAD PDIP
ORDER PART
NUMBER
LTC1590CN
LTC1590CS
LTC1590IN
LTC1590IS
VREF A
S PACKAGE
16-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 100°C/W (N)
TJMAX = 150°C, θJA = 150°C/W (S)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
VCC = 4.5V to 5.5V, VREF = 10V, VOUT1 = VOUT2 = AGND = DGND = 0V, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Accuracy
Resolution
●
12
Bits
INL
Integral Nonlinearity
(Note 1)
●
± 0.5
LSB
DNL
Differential Nonlinearity
Guaranteed Monotonic, TMIN to TMAX
●
± 0.5
LSB
GE
Gain Error
(Note 2), TA = 25°C
TMIN to TMAX
●
±1
±2
LSB
LSB
Gain Temperature Coefficient
(Note 3) ∆Gain/∆Temperature
●
5
ppm/°C
OUT1 A, OUT1 B Leakage Current
(Note 4), TA = 25°C
TMIN to TMAX
●
±5
±25
nA
nA
TA = 25°C
TMIN to TMAX
●
±0.03
±0.15
LSB
LSB
±0.0001
±0.002
%/%
11
15
kΩ
3
%
ILEAKAGE
Zero-Scale Error
PSRR
Power Supply Rejection
VCC = 5V ±10%
1
●
Reference Input
RREF
VREF Input Resistance
●
VREFA, VREFB Input Resistance Match
●
8
AC Performance (Note 3)
Digital-to-Analog Glitch Impulse
THD
2
(Notes 5, 6)
1
nV-s
Multiplying Feedthrough Error
(Note 11)
– 89
– 80
dB
Output Current Settling Time
(Note 5) To 0.01% for Full-Scale Change
0.3
0.8
µs
Channel-to-Channel Isolation
(Note 7)
Digital Crosstalk
(Notes 5, 8)
Output Noise Voltage Density
(Note 9)
13
Total Harmonic Distortion
(Note 10)
– 108
Multiplying Bandwidth
(Note 12)
1
– 90
1
dB
nV-s
nV/√Hz
– 92
dB
MHz
LTC1590
ELECTRICAL CHARACTERISTICS
VCC = 4.5V to 5.5V, VREF = 10V, VOUT1 = VOUT2 = AGND = DGND = 0V, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
60
30
90
60
UNITS
Analog Outputs
COUT
Output Capacitance (Note 3)
DAC Register Loaded to All 1s
DAC Register Loaded to All 0s
●
●
pF
pF
Digital Input
VIH
Digital Input High Voltage
●
VIL
Digital Input Low Voltage
●
IIN
Digital Input Current
CIN
Digital Input Capacitance
2.4
0.001
●
(Note 3) VIN = 0V
●
V
0.8
V
±1
µA
8
pF
Digital Output
VOH
Digital Output High Voltage
IOH = 200µA
●
VOL
Digital Output Low Voltage
IOH = 1.6mA
●
4
V
0.4
V
Timing Characteristics
t1
DIN to CLK Setup Time
●
50
ns
t2
DIN to CLK Setup Hold Time
●
0
ns
t3
CLK High Time
●
40
ns
t4
CLK Low Time
●
40
ns
t5
CS/LD High Time
●
50
ns
t6
LSB CLK to CS/LD
●
40
ns
t7
CS/LD Low to CLK High
●
20
ns
t8
CLK Low to CS/LD Low
●
20
ns
t9
CLK to DOUT Delay
●
10
●
4.5
160
ns
Power Supply
VCC
Operating Supply Range
ICC
Supply Current
Digital Inputs = 0V or VCC
The ● denotes specifications which apply over the full operating
temperature range.
Note 1: ±0.5LSB = ±0.012% of full scale.
Note 2: Using internal feedback resistor.
Note 3: Guaranteed by design, not subject to test.
Note 4: IOUT1 with DAC register loaded with all 0s.
Note 5: OUT1 load = 100Ω in parallel with 13pF.
Note 6: VREF = 0V. DAC register contents changed from all 0s to all 1s or
all 1s to all 0s.
Note 7: DAC A output with VREF A = 0V and VREF B = 10kHz 20VP-P, or
DAC B output with VREF B = 0V, VREF A = 10kHz 20VP-P. Both DAC registers
loaded with all 1s.
●
5
5.5
V
10
µA
Note 8: Glitch on DAC A or DAC B output when the other DAC makes a
full-scale transition.
Note 9: 10Hz to 100kHz. Calculation from en = √4KTRB where:
K = Boltzmann constant (J/K°); R = resistance (Ω); T = resistor temperature
(°K); B = bandwidth (Hz).
Note10: VREF = 6VRMS at 1kHz. DAC register loaded with all 1s, using
LT ®1124 op amp.
Note 11: VREF = ±10V, 10kHz sine wave, DAC register loaded with all 0s,
using LT1358 op amp.
Note 12: –3dB bandwidth using LT1358 op amp.
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LTC1590
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TYPICAL PERFORMANCE CHARACTERISTICS
Full-Scale Settling Waveform
Integral Nonlinearity (INL)
INTEGRAL NONLINEARITY (LSB)
1.0
DIFFERENTIAL NONLINEARITY (LSB)
1.0
VDD = 5V
0V TO 5V OUTPUT RANGE
LT1363 OP AMP
CFB 30pF
OUTPUT VOLTAGE (1V/DIV)
Differential Nonlinearity (DNL)
0.5
0
–0.5
–1.0
0.20
USING AN
LT1363 WITH
500kHz FILTER
–90
–100
DIFFERENTIAL NONLINEARITY (LSB)
VDD = 5V
INTEGRAL NONLINEARITY (LSB)
0.15
0.10
0.05
USING AN LT1007
WITH 22kHz FILTER
–110
1
10
FREQUENCY (kHz)
0
50
3
6
8
5
7
4
REFERENCE VOLTAGE (V)
1590 G10
30
40
50
60
70
ALL BITS
ON
ALL BITS
OFF
80
90
100
100
100k
10k
FREQUENCY (Hz)
1M
10M
1590 G07
4
9
0.05
2
10
3
4
5
6
7
8
REFERENCE VOLTAGE (V)
1.0
0.9
0.9
0.8
0.7
0.6
0.5
0.4
VREF = 2V
0.2
0
VREF = 10V
2
3
4
5
6
7
8
SUPPLY VOLTAGE (V)
10
1590 G06
1.0
0.3
9
Differential Nonlinearity vs
Supply Voltage
0.1
1k
0.10
Integral Nonlinearity vs
Supply Voltage
INTEGRAL NONLINEARITY (LSB)
ATTENUATION (dB)
20
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0.15
1590 G05
Multiplying Mode Frequency
Response vs Digital Code
0
VDD = 5V
0
2
DIFFERENTIAL NONLINEARITY (LSB)
SIGNAL-TO-(NOISE + DISTORTION) (dB)
Differential Nonlinearity vs
Reference Voltage
0.20
VDD = 5V
–80
512 1024 1536 2048 2560 3072 3584 4095
DIGITAL INPUT CODE
1590 G03
Integral Nonlinearity vs
Reference Voltage
–50
10
0
1590 G02
Multiplying Mode Signal-to(Noise + Distortion) vs Frequency
–70
–0.5
512 1024 1536 2048 2560 3072 3584 4095
DIGITAL INPUT CODE
1590 G12
–60
0
–1.0
0
TIME (500ns/DIV)
0.5
0.8
0.7
0.6
0.5
0.4
0.3
VREF = 2V
0.2
VREF = 10V
0.1
0
9
10
1590 G08
2
3
4
5
6
7
8
SUPPLY VOLTAGE (V)
9
10
1590 G09
LTC1590
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TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs
Logic Input Voltage
Logic Threshold vs
Supply Voltage
Midscale Glitch Impulse
1.0
3
2
1
0
TIME (500ns/DIV)
SUPPLY CURRENT (mA)
LOGIC THRESHOLD (V)
OUTPUT VOLTAGE (50mV/DIV)
4
VDD = 5V
LT1363 OP AMP
CFB = 30pF
0
5
10
SUPPLY VOLTAGE (V)
15
0.5
0
0
1
3
2
INPUT VOLTAGE (V)
4
5
1590 G11
1590 G04
1590 G01
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PIN FUNCTIONS
VREF B, VREF A (Pins 1, 9): Reference Inputs for DAC A/B.
Typically ±10V, accepts up to ±25V.
RFB B, RFB A (Pins 2, 8): Feedback Resistors for DAC A/B.
Normally tied to the output of current to voltage converter
op amp. Typically swings to ±10V. Swings from 0V to
– VREF.
OUT1 B, OUT1 A (Pins 3, 6): True Current Output for DAC
A/B. Normally tied to inverting input of current to voltage
converter op amp.
OUT2 B, OUT2 A (Pins 4, 5): Complement Current Output
for DAC A/B. Normally tied to ground.
AGND (Pin 7): Analog Ground Pin. Tie to ground.
DGND (Pin 10): Digital Ground Pin. Tie to ground.
CS/LD (Pin 11): The Serial Interface Enable and Load
Control Input. When CS/LD is low the CLK signal is
enabled so the data can be clocked in. When CS/LD is
pulled high, data is loaded from the shift register into the
DAC register, updating the DAC output.
DOUT (Pin 12): The Serial Data Output. Data becomes valid
on the rising edge of the CLK.
DIN (Pin 13): The Serial Data Input. Data on the DIN pin is
latched into the shift register on the rising edge of the serial
clock. Data is loaded as one 24-bit word. The first 12 bits
are for DAC A, MSB-first and the second 12 bits are for
DAC B, MSB-first.
CLK (Pin 14): The Serial Interface Clock Input.
CLR (Pin 15): The Clear Pin for the DAC. Clears both DACs
to zero scale when pulled low. This pin should be tied to
VCC for normal operation.
VCC (Pin 16): The Positive Supply Input. 4.5 ≤ VCC
≤ 5.5V. Requires a bypass capacitor to ground.
5
LTC1590
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BLOCK DIAGRA
20k
VREF B
20k
20k
2 RFB B
1
40k
40k
40k
40k
40k
40k
40k
10k
3 OUT1 B
4 OUT2 B
DECODER
D11
(MSB)
DAC B
D10
D9
D8
D0
(LSB)
DAC REGISTER B
LOAD
12
VREF A
8 RFB A
9
6 OUT1 A
DAC A
5 OUT2 A
CS/LD 11
12
CLK
CLK 14
INPUT 24-BIT SHIFT REGISTER
12 DOUT
OUT
IN
DIN 13
1590 • BD
16
VCC
10
DGND
7
AGND
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TIMING DIAGRAMS
OPERATING SEQUENCE
DAC A INPUT
DAC B INPUT
MSB
LSB MSB
DIN
D11
D10
D9
D8
D7
D6
CLK
1
2
3
4
5
6
D5
7
D4
D3
8
9
D2
10
D1
11
D0
12
D11
13
LSB
D10
14
D9
15
D8
16
D7
17
D6
18
D5
19
D4
20
D3
21
D2
22
D1
23
D0
24
CS/LD
(ENABLE CLOCK)
(UPDATE DAC OUTPUT)
LTC1590 • TD
6
LTC1590
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UW
TIMING DIAGRAMS
TIMING DIAGRAM
t8
t1
t7
t6
t2
3
CLK
1
2
D11 A
MSB
DIN
D10 A
23
t3
t4
D9 A
24
D0 B
LSB
D1 B
CS/LD
t5
t9
DOUT
D11 A
PREVIOUS WORD
D10 A
PREVIOUS WORD
D9 A
PREVIOUS WORD
D0 B
PREVIOUS WORD
D11 A
CURRENT WORD
1590 TD02
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APPLICATIONS INFORMATION
Description
Equivalent Circuit
The LTC1590 is a dual 12-bit multiplying DAC that has
serial inputs and current outputs. It uses precision R/2R
resistor ladder technology to provide exceptional linearity
and stability. The device operates from a single 5V supply
and provides a ±10V reference input and voltage output
range when used with an external op amp.
Figure 1 shows an equivalent analog circuit for the LTC1590
DACs. R is the reference input, RREF, which is nominally
11k. The DAC output is represented by the Thevinin
equivalent current source with a value of:
Serial I/O
The LTC1590 has a 3-wire SPI/MICROWIRETM compatible
serial port that accepts 24-bit serial words. Data is loaded
MSB first with the first 12 bits controlling DAC A and the
second 12 bits controlling DAC B. Data is shifted into the
DIN input on the rising edge of CLK. The CS/LD input must
be taken low before transferring data to enable the CLK
input. After transferring data, CS/LD is pulled high to load
data from the shift register to the DAC registers which
updates both DACs.
The buffered output of the 24-bit shift register is available
on the DOUT pin. Multiple DACs can be daisy-chained on
one 3-wire interface by connecting the DOUT pin to the DIN
pin of the next DAC (see the Timing Diagrams section).
(Code/4096)(VREF/R)
The current source ILKG models the junction leakage of the
DAC output switches. ILKG is typically less than 5nA at
85°C and decreases by roughly two times for every 10°C
reduction in temperature. COUT is the output capacitance,
and it also comes from the DAC output switches and varies
from 30pF at zero scale to 60pF at full scale. RO is the
equivalent output resistance, which varies with digital
input code (see Op Amp Selection section).
R
VREF A
VREF B
R
( )( )
CODE VREF
4096
R
ILKG
RO
RFB A
RFB B
OUT1 A
OUT1 B
COUT
OUT2 A
OUT2 B
AGND
1590 F01
Figure 1. Equivalent Circuit
MICROWIRE is a trademark of National Semiconductor Corporation.
7
LTC1590
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APPLICATIONS INFORMATION
Unipolar 2-Quadrant Multiplying Mode
(VOUT = 0V to – VREF)
Table 1. Unipolar Binary Code Table
DIGITAL INPUT
BINARY NUMBER
IN DAC REGISTER
The LTC1590 can be used with a dual op amp to provide
a dual 2-quadrant multiplying DAC as shown in Figure 2.
The unipolar DAC transfer function is shown in Table 1.
The 33pF feedback capacitor is recommended to compensate for the pole caused by the internal feedback resistor
and the OUT1 output capacitance. For high speed op amps
this feedback capacitor is required for stability, and a
smaller value, 8pF to 15pF, may be desired to get the
fastest transient response and shortest settling time. A
larger feedback capacitor can be used to reduce wideband
noise, glitch impulse and distortion for lower frequency
signals. A pole is introduced in the DAC transfer function
at approximately (CFB)(RFB). For example, a 100pF feedback capacitor will typically give a pole at:
145kHz =
5V
1
(
)(
1111
1000
0000
0000
1111
0000
0000
0000
1111
0000
0001
0000
– VREF (4095/4096)
– VREF (2048/4096) = – VREF/2
– VREF (1/4096)
0V
The circuit of Figure 3 can be used to provide a dual
4-quadrant multiplying DAC. This circuit starts with the
unipolar application circuit and adds three resistors and an
op amp. These extra devices provide a gain of – 2 from the
unipolar output to the bipolar output, plus an offset of
(–1)(VREF) to produce the transfer function shown in Table
2. A pack of matched 20k resistors, with two resistors in
parallel forming the 10k resistor, is recommended.
)
Table 2. Bipolar Offset Binary Code Table
VREF
–10V TO 10V
33pF
VREF
LSB
Bipolar 4-Quadrant Multiplying Mode
(VOUT = – VREF to +VREF)
2π 100pF 11kΩ
0.1µF
VCC
MSB
ANALOG OUTPUT
VOUT
RFB
OUT1
DIGITAL INPUT
BINARY NUMBER
IN DAC REGISTER
15V
–
LTC1590
DAC A OR DAC B
OUT2
DGND AGND
MSB
1/2
LT1112
+
VOUT
0V TO –VREF
–15V
1111
1000
1000
0111
0000
1590 F02
ANALOG OUTPUT
VOUT
LSB
1111
0000
0000
1111
0000
1111
0001
0000
1111
0000
+VREF (2047/2048)
+VREF (1/2048)
0V
– VREF (1/2048)
– VREF (2048/2048) = – VREF
Figure 2. Unipolar Operation (2-Quadrant Multiplication)
R2
20k
VREF
–10V TO 10V
R3
20k
5V
0.1µF
33pF
VCC
VREF
RFB
OUT1
LTC1590
DAC A OR DAC B
OUT2
DGND
15V
–
+
1/2
LT1112
R1
10k
15V
–
1/2
+ LT1112
AGND
VOUT
–VREF TO VREF
–15V
–15V
Figure 3. Bipolar Operation (4-Quadrant Multiplication)
8
1590 F03
LTC1590
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APPLICATIONS INFORMATION
Op Amp Selection
To maintain the excellent accuracy and stability of the
LTC1590 thought should be given to op amp selection.
Fortunately, the sensitivity of INL and DNL to op amp offset
has been significantly reduced compared to competing
parts of this type. The op amp’s VOS causes DAC output
offset. In addition, because the DAC’s equivalent output
resistance RO changes as a function of code, there is a
code-dependent DAC output error proportional to VOS. For
fixed reference applications this causes gain, INL and DNL
error. For multiplying applications, a code-dependent, DC
output voltage error is seen. At zero scale the DAC output
error is equal to the op amp offset, and at full scale the
output error is equal to twice the op amp offset. For
example, a 1mV op amp offset will cause a 0.41LSB zeroscale error and a 0.82LSB full-scale error with a 10V fullscale range. The offset caused INL error is approximately
0.4 times the op amp VOS and DNL error is 0.07 times op
amp VOS. For the same example of 1mV op amp VOS and
10V full-scale range, the INL degradation will be 0.17LSB
and DNL degradation will be 0.03LSB.
amp bias current causes a 1.1mV DAC offset, or 0.45LSB
for a 10V full-scale range. It is important to note that
connecting the op amp noninverting input to ground
through a resistor will not cancel bias current errors and
should never be done! Similarly an offset caused by op
amp bias current should not be adjusted by using the op
amp null pins since this increases offset between DAC
OUT1 and OUT2 pins, causing INL, DNL and gain errors.
If op amp offset error adjustment is required, the op amp
input offset voltage (the voltage difference between OUT1
and OUT2) should be nulled.
Grounding
As with any high precision data converter, clean grounding is important. A low impedance analog ground plane
and star grounding should be used. OUT2 carries the
complementary DAC output current and should be tied to
the star ground with as low a resistance as possible. Other
ground points that must be tied to the star ground point
include the VREF input ground, the op amp noninverting
input(s) and the VOUT ground reference point.
Op amp bias current causes only an offset error equal to
(IBIAS)(RFB) ≈ (IBIAS)(11kΩ). For example, a 100nA op
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TYPICAL APPLICATIONS
Dual Programmable Attenuator
5V
0.1µF
VIN B
±10V
15V
16
2
1
33pF
DATA IN
SERIAL CLOCK
CHIP SELECT/DAC LOAD
DATA OUT
CLEAR
VREF B
13 DIN
14 CLK
RFB B
15 CLR
–
OUT2 B 4
24-BIT
SHIFT
REG
AND
LATCH
3
7
AGND
1
VOUT = –VIN
LTC1590
VREF A
OUT2 A 5
5
OUT1 A 6
6
RFB A
DGND
8
( )
D
4096
+
1/2
LT1358
–
7
VOUT A
4
33pF
9
VOUT B
+
DAC A
10
8
1/2
LT1358
DAC B
11 CS/LD
12 DOUT
0.01µF
2
OUT1 B 3
0.01µF
–15V
1590 TA07
VIN A
±10V
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LTC1590
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TYPICAL APPLICATIONS
Very Low Power Single Supply Dual VOUT DAC
500k
50k
–
1/4
LT1179
VOUT A
+
500k
50k
–
1/4
LT1179
V+
3.3V
2
16
VCC
1
9
VREF B
RFB B
3 OUT1 B
V+
3.3V
VOUT B
0V TO 2.2V
+
DAC B
0.2V
4 OUT2 B
120k
8
–
LT1004-1.2
210k
+
1/4
LT1179
LTC1590
RFB A
6 OUT1 A
VREF A
DAC A
5 OUT2 A
0.1µF
50k
AGND
DGND
7
10
ISUPPLY TOTAL = 100µA (TYP)
(WORSE-CASE CODE)
1590 TA06
Dual Programmable Gain Amplifier
VIN B
±10V
5V
0.1µF
15V
16
2
1
33pF
DATA IN
SERIAL CLOCK
CHIP SELECT/DAC LOAD
DATA OUT
CLEAR
VREF B
13 DIN
14 CLK
RFB B
15 CLR
2
OUT2 B 4
3
–
24-BIT
SHIFT
REG
AND
LATCH
10
AGND
1
VOUT = –VIN
LTC1590
VREF A
OUT2 A 5
5
OUT1 A 6
6
RFB A
DGND
8
( )
4096
D
+
1/2
LT1358
–
7
VOUT A
4
0.01µF
33pF
9
VOUT B
+
DAC A
7
8
1/2
LT1358
DAC B
11 CS/LD
12 DOUT
0.01µF
OUT1 B 3
–15V
1590 TA08
VIN A
±10V
10
LTC1590
U
TYPICAL APPLICATIONS
Dual Programmable Gain Amplifier with Input Attenuation
VIN B
±10V
1k
15k
5V
15k
1k
15V
0.1µF
DATA IN
SERIAL CLOCK
CHIP SELECT/DAC LOAD
DATA OUT
CLEAR
16
2
1
14 CLK
0.01µF
RFB B
VREF B
13 DIN
33pF
OUT1 B 3
2
OUT2 B 4
3
1/2
LT1358
DAC B
11 CS/LD
12 DOUT
15 CLR
24-BIT
SHIFT
REG
AND
LATCH
10
1
VOUT B
+
VOUT = –VIN
LTC1590
OUT2 A 5
5
OUT1 A 6
6
AGND
VREF A
7
1/2
LT1358
–
9
8
VOUT A
0.01µF
33pF
1k
4096
16D
4
RFB A
DGND
( )
+
DAC A
7
8
–
–15V
15k
1590 TA09
1k
15k
VIN A
±10V
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
N Package
16-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.770*
(19.558)
MAX
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
0.255 ± 0.015*
(6.477 ± 0.381)
0.130 ± 0.005
(3.302 ± 0.127)
0.300 – 0.325
(7.620 – 8.255)
0.009 – 0.015
(0.229 – 0.381)
(
+0.025
0.325 –0.015
8.255
+0.635
–0.381
)
0.045 – 0.065
(1.143 – 1.651)
0.015
(0.381)
MIN
0.065
(1.651)
TYP
0.125
(3.175)
MIN
0.005
(0.127)
MIN
0.100 ± 0.010
(2.540 ± 0.254)
0.018 ± 0.003
(0.457 ± 0.076)
N16 0695
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LTC1590
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 – 0.394*
(9.804 – 10.008)
0.010 – 0.020
× 45°
(0.254 – 0.508)
16
0.053 – 0.069
(1.346 – 1.752)
0.008 – 0.010
(0.203 – 0.254)
0° – 8° TYP
12
11
10
9
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
0.016 – 0.050
0.406 – 1.270
13
14
15
0.004 – 0.010
(0.101 – 0.254)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1
3
2
4
5
7
6
8
S16 0695
U
TYPICAL APPLICATION
Dual Programmable Attenuator with Gain
VIN B
±10V
1k
5V
15k
15k
0.1µF
15V
16
2
1
1k
DATA IN
14 CLK
SERIAL CLOCK
RFB B
VREF B
13 DIN
12 DOUT
DATA OUT
15 CLR
CLEAR
0.01µF
OUT1 B 3
2
OUT2 B 4
3
–
24-BIT
SHIFT
REG
AND
LATCH
10
AGND
1
VOUT = –VIN
LTC1590
VREF A
OUT2 A 5
5
OUT1 A 6
6
1k
8
15k
( )
16D
4096
+
1/2
LT1358
–
RFB A
DGND
9
VOUT B
+
DAC A
7
8
1/2
LT1358
DAC B
11 CS/LD
CHIP SELECT/DAC LOAD
33pF
7
VOUT A
4
0.01µF
33pF
–15V
1590 TA10
1k
15k
VIN A
±10V
RELATED PARTS
PART NUMBER
LTC1595
LTC1596
LTC7541A
LTC7543/LTC8143
LTC7545A
LTC8043
12
DESCRIPTION
16-Bit Multiplying IOUT DAC in SO-8
16-Bit Multiplying IOUT DAC
Parallel I/O Multiplying IOUT 12-Bit DAC
Serial I/O Multiplying IOUT 12-Bit DACs
Parallel I/O Multiplying IOUT 12-Bit DAC
Serial I/O Multiplying IOUT 12-Bit DAC
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417● (408)432-1900
FAX: (408) 434-0507● TELEX: 499-3977 ● www.linear-tech.com
COMMENTS
True 16-Bit Upgrade for DAC8043
True 16-Bit Upgrade for DAC8143 and AD7543
12-Bit Wide Parallel Input
Clear Pin and Serial Data Output (LTC8143)
12-Bit Wide Latched Parallel Input
8-Pin SO and PDIP
1590f LT/TP 1197 4K • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 1997