LINER LTC2208-14 14-bit, 130msps adc Datasheet

LTC2208-14
14-Bit, 130Msps ADC
FEATURES
DESCRIPTION
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The LTC®2208-14 is a 130Msps, sampling 14-bit A/D
converter designed for digitizing high frequency, wide
dynamic range signals with input frequencies up to
700MHz. The input range of the ADC can be optimized
with the PGA front end.
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Sample Rate: 130Msps
77.1dBFS Noise Floor
98dB SFDR
SFDR >81dB at 250MHz (1.5VP-P Input Range)
PGA Front End (2.25VP-P or 1.5VP-P Input Range)
700MHz Full Power Bandwidth S/H
Optional Internal Dither
Optional Data Output Randomizer
LVDS or CMOS Outputs
Single 3.3V Supply
Power Dissipation: 1.32W
Clock Duty Cycle Stabilizer
Pin Compatible 16-Bit Version
130Msps: LTC2208 (16-Bit)
64-Pin (9mm × 9mm) QFN Package
The LTC2208-14 is perfect for demanding communications
applications, with AC performance that includes 77.1dBFS
Noise Floor and 98dB spurious free dynamic range (SFDR).
Ultralow jitter of 70fsRMS allows undersampling of high
input frequencies with excellent noise performance.
Maximum DC specs include ±1.5LSB INL, ±0.5LSB DNL
(no missing codes).
The digital output can be either differential LVDS or
single-ended CMOS. There are two format options for the
CMOS outputs: a single bus running at the full data rate or
demultiplexed buses running at half data rate. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 3.6V.
APPLICATIONS
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Telecommunications
Receivers
Cellular Base Stations
Spectrum Analysis
Imaging Systems
ATE
The ENC+ and ENC– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of
clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
3.3V
32k Point FFT, fIN = 15.11MHz,
–1dB, PGA = 0, RAND “On”,
Dither “OFF”
SENSE
2.2μF
AIN+
1.25V
COMMON MODE
BIAS VOLTAGE
+
ANALOG
INPUT
AIN–
14-BIT
PIPELINED
ADC CORE
S/H
AMP
–
OVDD
INTERNAL ADC
REFERENCE
GENERATOR
0.5V TO 3.6V
0
0.1μF
OF
CLKOUT
D13
•
•
•
D0
OUTPUT
DRIVERS
CORRECTION
LOGIC AND
SHIFT REGISTER
–10
–20
–30
AMPLITUDE (dBFS)
VCM
CMOS
OR
LVDS
OGND
CLOCK/DUTY
CYCLE
CONTROL
ENC +
ENC –
3.3V
0.1μF
0.1μF
0.1μF
SHDN
DITH
MODE
LVDS
RAND
–70
–80
–100
–110
–120
0
220814 TA01
PGA
–50
–60
–90
VDD
GND
–40
10
40
30
20
50
FREQUENCY (MHz)
60
220814 G05
ADC CONTROL INPUTS
220814fb
1
LTC2208-14
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
OVDD = VDD (Notes 1 and 2)
TOP VIEW
64 PGA
63 RAND
62 MODE
61 LVDS
60 OF+/0FA
59 OF–/DA13
58 D13+/DA12
57 D13–/DA11
56 D12+/DA10
55 D12–/DA9
54 D11+/DA8
53 D11–/DA7
52 D10+/DA6
51 D10–/DA5
50 OGND
49 OVDD
Supply Voltage (VDD) ................................... –0.3V to 4V
Digital Output Ground Voltage (OGND) ........ –0.3V to 1V
Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V)
Digital Input Voltage .................... –0.3V to (VDD + 0.3V)
Digital Output Voltage................ –0.3V to (OVDD + 0.3V)
Power Dissipation ............................................ 2000mW
Operating Temperature Range
LTC2208C-14 ........................................... 0°C to 70°C
LTC2208I-14 ........................................–40°C to 85°C
Storage Temperature Range ..................–65°C to 150°C
Digital Output Supply Voltage (OVDD) .......... –0.3V to 4V
SENSE 1
GND 2
VCM 3
GND 4
VDD 5
VDD 6
GND 7
AIN+ 8
AIN– 9
GND 10
GND 11
ENC+ 12
ENC– 13
GND 14
VDD 15
VDD 16
48 D9+/DA4
47 D9–/DA3
46 D8+/DA2
45 D8–/DA1
44 D7+/DA0
43 D7–/DNC
42 D6+/DNC
41 D6–/CLKOUTA
40 CLKOUT+/CLKOUTB
39 CLKOUT–/OFB
38 D5+_ /DB13
37 D5 /DB12
36 D4+/DB11
35 D4–/DB10
34 D3+/DB9
33 D3–/DB8
VDD 17
GND 18
SHDN 19
DITH 20
NC 21
NC 22
DNC/DB0 23
DNC/DB1 24
D0–/DB2 25
D0+/DB3 26
D1–/DB4 27
D1+/DB5 28
D2–/DB6 29
D2+/DB7 30
OGND 31
OVDD 32
65
UP PACKAGE
64-LEAD (9mm s 9mm) PLASTIC QFN
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB BOARD
TJMAX = 150°C, θJA = 20°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2208CUP-14#PBF
LTC2208CUP-14#TRPBF LTC2208UP-14
64-Lead (9mm × 9mm) Plastic Plastic QFN
0°C to 70°C
LTC2208IUP-14#PBF
LTC2208IUP-14#TRPBF
64-Lead (9mm × 9mm) Plastic Plastic QFN
–40°C to 85°C
LTC2208UP-14
Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based ﬁnish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/
CONVERTER CHARACTERISTICS
The l denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 4)
PARAMETER
CONDITIONS
Integral Linearity Error
Differential Analog Input (Note 5)
Differential Linearity Error
Offset Error
MIN
TYP
MAX
UNITS
l
±1
±1.5
LSB
Differential Analog Input
l
±0.2
±0.5
LSB
(Note 6)
l
±2
±10.8
mV
±10
Offset Drift
l
±0.2
μV/°C
±2.3
Gain Error
External Reference
Full-Scale Drift
Internal Reference
External Reference
±30
±15
ppm/°C
ppm/°C
Transition Noise
External Reference
0.8
LSBRMS
%FS
220814fb
2
LTC2208-14
ANALOG INPUT
The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise
speciﬁcations are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VIN
Analog Input Range (AIN+ – AIN–)
MIN
3.135V ≤ VDD ≤ 3.465V
VIN, CM
Analog Input Common Mode
Differential Input (Note 7)
l
1
IIN
Analog Input Leakage Current
0V ≤ AIN+, AIN– ≤ VDD
l
ISENSE
SENSE Input Leakage Current
0V ≤ SENSE ≤ VDD
l
IMODE
MODE Pin Pull-Down Current to GND
ILVDS
LVDS Pin Pull-Down Current to GND
CIN
Analog Input Capacitance
tAP
TYP
MAX
UNITS
1.5 to 2.25
1.25
VP-P
1.5
V
–1
1
μA
–3
3
μA
10
μA
10
μA
6.5
1.8
pF
pF
Sample-and-Hold
Acquisition Delay Time
1
ns
tJITTER
Sample-and-Hold
Acquisition Delay Time Jitter
70
fsRMS
CMRR
Analog Input
Common Mode Rejection Ratio
1V < (AIN+ = AIN–) <1.5V
80
dB
BW-3dB
Full Power Bandwidth
RS ≤ 25Ω
700
MHz
Sample Mode ENC+ < ENC–
Hold Mode ENC+ > ENC–
DYNAMIC ACCURACY
The l denotes the speciﬁcations which apply over the full operating temperature range,
otherwise speciﬁcations are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
SNR
Signal-to-Noise Ratio
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
30MHz Input (2.25V Range, PGA = 0), TA = 25ºC
30MHz Input (2.25V Range, PGA = 0)
30MHz Input (1.5V Range, PGA = 1)
MIN
l
75.7
75.4
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1), TA = 25ºC
140MHz Input (1.5V Range, PGA = 1)
l
73.5
73.3
250MHz Input (2.25V Range, PGA = 0)
250MHz Input (1.5V Range, PGA = 1)
SFDR
Spurious Free
Dynamic Range
2nd or 3rd
Harmonic
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
30MHz Input (2.25V Range, PGA = 0)
30MHz Input (1.5V Range, PGA = 1)
l
84
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
250MHz Input (2.25V Range, PGA = 0)
250MHz Input (1.5V Range, PGA = 1)
l
81.5
TYP
MAX
UNITS
77.1
74.9
dBFS
dBFS
77
77
74.9
dBFS
dBFS
dBFS
76.9
74.8
dBFS
dBFS
76.4
74.6
74.6
dBFS
dBFS
dBFS
75
73.6
dBFS
dBFS
98
98
dBc
dBc
96
98
dBc
dBc
90
93
dBc
dBc
85
95
dBc
dBc
76
81
dBc
dBc
220814fb
3
LTC2208-14
DYNAMIC ACCURACY
The l denotes the speciﬁcations which apply over the full operating temperature range,
otherwise speciﬁcations are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
SFDR
Spurious Free
Dynamic Range
4th Harmonic
or Higher
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
MIN
100
100
dBc
dBc
100
100
dBc
dBc
95
95
dBc
dBc
90
90
dBc
dBc
77
74.8
dBFS
dBFS
76.9
76.9
74.7
dBFS
dBFS
dBFS
76.6
74.6
dBFS
dBFS
76.3
74.5
74.5
dBFS
dBFS
dBFS
250MHz Input (2.25V Range, PGA = 0)
250MHz Input (1.5V Range, PGA = 1)
73.6
72.9
dBFS
dBFS
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
105
105
dBFS
dBFS
30MHz Input (2.25V Range, PGA = 0)
30MHz Input (1.5V Range, PGA = 1)
105
105
dBFS
dBFS
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
105
105
dBFS
dBFS
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
100
100
dBFS
dBFS
250MHz Input (2.25V Range, PGA = 0)
250MHz Input (1.5V Range, PGA = 1)
100
100
dBFS
dBFS
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
115
115
dBFS
dBFS
110
110
dBFS
dBFS
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
110
110
dBFS
dBFS
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
107
107
dBFS
dBFS
250MHz Input (2.25V Range, PGA = 0)
250MHz Input (1.5V Range, PGA = 1)
105
105
dBFS
dBFS
30MHz Input (2.25V Range, PGA = 0)
30MHz Input (1.5V Range, PGA = 1)
l
87
l
85
250MHz Input (2.25V Range, PGA = 0)
250MHz Input (1.5V Range, PGA = 1)
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
30MHz Input (2.25V Range, PGA = 0), TA = 25ºC
30MHz Input (2.25V Range, PGA = 0
30MHz Input (1.5V Range, PGA = 1)
l
75.4
75.1
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1), TA = 25ºC
140MHz Input (1.5V Range, PGA = 1)
SFDR
SFDR
Spurious Free Dynamic Range
at –25dBFS
Dither “OFF”
Spurious Free Dynamic Range
at –25dBFS
Dither “ON”
UNITS
dBc
dBc
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
Signal-to-Noise
Plus Distortion Ratio
MAX
100
100
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
S/(N+D)
TYP
30MHz Input (2.25V Range, PGA = 0)
30MHz Input (1.5V Range, PGA = 1)
l
l
73.4
73
95
220814fb
4
LTC2208-14
COMMON MODE BIAS CHARACTERISTICS
The l denotes the speciﬁcations which apply over
the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCM Output Voltage
IOUT = 0
1.15
1.25
1.35
V
VCM Output Tempco
IOUT = 0
40
ppm/°C
VCM Line Regulation
3.135V ≤ VDD ≤ 3.465V
1
mV/ V
VCM Output Resistance
| IOUT | ≤ 1mA
2
Ω
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the speciﬁcations which apply over the
full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ENCODE INPUTS (ENC+, ENC–)
VID
Differential Input Voltage
(Note 7)
VICM
Common Mode Input Voltage
Internally Set
Externally Set (Note 7)
l
0.2
V
1.6
1.2
V
3
RIN
Input Resistance
(See Figure 2)
6
kΩ
CIN
Input Capacitance
(Note 7)
3
pF
LOGIC INPUTS (DITH, PGA, SHDN, RAND)
VIH
High Level Input Voltage
VDD = 3.3V
l
VIL
Low Level Input Voltage
VDD = 3.3V
l
l
IIN
Digital Input Current
VIN = 0V to VDD
CIN
Digital Input Capacitance
(Note 7)
2
V
0.8
V
±10
μA
1.5
pF
3.299
3.29
V
V
LOGIC OUTPUTS (CMOS MODE)
OVDD = 3.3V
VOH
VOL
High Level Output Voltage
Low Level Output Voltage
VDD = 3.3V
VDD = 3.3V
IO = –10μA
IO = –200μA
l
IO = 160μA
IO = 1.60mA
l
3.1
0.01
0.1
0.4
V
V
ISOURCE
Output Source Current
VOUT = 0V
–50
mA
ISINK
Output Sink Current
VOUT = 3.3V
50
mA
VOH
High Level Output Voltage
VDD = 3.3V
IO = –200μA
2.49
V
VOL
Low Level Output Voltage
VDD = 3.3V
IO = 1.6mA
0.1
V
VOH
High Level Output Voltage
VDD = 3.3V
IO = –200μA
1.79
V
VOL
Low Level Output Voltage
VDD = 3.3V
IO = 1.6mA
0.1
V
OVDD = 2.5V
OVDD = 1.8V
LOGIC OUTPUTS (LVDS MODE)
STANDARD LVDS
VDD
Differential Output Voltage
100Ω Differential Load
l
247
350
454
VOS
Output Common Mode Voltage
100Ω Differential Load
l
1.125
1.2
1.375
VDD
Differential Output Voltage
100Ω Differential Load
l
125
175
250
VOS
Output Common Mode Voltage
100Ω Differential Load
l
1.125
1.2
1.375
mV
V
LOW POWER LVDS
mV
V
220814fb
5
LTC2208-14
POWER REQUIREMENTS
The l denotes the speciﬁcations which apply over the full operating temperature
range, otherwise speciﬁcations are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VDD
Analog Supply Voltage
(Note 8)
PSHDN
Shutdown Power
SHDN = VDD
l
MIN
TYP
MAX
UNITS
3.135
3.3
3.465
V
0.2
mW
STANDARD LVDS OUTPUT MODE
OVDD
Output Supply Voltage
IVDD
Analog Supply Current
IOVDD
PDIS
(Note 8)
l
3
3.3
3.6
V
l
401
470
mA
Output Supply Voltage
l
71
90
mA
Power Dissipation
l
1498
1782
mW
3.3
3.6
V
LOW POWER LVDS OUTPUT MODE
(Note 8)
l
OVDD
Output Supply Voltage
3
IVDD
Analog Supply Current
l
401
470
mA
IOVDD
Output Supply Voltage
l
40
50
mA
PDIS
Power Dissipation
l
1356
1650
mW
CMOS OUTPUT MODE
(Note 8)
l
OVDD
Output Supply Voltage
IVDD
Analog Supply Current
l
PDIS
Power Dissipation
l
0.5
3.6
V
401
470
mA
1320
1551
mW
TIMING CHARACTERISTICS
The l denotes the speciﬁcations which apply over the full operating temperature
range, otherwise speciﬁcations are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fS
Sampling Frequency
(Note 8)
l
130
MHz
tL
ENC Low Time
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
l
l
3.65
2.6
3.846
3.846
1000
1000
ns
ns
tH
ENC High Time
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
l
l
3.65
2.6
3.846
3.846
1000
1000
ns
ns
tAP
Sample-and-Hold Aperture Delay
1
–1
ns
LVDS OUTPUT MODE (STANDARD AND LOW POWER)
tD
ENC to DATA Delay
(Note 7)
l
1.3
2.5
1.3
–0.6
3.8
ns
2.5
3.8
ns
0
0.6
ns
tC
ENC to CLKOUT Delay
(Note 7)
l
tSKEW
DATA to CLKOUT Skew
(tC-tD) (Note 7)
l
tRISE
Output Rise Time
0.5
ns
tFALL
Output Fall Time
0.5
ns
Data Latency
Data Latency
7
Cycles
CMOS OUTPUT MODE
tD
ENC to DATA Delay
(Note 7)
l
1.3
2.7
4
ns
tC
ENC to CLKOUT Delay
(Note 7)
l
1.3
2.7
4
ns
tSKEW
DATA to CLKOUT Skew
(tC-tD) (Note 7)
l
–0.6
0
0.6
ns
Data Latency
Data Latency
Full Rate CMOS
Demuxed
7
7
Cycles
Cycles
220814fb
6
LTC2208-14
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND, with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3.3V, fSAMPLE = 130MHz, LVDS outputs, differential ENC+/
ENC– = 2VP-P sine wave with 1.6V common mode, input range = 2.25VP-P
with differential drive (PGA = 0), unless otherwise speciﬁed.
Note 5: Integral nonlinearity is deﬁned as the deviation of a code from a “best
ﬁt straight line” to the transfer curve. The deviation is measured from the
center of the quantization band.
Note 6: Offset error is the offset voltage measured from –1/2LSB when the
output code ﬂickers between 00 0000 0000 0000 and 11 1111 1111 1111 in
2’s complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: Recommended operating conditions.
TIMING DIAGRAM
LVDS Output Mode Timing
All Outputs are Differential and Have LVDS Levels
tAP
ANALOG
INPUT
N+1
N+4
N
N+3
N+2
tH
tL
ENC–
ENC+
tD
N–7
D0-D13, OF
CLKOUT+
CLKOUT –
N–6
N–5
N–4
N–3
tC
220814 TD01
220814fb
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LTC2208-14
TIMING DIAGRAM
Full-Rate CMOS Output Mode Timing
All Outputs are Single-Ended and Have CMOS Levels
tAP
ANALOG
INPUT
N+1
N+4
N
N+3
N+2
tH
tL
–
ENC
ENC+
tD
N–7
DA0-DA13, OFA
N–6
N–5
N–4
N–3
tC
CLKOUTA
CLKOUTB
HIGH IMPEDANCE
DB0-DB13, OFB
220814 TD02
Demultiplexed CMOS Output Mode Timing
All Outputs are Single-Ended and Have CMOS Levels
tAP
ANALOG
INPUT
N+1
N
N+4
N+2
N+3
tH
tL
–
ENC
ENC+
tD
DA0-DA13, OFA
N–8
N–6
N–4
N–7
N–5
N–3
tD
DB0-DB13, OFB
tC
CLKOUTA
CLKOUTB
220814 TD03
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8
LTC2208-14
TYPICAL PERFORMANCE CHARACTERISTICS
Differential Nonlinearity (DNL)
vs Output Code
1.0
0.5
0.8
0.4
0.6
0.3
0.4
0.2
0.2
0
–0.2
–0.4
200000
150000
0.1
0
–0.1
100000
–0.2
–0.6
–0.3
–0.8
–0.4
–1.0
50000
–0.5
0
4096
12288
8192
OUTPUT CODE
0
16384
4096
12288
8192
OUTPUT CODE
220814 G01
0
8176
16384
–20
–20
–20
–30
–30
–30
–70
–80
AMPLITUDE (dBFS)
0
–10
AMPLITUDE (dBFS)
0
–10
–60
–40
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
10
40
30
20
50
FREQUENCY (MHz)
60
–120
0
10
40
30
20
50
FREQUENCY (MHz)
220814 G04
0
0
–10
–10
–20
–20
–20
–30
–30
–30
–60
–70
–80
AMPLITUDE (dBFS)
0
–50
–40
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
10
40
30
20
50
FREQUENCY (MHz)
60
220814 G07
60
–40
–90
0
40
30
20
50
FREQUENCY (MHz)
32k Point 2-Tone FFT, fIN = 20.14MHz
and 14.25MHz, –25dBFS, PGA = 0,
RAND = “On”, Dither “Off”
–10
–40
10
220814 G06
32k Point 2-Tone FFT, fIN = 20.14MHz
and 14.25MHz, –7dBFS, PGA = 0,
RAND = “On”, Dither “Off”
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
60
220814 G05
128k Point FFT, fIN = 15.11MHz,
–40dBFS, PGA = 0, RAND = “On”,
Dither “On”
8186
–40
–90
0
8184
128k Point FFT, fIN = 15.11MHz,
–40dBFS, PGA = 0, RAND = “On”,
Dither “Off”
0
–50
8182
8180
OUTPUT CODE
220814 G03
32k Point FFT, fIN = 15.11MHz,
–1dBFS, PGA = 0, RAND = “On”,
Dither “Off”
–10
–40
8178
220814 G02
32k Point FFT, fIN = 5.21MHz,
–1dBFS, PGA = 0, RAND = “On”,
Dither “Off”
AMPLITUDE (dBFS)
AC Grounded Input Histogram
250000
COUNT
DNL ERROR (LSB)
INL ERROR (LSB)
Integral Nonlinearity (INL)
vs Output Code
–120
0
10
40
30
20
50
FREQUENCY (MHz)
60
220814 G08
0
10
40
30
20
50
FREQUENCY (MHz)
60
220814 G09
220814fb
9
LTC2208-14
TYPICAL PERFORMANCE CHARACTERISTICS
SFDR vs Input Level, fIN = 15.1MHz,
PGA = 0, RAND = “On”, Dither “Off”
32k Point FFT, fIN = 30.11MHz,
–1dBFS, PGA = 0, RAND = “On”,
Dither “Off”
SFDR vs Input Level, fIN = 15.1MHz,
PGA = 0, RAND = “On”, Dither “On”
120
0
120
–10
–20
100
80
60
40
20
–30
AMPLITUDE (dBFS)
SFDR (dBc AND dBFS)
SFDR (dBc AND dBFS)
100
80
60
40
–40
–50
–60
–70
–80
–90
–100
20
–110
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
220814 G10
0
–20
–20
–20
–30
–30
–30
–60
–70
–80
AMPLITUDE (dBFS)
0
–10
AMPLITUDE (dBFS)
0
–10
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
10
40
30
20
50
FREQUENCY (MHz)
60
–120
0
10
40
30
20
50
FREQUENCY (MHz)
0
60
220814 G13
220814 G14
128k Point FFT, fIN = 70.11MHz,
–40dBFS, PGA = 0, RAND = “On”,
Dither “Off”
128k Point FFT, fIN = 70.11MHz,
–40dBFS, PGA = 0, RAND = “On”,
Dither “On”
0
–10
–20
–20
–20
–30
–30
–30
–50
–60
–70
–80
AMPLITUDE (dBFS)
0
–10
–40
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
10
40
30
20
50
FREQUENCY (MHz)
60
220814 G16
60
–40
–90
0
40
30
20
50
FREQUENCY (MHz)
220814 G15
0
–40
10
32k Point FFT, fIN = 70.11MHz,
–1dBFS, PGA = 1, RAND = “On”,
Dither “Off”
–10
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
60
32k Point FFT, fIN = 70.11MHz,
–10dBFS, PGA = 0, RAND = “On”,
Dither “Off”
0
–50
40
30
20
50
FREQUENCY (MHz)
220814 G12
32k Point FFT, fIN = 70.11MHz,
–1dBFS, PGA = 0, RAND = “On”,
Dither “Off”
–10
–40
10
220814 G11
32k Point FFT, fIN = 30.11MHz,
–25dBFS, PGA = 0, RAND = “On”,
Dither “On”
AMPLITUDE (dBFS)
–120
0
–120
0
10
40
30
20
50
FREQUENCY (MHz)
60
220814 G17
0
10
40
30
20
50
FREQUENCY (MHz)
60
220814 G18
220814fb
10
LTC2208-14
TYPICAL PERFORMANCE CHARACTERISTICS
SFDR vs Input Level, fIN = 70.2MHz,
PGA = 0, RAND = “On”, Dither “Off”
32k Point 2-Tone FFT, fIN = 67.2MHz
and 74.4MHz, –7dBFS, PGA = 0,
RAND = “On”, Dither “Off”
SFDR vs Input Level, fIN = 70.2MHz,
PGA = 0, RAND = “On”, Dither “On”
120
0
120
–10
–20
100
80
60
40
20
–30
AMPLITUDE (dBFS)
SFDR (dBc AND dBFS)
SFDR (dBc AND dBFS)
100
80
60
40
–40
–50
–60
–70
–80
–90
–100
20
–110
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
220814 G19
0
–20
–20
–20
–30
–30
–30
–70
–80
AMPLITUDE (dBFS)
0
–10
AMPLITUDE (dBFS)
0
–10
–60
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
0
10
40
30
20
50
FREQUENCY (MHz)
–120
0
60
220814 G22
10
40
30
20
50
FREQUENCY (MHz)
0
60
10
40
30
20
50
FREQUENCY (MHz)
220814 G23
SFDR vs Input Level, fIN = 140.1MHz,
PGA = 1, RAND = “On”, Dither “Off”
60
220814 G24
32k Point FFT, fIN = 170.1MHz,
–1dBFS, PGA = 1, RAND = “On”,
Dither “Off”
SFDR vs Input Level, fIN = 140.1MHz,
PGA = 1, RAND = “On”, Dither “On”
0
120
120
60
32k Point FFT, fIN = 140.11MHz,
–1dBFS, PGA = 1, RAND = “On”,
Dither “Off”
0
–50
40
30
20
50
FREQUENCY (MHz)
220814 G21
32k Point FFT, fIN = 140.11MHz,
–1dBFS, PGA = 0, RAND = “On”,
Dither “Off”
–10
–40
10
220814 G20
32k Point 2-Tone FFT, fIN = 67.2MHz
and 74.4MHz, –15dBFS, PGA = 0,
RAND = “On”, Dither “Off”
AMPLITUDE (dBFS)
–120
0
–10
80
60
40
–30
AMPLITUDE (dBFS)
SFDR (dBc AND dBFS)
SFDR (dBc AND dBFS)
–20
100
100
80
60
40
–50
–60
–70
–80
–90
–100
20
20
–40
–110
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
220814 G25
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
–120
0
220814 G26
0
10
40
30
20
50
FREQUENCY (MHz)
60
220814 G27
220814fb
11
LTC2208-14
TYPICAL PERFORMANCE CHARACTERISTICS
32k Point FFT, fIN = 250.11MHz,
–10dBFS, PGA = 1, RAND = “On”,
Dither “Off”
32k Point FFT, fIN = 380.11MHz,
–1dBFS, PGA = 1, RAND = “On”,
Dither “Off”
0
0
–10
–10
–20
–20
–20
–30
–30
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
0
–10
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
32k Point FFT, fIN = 250.11MHz,
–1dBFS, PGA = 1, RAND = “On”,
Dither “Off”
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
0
10
40
30
20
50
FREQUENCY (MHz)
–120
0
60
10
40
30
20
50
FREQUENCY (MHz)
–10
100
–40
95
–70
–80
77
76
PGA = 0
PGA = 1
SNR (dBFS)
SFDR (dBc)
AMPLITUDE (dBFS)
–30
90
85
PGA = 0
–90
75
74
PGA = 1
80
73
75
–100
72
70
–110
–120
0
10
40
30
20
50
FREQUENCY (MHz)
71
65
60
0
50
100
150
250
200
INPUT FREQUENCY (MHz)
220814 G31
105
105
100
100
95
90
85
80
SNR
IVDD vs Sample Rate,
fIN = 5.1MHz, –1dBfs
470
450
SFDR
VDD = 3.47V
430
95
IVDD (mA)
SNR AND SFDR (dBFS)
110
300
220814 G33
SNR and SFDR vs Supply Voltage
(VDD), fIN = 5.1MHz, –1dBFS
110
SFDR
200
100
INPUT FREQUENCY (MHz)
0
300
220814 G32
SNR and SFDR vs Sample Rate
fIN = 5.1MHz, –1dBFS
SNR AND SFDR (dBFS)
SNR vs Input Frequency
105
–20
60
78
110
–60
40
30
20
50
FREQUENCY (MHz)
220814 G30
SFDR (HD2 and HD3)
vs Input Frequency
0
–50
10
220814 G29
220814 G28
32k Point FFT, fIN = 380.11MHz,
–10dBFS, PGA = 1, RAND = “On”,
Dither “Off”
90
85
80
VDD = 3.3V
410
VDD = 3.13V
390
SNR
370
75
75
70
0
60
0
25
50 75 100 125 150 175 200
SAMPLE RATE (Msps)
220814 G34
70
2.8
350
3.2
3.0
3.4
SUPPLY VOLTAGE (V)
3.6
220814 G35
0
20
40 60 80 100 120 140 160
SAMPLE RATE (Msps)
220814 G36
220814fb
12
LTC2208-14
TYPICAL PERFORMANCE CHARACTERISTICS
Gain Error Drift vs Temperature,
Internal Reference, Drift from 25°C
SNR and SFDR vs Duty Cycle
0.2
110
80
SNR DCS ON
70
60
0
–0.1
–0.2
–0.3
0
–0.02
–0.04
–0.06
–0.10
70
–0.5
–50 –30
DUTY CYCLE (%)
30
50
–10 10
TEMPERATURE (°C)
70
90
–0.12
–50
–30
30
–10 10
50
TEMPERATURE (°C)
220814 G38
220814 G37
Input Offset Voltage Drift
vs Temperature, Drift from 25°C
70
90
220814 G39
SNR and SFDR vs Input Common
Mode Voltage
0.24
100
SFDR
0.20
SNR (dBFS) AND SFDR (dBc)
INPUT OFFSET VOLTAGE (mV)
0.02
–0.08
–0.4
SNR DCS OFF
50
GAIN ERROR DRIFT (%)
GAIN ERROR DRIFT (%)
90
0.15
0.10
0.05
90
80
SNR
70
0
–0.05
–50 –30
30
50
–10 10
TEMPERATURE (°C)
70
60
0.50
90
0.8
4
0.6
3
FULL-SCALE ERROR (%)
5
0.2
0
–0.2
–0.4
2
1
0
–1
–2
–0.6
–3
–0.8
–4
–1.0
–5
0 50 100 150 200 250 300 350 400 450 500
TIME AFTER WAKE-UP OR CLOCK START (μs)
2208 G42
2.00
Full-Scale Settling After Wake
Up from Shutdown or Starting
Encode Clock
1.0
0.4
0.75 1.00 1.25 1.50 1.75
INPUT COMMON MODE VOLTAGE (V)
220814 G41
220814 G40
Mid-Scale Settling After Wake
Up from Shutdown or Starting
Encode Clock
FULL-SCALE ERROR (%)
SFDR AND SNR (dBFS)
SFDR DCS OFF
40
0.06
0.04
100
30
0.08
0.1
SFDR DCS ON
60
Gain Error Drift vs Temperature,
External Reference, Drift from 25°C
0 100 200 300 400 500 600 700 800 900 1000
TIME FROM WAKE-UP OR CLOCK START (μs)
2208 G43
220814fb
13
LTC2208-14
PIN FUNCTIONS
For CMOS Mode. Full Rate or Demultiplexed
SENSE (Pin 1): Reference Mode Select and External
Reference Input. Tie SENSE to VDD to select the internal
2.5V bandgap reference. An external reference of 2.5V or
1.25V may be used; both reference values will set a full
scale ADC range of 2.25V (PGA = 0).
GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground.
VCM (Pin 3): 1.25V Output. Optimum voltage for input common mode. Must be bypassed to ground with a minimum
of 2.2μF. Ceramic chip capacitors are recommended.
VDD (Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin.
Bypass to GND with 0.1μF ceramic chip capacitors.
AIN+ (Pin 8): Positive Differential Analog Input.
AIN– (Pin 9): Negative Differential Analog Input.
ENC+ (Pin 12): Positive Differential Encode Input. The
sampled analog input is held on the rising edge of ENC+.
Internally biased to 1.6V through a 6.2kΩ resistor. Output
data can be latched on the rising edge of ENC+.
ENC– (Pin 13): Negative Differential Encode Input. The
sampled analog input is held on the falling edge of ENC –.
Internally biased to 1.6V through a 6.2kΩ resistor. Bypass to ground with a 0.1μF capacitor for a single-ended
Encode signal.
SHDN (Pin 19): Power Shutdown Pin. SHDN = low results
in normal operation. SHDN = high results in powered
down analog circuitry and the digital outputs are placed
in a high impedance state.
DITH (Pin 20): Internal Dither Enable Pin. DITH = low
disables internal dither. DITH = high enables internal dither.
Refer to Internal Dither section of this data sheet for details
on dither operation.
NC (Pins 21, 22): No Connect.
DB0-DB13 (Pins 23-30 and 33-38): Digital Outputs, B Bus.
DB13 is the MSB. Active in demultiplexed mode. The B bus
is in high impedance state in full rate CMOS mode.
OGND (Pins 31 and 50): Output Driver Ground.
OVDD (Pins 32 and 49): Positive Supply for the Output
Drivers. Bypass to ground with O.1μF capacitor.
OFB (Pin 39): Overﬂow/Underﬂow Digital Output for the B
Bus. OFB is high when an over or under ﬂow has occurred
on the B bus. This pin goes to high impedance state in
full rate CMOS mode.
CLKOUTB (Pin 40): Data Valid Output. CLKOUTB will toggle
at the sample rate in full rate CMOS mode or at 1/2 the
sample rate in demultiplexed mode. Latch the data on the
falling edge of CLKOUTB.
CLKOUTA (Pin 41): Inverted Data Valid Output. CLKOUTA
will toggle at the sample rate in full rate CMOS mode or
at 1/2 the sample rate in demultiplexed mode. Latch the
data on the rising edge of CLKOUTA.
DNC (Pins 42, 43): Do Not Connect in CMOS Mode.
DA0-DA13 (Pins 44-48 and 51-59): Digital Outputs, A Bus.
DA13 is the MSB. Output bus for full rate CMOS mode
and demultiplexed mode.
OFA (Pin 60): Overﬂow/Underﬂow Digital Output for the
A Bus. OFA is high when an over or under ﬂow has occurred on the A bus.
LVDS (Pin 61): Data Output Mode Select Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting LVDS
to 1/3VDD selects demultiplexed CMOS mode. Connecting
LVDS to 2/3VDD selects Low Power LVDS mode. Connecting LVDS to VDD selects Standard LVDS mode.
MODE (Pin 62): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and disables the clock duty
cycle stabilizer. Connecting MODE to 1/3VDD selects offset
binary output format and enables the clock duty cycle stabilizer. Connecting MODE to 2/3VDD selects 2’s complement
output format and enables the clock duty cycle stabilizer.
Connecting MODE to VDD selects 2’s complement output
format and disables the clock duty cycle stabilizer.
RAND (Pin 63): Digital Output Randomization Selection
Pin. RAND low results in normal operation. RAND high
selects D1-D13 to be EXCLUSIVE-ORed with D0 (the
LSB). The output can be decoded by again applying an
XOR operation between the LSB and all other bits. This
mode of operation reduces the effects of digital output
interference.
220814fb
14
LTC2208-14
PIN FUNCTIONS
PGA (Pin 64): Programmable Gain Ampliﬁer Control Pin.
Low selects a front-end gain of 1, input range of 2.25VP-P.
High selects a front-end gain of 1.5, input range of
1.5VP-P.
GND (Exposed Pad): ADC Power Ground. The exposed
pad on the bottom of the package must be soldered to
ground.
NC (Pins 21, 22): No Connect.
NC (Pins 23, 24): Do Not Connect in LVDS Mode.
D0–/D0+ to D13–/D13+ (Pins 25-30, 33-38, 41-48 and
51-58): LVDS Digital Outputs. All LVDS outputs require
differential 100Ω termination resistors at the LVDS receiver.
D13+/D13– is the MSB.
OGND (Pins 31 and 50): Output Driver Ground.
For LVDS Mode. Standard or Low Power
OVDD (Pins 32 and 49): Positive Supply for the Output
Drivers. Bypass to ground with 0.1μF capacitor.
SENSE (Pin 1): Reference Mode Select and External
Reference Input. Tie SENSE to VDD to select the internal
2.5V bandgap reference. An external reference of 2.5V or
1.25V may be used; both reference values will set a full
scale ADC range of 2.25V (PGA = 0).
CLKOUT–/CLKOUT + (Pins 39 and 40): LVDS Data Valid
0utput. Latch data on the rising edge of CLKOUT +, falling
edge of CLKOUT –.
GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground.
VCM (Pin 3): 1.25V Output. Optimum voltage for input common mode. Must be bypassed to ground with a minimum
of 2.2μF. Ceramic chip capacitors are recommended.
VDD (Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin.
Bypass to GND with 0.1μF ceramic chip capacitors.
AIN + (Pin 8): Positive Differential Analog Input.
AIN – (Pin 9): Negative Differential Analog Input.
ENC + (Pin 12): Positive Differential Encode Input. The
sampled analog input is held on the rising edge of ENC+.
Internally biased to 1.6V through a 6.2kΩ resistor. Output
data can be latched on the rising edge of ENC+.
ENC – (Pin 13): Negative Differential Encode Input. The
sampled analog input is held on the falling edge of ENC –.
Internally biased to 1.6V through a 6.2kΩ resistor. Bypass to ground with a 0.1μF capacitor for a single-ended
Encode signal.
SHDN (Pin 19): Power Shutdown Pin. SHDN = low results
in normal operation. SHDN = high results in powered
down analog circuitry and the digital outputs are set in
high impedance state.
DITH (Pin 20): Internal Dither Enable Pin. DITH = low
disables internal dither. DITH = high enables internal dither.
Refer to Internal Dither section of the data sheet for details
on dither operation.
OF–/OF+ (Pins 59 and 60): Overﬂow/Underﬂow Digital Output OF is high when an over or under ﬂow has occurred.
LVDS (Pin 61): Data Output Mode Select Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting LVDS
to 1/3VDD selects demultiplexed CMOS mode. Connecting
LVDS to 2/3VDD selects Low Power LVDS mode. Connecting LVDS to VDD selects Standard LVDS mode.
MODE (Pin 62): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and disables the clock duty
cycle stabilizer. Connecting MODE to 1/3VDD selects offset
binary output format and enables the clock duty cycle stabilizer. Connecting MODE to 2/3VDD selects 2’s complement
output format and enables the clock duty cycle stabilizer.
Connecting MODE to VDD selects 2’s complement output
format and disables the clock duty cycle stabilizer.
RAND (Pin 63): Digital Output Randomization Selection Pin.
RAND low results in normal operation. RAND high selects
D1-D13 to be EXCLUSIVE-ORed with D0 (the LSB). The
output can be decoded by again applying an XOR operation
between the LSB and all other bits. The mode of operation
reduces the effects of digital output interference.
PGA (Pin 64): Programmable Gain Ampliﬁer Control Pin. Low
selects a front-end gain of 1, input range of 2.25VP-P. High
selects a front-end gain of 1.5, input range of 1.5VP-P.
GND (Exposed Pad Pin 65): ADC Power Ground. The
exposed pad on the bottom of the package must be soldered to ground.
220814fb
15
LTC2208-14
BLOCK DIAGRAM
AIN+
AIN–
VDD
INPUT
S/H
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
GND
DITHER
SIGNAL
GENERATOR
CORRECTION LOGIC
AND
SHIFT REGISTER
ADC CLOCKS
RANGE
SELECT
OVDD
SENSE
PGA
VCM
BUFFER
ADC
REFERENCE
DIFFERENTIAL
INPUT
LOW JITTER
CLOCK
DRIVER
CONTROL
LOGIC
OUTPUT
DRIVERS
•
•
•
VOLTAGE
REFERENCE
OGND
ENC+
ENC–
SHDN PGA RAND M0DE LVDS
CLKOUT+
CLKOUT–
OF+
OF–
D13+
D13–
D0+
D0–
220814 F01
DITH
Figure 1. Functional Block Diagram
220814fb
16
LTC2208-14
OPERATION
DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N+D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited to frequencies above DC to below half the sampling
frequency.
Signal-to-Noise Ratio
The signal-to-noise (SNR) is the ratio between the RMS
amplitude of the fundamental input frequency and the RMS
amplitude of all other frequency components, except the
ﬁrst ﬁve harmonics.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
THD = –20Log (√(V22 + V32 + V42 + ... VN2)/V1)
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second
through nth harmonics.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function
can create distortion products at the sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 3rd order IMD terms include (2fa + fb),
(fa + 2fb), (2fa - fb) and (fa - 2fb). The 3rd order IMD is
deﬁned as the ratio of the RMS value of either input tone
to the RMS value of the largest 3rd order IMD product.
Spurious Free Dynamic Range (SFDR)
The ratio of the RMS input signal amplitude to the RMS
value of the peak spurious spectral component expressed
in dBc. SFDR may also be calculated relative to full scale
and expressed in dBFS.
Full Power Bandwidth
The Full Power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is reduced
by 3dB for a full scale input signal.
Aperture Delay Time
The time from when a rising ENC + equals the ENC– voltage
to the instant that the input signal is held by the sampleand-hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from convertion
to conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π • fIN • tJITTER)
220814fb
17
LTC2208-14
APPLICATIONS INFORMATION
CONVERTER OPERATION
The LTC2208-14 is a CMOS pipelined multistep converter
with a front-end PGA. As shown in Figure 1, the converter
has ﬁve pipelined ADC stages; a sampled analog input
will result in a digitized value seven cycles later (see the
Timing Diagram). The analog input is differential for improved common mode noise immunity and to maximize
the input range. Additionally, the differential input drive
will reduce even order harmonics of the sample and hold
circuit. The encode input is also differential for improved
common mode noise immunity.
The LTC2208-14 has two phases of operation, determined
by the state of the differential ENC+/ENC – input pins. For
brevity, the text will refer to ENC+ greater than ENC – as
ENC high and ENC+ less than ENC – as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage ampliﬁer. In
operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is ampliﬁed and
output by the residue ampliﬁer. Successive stages operate out of phase so that when odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the voltage on the
sample capacitors is held. While ENC is high, the held
input voltage is buffered by the S/H ampliﬁer which drives
the ﬁrst pipelined ADC stage. The ﬁrst stage acquires
the output of the S/H ampliﬁer during the high phase of
ENC. When ENC goes back low, the ﬁrst stage produces
its residue which is acquired by the second stage. At
the same time, the input S/H goes back to acquiring the
analog input. When ENC goes high, the second stage
produces its residue which is acquired by the third stage.
An identical process is repeated for the third and fourth
stages, resulting in a fourth stage residue that is sent to
the ﬁfth stage for ﬁnal evaluation.
Each ADC stage following the ﬁrst has additional range to
accommodate ﬂash and ampliﬁer offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.
18
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2208-14
CMOS differential sample and hold. The differential analog inputs are sampled directly onto sampling capacitors
(CSAMPLE) through NMOS transitors. The capacitors shown
attached to each input (CPARASITIC) are the summation of
all other capacitance associated with each input.
During the sample phase when ENC is low, the NMOS
transistors connect the analog inputs to the sampling
capacitors and they charge to, and track the differential
input voltage. When ENC transitions from low to high, the
sampled input voltage is held on the sampling capacitors.
During the hold phase when ENC is high, the sampling
capacitors are disconnected from the input and the held
voltage is passed to the ADC core for processing. As ENC
transitions from high to low, the inputs are reconnected to
the sampling capacitors to acquire a new sample. Since
the sampling capacitors still hold the previous sample,
a charging glitch proportional to the change in voltage
between samples will be seen at this time. If the change
between the last sample and the new sample is small,
the charging glitch seen at the input will be small. If the
LTC2208-14
VDD
RPARASITIC
3Ω
AIN+
RON
20Ω
CSAMPLE
4.9pF
CPARASITIC
1.8pF
VDD
RPARASITIC
3Ω
AIN–
RON
20Ω
CSAMPLE
4.9pF
CPARASITIC
1.8pF
VDD
1.6V
6k
ENC+
ENC–
6k
1.6V
220814 F02
Figure 2. Equivalent Input Circuit
220814fb
LTC2208-14
APPLICATIONS INFORMATION
input change is large, such as the change seen with input
frequencies near Nyquist, then a larger charging glitch
will be seen.
Common Mode Bias
The ADC sample-and-hold circuit requires differential
drive to achieve speciﬁed performance. Each input should
swing ±0.5625V for the 2.25V range (PGA = 0) or ±0.375V
for the 1.5V range (PGA = 1), around a common mode
voltage of 1.25V. The VCM output pin (Pin 3) is designed
to provide the common mode bias level. VCM can be tied
directly to the center tap of a transformer to set the DC
input level or as a reference level to an op amp differential
driver circuit. The VCM pin must be bypassed to ground
close to the ADC with 2.2μF or greater.
Input Drive Impedance
As with all high performance, high speed ADCs the dynamic performance of the LTC2208-14 can be inﬂuenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and input reactance
can inﬂuence SFDR. At the falling edge of ENC the
sample and hold circuit will connect the 4.9pF sampling
capacitor to the input pin and start the sampling period.
The sampling period ends when ENC rises, holding the
sampled input on the sampling capacitor. Ideally, the
input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2F encode); however, this is not always possible and the
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
provide isolation from ADC S/H switching. The LTC2208-14
has a very broadband S/H circuit, DC to 700MHz; it can
be used in a wide range of applications; therefore, it is not
possible to provide a single recommended RC ﬁlter.
Figures 3, 4a and 4b show three examples of input RC
ﬁltering at three ranges of input frequencies. In general
it is desirable to make the capacitors as large as can be
tolerated—this will help suppress random noise as well
as noise coupled from the digital circuitry. The LTC220814 does not require any input ﬁlter to achieve data sheet
speciﬁcations; however, no ﬁltering will put more stringent
noise requirements on the input drive circuitry.
Transformer Coupled Circuits
Figure 3 shows the LTC2208-14 being driven by an RF
transformer with a center-tapped secondary. The secondary
center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used; however,
as the turns ratio increases so does the impedance seen by
the ADC. Source impedance greater than 50Ω can reduce
the input bandwidth and increase high frequency distortion. A disadvantage of using a transformer is the loss of
low frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
Center-tapped transformers provide a convenient means
of DC biasing the secondary; however, they often show
poor balance at high input frequencies, resulting in large
2nd order harmonics.
VCM
5Ω AIN+
10Ω
T1
8.2pF
35Ω
Input Filtering
A ﬁrst order RC low pass ﬁlter at the input of the ADC can
serve two functions: limit the noise from input circuitry and
LTC2208-14
8.2pF
0.1μF
10Ω
INPUT DRIVE CIRCUITS
2.2μF
5Ω
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2μF
35Ω
5Ω AIN–
8.2pF
220814 F03
Figure 3. Single-Ended to Differential Conversion
Using a Transformer. Recommended for Input
Frequencies from 5MHz to 100MHz
220814fb
19
LTC2208-14
APPLICATIONS INFORMATION
Figure 4a shows transformer coupling using a transmission line balun transformer. This type of transformer has
much better high frequency response and balance than
ﬂux coupled center tap transformers. Coupling capacitors are added at the ground and input primary terminals
to allow the secondary terminals to be biased at 1.25V.
Figure 4b shows the same circuit with components suitable for higher input frequencies.
VCM
2.2μF
0.1μF
0.1μF
5Ω AIN+
10Ω
ANALOG
INPUT
T1
1:1
25Ω
0.1μF
25Ω
10Ω
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2μF
LTC2208-14
4.7pF
4.7pF
5Ω AIN–
4.7pF
220814 F04a
Reference Operation
Figure 6 shows the LTC2208-14 reference circuitry consisting of a 2.5V bandgap reference, a programmable gain
ampliﬁer and control circuit. The LTC2208-14 has three
modes of reference operation: Internal Reference, 1.25V
external reference or 2.5V external reference. To use the
internal reference, tie the SENSE pin to VDD. To use an
external reference, simply apply either a 1.25V or 2.5V
reference voltage to the SENSE input pin. Both 1.25V
and 2.5V applied to SENSE will result in a full scale range
of 2.25VP-P (PGA = 0). A 1.25V output, VCM is provided
for a common mode bias for input drive circuitry. An
external bypass capacitor is required for the VCM output.
This provides a high frequency low impedance path to
ground for internal and external circuitry. This is also the
compensation capacitor for the reference; it will not be
stable without this capacitor. The minimum value required
for stability is 2.2μF.
Figure 4a. Using a Transmission Line Balun Transformer.
Recommended for Input Frequencies from 100MHz to 250MHz
VCM
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
VCM
ANALOG
INPUT
2.2μF
0.1μF
5Ω
ANALOG
INPUT
25Ω
0.1μF
T1
1:1
0.1μF
25Ω
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2μF
AIN+
+
CM
LTC2208-14
–
2.2μF
25Ω
AIN–
2.2pF
5Ω
2.2pF
AMPLIFIER = LTC6600-20,
LT1993, ETC.
AIN–
LTC2208-14
12pF
+
–
AIN+
25Ω
12pF
220814 F05
Figure 5. DC Coupled Input with Differential Ampliﬁer
220814 F04b
Figure 4b. Using a Transmission Line Balun Transformer.
Recommended for Input Frequencies from 250MHz to 500MHz
Direct Coupled Circuits
Figure 5 demonstrates the use of a differential ampliﬁer to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides
low frequency input response; however, the limited gain
bandwidth of any op amp or closed-loop ampliﬁer will degrade the ADC SFDR at high input frequencies. Additionally,
wideband op amps or differential ampliﬁers tend to have
high noise. As a result, the SNR will be degraded unless
the noise bandwidth is limited prior to the ADC input.
TIE TO VDD TO USE
INTERNAL 2.5V
REFERENCE
OR INPUT FOR
EXTERNAL 2.5V
REFERENCE
OR INPUT FOR
EXTERNAL 1.25V
REFERENCE
RANGE
SELECT
AND GAIN
CONTROL
INTERNAL
ADC
REFERENCE
SENSE
PGA
2.5V
BANDGAP
REFERENCE
VCM
BUFFER
1.25V
2.2μF
220814 F06
Figure 6. Reference Circuit
220814fb
20
LTC2208-14
APPLICATIONS INFORMATION
The internal programmable gain ampliﬁer provides the
internal reference voltage for the ADC. This ampliﬁer has
very stringent settling requirements and is not accessible
for external use.
The SENSE pin can be driven ±5% around the nominal 2.5V
or 1.25V external reference inputs. This adjustment range
can be used to trim the ADC gain error or other system
gain errors. When selecting the internal reference, the
SENSE pin should be tied to VDD as close to the converter
as possible. If the sense pin is driven externally it should
be bypassed to ground as close to the device as possible
with 1μF ceramic capacitor.
VCM
1.25V
2.2μF
3.3V
1μF
2
LT1461-2.5
4
6
SENSE
LTC2208-14
In applications where jitter is critical (high input frequencies), take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude possible. If using transformer coupling, use a higher turns ratio to increase the
amplitude.
3. If the ADC is clocked with a ﬁxed frequency sinusoidal
signal, ﬁlter the encode signal to reduce wideband
noise.
4. Balance the capacitance and series resistance at both
encode inputs such that any coupled noise will appear
at both inputs as common mode noise.
The encode inputs have a common mode range of 1.2V
to 3V. Each input may be driven from ground to VDD for
single-ended drive.
2.2μF
LTC2208-14
220814 F07
VDD
TO INTERNAL
ADC CLOCK
DRIVERS
Figure 7. A 2.25V Range ADC with an External 2.5V Reference
PGA Pin
The PGA pin selects between two gain settings for the ADC
front-end. PGA = 0 selects an input range of 2.25VP-P;
PGA = 1 selects an input range of 1.5VP-P. The 2.25V input
range has the best SNR; however, the distortion will be
higher for input frequencies above 100MHz. For applications with high input frequencies, the low input range
will have improved distortion; however, the SNR will be
approximately 1.8dB worse. See the Typical Performance
Characteristics section.
VDD
1.6V
6k
ENC
+
VDD
1.6V
6k
ENC–
220814 F08a
Figure 8a. Equivalent Encode Input Circuit
Driving the Encode Inputs
The noise performance of the LTC2208-14 can depend on
the encode signal quality as much as on the analog input.
The encode inputs are intended to be driven differentially,
primarily for noise immunity from common mode noise
sources. Each input is biased through a 6k resistor to a
1.6V bias. The bias resistors set the DC operating point
for transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.
Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
0.1μF
ENC+
T1
50Ω
100Ω
0.1μF
50Ω
0.1μF
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
LTC2208-14
8.2pF
ENC–
220814 F08b
Figure 8b. Transformer Driven Encode
220814fb
21
LTC2208-14
APPLICATIONS INFORMATION
ENC+
VTHRESHOLD = 1.6V
1.6V ENC– LTC2208-14
0.1μF
220814 F09
Figure 9. Single-Ended ENC Drive,
Not Recommended for Low Jitter
DIGITAL OUTPUTS
Digital Output Modes
3.3V
MC100LVELT22
3.3V
130Ω
Q0
130Ω
ENC+
D0
ENC–
LTC2208-14
Q0
83Ω
The lower limit of the LTC2208-14 sample rate is determined
by droop of the sample and hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The speciﬁed minimum operating frequency
for the LTC2208-14 is 1Msps.
83Ω
220814 F10
Figure 10. ENC Drive Using a CMOS to PECL Translator
The LTC2208-14 can operate in four digital output modes:
standard LVDS, low power LVDS, full rate CMOS, and
demultiplexed CMOS. The LVDS pin selects the mode of
operation. This pin has a four level logic input, centered at
0, 1/3VDD, 2/3VDD and VDD. An external resistor divider can
be used to set the 1/3VDD and 2/3VDD logic levels. Table 1
shows the logic states for the LVDS pin.
Table 1. LVDS Pin Function
LVDS
DIGITAL OUTPUT MODE
Maximum and Minimum Encode Rates
0V(GND)
Full-Rate CMOS
The maximum encode rate for the LTC2208-14 is 130Msps.
For the ADC to operate properly the encode signal should
have a 50% (±5%) duty cycle. Each half cycle must have at
least 3.65ns for the ADC internal circuitry to have enough
settling time for proper operation. Achieving a precise 50%
duty cycle is easy with differential sinusoidal drive using
a transformer or using symmetric differential logic such
as PECL or LVDS. When using a single-ended ENCODE
signal asymmetric rise and fall times can result in duty
cycles that are far from 50%.
1/3VDD
Demultiplexed CMOS
2/3VDD
Low Power LVDS
VDD
LVDS
An optional clock duty cycle stabilizer can be used if the
input clock does not have a 50% duty cycle. This circuit
uses the rising edge of ENC pin to sample the analog input.
The falling edge of ENC is ignored and an internal falling
edge is generated by a phase-locked loop. The input clock
duty cycle can vary from 30% to 70% and the clock duty
cycle stabilizer will maintain a constant 50% internal duty
cycle. If the clock is turned off for a long period of time,
the duty cycle stabilizer circuit will require one hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin must be
connected to 1/3VDD or 2/3VDD using external resistors.
Digital Output Buffers (CMOS Modes)
Figure 11 shows an equivalent circuit for a single output
buffer in CMOS Mode, Full-Rate or Demultiplexed. Each
buffer is powered by OVDD and OGND, isolated from the
ADC power and ground. The additional N-channel transistor
in the output driver allows operation down to low voltages.
The internal resistor in series with the output makes the
output appear as 50Ω to external circuitry and eliminates
the need for external damping resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2208-14 should drive a minimum
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as a ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF. A resistor in series with the
220814fb
22
LTC2208-14
APPLICATIONS INFORMATION
output may be used but is not required since the ADC has
a series resistor of 43Ω on-chip.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
LTC2208-14
OVDD
VDD
0.5V
TO 3.6V
VDD
0.1μF
OVDD
DATA
FROM
LATCH
PREDRIVER
LOGIC
43Ω
TYPICAL
DATA
OUTPUT
resistor, even if the signal is not used (such as OF+/OF– or
CLKOUT+/CLKOUT–). To minimize noise the PC board
traces for each LVDS output pair should be routed close
together. To minimize clock skew, all LVDS PC board traces
should have about the same length.
In Low Power LVDS Mode 1.75mA is steered between
the differential outputs, resulting in ±175mV at the LVDS
receiver’s 100Ω termination resistor. The output common mode voltage is 1.20V, the same as standard LVDS
Mode.
Data Format
The LTC2208-14 parallel digital output can be selected
for offset binary or 2’s complement format. The format
is selected with the MODE pin. This pin has a four level
logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An
external resistor divider can be used to set the 1/3VDD
and 2/3VDD logic levels. Table 2 shows the logic states
for the MODE pin.
OGND
220814 F11
Figure 11. Equivalent Circuit for a Digital Output Buffer
Digital Output Buffers (LVDS Modes)
Figure 12 shows an equivalent circuit for an LVDS output
pair. A 3.5mA current is steered from OUT+ to OUT– or
vice versa, which creates a ±350mV differential voltage
across the 100Ω termination resistor at the LVDS receiver.
A feedback loop regulates the common mode output voltage to 1.20V. For proper operation each LVDS output pair
must be terminated with an external 100Ω termination
Table 2. MODE Pin Function
MODE
OUTPUT FORMAT
CLOCK DUTY CYCLE STABILIZER
0(GND)
Offset Binary
Off
1/3VDD
Offset Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
OVDD
3.3V
LTC2208-14
0.1μF
3.5mA
VDD
VDD
OVDD
43Ω
DATA
FROM
LATCH
PREDRIVER
LOGIC
10k
10k
OVDD
100Ω
LVDS
RECEIVER
43Ω
1.20V
+
–
OGND
220814 F12
Figure 12. Equivalent Output Buffer in LVDS Mode
220814fb
23
LTC2208-14
APPLICATIONS INFORMATION
Overﬂow Bit
An overﬂow output bit (OF) indicates when the converter is
overranged or underranged. In CMOS mode, a logic high
on the OFA pin indicates an overﬂow or underﬂow on the
A data bus, while a logic high on the OFB pin indicates
an overﬂow on the B data bus. In LVDS mode, a differential logic high on OF+/OF– pins indicates an overﬂow or
underﬂow.
LSB and all other bits. The LSB, OF and CLKOUT outputs
are not affected. The output Randomizer function is active
when the RAND pin is high.
CLKOUT
CLKOUT
OF
OF
Output Clock
D13
The ADC has a delayed version of the encode input available as a digital output, CLKOUT. The CLKOUT pin can
be used to synchronize the converter data to the digital
system. This is necessary when using a sinusoidal encode. In both CMOS modes, A bus data will be updated
as CLKOUTA falls and CLKOUTB rises. In demultiplexed
CMOS mode the B bus data will be updated as CLKOUTA
falls and CLKOUTB rises.
In Full Rate CMOS Mode, only the A data bus is active;
data may be latched on the rising edge of CLKOUTA or
the falling edge of CLKOUTB.
In demultiplexed CMOS mode CLKOUTA and CLKOUTB
will toggle at 1/2 the frequency of the encode signal. Both
the A bus and the B bus may be latched on the rising edge
of CLKOUTA or the falling edge of CLKOUTB.
D13/D0
D12
D2
D12/D0
•
•
•
D2/D0
D1
RAND = HIGH,
RANDOMIZER
ENABLED
D1/D0
RAND
D0
D0
220814 F13
Figure 13. Functional Equivalent of Digital Output Randomizer
Digital Output Randomizer
Interference from the ADC digital outputs is sometimes
unavoidable. Interference from the digital outputs may be
from capacitive or inductive coupling or coupling through
the ground plane. Even a tiny coupling factor can result in
discernible unwanted tones in the ADC output spectrum.
By randomizing the digital output before it is transmitted
off chip, these unwanted tones can be randomized, trading
a slight increase in the noise ﬂoor for a large reduction in
unwanted tone amplitude.
The digital output is “Randomized” by applying an exclusive-OR logic operation between the LSB and all other data
output bits. To decode, the reverse operation is applied;
that is, an exclusive-OR operation is applied between the
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven.
For example, if the converter is driving a DSP powered
by a 1.8V supply, then OVDD should be tied to that same
1.8V supply. In CMOS mode OVDD can be powered with
any logic voltage up to the 3.6V. OGND can be powered
with any voltage from ground up to 1V and must be less
than OVDD. The logic outputs will swing between OGND
and OVDD. In LVDS Mode, OVDD should be connected to
a 3.3V supply and OGND should be connected to GND.
220814fb
24
LTC2208-14
APPLICATIONS INFORMATION
Internal Dither
PC BOARD
FPGA
The LTC2208-14 is a 14-bit ADC with a very linear transfer
function; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones.
Small errors in the transfer function are usually a result
of ADC element mismatches. An optional internal dither
mode can be enabled to randomize the input location on
the ADC transfer curve, resulting in improved SFDR for
low signal levels.
CLKOUT
OF
D13/D0
D13
D12/D0
As shown in Figure 15, the output of the sample-and-hold
ampliﬁer is summed with the output of a dither DAC. The
dither DAC is driven by a long sequence pseudo-random
number generator; the random number fed to the dither
DAC is also subtracted from the ADC result. If the dither
DAC is precisely calibrated to the ADC, very little of the
dither signal will be seen at the output. The dither signal
that does leak through will appear as white noise. The dither
DAC is calibrated to result in less than 0.5dB elevation in
the noise ﬂoor of the ADC, as compared to the noise ﬂoor
with dither off.
D12
•
•
•
LTC2208-14
D2/D0
D2
D1/D0
D1
D0
D0
220814 F14
Figure 14. Derandomizing a Randomized Digital Output
LTC2208-14
AIN+
ANALOG
INPUT
AIN–
14-BIT
PIPELINED
ADC CORE
S/H
AMP
CLOCK/DUTY
CYCLE
CONTROL
PRECISION
DAC
DIGITAL
SUMMATION
CLKOUT
OF
D13
•
•
•
D0
OUTPUT
DRIVERS
MULTIBIT DEEP
PSEUDO-RANDOM
NUMBER
GENERATOR
220814 F15
ENC
+
ENC
–
DITH
DITHER ENABLE
HIGH = DITHER ON
LOW = DITHER OFF
Figure 15. Functional Equivalent Block Diagram of Internal Dither Circuit
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25
LTC2208-14
APPLICATIONS INFORMATION
Grounding and Bypassing
The LTC2208-14 requires a printed circuit board with a
clean unbroken ground plane; a multilayer board with an
internal ground plane is recommended. The pinout of the
LTC2208-14 has been optimized for a ﬂowthrough layout
so that the interaction between inputs and digital outputs
is minimized. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated
as much as possible. In particular, care should be taken
not to run any digital track alongside an analog signal
track or underneath the ADC.
High quality ceramic bypass capacitors should be used
at the VDD, VCM, and OVDD pins. Bypass capacitors must
be located as close to the pins as possible. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
The LTC2208-14 differential inputs should run parallel and
close to each other. The input traces should be as short as
possible to minimize capacitance and to minimize noise
pickup.
Heat Transfer
Most of the heat generated by the LTC2208-14 is transferred from the die through the bottom-side exposed pad.
For good electrical and thermal performance, the exposed
pad must be soldered to a large grounded pad on the PC
board. It is critical that the exposed pad and all ground
pins are connected to a ground plane of sufﬁcient area
with as many vias as possible.
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26
LTC2208-14
PACKAGE DESCRIPTION
UP Package
64-Lead Plastic QFN (9mm × 9mm)
(Reference LTC DWG # 05-08-1705 Rev C)
0.70 p 0.05
7.15 p 0.05
7.50 REF
8.10 p 0.05 9.50 p 0.05
(4 SIDES)
7.15 p 0.05
PACKAGE OUTLINE
0.25 p 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
9 .00 p 0.10
(4 SIDES)
0.75 p 0.05
R = 0.10
TYP
R = 0.115
TYP
63 64
0.40 p 0.10
PIN 1 TOP MARK
(SEE NOTE 5)
1
2
PIN 1
CHAMFER
C = 0.35
7.15 p 0.10
7.50 REF
(4-SIDES)
7.15 p 0.10
(UP64) QFN 0406 REV C
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
0.25 p 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
220814fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC2208-14
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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LTC2204
16-Bit, 40Msps ADC
480mW, 79.1dB SNR, 100dB SFDR
LTC2205
16-Bit, 65Msps ADC
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LTC2206
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LTC2207
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LTC2220-1
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LTC2249
14-Bit, 65Msps ADC
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LTC2250
10-Bit, 105Msps ADC
320mW, 61.6dB SNR, 5mm × 5mm QFN Package
LTC2251
10-Bit, 125Msps ADC
395mW, 61.6dB SNR, 5mm × 5mm QFN Package
LTC2252
12-Bit, 105Msps ADC
320mW, 70.2dB SNR, 5mm × 5mm QFN Package
LTC2253
12-Bit, 125Msps ADC
395mW, 70.2dB SNR, 5mm × 5mm QFN Package
LTC2254
14-Bit, 105Msps ADC
320mW, 72.5dB SNR, 5mm × 5mm QFN Package
LTC2255
14-Bit, 125Msps ADC
395mW, 72.4dB SNR, 5mm × 5mm QFN Package
LTC2299
Dual 14-Bit, 80Msps ADC
445mW, 73dB SNR, 9mm × 9mm QFN Package
LT5512
DC-3GHz High Signal Level Downconverting Mixer
DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
LT5514
Ultralow Distortion IF Ampliﬁer/ADC Driver with
Digitally Controlled Gain
450MHz 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step
LT5522
600MHz to 2.7GHz High Linearity
Downconverting Mixer
4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB,
50Ω Single-Ended RF and LO Ports
220814fb
28 Linear Technology Corporation
LT 0909 REV B • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006

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