Maxim DS1556W-120+ 1m, nonvolatile, y2k-compliant timekeeping ram Datasheet

19-5500; Rev 9/10
DS1556
1M, Nonvolatile, Y2K-Compliant
Timekeeping RAM
www.maxim-ic.com
FEATURES


Integrated NV SRAM, Real-Time Clock
(RTC), Crystal, Power-Fail Control Circuit,
and Lithium Energy Source
TOP VIEW
RST
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
Clock Registers are Accessed Identically to
the Static RAM; These Registers Reside in
the 16 Top RAM Locations

Century Byte Register (i.e., Y2K Compliant)

Totally Nonvolatile with Over 10 Years of
Operation in the Absence of Power

Precision Power-On Reset

Programmable Watchdog Timer and RTC
Alarm

PIN CONFIGURATIONS
Battery Voltage-Level Indicator Flag

Power-Fail Write Protection Allows for 10%
VCC Power-Supply Tolerance

Also Available in Industrial Temperature
Range: -40°C to +85°C
VCC
A15
DQ0
13
20
DQ6
DQ1
DQ2
14
19
DQ5
15
18
DQ4
GND
16
17
DQ3
IRQ/FT
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
Encapsulated DIP

Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until
Power is Applied for the First Time
32
31
30
29
28
27
26
25
24
23
22
21
A0
BCD-Coded Year, Month, Date, Day, Hours,
Minutes, and seconds with Automatic LeapYear Compensation Valid Up to the Year
2100

1
Maxim
2 DS1556
3
4
5
6
7
8
9
10
11
12
IRQ/FT
A15
A16
RST
VCC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Maxim
DS1556
X1
GND
VBAT
X2
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
N.C.
N.C.
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
PowerCap Module Board
(Uses DS9034PCX PowerCap)
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
1 of 18
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
PIN DESCRIPTION
A0–A16
DQ0–DQ7
IRQ/FT
RST
CE
OE
WE
VCC
GND
N.C.
X1, X2
VBAT
- Address Input
- Data Input/Outputs
- Interrupt, Frequency Test Output (Open Drain)
- Power-On Reset Output (Open Drain)
- Chip Enable
- Output Enable
- Write Enable
- Power Supply Input
- Ground
- No Connection
- Crystal Connection
- Battery Connection
ORDERING INFORMATION
PART
TEMP RANGE
VOLTAGE
(V)
PIN-PACKAGE
TOP MARK**
DS1556-70+
DS1556-70IND+
DS1556P-70+
DS1556P-70IND+
DS1556W-120+
DS1556W-120IND+
DS1556WP-120+
DS1556WP-120IND+
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
5.0
5.0
5.0
5.0
3.3
3.3
3.3
3.3
32 EDIP (0.740a)
32 EDIP (0.740a)
34 PowerCap*
34 PowerCap*
32 EDIP (0.740a)
32 EDIP (0.740a)
34 PowerCap*
34 PowerCap*
DS1556+070
DS1556+070 IND
DS1556P+70
DS1556P+70 IND
DS1556W+120
DS1556W+120 IND
DS1556WP+120
DS1556WP+120 IND
+Denotes a lead(Pb)-free/RoHS-compliant package.
*DS9034-PCX+ or DS9034I-PCX+ required (must be ordered separately).
**A “+” in top mark denotes a lead(Pb)-free device. An “IND” anywhere on the top mark indicates an industrial temperature grade device.
2 of 18
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
DESCRIPTION
The DS1556 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) with an
RTC alarm, watchdog timer, power-on reset, battery monitor, and 128k x 8 nonvolatile static RAM. User
access to all registers within the DS1556 is accomplished with a byte-wide interface as shown in Figure 1.
The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour
BCD format. Corrections for day of month and leap year are made automatically.
The RTC registers are double-buffered into an internal and external set. The user has direct access to the
external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow
the user to access static data. Assuming the internal oscillator is turned on, the internal set of registers is
continuously updated, which occurs regardless of external registers settings to guarantee that accurate
RTC information is always maintained.
The DS1556 has interrupt (IRQ/FT) and reset (RST) outputs which can be used to control CPU activity.
The IRQ/FT interrupt output can be used to generate an external interrupt when the RTC register values
match user programmed alarm values. The interrupt is always available while the device is powered from
the system supply and can be programmed to occur when in the battery-backed state to serve as a system
wake-up. Either the IRQ/FT or RST outputs can also be used as a CPU watchdog timer, CPU activity is
monitored and an interrupt or reset output will be activated if the correct activity is not detected within
programmed limits. The DS1556 power-on reset can be used to detect a system power down or failure
and hold the CPU in a safe reset state until normal power returns and stabilizes; the RST output is used
for this function.
The DS1556 also contains its own power-fail circuitry, which automatically deselects the device when the
VCC supply enters an out of tolerance condition. This feature provides a high degree of data security
during unpredictable system operation brought on by low VCC levels.
PACKAGES
The DS1556 is available in two packages (32-pin DIP and 34-pin PowerCap module). The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap module board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1556P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
3 of 18
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
Figure 1. Block Diagram
Maxim
DS1556
Table 1. Operating Modes
VCC
VCC > VPF
VSO < VCC <VPF
VCC <VSO < VPF
CE
VIH
VIL
VIL
VIL
X
X
OE
X
X
VIL
VIH
X
X
WE
X
VIL
VIH
VIH
X
X
DQ0–DQ7
High-Z
DIN
DOUT
High-Z
High-Z
High-Z
MODE
Deselect
Write
Read
Read
Deselect
Data Retention
POWER
Standby
Active
Active
Active
CMOS Standby
Battery Current
DATA READ MODE
The DS1556 is in the read mode whenever CE (chip enable) is low and WE (write enable) is high. The
device architecture allows ripple-through access to any valid address location. Valid data will be available
at the DQ pins within tAA after the last address input is stable, providing that CE and OE access times are
satisfied. If CE or OE access times are not met, valid data will be available at the latter of chip enable
access (tCEA) or at output enable access time (tOEA). The state of the data input/output pins (DQ) is
controlled by CE and OE. If the outputs are activated before tAA, the data lines are driven to an
intermediate state until tAA. If the address inputs are changed while CE and OE remain valid, output data
will remain valid for output data hold time (tOH) but will then go indeterminate until the next address
access.
DATA WRITE MODE
The DS1556 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE. The addresses must be held valid throughout the
cycle. CE and WE must return inactive for a minimum of tWR prior to the initiation of a subsequent read
or write cycle. Data in must be valid tDS prior to the end of the write and remain valid for tDH afterward. In
4 of 18
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
a typical application, the OE signal will be high during a write cycle. However, OE can be active
provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE
transitioning low, the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the outputs tWEZ after WE goes active.
DATA-RETENTION MODE
The 5V device is fully accessible and data can be written and read only when VCC is greater than VPF.
However, when VCC is below the power-fail point VPF (point at which write protection occurs) the
internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch
point VSO (battery supply level), device power is switched from the VCC pin to the internal backup lithium
battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal
levels.
The 3.3V device is fully accessible and data can be written and read only when VCC is greater than VPF.
hen VCC falls below VPF, access to the device is inhibited. If VPF is less than VSO, the device power is
switched from VCC to the internal backup lithium battery when VCC drops below VPF. If VPF is greater
than VSO, the device power is switched from VCC to the internal backup lithium battery when VCC drops
below VSO. RTC operation and SRAM data are maintained from the battery until VCC is returned to
nominal levels.
All control, data, and address signals must be powered down when VCC is powered down.
BATTERY LONGEVITY
The DS1556 has a lithium power source that is designed to provide energy for the clock activity, and
clock and RAM data retention when the VCC supply is not present. The capability of this internal power
supply is sufficient to power the DS1556 continuously for the life of the equipment in which it is
installed. For specification purposes, the life expectancy is 10 years at 25C with the internal clock
oscillator running in the absence of VCC. Each DS1556 is shipped from Maxim with its lithium energy
source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than
VPF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the
DS1556 will be much longer than 10 years since no internal battery energy is consumed when VCC is
present.
INTERNAL BATTERY MONITOR
The DS1556 constantly monitors the battery voltage of the internal battery. The Battery Low Flag (BLF)
bit of the Flags Register (B4 of 1FFF0h) is not writable and should always be a 0 when read. If a 1 is ever
present, an exhausted lithium energy source is indicated and both the contents of the RTC and RAM are
questionable.
POWER-ON RESET
A temperature compensated comparator circuit monitors the level of VCC. When VCC falls to the power
fail trip point, the RST signal (open drain) is pulled low. When VCC returns to nominal levels, the RST
signal continues to be pulled low for a period of 40 ms to 200 ms. The power-on reset function is
independent of the RTC oscillator and thus is operational whether or not the oscillator is enabled.
5 of 18
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
CLOCK OPERATIONS
Table 2 and the following paragraphs describe the operation of RTC, alarm, and watchdog functions.
Table 2. Register Map
ADDRESS
DATA
B7
B6
1FFFFh
B5
B4
B3
FUNCTION
RANGE
Year
Year
00-99
Month
Month
01-12
Date
Date
01-31
Day
01-07
Hour
Hour
00-23
B2
10 Year
X
10
Month
10 Date
B1
B0
1FFFEh
X
X
1FFFDh
X
X
1FFFCh
X
Ft
1FFFBh
X
X
1FFFAh
X
10 Minutes
Minutes
Minutes
00-59
1FFF9h
OSC
10 Seconds
Seconds
Seconds
00-59
1FFF8h
W
R
Century
Control
00-39
1FFF7h
WDS
BMB4
BMB3
BMB2
BMB1
BMB0
RB1
RB0
1FFF6h
AE
Y
ABE
Y
Y
Y
Y
Y
1FFF5h
AM4
Y
10 Date
Date
Alarm Date
01-31
1FFF4h
AM3
Y
10 Hours
Hours
Alarm Hours
00-23
1FFF3h
AM2
10 Minutes
Minutes
Alarm Minutes
00-59
1FFF2h
AM1
10 Seconds
Seconds
Alarm Seconds
00-59
1FFF1h
Y
Y
Y
Y
Y
Y
Y
Y
Unused
1FFF0h
WF
AF
0
BLF
0
0
0
0
Flags
X
X
X
Day
10 Hour
10 Century
X = Unused, Read/Writable Under Write and Read Bit Control
Y = Unused, Read/Writable Without Write and Read Bit Control
FT = Frequency Test Bit
OSC = Oscillator Start/Stop Bit
W = Write Bit
R = Read Bit
WDS = Watchdog Steering Bit
BMB0 to BMB4 = Watchdog Multiplier Bits
Watchdog
Interrupts
AE = Alarm Flag Enable
ABE = Alarm in Battery-Backup Mode Enable
AM1 to AM4 = Alarm Mask Bits
WF = Watchdog Flag
AF = Alarm Flag
0 = 0 (Read Only)
BLF = Battery Low Flag
RB0 to RB1 = Watchdog Resolution Bits
CLOCK OSCILLATOR CONTROL
The clock oscillator can be stopped at any time. To increase the shelf life of the backup lithium battery
source, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the
MSB of the Seconds Register (B7 of 1FFF9h). Setting it to a 1 stops the oscillator, setting to a 0 starts the
oscillator. The DS1556 is shipped from Maxim with the clock oscillator turned off, OSC bit set to a 1.
6 of 18
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
READING THE CLOCK
When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC
Registers. This puts the external registers into a static state allowing data to be read without register
values changing during the read process. Normal updates to the internal registers continue while in this
state. External updates are halted when a 1 is written into the read bit, B6 of the Control Register
(1FFF8h). As long as a 1 remains in the Control Register read bit, updating is halted. After a halt is
issued, the registers reflect the RTC count (day, date, and time) that was current at the moment the halt
command was issued. Normal updates to the external set of registers will resume within 1 second after the
read bit is set to a 0 for a minimum of 500s. The read bit must be a zero for a minimum of 500s to
ensure the external registers will be updated.
SETTING THE CLOCK
The MSB bit, B7, of the Control Register is the write bit. Setting the write bit to a 1, like the read bit,
halts updates to the DS1556 (1FFF8h to 1FFFFh) registers. After setting the write bit to a 1, RTC
Registers can be loaded with the desired RTC count (day, date, and time) in 24-hour BCD format. Setting
the write bit to a 0 then transfers the values written to the internal RTC Registers and allows normal
operation to resume.
CLOCK ACCURACY (DIP MODULE)
The DS1556 is guaranteed to keep time accuracy to within 1 minute per month at 25C. The RTC is
calibrated at the factory by Maxim using nonvolatile tuning elements, and does not require additional
calibration. For this reason, methods of field clock calibration are not available and not necessary. The
electrical environment also affects clock accuracy, and caution should be taken to place the RTC in the
lowest-level EMI section of the PC board layout. For additional information, refer to Application Note
58.
CLOCK ACCURACY (PowerCap MODULE)
The DS1556 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within 1.53 minutes per month (35 ppm) at 25°C. The
electrical environment also affects clock accuracy, and caution should be taken to place the RTC in the
lowest-level EMI section of the PC board layout. For additional information, refer to
Application Note 58.
FREQUENCY TEST MODE
The DS1556 frequency test mode uses the open drain IRQ/FT output. With the oscillator running, the
IRQ/FT output will toggle at 512 Hz when the FT bit is a 1, the Alarm Flag Enable bit (AE) is a 0, and
the Watchdog Steering bit (WDS) is a 1 or the Watchdog Register is reset (Register 1FFF7h = 00h). The
IRQ/FT output and the frequency test mode can be used as a measure of the actual frequency of the
32.768 kHz RTC oscillator. The IRQ/FT pin is an open-drain output that requires a pullup resistor for
proper operation. The FT bit is cleared to a 0 on power-up.
7 of 18
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
USING THE CLOCK ALARM
The alarm settings and control for the DS1556 reside within Registers 1FFF2h to 1FFF5h. Register
1FFF6h contains two alarm enable bits: Alarm Enable (AE) and Alarm in Backup Enable (ABE). The AE
and ABE bits must be set as described below for the IRQ/FT output to be activated for a matched alarm
condition.
The alarm can be programmed to activate on a specific day of the month or repeat every day, hour,
minute, or second. It can also be programmed to go off while the DS1556 is in the battery-backed state of
operation to serve as a system wake-up. Alarm mask bits AM1 to AM4 control the alarm mode. Table 3
shows the possible settings. Configurations not listed in the table default to the once per second mode to
notify the user of an incorrect alarm setting.
Table 3. Alarm Mask Bits
AM4
AM3
AM2
AM1
ALARM RATE
1
1
1
1
Once per second
1
1
1
0
When seconds match
1
1
0
0
When minutes and seconds match
1
0
0
0
When hours, minutes, and seconds match
0
0
0
0
When date, hours, minutes, and seconds match
When the RTC Register values match Alarm Register settings, the Alarm Flag bit (AF) is set to a 1. If
Alarm Flag Enable (AE) is also set to a 1, the alarm condition activates the IRQ/FT pin. The IRQ/FT
signal is cleared by a read or write to the Flags Register (Address 1FFF0h) as shown in Figure 2 and 3.
When CE is active, the IRQ/FT signal may be cleared by having the address stable for as short as 15 ns
and either OE or WE active, but is not guaranteed to be cleared unless tRC is fulfilled. The alarm flag is
also cleared by a read or write to the Flags Register but the flag will not change states until the end of the
read/write cycle and the IRQ/FT signal has been cleared.
Figure 2. Clearing IRQ Waveforms
CE,
0V
8 of 18
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
Figure 3. Clearing IRQ Waveforms
CE=0
The IRQ/FT pin can also be activated in the battery-backed mode. The IRQ/FT will go low if an alarm
occurs and both ABE and AE are set. The ABE and AE bits are cleared during the power-up transition,
however an alarm generated during power-up will set AF. Therefore, the AF bit can be read after system
power-up to determine if an alarm was generated during the power-up sequence. Figure 4 illustrates alarm
timing during the battery-backup mode and power-up states.
Figure 4. Backup Mode Alarm Waveforms
9 of 18
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
USING THE WATCHDOG TIMER
The watchdog timer can be used to detect an out-of-control processor. The user programs the watchdog
timer by setting the desired amount of time-out into the 8-bit Watchdog Register (Address 1FFF7h). The
five Watchdog Register bits BMB4 to BMB0 store a binary multiplier and the two lower order bits RB1
to RB0 select the resolution, where 00=1/16 second, 01=1/4 second, 10=1 second, and 11=4 seconds. The
watchdog timeout value is then determined by the multiplication of the 5-bit multiplier value with the
2-bit resolution value. (For example: writing 00001110 in the Watchdog Register = 3 x 1 second or
3 seconds.) If the processor does not reset the timer within the specified period, the Watchdog Flag (WF)
is set and a processor interrupt is generated and stays active until either the Watchdog Flag (WF) is read
or the Watchdog Register (1FFF7h) is read or written.
The most significant bit of the Watchdog Register is the Watchdog Steering Bit (WDS). When set to a 0,
the watchdog will activate the IRQ/FT output when the watchdog times out.
When WDS is set to a 1, the watchdog will output a negative pulse on the RST output for a duration of
40ms to 200ms. The Watchdog Register (1FFF7h) and the FT bit will reset to a 0 at the end of a
watchdog timeout when the WDS bit is set to a 1.
The watchdog timer resets when the processor performs a read or write of the Watchdog Register. The
time-out period then starts over. The watchdog timer is disabled by writing a value of 00h to the
Watchdog Register. The watchdog function is automatically disabled upon power-up and the Watchdog
Register is cleared. If the watchdog function is set to output to the IRQ/FT output and the frequency test
function is activated, the watchdog function prevails and the frequency test function is denied.
POWER-ON DEFAULT STATES
Upon application of power to the device, the following register bits are set to a 0:
WDS = 0, BMB0 to BMB4 = 0, RB0 to RB1 = 0, AE = 0, ABE = 0.
10 of 18
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground……………………..……………………………………………..-0.3V to +6.0V
Storage Temperature Range
EDIP........................………………………………………………………………...................................-40°C to +85°C
PowerCap..............………………………………………………….…………………………………..-55°C to +125°C
Lead Temperature (soldering, 10s).………..........................................................................................................................+260°C
Note: EDIP is hand or wave-soldered only.
Soldering Temperature (reflow, PowerCap)………………………………….....................................................................+260°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
OPERATING RANGE
RANGE
Commercial
Industrial
TEMP RANGE
0°C to +70°C
-40°C to +85°C
VCC
3.3V 10% or 5V 10%
3.3V 10% or 5V 10%
RECOMMENDED DC OPERATING CONDITIONS
(Over the Operating Range)
PARAMETER
Logic 1 Voltage All Inputs
(Note 1)
Logic 0 Voltage All Inputs
(Note 1)
SYMBOL
CONDITIONS
MIN
TYP
MAX
VCC +
0.3V
VCC +
0.3V
VIH
VCC = 5V 10%
2.2
VIH
VCC = 3.3V 10%
2.0
VIL
VCC = 5V 10%
-0.3
+0.8
VIL
VCC = 3.3V 10%
-0.3
+0.6
UNITS
V
V
DC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V 10%, Over the Operating Range.)
PARAMETER
Active Supply Current
TTL Standby Current
(CE = VIH)
CMOS Standby Current
(CE VCC - 0.2V)
Input Leakage Current
(Any Input)
Output Leakage Current
(Any Output)
Output Logic 1 Voltage
(IOUT = -1.0 mA)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ICC
(Notes 2, 3, 11)
30
85
mA
ICC1
(Notes 2, 3)
4
6
mA
ICC2
(Notes 2, 3)
2
6
mA
IIL
-1
+1
A
IOL
-1
+1
A
VOH
(Note 1)
Write Protection Voltage
VPF
IOUT = 2.1 mA, DQ0–7
Outputs (Note 1)
IOUT = 7.0 mA, IRQ/FT,
and RST Outputs
(Notes 1, 5)
(Note 1)
Battery Switchover Voltage
VSO
(Notes 1,4)
VOL1
Output Logic 0 Voltage
VOL2
11 of 18
2.4
V
4.20
VBAT
0.4
V
0.4
V
4.50
V
V
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V 10%, Over the Operating Range.)
PARAMETER
Active Supply Current
TTL Standby Current
(CE = VIH)
CMOS Standby Current
(CE VCC - 0.2V)
Input Leakage Current
(Any Input)
Output Leakage Current
(Any Output)
Output Logic 1 Voltage
(IOUT = -1.0 mA)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ICC
(Notes 2, 3, 11)
20
30
mA
ICC1
(Notes 2, 3)
2
6
mA
ICC2
(Notes 2, 3)
1
4
mA
IIL
-1
+1
A
IOL
-1
+1
A
VOH
(Note 1)
VOL1
IOUT = 2.1 mA, DQ0–7
Outputs (Note 1)
0.4
V
VOL2
IOUT = 7.0 mA, IRQ/FT
and RST Outputs
(Notes 1, 5)
0.4
V
Write Protection Voltage
VPF
(Note 1)
2.97
V
Battery Switchover Voltage
VSO
(Notes 1,4)
Output Logic 0 Voltage
Figure 5. Read Cycle Timing Diagram
12 of 18
2.4
V
2.75
VBAT
or VPF
V
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
AC CHARACTERISTICS—READ CYCLE
(Over the Operating Range)
PARAMETER
SYMBOL
VCC = 5.0V 10%
MIN
MAX
70
VCC = 3.3V 10%
MIN
MAX
120
UNITS
Read Cycle Time
tRC
Address Access Time
tAA
CE to DQ Low-Z
tCEL
CE Access Time
tCEA
70
120
ns
CE Data Off Time
tCEZ
25
40
ns
OE to DQ Low-Z
tOEL
OE Access Time
tOEA
35
100
ns
OE Data Off Time
tOEZ
25
35
ns
Output Hold from Address
tOH
70
5
ns
120
5
5
ns
5
5
ns
ns
5
ns
AC CHARACTERISTICS—WRITE CYCLE
(Over the Operating Range)
PARAMETER
SYMBOL
VCC = 5.0V 10%
MIN
MAX
VCC = 3.3V 10%
MIN
MAX
UNITS
Write Cycle Time
tWC
70
120
ns
Address Access Time
tAS
0
0
ns
WE Pulse Width
tWEW
50
100
ns
CE Pulse Width
tCEW
60
110
ns
Data Setup Time
tDS
30
80
ns
Data Hold Time (Note 9)
tDH1
5
5
ns
Data Hold Time (Note 10)
tDH2
5
5
ns
Address Hold Time (Note 9)
Address Hold Time
(Note 10)
WE Data Off Time
tAH1
5
0
ns
tAH2
5
5
ns
tWEZ
Write Recovery Time
tWR
25
5
13 of 18
40
10
ns
ns
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
Figure 6. Write Cycle Timing, Write-Enable Controlled
Figure 7. Write Cycle Timing, Chip-Enable Controlled
14 of 18
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
POWER-UP/DOWN CHARACTERISTICS—5V
(VCC = 5.0V 10%, Over the Operating Range.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CE or WE at VIH, Before
Power-Down
tPD
0
s
VCC Fall Time: VPF(MAX) to VPF(MIN)
VCC Fall Time: VPF(MIN) to VSO
VCC Rise Time: VPF(MIN) to VPF(MAX)
tF
tFB
tR
300
10
0
s
s
s
VPF to RST High
Expected Data-Retention Time
(Oscillator On)
tREC
40
tDR
(Notes 6, 7)
Figure 8. Power-Up/Down Waveform Timing (5V Device)
15 of 18
10
200
ms
years
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
POWER-UP/DOWN CHARACTERISTICS—3.3V
(VCC = 3.3V 10%, Over the Operating Range.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CE or WE at VIH, Before
Power-Down
tPD
0
s
VCC Fall Time: VPF(MAX) to VPF(MIN)
VCC Rise Time: VPF(MIN) to VPF(MAX)
tF
tR
300
0
s
s
VPF to RST High
tREC
40
Expected Data-Retention Time
(Oscillator On)
tDR
(Notes 6, 7)
200
10
ms
years
Figure 9. Power-Up/Down Waveform Timing (3.3V Device)
CAPACITANCE
(TA = +25°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Capacitance on All Input Pins
CIN
(Note 1)
14
pF
Capacitance on IRQ/FT, RST,
and DQ Pins
CIO
(Note 1)
10
pF
16 of 18
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
AC TEST CONDITIONS
Output Load: 50 pF + 1TTL Gate
Input Pulse Levels: 0.0 to 3.0V
Timing Measurement Reference Levels:
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5 ns
NOTES:
1.
2.
3.
4.
5.
6.
7.
Voltage referenced to ground.
Typical values are at +25C and nominal supplies.
Outputs are open.
Battery switchover occurs at the lower of either the battery voltage or VPF.
The IRQ/FT and RST outputs are open drain.
Data-retention time is at +25C.
Each DS1556 has a built-in switch that disconnects the lithium source until VCC is first applied by the
user. The expected tDR is defined for DIP modules and PowerCap modules as a cumulative time in the
absence of VCC starting from the time power is first applied by the user.
8. RTC modules (DIP) can be successfully processed through conventional wave-soldering techniques
as long as temperature exposure to the lithium energy source contained within does not exceed
+85C. Post-solder cleaning with water-washing techniques is acceptable, provided that ultrasonic
vibration is not used.
In addition, for the PowerCap:
a. Maxim recommends that PowerCap Module bases experience one pass through solder reflow
oriented with the label side up (“live-bug”).
b. Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than
3 seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove
the part, apply flux, heat the lead frame pad until the solder reflow and use a solder wick to
remove solder.
9. tAH1, tDH1 are measured from WE going high.
10. tAH2, tDH2 are measured from CE going high.
11. tWC = 200ns.
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-”
in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
32 EDIP
34 PWRCP
MDF32+1
PC2+6
21-0245
21-0246
—
—
17 of 18
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
9/10
Updated the Ordering Information table to include only lead-free parts; updated the Absolute
Maximum Ratings section to include the storage temperature range and lead and soldering
temperatures for EDIP and PowerCap packages; added Note 11 to the ICC parameter in the DC
Electrical Characteristics tables (for 5.0V and 3.3V) and the Notes section; replaced the
package outline drawings with the Package Information table
2, 11, 12, 17
18 of 18
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses
are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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