PHILIPS HEF4015BN Dual 4-bit static shift register Datasheet

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4015B
MSI
Dual 4-bit static shift register
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
HEF4015B
MSI
Dual 4-bit static shift register
present on D is shifted to the first register position, and all
the data in the register is shifted one position to the right
on the LOW-to-HIGH transition of CP. A HIGH on MR
clears the register and forces O0 to O3 to LOW,
independent of CP and D. Schmitt-trigger action in the
clock input makes the circuit highly tolerant to slower clock
rise and fall times.
DESCRIPTION
The HEF4015B is a dual edge-triggered 4-bit static shift
register (serial-to-parallel converter). Each shift register
has a serial data input (D), a clock input (CP), four fully
buffered parallel outputs (O0 to O3) and an overriding
asynchronous master reset input (MR). Information
Fig.2 Pinning diagram.
HEF4015BP(N):
16-lead DIL; plastic
HEF4015BD(F):
16-lead DIL; ceramic (cerdip)
(SOT38-1)
(SOT74)
HEF4015BT(D):
16-lead SO; plastic
(SOT109-1)
Fig.1 Functional diagram.
( ): Package Designator North America
FAMILY DATA, IDD LIMITS category MSI
PINNING
DA, DB
serial data input
MRA, MRB
master reset input (active HIGH)
CPA, CPB
clock input (LOW-to-HIGH
edge-triggered)
O0A, O1A, O2A, O3A
parallel outputs
O0B, O1B, O2B, O3B
parallel outputs
See Family Specifications
APPLICATION INFORMATION
Some examples of applications for the HEF4015B are:
• Serial-to-parallel converter
• Buffer stores
• General purpose register
January 1995
2
Philips Semiconductors
Product specification
HEF4015B
MSI
Dual 4-bit static shift register
LOGIC DIAGRAM (one register)
Fig.3 Logic diagram.
Note
FUNCTION TABLE
INPUTS
n
CP
1. H = HIGH state (the more positive voltage)
OUTPUTS
D
MR
O0
O1
O2
O3
1
D1
L
D1
X
X
X
2
D2
L
D2
D1
X
X
3
D3
L
D3
D2
D1
X
D4
L
D4
D3
D2
D1
X
L
X
H
4
X
January 1995
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
L
L
= positive-going transition
5.
= negative-going transition
6. Dn = either HIGH or LOW
7. n
no change
L
4.
L
3
= number of clock pulse transitions
Philips Semiconductors
Product specification
HEF4015B
MSI
Dual 4-bit static shift register
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
MIN.
TYPICAL EXTRAPOLATION
FORMULA
TYP.
MAX.
130
260
ns
103 ns +
(0,55 ns/pF) CL
55
110
ns
44 ns +
(0,23 ns/pF) CL
40
80
ns
32 ns +
(0,16 ns/pF) CL
120
240
ns
93 ns +
(0,55 ns/pF) CL
55
110
ns
44 ns +
(0,23 ns/pF) CL
40
80
ns
32 ns +
(0,16 ns/pF) CL
105
210
ns
78 ns +
(0,55 ns/pF) CL
45
90
ns
34 ns +
(0,23 ns/pF) CL
35
70
ns
27 ns +
(0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
Propagation delays
CP → On
HIGH to LOW
5
10
tPHL
15
5
LOW to HIGH
10
tPLH
15
MR → On
HIGH to LOW
5
10
tPHL
15
Output transition times
HIGH to LOW
5
10
tTHL
15
5
LOW to HIGH
10
tTLH
15
Set-up time
5
D → CP
10
Hold time
D → CP
Minimum clock
pulse width; LOW
Minimum MR
pulse width; HIGH
Recovery time
for MR
Maximum clock
pulse frequency
120
ns
60
ns
9 ns +
(0,42 ns/pF) CL
20
40
ns
6 ns +
(0,28 ns/pF) CL
60
120
ns
10 ns +
(1,0 ns/pF) CL
30
60
ns
9 ns +
(0,42 ns/pF) CL
20
40
ns
6 ns +
(0,28 ns/pF) CL
25
−15
ns
25
−10
ns
15
20
−5
ns
5
40
20
ns
10
tsu
thold
20
10
ns
15
15
8
ns
5
60
30
ns
10
tWCPL
30
15
ns
15
20
10
ns
5
80
40
ns
10
tWMRH
30
15
ns
15
24
12
ns
5
50
20
ns
10
tRMR
30
10
ns
15
20
5
ns
5
7
15
MHz
15
30
MHz
22
44
MHz
10
15
January 1995
60
30
fmax
4








 see waveforms Figs 4 and 5









Philips Semiconductors
Product specification
HEF4015B
MSI
Dual 4-bit static shift register
Dynamic power
VDD
V
TYPICAL FORMULA FOR P (µW)
5
1 500 fi + ∑ (foCL) × VDD2
where
fi = input freq. (MHz)
dissipation per
10
6 300 fi + ∑ (foCL) ×
package (P)
15
17 000 fi + ∑ (foCL) ×
VDD2
VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
Fig.4
Waveforms showing set-up times, hold times and minimum clock pulse width. Set-up and hold times are
shown as positive values but may be specified as negative values.
Fig.5 Waveforms showing recovery time for MR and minimum MR pulse width.
January 1995
5
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