HSP45116/883 TM Data Sheet May 1999 Numerically Controlled Oscillator/Modulator FN2813.3 Features The Intersil HSP45116/883 combines a high performance quadrature numerically controlled oscillator (NCO) and a high speed 16-bit Complex Multiplier/Accumulator (CMAC) on a single IC. This combination of functions allows a complex vector to be multiplied by the internally generated (cos, sin) vector for quadrature modulation and demodulation. As shown in the Block Diagram, the HSP45116/883 is divided into three main sections. The Phase/Frequency Control Section (PFCS) and the Sine/Cosine Section together form a complex NCO. The CMAC multiplies the output of the Sine/Cosine Section with an external complex vector. • This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. • NCO and CMAC on One Chip • 15MHz and 25.6MHz Versions • 32-Bit Frequency Control • 16-Bit Phase Modulation • 16-Bit CMAC • 0.006Hz Tuning Resolution at 25.6MHz • Spurious Frequency Components < -90dBc The inputs to the Phase/Frequency Control Section consist of a microprocessor interface and individual control lines. The phase resolution of the PFCS is 32 bits, which results in frequency resolution better than 0.006Hz at 25.6MHz. The output of the PFCS is the argument of the sine and cosine. The spurious free dynamic range of the complex sinusoid is greater than 90dBc. The output vector from the Sine/Cosine Section is one of the inputs to the Complex Multiplier/Accumulator. The CMAC multiplies this (cos, sin) vector by an external complex vector and can accumulate the result. The resulting complex vectors are available through two 20-bit output ports which maintain the 90dB spectral purity. This result can be accumulated internally to implement an accumulate and dump filter. A quadrature down converter can be implemented by loading a center frequency into the Phase/Frequency Control Section. The signal to be downconverted is the Vector Input of the CMAC, which multiplies the data by the rotating vector from the Sine/Cosine Section. The resulting complex output is the down converted signal. • Fully Static CMOS Applications • Frequency Synthesis • Modulation - AM, FM, PSK, FSK, QAM • Demodulation, PLL • Phase Shifter • Polar to Cartesian Conversions Ordering Information PART NUMBER TEMP. RANGE ( oC) HSP45116GM-15/883 -55 to 125 145 Ld PGA G145.A HS45116GM-25/883 -55 to 125 145 Ld PGA G145.A PACKAGE PKG. NO. Block Diagram VECTOR INPUT R MICROPROCESSOR INTERFACE INDIVIDUAL CONTROL SIGNALS PHASE/ FREQUENCY CONTROL SECTION SINE/ COSINE ARGUMENT I SIN SINE/ COSINE SECTION COS CMAC R I VECTOR OUTPUT 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved HSP45116/883 Absolute Maximum Ratings Thermal Information Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input or Output Voltage Applied. . . . . . . . . GND -0.5V to VCC +0.5V ESD Rating Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC ( oC/W) PGA Package . . . . . . . . . . . . . . . . . . . 30.0 5.0 Maximum Package Power Dissipation at 125oC PGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.16W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Number of Transistors or Gates . . . . . . . . . . . . 103,000 Transistors Operating Conditions Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested PARAMETER SYMBOL TEST CONDITIONS GROUP A SUBGROUPS TEMPERATURE (oC) MIN MAX UNITS Logical One Input Voltage VIH VCC = 5.5V 1, 2, 3 55 ≤ TA ≤ 125 2.2 - V Logical Zero Input Voltage VIL VCC = 4.5V 1, 2, 3 55 ≤ TA ≤ 125 - 0.8 V Logical One Input Voltage Clock VIHC VCC = 5.5V 1, 2, 3 55 ≤ TA ≤ 125 3.0 - V Logical Zero Input Voltage Clock VILC VCC = 4.5V 1, 2, 3 55 ≤ TA ≤ 125 - 0.8 V Output HIGH Voltage VOH IOH = -400µA VCC = 4.5V (Note 2) 1, 2, 3 55 ≤ TA ≤ 125 2.6 - V Output LOW Voltage V OL IOL = +2.0mA VCC = 4.5V (Note 2) 1, 2, 3 55 ≤ TA ≤ 125 - 0.4 V Input Leakage Current II VIN = VCC or GND VCC = 5.5V 1, 2, 3 55 ≤ TA ≤ 125 -10 +10 µA Output or I/O Leakage Current IO VOUT = VCC or GND VCC = 5.5V 1, 2, 3 55 ≤ TA ≤ 125 -10 +10 µA Standby Power Supply Current ICCSB VIN = VCC or GND, VCC = 5.5V, (Note 5) 1, 2, 3 55 ≤ TA ≤ 125 - 500 µA Operating Power Supply Current ICCOP f = 15MHz, VIN = VCC or GND VCC = 5.5V (Notes 3, 5) 1, 2, 3 55 ≤ TA ≤ 125 - 150 mA 7, 8 55 ≤ TA ≤ 125 - - Functional Test FT (Note 4) NOTES: 2. Interchanging of force and sense conditions is permitted. 3. Operating Supply Current is proportional to frequency, typical rating is 10mA/MHz. 4. Tested as follows: f = 1MHz, VIH (clock inputs) = 3.4V, VIH (all other inputs) = 2.6V, VIL = 0.4V, VOH ≥ 1.5V, and VOL ≤ 1.5V. 5. Output per test load circuit with switch open and CL = 40pF. 2 HSP45116/883 TABLE 2. ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested -15 (15MHz) PARAMETER SYMBOL NOTES -25 (25.6MHz) GROUP A SUBGROUPS TEMPERATURE (oC) MIN MAX MIN MAX UNITS CLK Period tCP 9, 10, 11 -55 ≤ TA ≤ 125 66 - 39 - ns CLK High tCH 9, 10, 11 -55 ≤ TA ≤ 125 26 - 15 - ns CLK Low tCL 9, 10, 11 -55 ≤ TA ≤ 125 26 - -15 - ns WR Low tWL 9, 10, 11 -55 ≤ TA ≤ 125 26 - 15 - ns WR High tWH 9, 10, 11 -55 ≤ TA ≤ 125 26 - 15 - ns Setup Time; ADO-1, CS to WR Going High tAWS 9, 10, 11 -55 ≤ TA ≤ 125 20 - 18 - ns Hold Time; AD0, AD1, CS from WR Going High tAWH 9, 10, 11 -55 ≤ TA ≤ 125 0 - 0 - ns Setup Time CO-15 from WR Going High tCWS 9, 10, 11 -55 ≤ TA ≤ 125 20 - 18 - ns Hold Time CO-15 from WR Going High tCWA 9, 10, 11 -55 ≤ TA ≤ 125 0 - 0 - ns 9, 10, 11 -55 ≤ TA ≤ 125 20 - 16 - ns Setup Time WR to CLK High tWC Setup Time MODO-1 to CLK Going High tMCS 9, 10, 11 -55 ≤ TA ≤ 125 20 - 18 - ns Hold Time MODO-1 from CLK Going High tMCH 9, 10, 11 -55 ≤ TA ≤ 125 0 - 0 - ns Setup Time PACI to CLK Going High tPCS 9, 10, 11 -55 ≤ TA ≤ 125 25 - 18 - ns Hold Time PACI from CLK Going High tPCH 9, 10, 11 -55 ≤ TA ≤ 125 0 - 0 - ns Setup Time ENPHREG, ENCFRCTL, ENPHAC, ENTICTL, CLROFR, PMSEL, LOAD, ENI, ACC, BINFMT, PEAK, MODPI/2PI, SHO-1, RBYTILD from CLK Going High tECS 9, 10, 11 -55 ≤ TA ≤ 125 20 - 15 - ns Hold Time ENPHREG, ENCFRCTL, ENPHAC, ENTICTL, CLROFR, PMSEL, LOAD, ENI, ACC, BINFMT, PEAK, MODPI/2PI, SHO-1, RBYTILD from CLK Going High tECH 9, 10, 11 -55 ≤ TA ≤ 125 0 - 0 - ns Setup Time RINO-18, IMINO-18 to CLK Going High tDS 9, 10, 11 -55 ≤ TA ≤ 125 20 - 15 - ns Hold Time RINO-18, IMINO-18, to CLK Going High tDH 9, 10, 11 -55 ≤ TA ≤ 125 0 - 0 - ns CLK to Output Delay R0O-19, I0O-19 tDO 9, 10, 11 -55 ≤ TA ≤ 125 40 - 25 - ns 3 (Note 7) HSP45116/883 TABLE 2. ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) Device Guaranteed and 100% Tested -15 (15MHz) -25 (25.6MHz) GROUP A SUBGROUPS TEMPERATURE (oC) MIN MAX MIN MAX UNITS tDEO 9, 10, 11 -55 ≤ TA ≤ 125 40 - 27 - ns CLK to Output Delay PACO tPO 9, 10, 11 -55 ≤ TA ≤ 125 - 30 - 20 ns CLK to Output Delay TICO tTO 9, 10, 11 -55 ≤ TA ≤ 125 - 30 - 20 ns Output Enable Time OER, OEI, OEREXT, OEIEXT tOE 9, 10, 11 -55 ≤ TA ≤ 125 - 25 - 20 ns OUTMUXO-1 to Output Delay tMD 9, 10, 11 -55 ≤ TA ≤ 125 - 40 - 28 ns PARAMETER SYMBOL CLK to Output Delay DETO-1 NOTES (Note 8) NOTES: 6. AC testing is performed as follows: VCC = 4.5V and 5.5V. Input levels (CLK Input) 4.0V and 0V; input levels (all other inputs) 3.0V and 0V; timing reference levels (CLK) 2.0V; all others 1.5V. Output load per test load circuit with switch closed and CL = 40pF. Output transition is measured at VOH ≥ 1.5V and V OL ≤ 1.5V. 7. Applicable only when outputs are being monitored and ENCFREG, ENPHREG, or ENTIREG is active. 8. Transition is measured at ±200mV from steady state voltage, output loading per test load circuit, with switch closed and CL = 40pF. TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS PARAMETER Input Capacitance -15 -25 SYMBOL TEST CONDITIONS NOTES TEMPERATURE (oC) CIN VCC = Open, f = 1MHz All measurements are referenced to device GND 9 TA - +25 - 15 - 15 pF MIN MAX MIN MAX UNITS Output Capacitance COUT 9 TA - +25 - 15 - 15 pF Output Disable Time tOD 9, 10 -55 ≤ TA ≤ 125 - 20 - 15 ns Output Rise Time tR From 0.8V to 2.0V 9, 10 -55 ≤ TA ≤ 125 - 8 - 8 ns Output Fall Time tF From 2.0V to 0.8V 9, 10 -55 ≤ TA ≤ 125 - 8 - 8 ns NOTES: 9. The parameters in Table 3 are controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. 10. Loading is as specified in the test load circuit with CL = 40pF. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS METHOD SUBGROUPS Initial Tess 100%/5004 - Interim Test 100%/5004 - PDA 100% 1 Final Test 100% 2, 3, 8A, 8B, 10, 11 - 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Samples 1, 7, 9 Group A Groups C & D 4 HSP45116/883 Burn-In Circuit 145 PIN PGA TOP VIEW 1 2 3 4 A VCC IMIN4 IMIN8 IMIN9 B GND IMIN 1 IMIN5 C RIN15 RIN18 D RIN13 E 8 9 10 11 12 13 14 15 IMIN11 IMIN15 IMIN16 GND VCC IO18 IO15 IO12 IO10 GND VCC A IMIN7 IMIN10 IMIN13 IMIN14 IO19 IO16 IO14 IO11 IO8 IO7 IO5 IO2 B IMIN2 IMIN3 IMIN6 IO17 IO13 IO9 IO6 IO4 IO1 RO18 C RIN17 IMIN0 INDEX IO3 RO19 RO17 D RIN10 RIN14 RIN16 IO0 RO16 RO15 E F RIN7 RIN11 RIN12 RO14 RO13 RO11 F G VCC RIN9 RIN8 RO9 RO12 RO10 G H GND RIN6 RIN5 RO8 RO7 GND H J RIN3 RIN1 RIN4 RO5 RO4 VCC J K RIN2 RIN0 SH1 RO1 RO2 RO6 K L SH0 ACC RBYTILD PACO DET1 RO3 L M ENPH REG PEAK MOD1 OEREXT OEI RO0 M N ENOF REG BINFMT MOD0 P TICO PACI PMSEL CLROFR ENTIREG Q VCC GND ENPHAC ENI 1 2 3 4 LOAD 5 ENCF REG 6 7 IMIN12 IMIN17 IMIN18 MODPI /2PI AD0 C14 C13 C8 C2 OUTMUX1 OUTMUX0 OEIEXT DET0 N CS AD1 C15 C10 C9 C6 C3 C1 OER GND P CLK WR VCC GND C12 C11 C7 C5 C4 C0 VCC Q 5 6 7 8 9 10 11 12 13 14 15 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 5 HSP45116/883 Burn-in Circuit PGA PIN PIN NAME BURN-INSIGNAL PGA PIN PIN NAME BURN-IN SIGNAL PGA PIN D3 IMIN(0) F4 C2 RIN(18) F9 Q3 ENPHAC F1 K14 P5 ENTIREG F4 L15 D2 RIN(17) F8 Q4 ENI F1 J14 E3 RIN(16) F7 N6 MODPI/2PI F16 J13 C1 RIN(15) F6 P6 CS F2 K15 E2 RIN(14) F5 Q5 CLK F0 D1 RIN(13) F4 P7 AD(1) F3 RIN(12) F16 N7 F2 RIN(11) F15 E1 RIN(10) G2 G3 PIN NAME BURN-IN SIGNAL PGA PIN PIN NAME BURN-IN SIGNAL RO(2) VCC /2 A10 IO(18) VCC /2 RO(3) VCC /2 B8 IO(19) VCC /2 RO(4) VCC /2 C8 IMIN(18) F9 RO(5) VCC /2 C7 IMIN(17) F8 RO(6) VCC /2 A7 IMIN(16) F7 H14 RO(7) VCC /2 A6 IMIN(15) F6 F4 H13 RO(8) VCC /2 B7 IMIN(14) F5 AD(0) F3 G13 RO(9) VCC /2 B6 IMIN(13) F4 Q6 WR F1 G15 RO(10) VCC /2 C6 IMIN(12 F16 F14 P8 C(15) GND F15 RO(11) VCC /2 A5 IMIN(11) F15 RIN(9) F13 N8 C(14) GND G14 RO(12) VCC /2 B5 IMIN(10) F14 RIN(8) F12 N9 C(13) GND F14 RO(13) VCC /2 A4 IMIN(9) F13 F1 RIN(7) F11 Q9 C(12) GND F13 RO(14) VCC /2 A3 IMIN(8) F12 H2 RIN(6) F10 Q10 C(11) GND E15 RO(15) VCC /2 B4 IMIN(7) F11 H3 RIN(5) F9 P9 C(10) GND E14 RO(16) VCC /2 C5 IMIN(6) F10 J3 RIN(4) F8 P10 C(9) GND D15 RO(17) VCC /2 B3 IMIN(5) F9 J1 RIN(3) F7 N10 C(8) GND C15 RO(18) VCC /2 A2 IMIN(4) F8 K1 RIN(2) F6 Q11 C(7) GND D14 RO(19) VCC /2 C4 IMIN(3) F7 F6 J2 RIN(1) F5 P11 C(6) GND E13 IO(0) VCC /2 C3 IMIN(2) K2 RIN(0) F4 Q12 C(5) GND C14 IO(1) VCC /2 B2 IMIN(1) F5 K3 SH(1) F3 Q13 C(4) GND B15 IO(2) VCC /2 A1 VC None L1 SH(0) F2 P12 C(3) GND D13 IO(3) VCC /2 A9 VCC VCC L2 ACC F4 N11 C(2) GND C13 IO(4) VCC /2 A15 VCC None M1 ENPHREG F16 P13 C(1) GND B14 IO(5) VCC /2 G1 VCC VCC N1 ENOFREG F4 Q14 C(0) V CC C12 IO(6) VCC /2 J15 VCC VCC M2 PEAK F8 N12 OUTMUX(1) F11 B13 IO(7) VCC /2 Q1 VCC None L3 RBYTILD F16 N13 OUTMUX(0) F10 B12 IO(8) VCC /2 Q7 VCC VCC N2 BINFMT F4 P14 OER F0 C11 IO(9) VCC /2 Q15 VCC None P1 TICO VCC /2 M13 OEREXT F0 A13 IO(10) VCC /2 A8 GND GND M3 MOD(1) GND N14 OEIEXT F0 B11 IO(11) VCC /2 A14 GND None N3 MOD(0) GND M14 OEI F0 A12 IO(12) VCC /2 B1 GND None P2 PACI F4 L13 PACO VCC /2 C10 IO(13) VCC /2 H1 GND GND N4 LOAD F15 N15 DET0 VCC /2 B10 IO(14) VCC /2 H15 GND GND P3 PMSEL F1 L14 DET1 VCC /2 A11 IO(15) VCC /2 P15 GND None P4 CLROFR F4 M15 RO(0) VCC /2 B9 IO(16) VCC /2 Q2 GND None N5 ENCFREG F4 K13 RO(1) VCC /2 C9 IO(17) VCC /2 Q8 GND GND NOTE: 11. 47kΩ ±20%) resistor connected to all pins except VCC and GND. 12. V CC = 5.5V ±0.5V with 0.1µF (min) capacitor between VCC and GND per position. 13. F0 = 100kHz ±10%, F1 = F0/2, F2 = F1/2 . . . . . , F11 = F10/2, 40% to 60% duty cycle. 14. Input Voltage limits: V IL = 0.8V max, VIH = 4.5V ±10%. Die Characteristics DIE DIMENSIONS: GLASSIVATION: 350 mils x 353 mils x 19 ± 1mils METALLIZATION: Type: Nitrox Thickness: 10kÅ WORST CASE DENSITY: Type: Si-Al, or Si-Al-Cu Thickness: 8kÅ 1.6 x 105A/cm2 6