LODEV LF9501 Programmable line buffer Datasheet

LF9501
LF9501
DEVICES INCORPORATED
Programmable Line Buffer
Programmable Line Buffer
DEVICES INCORPORATED
FEATURES
DESCRIPTION
❑ 50 MHz Maximum Operating
Frequency
The LF9501 is a high-speed, 10-bit
programmable line buffer. Some
applications the LF9501 is useful for
include sample rate conversion, data
time compression/expansion, software controlled data alignment, and
programmable serial data shifting. By
using the MODSEL pin, two different
modes of operation can be selected:
delay mode and data recirculation
mode. The delay mode provides a
minimum of 2 to a maximum of 1281
clock cycles of delay between the
input and output of the device. The
data recirculation mode provides a
feedback path from the data output to
the data input for use as a programmable circular buffer.
❑ Programmable Buffer Length from
2 to 1281 Clock Cycles
❑ 10-bit Data Inputs and Outputs
❑ Data Delay and Data Recirculation
Modes
❑ Supports Positive or Negative Edge
System Clocks
❑ Expandable Data Word Width or
Buffer Length
❑ Replaces Harris HSP9501
❑ 44-pin PLCC, J-Lead
By using the length control input
(LC10-0) and the length control enable
(LCEN) the length of the delay buffer
or amount of recirculation delay can
be programmed. Providing a delay
value on the LC10-0 inputs and driving
LCEN LOW will load the delay value
into the length control register on the
next selected clock edge. Two registers, one preceeding the programmable delay RAM and one following,
are included in the delay path. Therefore, the programmed delay value
should equal the desired delay minus
2. This consequently means that the
value loaded into the length control
register must range from 0 to 1279 (to
provide an overall range of 2 to 1281).
The active edge of the clock input,
either positive or negative edge, can
be selected with the clock select
(CLKSEL) input. All timing is based
on the active clock edge selected by
CLKSEL. Data can be held temporarily by using the clock enable
(CLKEN) input.
LF9501 BLOCK DIAGRAM
MODSEL
LCO10-0
LCEN
11
REGISTER
REGISTER
10
OE
10
REGISTER
10
PROGRAMMABLE
DELAY RAM
10
MUX
DI9-0
REGISTER
11
10
10
DO9-0
CLKSEL
CLKEN
CLK
CLOCK
GENERATOR
10
TO ALL REGISTERS
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08/16/2000–LDS.9501-H
LF9501
DEVICES INCORPORATED
Programmable Line Buffer
SIGNAL DEFINITIONS
Outputs
CLKSEL — Clock Select
Power
DO9-0 — Data Output
VCC and GND
The 10-bit data output appears on
DO9-0 on the Nth clock cycle, where N
is the overall delay (desired delay).
The CLKSEL control allows the
selection of the active edge of CLK. A
LOW on CLKSEL selects negativeedge triggering of the device. Driving
CLKSEL HIGH selects positive-edge
triggering. All timing specifications
are referrenced to the selected active
edge of CLK.
+5 V power supply. All pins must be
connected.
Clock
CLK — Master Clock
The active edge of CLK, selected by
CLKSEL, strobes all registers. All
timing specifications are referenced to
the active edge of CLK.
Inputs
DI9-0 — Data Input
10-bit data, from the data input, is
latched into the device on the active
edge of CLK when MODSEL is LOW.
LC10-0 — Length Control Input
The 11-bit value is used to specify the
length of the delay buffer, between
DI9-0 and DO9-0, or the amount of
recirculation delay. An integer value
ranging from 0 to 1279 is used to
select a delay ranging from 2 to 1281
clock cycles. The value placed on the
LC10-0 inputs is equal to the desired
delay minus 2. The data presented on
LC10-0 is loaded into the device on the
active edge of CLK, selected by
CLKSEL, in conjunction with LCEN
being driven LOW.
Controls
LCEN — Length Control Enable
When LCEN is driven LOW, the next
active clock edge will cause the
loading of the delay value present at
the LC10-0 input.
OE — Output Enable
The Output Enable controls the state
of DO9-0. Driving OE LOW enables
the output port. When OE is HIGH,
DO9-0 is placed in a high-impedance
state. The internal transfer of data is
not affected by this control.
MODSEL — Mode Select
The Mode Select pin is used to choose
the desired mode of operation: data
delay mode or data recirculation
mode. Driving MODSEL LOW places
the device in the delay mode. The
device operates as a programmable
pipeline register. New data from the
DI9-0 input is loaded on every active
edge of CLK. Driving MODSEL
HIGH places the device in the data
recirculation mode. The device
operates as a programmable circular
buffer. The output of the device is
routed back to the input. MODSEL
may be changed during device
operation (synchronously), however,
the required setup and hold times,
with respect to CLK, must be met.
CLKEN — Clock Enable
The Clock Enable control enables and
disables the CLK input. Driving
CLKEN LOW enables CLK and causes
the device to operate in a normal
fashion. When CLKEN is HIGH, CLK
is disabled and the device will hold all
internal operations and data. CLKEN
may be changed during device
operation (synchronously), however,
the required setup and hold times,
with respect to CLK, must be met.
The changing of CLKEN takes effect
on the active edge of CLK following
the edge in which it was latched.
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LF9501
DEVICES INCORPORATED
Programmable Line Buffer
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature ........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ............................................................................... –0.5 V to V CC + 0.5 V
Signal applied to high impedance output ...................................................................... –0.5 V to VCC + 0.5 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode
Active Operation, Commercial
Temperature Range (Ambient)
0°C to +70°C
Supply Voltage
4.75 V ≤ VCC ≤ 5.25 V
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol
Parameter
Test Condition
Min
VOH
Output High Voltage
VCC = Min., IOH = –4.0 mA
2.4
VOL
Output Low Voltage
VCC = Min., IOL = 4.0 mA
VIH
Input High Voltage
VIL
Input Low Voltage
(Note 3)
IIX
Input Current
IOZ
Typ
Max
Unit
V
0.4
V
2.0
VCC
V
0.0
0.8
V
Ground ≤ VIN ≤ VCC (Note 12)
±10
µA
Output Leakage Current
Ground ≤ VOUT ≤ VCC (Note 12)
±10
µA
ICC1
VCC Current, Dynamic
(Notes 5, 6)
125
mA
ICC2
VCC Current, Quiescent
(Note 7)
500
µA
CIN
Input Capacitance
TA = 25°C, f = 1 MHz
10
pF
COUT
Output Capacitance
TA = 25°C, f = 1 MHz
10
pF
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LF9501
DEVICES INCORPORATED
Programmable Line Buffer
SWITCHING CHARACTERISTICS
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)
Symbol
LF9501–
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*
*
40
31
25
20
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Min Max Min Max Min Max Min Max
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15
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10
8
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6
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2
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2
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12
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6
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2
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2
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4
4
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15
14
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24
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14
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Parameter
tCYC
Cycle Time
tPW
Clock Pulse Width
tDS
Data Input Setup Time
tDH
Data Input Hold Time
tES
Clock Enable to Clock Setup Time
tEH
Clock Enable to Clock Hold Time
tLS
Length Control Input Setup Time
tLH
Length Control Input Hold Time
tLES
Length Control Enable to Clock Setup Time
tLEH
Length Control Enable to Clock Hold Time
tMS
Mode Select Setup Time
tMH
Mode Select Hold Time
tOUT
Clock to Data Out
tOH
Output Hold Time (Note 8)
tENA
Three-State Output Enable Delay (Note 11)
tDIS
Three-State Output Disable Delay (Note 11)
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15*
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Min Max
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15
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6
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5
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0
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5
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0
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5
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0
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5
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0
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4
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FUNCTIONAL TIMING — CLKSEL LOW
tCYC
CLK*
tMS
tPW
tMH
tPW
MODSEL
tDS
tDH
DI9-0
tOUT
tOH
HIGH IMPEDANCE
DO9-0
tDIS
tENA
OE
*When CLKSEL is HIGH, assume CLK is inverted.
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*DISCONTINUED SPEED GRADE
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Video Imaging Products
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08/16/2000–LDS.9501-H
LF9501
DEVICES INCORPORATED
Programmable Line Buffer
SWITCHING CHARACTERISTICS
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)
Symbol
LF9501–
12345678901234567890
12345678901234567890
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*
*
40
31
25
20
12345678901234567890
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Min Max Min Max Min Max Min Max
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40
31
25
20
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15
12
10
8
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12
10
8
6
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2
2
2
2
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12
10
8
6
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2
2
2
2
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13
10
8
6
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2
2
2
2
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13
10
8
6
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2
2
2
2
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13
10
8
6
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2
2
2
2
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22
16
15
14
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4
4
4
4
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25
20
15
14
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25
24
15
14
Parameter
tCYC
Cycle Time
tPW
Clock Pulse Width
tDS
Data Input Setup Time
tDH
Data Input Hold Time
tES
Clock Enable to Clock Setup Time
tEH
Clock Enable to Clock Hold Time
tLS
Length Control Input Setup Time
tLH
Length Control Input Hold Time
tLES
Length Control Enable to Clock Setup Time
tLEH
Length Control Enable to Clock Hold Time
tMS
Mode Select Setup Time
tMH
Mode Select Hold Time
tOUT
Clock to Data Out
tOH
Output Hold Time (Note 8)
tENA
Three-State Output Enable Delay (Note 11)
tDIS
Three-State Output Disable Delay (Note 11)
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15*
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Min Max
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15
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6
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5
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0
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5
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0
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5
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0
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5
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0
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10
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4
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12
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12
CLOCK ENABLE TIMING — CLKSEL LOW
CLK*
tES
tPW
tES
tMH
CLKEN
INTERNAL
CLOCK
LENGTH CONTROL TIMING — CLKSEL LOW
CLK*
tLES
tLEH
tLS
tLH
tMH
LCEN
LC10-0
*When CLKSEL is HIGH, assume CLK is inverted.
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*DISCONTINUED SPEED GRADE
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LF9501
DEVICES INCORPORATED
Programmable Line Buffer
NOTES
1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond
those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tDIS test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified IOH and IOL at an output
voltage of VOH min and VOL max
2. The products described by this spec- respectively. Alternatively, a diode
ification include internal circuitry de- bridge with upper and lower current
signed to protect the chip from damagsources of IOH and I OL respectively,
ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be
cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF
less, conventional precautions should minimum, and may be distributed.
be observed during storage, handling,
and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current
stress values.
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
3. This device provides hard clamping of testing of this device. The following
transient undershoot and overshoot. In- measures are recommended:
put levels below ground or above VCC
will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be
VCC + 0.6 V. The device can withstand installed between VCC and Ground
indefinite operation with inputs in the leads as close to the Device Under Test
range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors
tion will not be adversely affected, how- should be installed between device VCC
ever, input current levels will be well in and the tester common, and device
ground and tester common.
excess of 100 mA.
4. Actual test conditions may vary from b. Ground and VCC supply planes
those designated but operation is guar- must be brought directly to the DUT
anteed as specified.
socket or contactor fingers.
5. Supply current for a given applica- c. Input voltages should be adjusted to
tion can be accurately approximated by: compensate for inductive ground and VCC
noise to maintain required DUT input
NCV2 F
levels relative to the DUT ground pin.
4
where
10. Each parameter is shown as a minN = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing every cycle and no load, at a 25 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
11. For the tENA test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the tDIS test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
S1
DUT
IOL
VTH
CL
IOH
FIGURE B. THRESHOLD LEVELS
tENA
OE
Z
tDIS
1.5 V
1.5 V
3.5V Vth
0
1.5 V
1.5 V
Z
1
VOL*
0.2 V
VOH*
0.2 V
0
Z
1
Z
0V Vth
VOL* Measured VOL with IOH = –10mA and IOL = 10mA
VOH* Measured VOH with IOH = –10mA and IOL = 10mA
imum or maximum value. Input requirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the external system must supply at least that
much time to meet the worst-case requirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
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LF9501
DEVICES INCORPORATED
Programmable Line Buffer
ORDERING INFORMATION
LCEN
CLKSEL
NC
NC
CLKEN
CLK
LC2
LC3
LC4
LC5
MODSEL
44-pin
7
6 5 4 3 2 1 44 43 42 41 40
39
8
38
9
37
10
36
11
12
13
Top
View
35
34
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
DI0
DI1
DI2
DI3
DI4
VCC
GND
DI5
DI6
DI7
DI8
DO9
OE
LC0
LC1
LC10
LC9
LC8
LC7
LC6
DI9
NC
DO0
DO1
DO2
DO3
DO4
VCC
GND
DO5
DO6
DO7
DO8
Plastic J-Lead Chip Carrier
(J1)
Speed
0°C to +70°C — COMMERCIAL SCREENING
25 ns
20 ns
LF9501JC25
LF9501JC20
–40°C to +85°C — COMMERCIAL SCREENING
Video Imaging Products
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08/16/2000–LDS.9501-H
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