Mitel MP1S Quadrature downconverter Datasheet

SL1714
Quadrature Downconverter
Advance Information
Supersedes November 1997 issue 1.7
FEATURES
■ Single chip system for wideband quadrature
downconversion
■ Compatible with all standard high IF frequencies
1
16
SL1714
AGC
IOUT
VEEA
IFINB
IFIN
IVCCA
QOUT
VEEC
VCCB
VCODIS
VCO B
VCO A
VEEB
PSCAL
PSCALB
VCCC
MP16
AGC
IOUT
VEEA
IFINB
IFIN
IVCCA
QOUT
VEEC
1
16
SL1714 C
The SL1714 is a quadrature downconverter, intended
primarily for application in professional and consumer digital
satellite tuners.
The device contains all elements necessary, with the
exception of external local oscillator tank to form a complete
system operating at standard satellite receiver intermediate
frequencies. It is intended for use with external carrier
recovery.
The device includes a low noise RF input amplifier, a
reference VCO with prescaler output buffer and In-phase and
Quadrature mixers with baseband buffer amplifiers containing
AGC gain control.
The SL1714 is optimised to drive a dual ADC converter
such as the VP216.
The SL1714 utilises a standard MP16 plastic package,
the SL1714C a power MH16 plastic package.
DS4619 - 2.0 April 1998
VCCB
VCODIS
VCO B
VCO A
VEEB
PSCAL
PSCALB
VCCC
■ Excellent gain and phase match up to 30MHz
baseband
■ High output referred linearity for low distortion and
multi channel application
MH16
Fig. 1 Pin allocation SL1714
■ Simple low component application
■ Fully balanced low radiation design with fully
integrated quadrature generation
APPLICATIONS
■ High operating input sensitivity
■ Data communications systems
■ On-board AGC facility
■ Cable systems
■ On chip oscillator for varactor tuning or SAW
resonator operation
■ ESD protection (Normal ESD handling procedures
should be observed)
■ Satellite receiver systems
ORDERING INFORMATION
SL1714/KG/MP1S (Sticks)
SL1714/KG/MP1T (Tape and Reel)
SL1714C/KG/MH1P (Sticks)
SL1714C/KG/MH1Q (Tape and Reel)
SL1714
QUICK REFERENCE DATA
Characteristic
Value
Units
Input noise figure, DSB
17
dB
Maximum conversion gain
48
dB
Minimum conversion gain
28
dB
IP32T output referred
+8
dBV
Output clip voltage
1.5
V
± 0.5
dB
Phase match up to 15MHz
±1
deg
Phase match up to 30MHz
± 1.5
deg
Gain flatness up to 30MHz
± 0.5
dB
- 96
dBc/Hz
Gain match up to 30MHz
VCO phase noise, SSB @ 10kHz offset
Prescaler division ratio
32
Prescaler output swing
1.6
Vp-p
AGC
IFIN
I OUT
AGC
IFINB
AGC
VCODIS
0 deg
VCO
VCO
LO
90 deg
Quadrature
generator
÷32
Fig. 2 SL1714 block diagram
2
Q OUT
PSCAL
PSCALB
SL1714
FUNCTIONAL DESCRIPTION
The SL1714 is a wideband quadrature downconverter,
optimised for application in both professional and consumer
digital satellite receiver systems and requiring a minimum
external component count. It contains all the elements
required for construction of a quadrature demodulator, with
the exception of tank circuit for the local oscillator.
A block diagram is shown in Fig. 2.
The SL1714 oscillator can be used with either a varactor
tuned tank circuit or with a SAW resonator. Both
configurations are described in the Application Notes section
of this Data Sheet.
A typical digital satellite tuner application from tuner input
to data transport stream is shown in Fig. 13.
In normal applications the second satellite IF frequency of
typically 402.75 or 479.5 MHz is fed from the tuner SAW filter
to the RF preamplifier, which is optimised for impedance
match and signal handling. The amplifier output signal is then
split into two balanced channels to drive the In-phase and
Quadrature mixers. The typical RF input impedance is shown
in Fig. 3.
In-phase and Quadrature LO signals for the mixers are
derived from the on board local oscillator, which uses an
external varactor tuned resonant network and is optimised for
low phase noise. The VCO also drives an on board divide by
32 prescaler whose outputs can be used for driving an external
PLL control loop for the VCO, where the PLL loop is contained
within the QPSK demodulator, for example the VP305. For
optimum performance in the varactor tuned application the
VCO should be fully symmetric. The VCO has a disable facility
by grounding pin 15, VCODIS; in normal application this pin is
pulled to Vcc via a 4K7 resistor.
The mixer outputs are fed to balanced baseband AGC
amplifier stages, which provide for a minimum of 12 dB of AGC
control. The typical AGC characteristic is shown in Fig. 4.
These amplifiers then feed a low output impedance true
differential to single-ended converter output stage. In normal
application the output can be either directly AC coupled to the
ADC converter such as the VP216, which will generally have
a high input impedance, or to drive an anti alias filter. In this
later case the maximum load presented to the SL1714 must
not exceed a parallel combination of 1KΩ and 15pF. The
typical baseband output impedance is contained in Fig. 5.
It is recommended that the device is operated with an
output amplitude of 760mV under lock conditions.
Under transient conditions the output should not exceed
the clipping voltage.
Input and output interface circuitry is contained in Fig. 6.
The typical key performance numbers at 480 MHz IF, 5V
Vcc, 1 KΩ load and 25 deg C ambient are contained in table
headed 'QUICK REFERENCE DATA'. With SAWR oscillator
application the gain and phase match performance will
typically exceed these numbers.
3
SL1714
Marker 1 480MHz
+j1
Zreal
= 96Ω
Zimag = 54Ω
+j0.5
+j2
+j0.2
0
0.2
0.5
1
X
-j0.2
-j0.5
-j2
START 350 MHz
STOP 650 MHz
-j1
Fig.3 Typical RF input impedance
4
SL1714
50.00
GAIN (dB)
45.00
40.00
33.00
30.00
25.00
0
1
2
3
4
5
Vagc (V)
Fig.4 Typical AGC characteristic
j1
+j0.5
+j2
+j0.2
X3
0
X2
0.5
1
0.2
X1
-j0.2
1 1MHz
2 15MHz
-j0.5
-j2
3 30MHz
-j1
Fig. 5 Typical baseband output impedance
5
SL1714
VCO
IFIN
IFINB
VCO
2x20k
Vref
IF Input
VCO
Vcc
O/P
55k
VCODIS
Vref
I & Q baseband output
VCO disable input
Vcc
50k
AGC
O/P
Vref
Prescaler outputs
AGC input
Fig. 6 I/O port peripheral circuitry
6
VR1
1K
1
5V
9
C8
100pF
+
I C 1 SL1714
C7
100nF
IOUT
C9
47uF
R1
75R
C15
10nF
L5
4u7
C2
100nF
C14
10nF
/32
5V
R2
4K7
Osc
SW1
VCO DISABLE
Q Mixer
VEEA VEEB VEEC
12
8
3
PSCALB
AGC
5
4 IFIN
IFINB
11
10 PSCAL
L6
4u7
16
VCCA VCCB VCCC
I Mixer
6
2
15
7
14
13
C11
220nF
2
1
LK2
12nH
L1
C10
220nF
LK1
D1
BB811
SK3
I CH O/P
4
3
3p9
C13
3p3 5V
C12
4
3
R4
110R
T2
BCW31
C21
10nF
R11
10K
R3
110R
T1
BCW31
Fig.7 SL1714 standard evaluation board
SK4
Q CH O/P
VCODIS
QOUT
VCOB
VCOA
2
5V
C6
100pF
4K7
5V
C4
C5
100pF 100nF
1
C1
100nF
C3
100nF
R6
SK1
RF IN
R7
680R
R5
680R
5V
C16
10nF
C17
100pF
5V
XTAL1
XTAL2
SDA
SCL
P7
P6
P5
R10 4K7
R9 22K
R8 22K
C20
47nF
DRV CH PUMP
Vee
RF I/P
RF I/P
Vcc
NC
P3
P4
T3
BCW31
16
15
14
13
12
11
10
9
30V
CN1
DC POWER
2 3
SP5611
IC2
1
1
2
3
4
5
6
7
8
30V
C18
18pF
C19
220nF
6
5
4
3
X1
4 MHz
5V
SCL5
GND
5V0
SDA5
I2C
SK4
SL1714
7
SL1714
SL1714 EVALUATION BOARD
VERSION 2.0 19-MAR-97
Fig.8
Fig.9
8
5V
IF IN
1
SK1
2 3
CN1
POWER
R1
75R
C2
100nF
C1
100nF
R7
680R
VR1
1K
R5
680R
Q Mixer
VEEA VEEB VEEC
12
8
3
VCO DISABLE
11
10 PSCAL
PSCALB
5V
4K7
R2
15
7
14
13
2
SW1
VCODIS
QOUT
VCOB
VCOA
5
IFIN
4
IFINB
/32
SL1714
C8
100nF
IOUT
Osc
IC1
C7
100pF
AGC
1
5V
C6
100nF
Fig.10. SL1714 I & Q downconverter with SAW resonator
TP1
5V
C5
100pF
16
9
6
VCCA VCCB VCCC
I Mixer
5V
C4
100nF
AGC VOLTS
R6
4K7
C3
100pF
5V
C9
47uF
4
2
Q CH OUT
C11
220nF
4
2
SK3
3
R3
110R
L1 15nH
R4
110R
2
C13
1nF
3
4
SAW
RESONATOR
SAW1
5V
1
T2
BCW31
1
LK2
C15
180pF
C14
10nF
SK2
T1
BCW31
I CH OUT
3
1
LK1
C10
220nF
+
C12
1nF
SL1714
9
SL1714
Fig. 11
Fig. 12
10
SL1714
APPLICATION NOTES
These application notes should be read in conjunction with
circuit diagrams contained in Fig. 7 and 10, and a
recommended front end tuner solution contained in Fig. 12.
These boards have been designed to demonstrate
performance and to allow for initial evaluation of the SL1714.
Varator Tuned Oscillator
Refer to Fig. 7 circuit diagram and Figs. 8 and 9PCB layout.
This application uses a synthesised VCO with a tuning
range of 460 MHz to 500 MHz. The surface mount inductor L1
is 12 nH. The VCO frequency is controlled by the SP5611
synthesiser which is programmed via an I2C bus. The RF input
to the synthesiser is from the SL1714 prescaler outputs
coupled via RF inductors L3 and L4.
For functional checking the VCO can be tuned by
physically shorting the base of transistor T3 to ground and
then adjusting the +30 volt supply to tune the VCO. Under
these conditions, due to the unlocked state of the LO, the
board WILL NOT BE representative of locked gain and phase
match or phase noise performance.
In real applications the VCO control voltage will be
provided by the QPSK demodulator circuit, such as the
VP305. This circuit provides a line voltage to align the
reference LO in the SL1714 in both frequency and phase to the
centre of the modulation bandwidth, normally 402.75 or 479.5
MHz.
As in all feedback loops the bandwidth of the varactor line
must be optimised for the symbol rate of the received
modulation.
It is recommended for optimum performance that the VCO
application is implemented symmetrically, in presented drive
and impedance to the VCO ports, as demonstrated in the
evaluation schematic and PCB.
In the recommended application the varactor diodes are
referenced to the VCO port DC bias voltages. This limits the
minimum tuning voltage on the varactor line to 3V. If lower
tuning voltage is required the tank can be AC coupled to the
VCO ports by 390pF capacitor and a DC reference voltage for
the varactor diodes applied by centre tapping the tank
inductors. NB the varactor diodes require a minimum of 1V
reverse bias for correct operation.
In real applications the maximum tuning range required for
the VCO will be determined by the required lock range of the
tuner and the manufacturing tolerance of the tank, assuming
the quadrature downconverter section will be alignment free.
This tuning range will typically be much smaller than the
demonstration board, which will consequently improve the
VCO phase noise performance.
This application can be ported direct to real system
implementations. Normal good RF practice must be applied to
the layout implementation.
Prescaler Outputs (varactor tuned VCO)
The VCO frequency divided by 32 is available at the
differential prescaler outputs, pins 10 and 11.
These enable the VCO frequency to be synthesised by a PLL
frequency synthesiser; on the demo board an SP5611 is used
for this function however in a real application this function will
be provided by the QPSK demodulator function contained in
for example the VP305.
It is recommended that the prescaler outputs are loaded
symmetrically to balance radiation effects.
Saw Resonator Oscillator
Refer to Fig. 10 circuit diagram and Figs 11 and 12 PCB
layout.
In the standard application the oscillator uses a varactor
diode tuned tank circuit which allows fine tuning of the
oscillator frequency via a voltage control line. This control
voltage is usually derived from the QPSK/FEC decoder
VP305/VP306.
Certain applications do not require this fine tune facility so
a fixed frequency application using a SAW resonator has been
developed. In this application the frequency of the oscillator is
determined by the SAW resonator. The SAW is AC coupled
into the VCO pins of the device pins 13 and 14 via 100pF
coupling capacitors.
The SAW resonator used in this application is a ;
Murata Part No SAR479.45MB10X200
Prescaler Outputs (SAWR tuned VCO)
The VCO frequency divided by 32 is available at the
differential prescaler outputs, pins 10 and 11. Normally these
outputs will not be required since the derotation and fine tuning
required will be processed by the QPSK demodulator.
However these frequencies could be used if required for other
system reference frequencies or clocks.
If used it is recommended that the prescaler outputs are
loaded symmetrically to balance radiation effects.
VCO Disable
The on-chip oscillator can be disabled by connecting
VCODIS, pin 15, to ground and enabled by connecting to Vcc
via a 4K7 pull up resistor.
AGC
The AGC facility can be used to control the conversion gain
of the SL1714.
On the demonstration boards the conversion gain is
adjusted by means of a potentiometer, which is set to 2.5V so
giving a conversion gain of 40 dB. The voltage adjustment
range for the AGC is approximately 0.5 to 4.5 V.
It is important that the AGC voltage minimum does not give
a conversion gain of greater than 44dBs otherwise the
channel amplitude match may be degraded. In real
applications the AGC can be either set at a fixed control
voltage or controlled by means of the AGC control signal from
the QPSK demodulator dependant on the overall dynamic
range requirement of the tuner and it’s gain distribution.
11
SL1714
I & Q baseband outputs
I2C Bus connections
The SL1714 offers a greatly improved drive capability over
the SL1710 and as such is much less sensitive to the load
conditions.
It is still important however to carefully balance the loads
presented to the SL1714 to ensure no differential gain or
phase degradation is introduced by the load circuits, which will
also include effects due to track striplines etc.
For demonstration purposes the output is unsuitable for
connection via co-axial cables to standard test equipment,
where such equipment is normally 50 Ω or highly capacitive.
To overcome this problem the outputs of the SL1714 are
therefore buffered through emitter followers which are
optimised to drive 50 Ω loads without appreciable degradation
in the SL1714 performance. These buffer stages are
selectable so enabling the outputs to be loaded directly for
interfacing direct with an ADC via a low capacitive link.
In most applications the SL1714 will normally interface
direct into the ADC converter such as the VP216, which will
present a >1 KΩ low capacitive load.
The output is optimised for typical drive levels of 760
mVp-p and the onset of clipping is typically > 1.5V p-p.
The board is provided with an RJ11 I2C bus connector
which feeds directly to the SP5611 synthesiser.
This connects to a standard 6-way connector cable which
is supplied with the I2C/3-wire bus interface box.
Input and Output connections
The board is provided with the following connectors:
A) IF I/P SMA connector SK1which is AC coupled to the
RF input of the SL1714.
B) I CH OUT SK2 and Q CH OUT SK3 which provide
either a buffered or direct baseband output signal from
the SL1714 (depending on which way the links LK1
and LK2 are set). The output buffers should be used
when driving 50Ω test equipment or co-axial lines.
Links and Switches
The board is provided with the following:
SL1714 Evaluation Board
This board has been created to show the operation of the
SL1714 I/Q downconverter.
It does not attempt to simulate a real system, since in
practice the 479.5MHz IF oscillator on the SL1714 (and the
60MHz clock on the subsequent ADC) would be controlled via
the baseband IQ demodulator chip such as the VP305 which
follows the dual channel ADC. For simplicity, the VCO is
locked using GPS SP5611 synthesiser, controlled via an I2C
bus.
For full evaluation, 30V and 5V supplies are necessary.
Supplies
The board must be provided with the following supplies:
A) 5V for the SL1714 and SP5611 and 30V for the
varactor line.
The supply connector is a 3 pin 0.1" pitch pin header. The
centre pin of the connector is GND.
Outputs driven into hard clipping can exhibit amplitude
decline. AGC loops should be designed to take account of this.
12
VCO DISABLE switch
This disables the VCO of the SL1714. It does NOT power
down the chip.
AGC ADJUST potentiometer
The potentiometer sets the AGC input voltage of the
SL1714 which controls the gain of the chip. TP1 is provided as
a means of monitoring the AGC voltage.
LK1 and LK2
These are links which may be placed either vertically or
horizontally to connect the outputs of the SL1714 either
directly or via buffers to the SMA output connectors of the
board.
If the links are placed vertically 1-2 and 3-4 the outputs are
connected directly.
If the links are placed horizontally 1-3 and 2-4 the ouputs
are connected via buffers.
SL1714
Programming of Synthesisers
SL1714 Operation
A SP5611 synthesiser is used to set the frequency of the
SL1714 VCO (480MHz). Since the SL1714 incorporates a
divide by 32 the synthesised frequency that the SP5611 must
be programmed to is 480/32=15MHz.
The SL1714 will mix an IF input with its own local oscillator.
This is controlled as above via a SP5611 synthesiser.
Normally the VCO will be set to the same frequency as the
IF input, and the signal mixed directly down to baseband.
Alternatively, a CW RF source may be fed into the input of
the SL1714 which is deliberately offset from the VCO. By
varying the offset from 0-20MHz and monitoring the I and Q
channel baseband outputs, the flatness response of the chip/
output filter can be measured.
The SL1714 oscillator may also be disabled by setting the
ON-VCO-OFF switch to the OFF position.
An AGC voltage adjust pot marked AGC ADJUST is
provided, together with a test point.
Example
a) To program the SL1714 to 480MHz.
I2C Byte
Hex Code
Byte 1 (address)
Byte 2 (programmable divider 8 MSBs)
C2
00
Byte 3 (programmable divider 8 LSBs)
Byte 4 (control data)
F0
CE
Byte 5 (port data)
00
C2 is the address byte (byte 1).
0F00 is the programmable divider information (bytes 2 and 3).
CE is the control data information (byte 4).
**Note - the programmable divider information should be
set to program 480MHz /32 = 15MHz since the SL1714
provides a divide by 32 prescaler output rather than the VCO
carrier frequency.
It is not possible to program the VCO to 479.5MHz when
using a 7.8125kHz phase comparator frequency. The minimum step size is 7.8125KHz x 8 (RF prescaler inside SP5611)
x 32 (SL1714 output prescaler) = 2MHz.
If the reference divider is set to 1024 mode (3.90625kHz
phase comparator frequency), the minimum step size will be
1MHz.
This may be achieved by programming the control byte to
CC and modifying the programmable divider information for
the new step size.
Measurement of Gain and Phase Match.
a) Synthesise the required frequency (480MHz is used in the
example above).
b) Connect an RF signal generator to the input.
c)Input a signal which should give an output of approx 0dBm
(0.707V p-p), in combination with the appropriate AGC
setting.
d) Connect a vector voltmeter to the BUFFERED outputs
when using 50Ω inputs. When using high impedance probes,
the direct outputs may be used. Selection of outputs is via the
on board U links.
e) CALIBRATE the vector voltmeter and the leads to be used.
The calibration should be performed at the chosen baseband
frequency and level for maximum accuracy.
f) Vary the RF input frequency either side of the LO and note
the relative I and Q gain and phase reading.
If you experience any difficulties with this board, or require
further help, please contact Robert Marsh on 01793 518234
or Fred Herman on 01793 518423
13
SL1714
RF I/P
from
LNB
950MHz
2.15GHz
0.22MHz
0.7V pk-pk
480MHz IF
I/P
Filter
IF
Filter
TUNER
(SL2015)
SL1714
(SL1711)
I
Q
AGC
Tank
circuit
ADC
2x6 bit, 90MS/s
(VP216)
VCO I/p
AGC
TANK
VCO
PLL SYNTH. options
(SP5658) (3w bus)
(SP5055) (I2C bus)
(SP5655) (I2C bus)
(SP5659) (I2C bus)
AGC
Loop/line
Filters
RF TUNER
MODULE
Fig.13 Example digital front end architecture
Note: All ICs shown in Fig. 12 are available from Mitel Semiconductor.
14
QPSK
Demod & FEC
(VP305)
Data
Stream
SL1714
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated)
Tamb= see note 7, Vee= 0V, Vcc = 4.75 to 5.25 V, Fif = 479.5 MHz, IF bandwidth ± 30 MHz, output amplitude -11dBV
These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature
and supply voltage unless otherwise stated.
Characteristic
Pin
Min
Supply voltage
6,9,16
4.75
Supply current
IF input operating
6,9,16
4, 5
frequency (1)
IF input impedance
4, 5
Input return loss
4, 5
Input noise figure, DSB
4, 5
Typ
109
350
350
VCO phase noise, SSB
-96
@ 10kHz offset
VCO Vcc sensitivity
VCO temperature
stability
Prescaler output swing
Prescaler output duty
10, 11
10, 11
V
125
550
mA
MHz
1.2
40
1.5
50
Conditions
Ω
Over specified frequency
dB
operating range, see Fig. 6.
Over specified frequency
19
dB
operating range, see Fig. 6.
Maximum gain setting
1
dB/dB
550
MHz
-85
dBc/Hz
application.
Varactor tuned, determined
2E3
ppm/V
by application.
Free running
100
ppm/°C
Uncompensated
60
Vp-p
%
±1
dB
dB
For any gain setting 0V to 5V
See Fig. 4
See Fig. 4
12
17
Units
5.25
75
Variation in NF with gain
setting
VCO operation range
Max
Centre frequency and tuning
range determined by
cycle
AGC
Gain, Vagc = +2.5V
Temp stability of gain
1
40
Gain, Vagc = +0.5V
Gain, Vagc = +VCC -0.5V
1
1
44
32
dB
dB
AGC range
I Q gain match
18
±0.5
±1
dB
dB
See Note 3.
I Q phase match
I Q phase match
±1
±1.5
±2
±6
deg
deg
See Note 4.
See Note 5.
I & Q channel in band ripple
I & Q channel in band ripple
±0.3
±0.5
±1
±1
dB
dB
see Note 3.
See Note 4.
I Q crosstalk
-29
-20
dB
See Note 2 and 4
for derivation of cross
modulation
15
SL1714
ELECTRICAL CHARACTERISTICS (continued)
Test conditions (unless otherwise stated)
Tamb= See note 7. Vee= 0V, Vcc = 4.75 to 5.25 V, Fif = 479.5 MHz, IF bandwidth ± 30 MHz, output ampltude -11dBV
These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature
and supply voltage unless otherwise stated.
Characteristic
Pin
Min
Typ
Max
Units
20
Ω
I & Q baseband output
2,7
8
impedance
I & Q baseband output
2, 7
-11
recommended level
I & Q baseband output
2, 7
1.5
Conditions
See note (5), and Fig. 5.
dBV
See note( 8)
Vp-p
See note(6)
dBV
2 input carriers at -39 dBV
within IF bandwidth of ±30MHz
AGC set to give composite
clipping level
IP32T, output referred
+3
+9
output of -11 dBV, IM3 tone
within baseband bandwidth
IM32T output referred
-40
dBc
2 input carriers within IF
bandwidth of ±30MHz, AGC
set to give composite output
of -11 dBV, IM3 tone within
All prescaler and other
-30
dBc
spurs in I & Q baseband
output.
Power supply rejection
baseband bandwidth
0.1 - 100MHz, referred to output
amplitude of - 11 dBV.
20
dBc
Attenuation Vcc to I & Q outputs,
over 0-500KHz
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
16
Performance not guaranteed over full specified IF input operating range.
I Q crosstalk is determined from the gain and phase match by the following formula.
Crosstalk = 20* Log (tan(phase error + Atan (1+amplitude imbalance) -45°)).
Over specified gain dynamic range, 1KΩ and 15pF load up to 30MHz baseband.
Over specified gain dynamic range, 1KΩ and 15pF load up to 15MHz baseband.
Over specified gain dynamic range, 1KΩ and 15pF load up to 30MHz baseband.
The device should not be operated beyond the point of output clipping since gain match may be
compromised.
* Operating temperature range for the SL1714 is 0°C to 70°C. This applies to applications featuring a double sided
copper board. For other applications not using such a board, the maximum operating temperature may be
reduced. Operating temperature range for the SL1714C is 0° to 85°C.
Operation above the recommended IQ output level may result in outputs with harmonic performance degraded.
SL1714
ABSOLUTE MAXIMUM RATINGS
All voltages are reffered to Vee at 0V
Characteristics
Min
Max
Units
Supply voltage, Vcc
-0.3
7
V
2.5
Vp-p
IFFIN &IFINB input voltage
IFIN & IFINB input DC offset
-0.3
Vcc+0.3
V
IOUT & QOUT DC offset
-0.3
Vcc+0.3
V
AGC DC offset
-0.3
Vcc+0.3
V
VCO1 & 2 DC offset
-0.3
Vcc+0.3
V
VCODDIS DC offset
-0.3
Vcc+0.3
V
PSCAL & PSCALB DC offset
-0.3
Vcc+0.3
Storage temperature
-55
150
°C
Junction temperature
125
°C
MP16 package thermal resistance
chip to Ambient
81
°C/W
MH16 package thermal resistance
chip to Ambient
60
°C/W
MP16 package thermal resisstance
chip to case
28
°C/W
Power consumption at 5.25V
656
mW
ESD protection
3
kV
Conditions
Mil std 883 latest revision
method 3015 cat 1
17
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