[ /Title (CD74H C151, CD74H CT151) /Subject (High Speed CMOS Logic 8Input Multi- CD54HC151, CD74HC151, CD54HCT151, CD74HCT151 Data sheet acquired from Harris Semiconductor SCHS150C High-Speed CMOS Logic 8-Input Multiplexer September 1997 - Revised October 2003 Features Description • Complementary Data Outputs The ’HC151 and ’HCT151 are single 8-channel digital multiplexers having three binary control inputs, S0, S1 and S2 and an active low enable (E) input. The three binary signals select 1 of 8 channels. Outputs are both inverting (Y) and non-inverting (Y). • Buffered Inputs and Outputs • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Ordering Information • Wide Operating Temperature Range . . . -55oC to 125oC TEMP. RANGE (oC) PACKAGE CD54HC151F3A -55 to 125 16 Ld CERDIP CD54HCT151F3A -55 to 125 16 Ld CERDIP CD74HC151E -55 to 125 16 Ld PDIP CD74HC151M -55 to 125 16 Ld SOIC CD74HC151MT -55 to 125 16 Ld SOIC CD74HC151M96 -55 to 125 16 Ld SOIC CD74HCT151E -55 to 125 16 Ld PDIP CD74HCT151M -55 to 125 16 Ld SOIC CD74HCT151MT -55 to 125 16 Ld SOIC CD74HCT151M96 -55 to 125 16 Ld SOIC PART NUMBER • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • Alternate Source is Philips/Signetics • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC151, CD54HCT151 (CERDIP) CD74HC151, CD74HCT151 (PDIP, SOIC) TOP VIEW I3 1 16 VCC I2 2 15 I4 I1 3 14 I5 I0 4 13 I6 Y 5 12 I7 Y 6 11 S0 E 7 10 S1 GND 8 9 S2 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 CD54HC151, CD74HC151, CD54HCT151, CD74HCT151 Functional Diagram 4 I0 3 I1 2 I2 5 1 I3 Y 15 6 I4 Y 14 I5 13 I6 12 I7 11 S0 S1 10 9 S2 GND = 8 VCC = 16 7 E TRUTH TABLE SELECT INPUTS DATA INPUTS ENABLE OUTPUT S2 S1 S0 I0 I1 I2 I3 I4 I5 I6 I7 E Y Y X X X X X X X X X X X H H L L L L L X X X X X X X L H L L L L H X X X X X X X L L H L L H X L X X X X X X L H L L L H X H X X X X X X L L H L H L X X L X X X X X L H L L H L X X H X X X X X L L H L H H X X X L X X X X L H L L H H X X X H X X X X L L H H L L X X X X L X X X L H L H L L X X X X H X X X L L H H L H X X X X X L X X L H L H L H X X X X X H X X L L H H H L X X X X X X L X L H L H H L X X X X X X H X L L H H H H X X X X X X X L L H L H H H X X X X X X X H L L H H = High Voltage Level, L = Low Voltage Level, X = Don’t Care 2 CD54HC151, CD74HC151, CD54HCT151, CD74HCT151 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 1) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) VIH - - 2 1.5 - - 1.5 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V MIN TYP MAX MIN MAX MIN MAX UNITS - 1.5 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA 3 CD54HC151, CD74HC151, CD54HCT151, CD74HCT151 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) IO (mA) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL PARAMETER 25oC VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V ±0.1 - ±1 - ±1 µA HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II VCC and GND 0 5.5 - ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA ∆ICC (Note 2) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS Select 1.5 Data 0.45 Enable 0.3 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC. Switching Specifications Input tr, tf = 6ns PARAMETER SYMBOL TEST CONDITIONS -40oC TO 85oC 25oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 170 - 215 - 255 ns 4.5 - - 34 - 43 - 51 ns CL =15pF 5 - 14 - - - - - ns CL = 50pF 6 - - 29 - 37 - 43 ns HC TYPES Propagation Delay (Figure 1) tPLH, tPHL CL = 50pF Any Data Input to Y 4 CD54HC151, CD74HC151, CD54HCT151, CD74HCT151 Switching Specifications Input tr, tf = 6ns PARAMETER Any Data Input to Y Any Select to Y Any Select to Y Enable to Y Enable to Y Output Transition Time (Figure 1) (Continued) TEST CONDITIONS -40oC TO 85oC 25oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 185 - 230 - 280 ns 4.5 - - 37 - 46 - 56 ns CL =15pF 5 - 15 - - - - - ns CL = 50pF 6 - - 31 - 39 - 48 ns tPLH, tPHL CL = 50pF 2 - - 185 - 230 - 280 ns 4.5 - - 37 - 46 - 56 ns CL =15pF 5 - 15 - - - - - ns CL = 50pF 6 - - 31 - 39 - 48 ns tPLH, tPHL CL = 50pF 2 - - 205 - 255 - 310 ns 4.5 - - 41 - 51 - 62 ns CL =15pF 5 - 17 - - - - - ns CL = 50pF 6 - - 35 - 43 - 53 ns tPLH, tPHL CL = 50pF 2 - - 140 - 175 - 210 ns 4.5 - - 28 - 35 - 42 ns CL =15pF 5 - 11 - - - - - ns CL = 50pF 6 - - 24 - 30 - 36 ns tPLH, tPHL CL = 50pF 2 - - 145 - 180 - 220 ns 4.5 - - 29 - 36 - 44 ns CL =15pF 5 - 12 - - - - - ns CL = 50pF 6 - - 25 - 31 - 38 ns tTLH, tTHL CL = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns SYMBOL tPLH, tPHL CL = 50pF Input Capacitance CIN - - - - 10 - 10 - 10 pF Power Dissipation Capacitance (Notes 3, 4) CPD - 5 - 59 - - - - - pF CL = 50pF 4.5 - - 38 - 48 - 57 ns CL =15pF 5 - 16 - - - - ns 4.5 - - 36 - 45 - 54 ns 5 - 15 - - - - - ns 4.5 - 41 - 51 - 62 ns 5 - 17 - - - - - ns 4.5 - - 43 - 54 - 65 ns 5 - 18 - - - - - ns 4.5 - - 29 - 36 - 44 ns 5 - 12 - - - - - ns HCT TYPES Propagation Delay (Figure 2) Any Data Input to Y Any Data Input to Y tPLH, tPHL tPLH, tPHL CL = 50pF CL =15pF Any Select to Y tPLH, tPHL CL = 50pF CL =15pF Any Select to Y tPLH, tPHL CL = 50pF CL =15pF Enable to Y tPLH, tPHL CL = 50pF CL =15pF 5 CD54HC151, CD74HC151, CD54HCT151, CD74HCT151 Switching Specifications Input tr, tf = 6ns PARAMETER Enable to Y SYMBOL TEST CONDITIONS CL = 50pF CL = 50pF CL =15pF Output Transition Time (Continued) CL =15pF tTLH, tTHL CL = 50pF -40oC TO 85oC 25oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 - - 36 - 46 - 54 ns 5 15 - - - - - - ns 4.5 - - 15 - 19 - 22 ns - - 10 - 10 - 10 pF 58 - - - - - pF Input Capacitance CIN - - Power Dissipation Capacitance (Notes 3, 4) CPD - 5 NOTES: 3. CPD is used to determine the dynamic power consumption, per gate. 4. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage. Test Circuit and Waveform tr = 6ns tf = 6ns INPUT LEVEL ENABLE SELECT In 90% VS 10% tTHL tTLH GND 90% VS 10% Y OUTPUT tPLH tPLH tPHL tPHL VS Y OUTPUT tTHL FIGURE 1. 6 tTLH PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 PACKAGING INFORMATION (1) Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-9065201MEA ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD54HC151F3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD54HCT151F3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD74HC151E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC151EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC151M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC151M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC151M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC151M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC151ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC151MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC151MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC151MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC151MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT151E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT151EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT151M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT151M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT151M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT151M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT151ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT151MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT151MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT151MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT151MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM The marketing status values are defined as follows: Addendum-Page 1 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC151M96 D 16 SITE 27 330 16 6.5 10.3 2.1 8 16 Q1 CD74HCT151M96 D 16 SITE 27 330 16 6.5 10.3 2.1 8 16 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) CD74HC151M96 D 16 SITE 27 342.9 336.6 28.58 CD74HCT151M96 D 16 SITE 27 342.9 336.6 28.58 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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