INTEGRATED CIRCUITS 74ABT16823A 74ABTH16823A 18-bit bus interface D-type flip-flop with reset and enable (3-State) Product specification Supersedes data of 1995 Sep 28 IC23 Data Handbook 1998 Feb 27 Philips Semiconductors Product specification 18-bit bus-interface D-type flip-flop with reset and enable (3-State) 74ABT16823A 74ABTH16823A FEATURES DESCRIPTION • Two sets of high speed parallel registers with positive The 74ABT16823A 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. edge-triggered D-type flip-flops • Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors The 74ABT16823A has two 9-bit wide buffered registers with Clock Enable (nCE) and Master Reset (nMR) which are ideal for parity bus interfacing in high microprogrammed systems. • Live insertion/extraction permitted • Power-up 3-State • 74ABTH16823A incorporates bus-hold data inputs which The registers are fully edge-triggered. The state of each D input, one set-up time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output. eliminate the need for external pull-up resistors to hold unused inputs • Power-up Reset • Output capability: +64mA/–32mA • Latch-up protection exceeds 500mA per Jedec Std 17 • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 Two options are available, 74ABT16823A which does not have the bus-hold feature and 74ABTH16823A which incorporates the bus-hold feature. and 200 V per Machine Model QUICK REFERENCE DATA SYMBOL CONDITIONS Tamb = 25°C; GND = 0V PARAMETER TYPICAL UNIT 2.3 1.9 ns tPLH tPHL Propagation delay nCP to nQx CL = 50pF; VCC = 5V CIN Input capacitance VI = 0V or VCC 4 pF Output capacitance VO = 0V or VCC; 3-State 6 pF 500 µA 9 mA COUT ICCZ Outputs disabled; VCC = 5.5V Quiescent su supply ly current ICCL Outputs low; VCC = 5.5V ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 56-Pin Plastic SSOP Type III –40°C to +85°C 74ABT16823A DL BT16823A DL SOT371-1 56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABT16823A DGG BT16823A DGG SOT364-1 56-Pin Plastic SSOP Type III –40°C to +85°C 74ABTH16823A DL BH16823A DL SOT371-1 56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABTH16823A DGG BH16823A DGG SOT364-1 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 2, 27 1OE, 2OE Output enable input (active-Low) 54, 52, 51, 49, 48, 47, 45, 44, 43 42, 41, 40, 38, 37, 36, 34, 33, 31 1D0-1D8 2D0-2D8 Data inputs 3, 5, 6, 8, 9, 10, 12, 13, 14 15, 16, 17, 19, 20, 21, 23, 24, 26 1Q0-1Q8 2Q0-2Q8 Data outputs 56, 29 1CP, 2CP Clock pulse input (active rising edge) 55, 30 1CE, 2CE Clock enable input (active-Low) Master reset input (active-Low) 1, 28 1MR, 2MR 4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0V) 7, 22, 35, 50 VCC Positive supply voltage 1998 Feb 27 2 853-1791 19025 Philips Semiconductors Product specification 18-bit bus-interface D-type flip-flop with reset and enable (3-State) 74ABT16823A 74ABTH16823A PIN CONFIGURATION LOGIC SYMBOL (IEEE/IEC) 1MR 1 56 1CP 1OE 2 55 1CE 1Q0 3 54 1D0 GND 4 53 GND 1Q1 5 52 1Q2 6 VCC 7 1Q3 1OE 2 EN1 1MR 1 R2 1CE 55 G3 1CP 56 1D1 2OE 27 EN5 51 1D2 2MR 28 R6 50 VCC 2CE 30 G7 8 49 1D3 2CP 29 1Q4 9 48 1D4 3 10 47 1D5 1D0 54 1Q5 1Q0 1D1 52 5 1Q1 1D2 51 6 1Q2 1D3 49 8 1Q3 1D4 48 9 1Q4 1D5 47 10 1Q5 1D6 45 12 1Q6 1D7 44 13 1Q7 1D8 43 14 1Q8 42 15 2Q0 16 2Q1 GND 1Q6 1Q7 1Q8 2Q0 2Q1 2Q2 GND 11 12 13 14 15 16 17 18 46 45 44 43 42 41 40 39 GND 1D6 1D7 1D8 2D0 2D1 2D2 GND 2D0 2Q3 19 38 2D3 2Q4 20 37 2D4 2Q5 21 36 2D5 VCC 22 35 VCC 2Q6 23 34 2D6 2Q7 24 33 2D7 GND 25 32 GND 2Q8 26 31 2D8 2OE 27 30 2CE 2MR 28 29 2CP 3C4 7C8 4D 1, 2 ∇ 2D1 41 2D2 40 17 2Q2 2D3 38 19 2Q3 2D4 37 20 2Q4 2D5 36 21 2Q5 2D6 34 23 2Q6 2D7 33 24 2Q7 2D8 31 25 2Q8 8D 5, 6 ∇ SH00015 SH00014 1998 Feb 27 3 Philips Semiconductors Product specification 18-bit bus-interface D-type flip-flop with reset and enable (3-State) 74ABT16823A 74ABTH16823A LOGIC DIAGRAM nCE nD0 nD1 nD2 nD3 nD4 nD5 nD6 nD7 nD8 nCP nD CP R nD CP R Q nD CP R Q Q CP nD nD R R Q CP nD R Q CP nD R Q CP nD R Q CP nD R Q CP Q nMR nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 nQ8 n = 1 or 2 SH00016 FUNCTION TABLE INPUTS OUTPUTS nOE nMR nCE nCP nDx nQ0 – nQ8 L L X X X L L H L ↑ h H L H L ↑ l L L H H ↑ X NC H = h = L = l = NC= X = Z = ↑ = ↑ = H X X X X Z High voltage level High voltage level one set-up time prior to the Low-to-High clock transition Low voltage level Low voltage level one set-up time prior to the Low-to-High clock transition No change Don’t care High impedance “off” state Low to High clock transition Not a Low-to-High clock transition 1998 Feb 27 4 OPERATING MODE Clear Load and read data Hold High impedance Philips Semiconductors Product specification 18-bit bus-interface D-type flip-flop with reset and enable (3-State) 74ABT16823A 74ABTH16823A ABSOLUTE MAXIMUM RATINGS1, 2 PARAMETER SYMBOL VCC IIK CONDITIONS RATING UNIT –0.5 to +7.0 V –18 mA –1.2 to +7.0 V VO < 0 –50 mA output in Off or High state –0.5 to +5.5 V output in Low state 128 output in High state –64 DC supply voltage DC input diode current VI < 0 voltage3 VI DC input IOK DC output diode current voltage3 VOUT DC output IOUT O DC output current Tstg Storage temperature range mA –65 to 150 °C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VCC PARAMETER UNIT DC supply voltage MIN MAX 4.5 5.5 V 0 VCC V VI Input voltage VIH High-level input voltage VIL Low-level input voltage 0.8 V IOH High-level output current –32 mA IOL Low-level output current 64 mA 0 10 ns/V –40 +85 °C ∆t/∆v Input transition rise or fall rate Tamb Operating free-air temperature range 1998 Feb 27 2.0 5 V Philips Semiconductors Product specification 18-bit bus-interface D-type flip-flop with reset and enable (3-State) 74ABT16823A 74ABTH16823A DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VIK VOH Input clamp voltage High-level output voltage Tamb = –40°C to +85°C Tamb = +25°C VCC = 4.5V; IIK = –18mA TYP MAX –0.9 –1.2 MIN UNIT MAX –1.2 V VCC = 4.5V; IOH = –3mA; VI = VIL or VIH 2.5 2.9 2.5 V VCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 3.4 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 2.4 2.0 V VOL Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or VIH 0.42 0.55 0.55 V VRST Power-up output low voltage3 VCC = 5.5V; IOL = 1mA; VI = GND or VCC 0.13 0.55 0.55 V II Input In ut leakage curent 5.5V; VI = VCC or GND VCC = 5.5V ±0.01 ±1 ±1 µA ±0.01 ±1 ±1 µA 0.01 1 1 µA –2 –3 –5 µA VCC = 5.5V; VI = VCC or GND II Input In ut leakage current 74ABTH16823A VCC = 5.5V; VI = VCC Control pins Data pins VCC = 5.5V; VI = 0 IHOLD Bus Hold current inputs5 74ABTH16823A VCC = 4.5V; VI = 0.8V 35 35 VCC = 4.5V; VI = 2.0V –75 –75 VCC = 5.5V; VI = 0 to 5.5V ±800 µA Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA Power-up/down 3-State output current4 VCC = 2.1V; VO = 0.5V; VI = GND or VCC, VOE = Don’t care ±5.0 ±50 ±50 µA IOZH 3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or VIH 1.0 10 10 µA IOZL 3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or VIH –1.0 –10 –10 µA ICEX Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC 50 50 50 µA Output current1 VCC = 5.5V; VO = 2.5V –80 –180 –180 mA VCC = 5.5V; Outputs High, VI = GND or VCC 0.5 1 1 mA VCC = 5.5V; Outputs Low, VI = GND or VCC 9.0 19 19 mA VCC = 5.5V; Outputs 3–State; VI = GND or VCC 0.5 1 1 mA VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND 0.2 1 1 mA IOFF IPU/PD IO ICCH ICCL Quiescent supply current ICCZ ∆ICC Additional supply current per input pin2 –50 –50 NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10% a transition time of up to 100µsec is permitted. 5. This is the bus hold overdrive current required to force the input to the opposite logic state. 1998 Feb 27 6 Philips Semiconductors Product specification 18-bit bus-interface D-type flip-flop with reset and enable (3-State) 74ABT16823A 74ABTH16823A AC CHARACTERISTICS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = –40°C to +85°C VCC = +5.0V ±0.5V Tamb = +25°C VCC = +5.0V WAVEFORM MIN TYP MAX MIN UNIT MAX fMAX Maximum clock frequency 1 140 190 tPLH tPHL Propagation delay nCP to nQx 1 1.4 1.2 2.3 1.9 3.2 2.6 140 1.4 1.2 3.7 2.9 MHz ns tPHL Propagation delay nMR to nQx 2 2.0 3.3 4.3 2.0 5.0 ns tPZH tPZL Output enable time to High and Low level 4 5 1.3 1.2 2.4 2.1 3.2 2.9 1.3 1.2 3.9 3.4 ns tPHZ tPLZ Output disable time from High and Low level 4 5 1.7 1.6 2.9 2.3 4.0 3.2 1.7 1.6 4.7 3.4 ns AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = +25°C VCC = +5.0V WAVEFORM Tamb = –40 to +85°C VCC = +5.0V ±0.5V UNIT MIN TYP MIN 3 2.0 1.5 1.3 0.9 2.0 1.5 ns Hold time, High or Low nDx to nCP 3 1.5 1.5 –0.9 –1.2 1.5 1.5 ns tw(H) tw(L) nCP pulse width High or Low 1 3.3 3.3 1.7 1.7 3.3 3.3 ns ts(H) ts(L) Setup time, High or Low nCE to nCP 3 1.5 2.0 0.9 0.9 1.5 2.0 ns th(H) th(L) Hold time, High or Low nCE to nCP 3 1.5 1.5 –0.8 –0.9 1.5 1.5 ns tw(L) nMR pulse width, Low 2 3.0 1.7 3.0 ns trec Recovery time nMR to nCP 2 2.5 1.0 2.5 ns ts(H) ts(L) Setup time, High or Low nDx to nCP th(H) th(L) 1998 Feb 27 7 Philips Semiconductors Product specification 18-bit bus-interface D-type flip-flop with reset and enable (3-State) 74ABT16823A 74ABTH16823A AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fMAX nCP VM VM VM 0V tPLH tw(L) tPHL VM tPZH 0V tw(H) tPHZ VOH nQx VOH VOH–0.3V VM nQx VM VM 3.0V or VCC whichever is less nOE 3.0V or VCC whichever is less 0V 0V SH00020 SH00017 Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency VM nMR 3.0V or VCC whichever is less 3.0V or VCC whichever is less VM nOE tREC VM nCP tPZL 3.0V or VCC whichever is less nQx 0V tPHL SH00021 Waveform 2. Master Reset Pulse WIdth, Master Reset to Output Delay and Master Reset to Clock Recovery Time VM VM 3.0V or VCC whichever is less VM 0V nCP th(H) VM ts(L) th(L) VM 3.0V or VCC whichever is less 0V SH00019 Waveform 3. Data Setup and Hold Times 1998 Feb 27 VOL +0.3V Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level 0V SH00018 ts(H) VM 3.0V or VCC whichever is less VOL VM VM tPLZ VOH nQx nDx, nCE VM 0V 0V tw(L) VM 8 Philips Semiconductors Product specification 18-bit bus-interface D-type flip-flop with reset and enable (3-State) 74ABT16823A 74ABTH16823A TEST CIRCUIT AND WAVEFORM VCC 7.0V VIN RL VOUT PULSE GENERATOR 90% VM CL AMP (V) VM 10% D.U.T. RT tW 90% NEGATIVE PULSE 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V RL AMP (V) 90% 90% Test Circuit for 3-State Outputs POSITIVE PULSE VM VM 10% TEST tPLZ tPZL All other SWITCH closed closed open 10% tW SWITCH POSITION 0V VM = 1.5V Input Pulse Definition DEFINITIONS: RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. INPUT PULSE REQUIREMENTS FAMILY 74ABT16 Amplitude Rep. Rate tw tR tF 3.0V 1MHz 500ns 2.5ns 2.5ns SH00022 1998 Feb 27 9 Philips Semiconductors Product specification 18-bit bus-interface D-type flip-flop with reset and enable (3-State) 74ABT16823A 74ABTH16823A SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm 1998 Feb 27 10 SOT371-1 Philips Semiconductors Product specification 18-bit bus-interface D-type flip-flop with reset and enable (3-State) 74ABT16823A 74ABTH16823A TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm 1998 Feb 27 11 SOT364-1 Philips Semiconductors Product specification 18-bit bus-interface D-type flip-flop with reset and enable (3-State) 74ABT16823A 74ABTH16823A Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 12 Date of release: 05-96 9397-750-03502