MM54C95/MM74C95 4-Bit Right-Shift Left-Shift Register General Description Features This 4-bit shift register is a monolithic complementary MOS (CMOS) integrated circuit composed of four D flip-flops. This register will perform right-shift or left-shift operations dependent upon the logical input level to the mode control. A number of these registers may be connected in series to form an N-bit right-shift or left-shift register. When a logical ‘‘0’’ level is applied to the mode control input, the output of each flip-flop is coupled to the D input of the succeeding flip flop. Right-shift operation is performed by clocking at the clock 1 input, and serial data entered at the serial input, clock 2 and parallel inputs A through D are inhibited. With a logical ‘‘1’’ level applied to the mode control, outputs to succeeding stages are decoupled and parallel loading is possible, or with external interconnection, shiftleft operation can be accomplished by connecting the output of each flip-flop to the parallel input of the previous flip-flop and serial data is entered at input D. Y Y Y Y Y Y Y Y Y Medium speed operation 10 MHz (typ.) VCC e 10V, CL e 50 pF High noise immunity 0.45 VCC (typ.) Low power 100 nW/(typ.) Tenth power TTL compatible Drive 2 LTTL loads Wide supply voltage range 3V to 15V Synchronous parallel load Parallel inputs and outputs from each flip-flop Negative edge triggered clocking The MM54C95/MM74C95 follows the MM54L95/ MM74L95 Pinout Applications Y Y Y Y Data terminals Instrumentation Automotive Medical electronics Y Y Y Y Alarm systems Remote metering Industrial electronics Computers Block and Connection Diagrams TL/F/5890 – 2 TL/F/5890 – 1 Dual-In-Line Package TL/F/5890 – 3 Mode Control e 0 for Right Shift Mode Control e 1 for Left Shift or Parallel Load TL/F/5890 – 4 Order Number MM54C95 or MM74C95 C1995 National Semiconductor Corporation TL/F/5890 RRD-B30M105/Printed in U. S. A. MM54C95/MM74C95 4-Bit Right-Shift Left-Shift Register February 1988 Absolute Maximum Ratings (Note 1) Storage Temperature (TS) Maximum VCC Voltage If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage at any Pin 18V Power Dissipation (PD) Dual-In-Line Small Outline Operating VCC Range b 0.3V to VCC a 0.3V Operating Temperature Range (TA) MM54C95 MM74C95 b 65§ C to a 150§ C b 55§ C to a 125§ C b 40§ C to a 85§ C 700 mW 500 mW a 3V to a 15V Lead Temperature (TL) (Soldering, 10 seconds) 260§ C DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical ‘‘1’’ Input Voltage VCC e 5V VCC e 10V VIN(0) Logical ‘‘0’’ Input Voltage VCC e 5V VCC e 10V VOUT(1) Logical ‘‘1’’ Output Voltage VCC e 5V VCC e 10V VOUT(0) Logical ‘‘0’’ Output Voltage VCC e 5V VCC e 10V IIN(1) Logical ‘‘1’’ Input Current VCC e 15V IIN(0) Logical ‘‘0’’ Input Current VCC e 15V ICC Supply Current VCC e 15V 3.5 8.0 V V 1.5 2.0 4.5 9.0 V V V V 0.5 1.0 V V 1.0 mA b 1.0 mA 0.050 300 mA LOW POWER TTL/CMOS INTERFACE VIN(1) Logical ‘‘1’’ Input Voltage 54C, VCC e 4.5V 74C, VCC e 4.75V VIN(0) Logical ‘‘0’’ Input Voltage 54C, VCC e 4.5V 74C, VCC e 4.75V VOUT(1) Logical ‘‘1’’ Output Voltage 54C, VCC e 4.5V, IO e 360 mA 74C, VCC e 4.75V, IO e 360 mA VOUT(0) Logical ‘‘0’’ Output Voltage 54C, VCC e 4.5V, IO e 360 mA 74C, VCC e 4.75V, IO e 360 mA VCC b 1.5 VCC b 1.5 V V 0.8 0.8 2.4 2.4 V V V V 0.4 0.4 V V OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) ISOURCE Output Source Current VCC e 5V, VIN(0) e 0V TA e 25§ C, VOUT e 0V b 1.75 mA ISOURCE Output Source Current VCC e 10V, VIN(0) e 0V TA e 25§ C, VOUT e 0V b 8.0 mA ISINK Output Sink Current VCC e 5V, VIN(1) e 5V TA e 25§ C, VOUT e VCC 1.75 mA ISINK Output Sink Current VCC e 10V, VIN(1) e 10V TA e 25§ C, VOUT e VCC 8.0 mA Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’, they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. 2 AC Electrical Characteristics* TA e 25§ C, CL e 50 pF, unless otherwise noted Symbol Parameter Conditions Min Typ Max Units 200 80 400 160 ns ns tpd Propagation Delay Time to a Logical ‘‘0’’ or Logical ‘‘1’’ from Clock to Q or Q VCC e 5V VCC e 10V tS0, tS1 Time Prior to Clock Pulse that Data must be Preset VCC e 5V VCC e 10V 60 25 30 10 ns ns tH0, tH1 Time After Clock Pulse that Data must be Held VCC e 5V VCC e 10V 25 10 10 50 ns ns tPW Minimum Clock Pulse Width (tWL e tWH) VCC e 5V VCC e 10V 100 50 ns ns tSM Time Prior to Clock Pulse that Mode Control must be Preset VCC e 5V VCC e 10V 200 100 100 50 ns ns fMAX Maximum Input Clock Frequency VCC e 5V VCC e 10V 3 6.5 5 10 MHz MHz CIN Input Capacitance Any Input (Note 2) 5 pF CPD Power Dissipation Capacitance (Note 3) 100 pF *AC Parameters are guaranteed by DC correlated testing. Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’, they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: Capacitance is guaranteed by periodic testing. Note 3: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 54C/74C Family Characteristics, Application Note AN-90. Function Table Inputs Mode Control H H H L L L u v v u u u v Clocks 2 (L) 1 (R) H X X X H v v L X X L L L H H L H v v L L H L H H L Outputs Parallel Serial X X X X H L X X X X X X X QA A B C D X a QB ² X X X X X X X X X X X b QC ² X X X X X X X X X X X c QD ² X X X X X X X X X X X c d X X X X X X X X X X QB QC QA0 QB0 QC0 a b c QBn QCn QDn QA0 QB0 QC0 H QAn QBn L QAn QBn QA0 QB0 QC0 QA0 QB0 QC0 QA0 QB0 QC0 QA0 QB0 QC0 QA0 QB0 QC0 Undefined Operating Conditions QD QD0 d d QD0 QCn QCn QD0 QD0 QD0 QD0 QD0 ² Shifting left requires external connection of QB to A, QC to B, and QD to C. Serial data is entered at input D. H e high level (steady state), L e low level (steady state), X e irrelevant (any input, including transitions) v e transition from high to low level, u e transition from low to high level. a, b, c, d e the level of steady-state input at inputs A, B, C or D, respectively. QA0, QB0, QC0, QD0 e the level of QA, QB, QC or QD respectively, before the indicated steady-state input conditions were established. QAn, QBn, QCn, QDn e the level of QA, QB, QC or QD respectively, before the most recent transition of the clock. 3 MM54C95/MM74C95 4-Bit Right-Shift Left-Shift Register Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C95J or MM74C95J NS Package Number J14A Molded Dual-In-Line Package (N) Order Number MM54C95N or MM74C95N NS Package Number N14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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