Cypress CY7C4265-10AXI 8k/16k x 18 deep sync fifo Datasheet

CY7C4255, CY7C4265, CY7C4265A
8K/16K x 18 Deep Sync FIFOs
Features
Functional Description
■
High Speed, Low Power, First-In First-Out (FIFO) Memories
❐ 8K x 18 (CY7C4255)
[1]
❐ 16K x 18 (CY7C4265/4265A)
■
0.5 Micron CMOS for Optimum Speed and Power
■
High Speed 100 MHz Operation (10 ns read/write cycle times)
■
Low Power — ICC = 45 mA
■
Fully Asynchronous and Simultaneous Read and Write
Operation
■
Empty, Full, Half Full, and Programmable Almost Empty and
Almost Full Status Flags
■
TTL compatible
■
Retransmit Function
■
Output Enable (OE) Pins
■
Independent Read and Write Enable Pins
■
Center Power and Ground Pins for Reduced Noise
■
Supports Free-running 50 percent Duty Cycle Clock Inputs
■
Width and Depth Expansion Capability
■
64-pin TQFP and 64-pin STQFP
■
Pin-compatible Density Upgrade to CY7C42X5 Family
■
Pin-compatible Density Upgrade to IDT72205/15/25/35/45
■
Pb-free Packages Available
Logic Block Diagram
The CY7C4255/65/65A are high speed, low power, first-in
first-out (FIFO) memories with clocked read and write interfaces.
All are 18 bits wide and are pin/functionally compatible to the
CY7C42X5 Synchronous FIFO family. The CY7C4255/65/65A
can be cascaded to increase FIFO depth. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs, including
high speed data acquisition, multiprocessor interfaces, and communications buffering.
These FIFOs have 18-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free running Clock (WCLK) and a Write Enable
pin (WEN). When WEN is asserted, data is written into the FIFO on the
rising edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled in
a similar manner by a free-running Read Clock (RCLK) and a Read
Enable pin (REN). In addition, the CY7C4255/65/65A have an Output
Enable pin (OE). The read and write clocks may be tied together for
single-clock operation or the two clocks may be run independently for
asynchronous read/write applications. Clock frequencies up to
100 MHz are achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices. Depth expansion is
possible using the Cascade Input (WXI, RXI), Cascade Output
(WXO, RXO), and First Load (FL) pins. The WXO and RXO pins are
connected to the WXI and RXI pins of the next device, and the WXO
and RXO pins of the last device should be connected to the WXI and
RXI pins of the first device. The FL pin of the first device is tied to VSS
and the FL pin of all the remaining devices should be tied to VCC.
D0–17
INPUT
REGISTER
WCLK
WEN
FLAG
PROGRAM
REGISTER
WRITE
CONTROL
FLAG
LOGIC
RAM
ARRAY
8K x 18
16K x 18
WRITE
POINTER
RS
FL/RT
WXI
WXO/HF
RXI
RXO
FF
EF
PAE
PAF
SMODE
READ
POINTER
RESET
LOGIC
EXPANSION
LOGIC
THREE–STATE
OUTPUT REGISTER
READ
CONTROL
OE
Q0–17
RCLK
REN
Note
1. CY7C4265 and CY7C4265A are functionally identical
Cypress Semiconductor Corporation
Document #: 38-06004 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 03, 2009
[+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Pin Configurations
REN
LD
OE
RS
VCC
GND
EF
Q17
Q16
GND
Q15
VCC/SMODE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Q14
Q13
GND
Q12
Q11
VCC
Q10
Q9
GND
Q8
Q7
Q6
Q5
GND
Q4
VCC
Q3
Q0
Q1
GND
Q2
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CY7C4255
CY7C4265/65A
PAE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FL/RT
WCLK
WEN
WXI
VCC
PAF
RXI
FF
WXO/HF
RXO
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
D16
D17
GND
RCLK
Figure 1. 64-Pin TQFP/STQFP (Top View)
Pin Description
(WCLK). When entering or exiting the Empty states, the flag is
updated exclusively by the RCLK. The flag denoting Full states
is updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags remain valid from one clock
cycle to the next. The Almost Empty/Almost Full flags become
synchronous if the VCC/SMODE is tied to VSS. All configurations are fabricated using an advanced 0.5μ CMOS
technology. Input ESD protection is greater than 2001V, and
latch up is prevented by the use of guard rings.
The CY7C4255/65/65A provides five status pins. These pins are
decoded to determine one of five states: Empty, Almost Empty,
Half Full, Almost Full, and Full. The Half Full flag shares the WXO
pin. This flag is valid in the standalone and width-expansion
configurations. In the depth expansion, this pin provides the
expansion out (WXO) information that is used to signal the next
FIFO when it is activated.
The Empty and Full flags are synchronous, that is, they change
state relative to either the Read Clock (RCLK) or the Write Clock
Table 1. Selection Guide
Description
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Active Power Supply
Commercial
Current (ICC1) (mA)
Industrial
7C4255/65-10
100
8
10
3
0.5
8
45
50
7C4255/65/65A-15
66.7
10
15
4
1
10
45
50
7C4255/65-25
40
15
25
6
1
15
45
50
7C4255/65-35
28.6
20
35
7
2
20
45
50
Table 2. Density and Package
Description
CY7C4255
CY7C4265/65A
Density
8K x 18
16K x18
Package
64-pin TQFP, STQFP
64-pin TQFP, STQFP
Document #: 38-06004 Rev. *E
Page 2 of 23
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CY7C4255, CY7C4265, CY7C4265A
Table 3. Pin Definitions
Signal Name
Description
I/O
Function
D0 –17
Data Inputs
I
Q0–17
Data Outputs
O
Data outputs for an 18-bit bus.
WEN
Write Enable
I
Enables the WCLK input.
REN
Read Enable
I
Enables the RCLK input.
WCLK
Write Clock
I
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full.
When LD is asserted, WCLK writes data into the programmable flag-offset register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-offset
register.
WXO/HF
Write Expansion
Out/Half Full Flag
O
Dual-Mode Pin:
Single device or width expansion – Half Full status flag.
Cascaded – Write Expansion Out signal, connected to WXI of next device.
EF
Empty Flag
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF
Full Flag
O
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE
Programmable
Almost Empty
O
When PAE is LOW, the FIFO is almost empty based on the almost-empty offset value
programmed into the FIFO. PAE is asynchronous when VCC/SMODE is tied to VCC; it
is synchronized to RCLK when VCC/SMODE is tied to VSS.
PAF
Programmable
Almost Full
O
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when VCC/SMODE is tied to VCC; it
is synchronized to WCLK when VCC/SMODE is tied to VSS.
LD
Load
I
When LD is LOW, D0–17 (Q0–17) are written (read) into (from) the programmable-flag-offset register.
FL/RT
First Load/
Retransmit
I
Dual-Mode Pin:
Cascaded – The first device in the daisy chain has FL tied to VSS; all other devices
has FL tied to VCC. In standard mode or width expansion, FL is tied to VSS on all
devices.
Not Cascaded – Tied to VSS. Retransmit function is also available in stand-alone mode
by strobing RT.
WXI
Write Expansion
Input
I
Cascaded – Connected to WXO of previous device.
Not Cascaded – Tied to VSS.
RXI
Read Expansion
Input
I
Cascaded – Connected to RXO of previous device.
Not Cascaded – Tied to VSS.
RXO
Read Expansion
Output
O
Cascaded – Connected to RXI of next device.
RS
Reset
I
Resets device to empty condition. A reset is required before an initial read or write
operation after power up.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected.
If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
VCC/SMODE
Synchronous
Almost Empty/
Almost Full Flags
I
Dual-Mode Pin:
Asynchronous Almost Empty/Almost Full flags – tied to VCC.
Synchronous Almost Empty/Almost Full flags – tied to VSS.
(Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.)
Document #: 38-06004 Rev. *E
Data inputs for an 18-bit bus.
Page 3 of 23
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CY7C4255, CY7C4265, CY7C4265A
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.[2]
Output Current into Outputs (LOW)............................. 20 mA
Storage Temperature ................................ –65°C to +150°C
Static Discharge Voltage............................................ >2001V
(per MIL–STD–883, Method 3015)
Ambient Temperature with Power Applied. –55°C to +125°C
Latch Up Current ..................................................... >200 mA
Supply Voltage to Ground Potential................–0.5V to +7.0V
Operating Range
DC Voltage Applied to Outputs
in High Z State ................................................–0.5V to +7.0V
DC Input Voltage ......................................... −0.5V to VCC+0.5V
Ambient
Temperature[3]
VCC
Commercial
0°C to +70°C
5V ± 10%
Industrial[4]
–40°C to +85°C
5V ± 10%
Range
Electrical Characteristics Over the Operating Range[4]
Parameter
Description
Test Conditions
7C42X5-10
7C42X5,
7C4265A-15
7C42X5-25
7C42X5-35
Min
Min
Min
Min
Max
Max
Max
Unit
Max
VOH
Output HIGH Voltage
VCC = Min.,
IOH = –2.0 mA
VOL
Output LOW Voltage
VCC = Min.,
IOL = 8.0 mA
VIH[5]
Input HIGH Voltage
2.0
VCC
2.0
VCC
2.0
VCC
2.0
VCC
V
VIL[5]
Input LOW Voltage
–0.5
0.8
–0.5
0.8
–0.5
0.8
–0.5
0.8
V
IIX
Input Leakage
Current
VCC = Max.
–10
+10
–10
+10
–10
+10
–10
+10
μA
IOZL
IOZH
Output OFF,
High Z Current
OE > VIH,
VSS < VO < VCC
–10
+10
–10
+10
–10
+10
–10
+10
μA
ICC1[6]
Active Power Supply
Current
Commercial
45
45
45
45
mA
Industrial
50
50
50
50
mA
Average Standby
Current
Commercial
10
10
10
10
mA
Industrial
15
15
15
15
mA
ICC2
[7]
2.4
2.4
0.4
2.4
0.4
2.4
V
0.4
0.4
V
Capacitance[8, 9]
Description
Test Conditions
CIN
Parameter
Input Capacitance
COUT
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max
Unit
5
pF
7
pF
Notes
2. The Voltage on any input or I/O pin cannot exceed the power pin during power up.
3. TA is the “Instant On” case temperature.
4. See the last page of this specification for Group A subgroup testing information.
5. The VIH and VIL specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the previous device
or VSS.
6. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs are
unloaded. ICC1(typical) = (25 mA + (freq – 20 MHz) * (1.0 mA/MHz)).
7. All inputs = VCC – 0.2V, except RCLK and WCLK (which are switching at frequency = 20 MHz), and FL/RT which is at VSS. All outputs are unloaded.
8. Tested initially and after any design changes that may affect these parameters.
9. Tested initially and after any process changes that may affect these parameters.
Document #: 38-06004 Rev. *E
Page 4 of 23
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CY7C4255, CY7C4265, CY7C4265A
Figure 2. AC Test Loads and Waveforms[10, 11]
R1 1.1 KΩ
ALL INPUT PULSES
5V
3.0V
OUTPUT
CL
GND
≤ 3 ns
R2
680Ω
INCLUDING
JIG AND
SCOPE
Equivalent to:
90%
10%
90%
10%
≤ 3 ns
THÉVENIN EQUIVALENT
410Ω
OUTPUT
1.91V
Switching Characteristics Over the Operating Range
Parameter
Description
7C42X5-10
7C42X5,
7C4265A-15
7C42X5-25
7C42X5-35
Min
Min
Min
Min
Max
100
Max
Clock Cycle Frequency
tA
Data Access Time
tCLK
Clock Cycle Time
10
15
25
35
ns
tCLKH
Clock HIGH Time
4.5
6
10
14
ns
tCLKL
Clock LOW Time
4.5
6
10
14
ns
tDS
Data Set Up Time
3
4
6
7
ns
tDH
Data Hold Time
0.5
1
1
2
ns
tENS
Enable Set Up Time
3
4
6
7
ns
tENH
Enable Hold Time
8
2
10
40
Max
tS
2
66.7
Max
Unit
2
15
2
28.6
MHz
20
ns
0.5
1
1
2
ns
tRS
Reset Pulse
Width[12]
10
15
25
35
ns
8
tRSR
Reset Recovery Time
tRSF
Reset to Flag and Output Time
tPRT
Retransmit Pulse Width
tRTR
Retransmit Recovery Time
10
10
[12]
15
15
20
25
ns
35
ns
30
35
45
55
ns
60
65
75
85
ns
tOLZ
Output Enable to Output in Low Z
0
tOE
Output Enable to Output Valid
3
7
3
8
3
12
3
15
ns
tOHZ
Output Enable to Output in High Z[13]
3
7
3
8
3
12
3
15
ns
tWFF
Write Clock to Full Flag
20
ns
tREF
Read Clock to Empty Flag
8
10
15
20
ns
tPAFasynch
Clock to Programmable Almost-Full Flag[13]
(Asynchronous mode, VCC/SMODE tied to VCC)
12
16
20
25
ns
tPAFsynch
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to VSS)
8
10
15
20
ns
tPAEasynch
Clock to Programmable Almost-Empty Flag[14]
(Asynchronous mode, VCC/SMODE tied to VCC)
12
16
20
25
ns
tPAEsynch
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to VSS)
8
10
15
20
ns
tHF
Clock to Half-Full Flag
12
16
20
25
ns
tXO
Clock to Expansion Out
6
10
15
20
ns
Document #: 38-06004 Rev. *E
0
8
0
10
0
15
ns
Page 5 of 23
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CY7C4255, CY7C4265, CY7C4265A
Switching Characteristics Over the Operating Range (continued)
Parameter
Description
7C42X5-10
7C42X5,
7C4265A-15
7C42X5-25
7C42X5-35
Min
Min
Min
Min
Max
Max
Max
Unit
Max
tXI
Expansion in Pulse Width
4.5
6.5
10
14
ns
tXIS
Expansion in Set-Up Time
4
5
10
15
ns
tSKEW1
Skew Time between Read Clock and Write Clock
for Full Flag
5
6
10
12
ns
tSKEW2
Skew Time between Read Clock and Write Clock
for Empty Flag
5
6
10
12
ns
tSKEW3
Skew Time between Read Clock and Write Clock
for Programmable Almost Empty and Programmable Almost Full Flags (Synchronous Mode
only)
10
15
18
20
ns
Notes
10. CL = 30 pF for all AC parameters except for tOHZ.
11. CL = 5 pF for tOHZ.
12. Pulse widths less than minimum values are not enabled.
13. Values guaranteed by design, not currently tested.
14. tPAFasynch, tPAEasynch, after program register write is not be valid until 5 ns + tPAF(E).
Document #: 38-06004 Rev. *E
Page 6 of 23
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CY7C4255, CY7C4265, CY7C4265A
Switching Waveforms
Figure 3. Write Cycle Timing
tCLK
tCLKH
tCLKL
WCLK
tDS
tDH
D0 –D17
tENS
tENH
WEN
NO OPERATION
tWFF
tWFF
FF
tSKEW1 [15]
RCLK
REN
Figure 4. Read Cycle Timing
tCLK
tCLKH
tCLKL
RCLK
tENS
tENH
REN
NO OPERATION
tREF
tREF
EF
tA
Q0 –Q17
VALID DATA
tOLZ
tOHZ
tOE
OE
tSKEW2[16]
WCLK
WEN
Notes
15. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF goes HIGH during the current clock cycle. If the time
between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.
16. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF goes HIGH during the current clock cycle. It the time
between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge.
Document #: 38-06004 Rev. *E
Page 7 of 23
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CY7C4255, CY7C4265, CY7C4265A
Switching Waveforms (continued)
Figure 5. Reset Timing[17]
tRS
RS
tRSR
REN, WEN,
LD
tRSF
EF,PAE
tRSF
FF,PAF,
HF
tRSF
[18]
OE = 1
Q0–Q17
OE = 0
Figure 6. First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
tDS
D0 –D17
D0 (FIRSTVALID WRITE)
D1
tENS
D2
D3
D4
[19]
tFRL
WEN
tSKEW2
RCLK
tREF
EF
REN
tA
Q0 –Q17
tA
D0
tOLZ
[20]
D1
tOE
OE
Notes
17. The clocks (RCLK, WCLK) can be free-running during reset.
18. After reset, the outputs are LOW if OE = 0 and three-state if OE = 1.
19. When tSKEW2 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or
tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW).
20. The first word is available the cycle after EF goes HIGH, always.
Document #: 38-06004 Rev. *E
Page 8 of 23
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CY7C4255, CY7C4265, CY7C4265A
Switching Waveforms (continued)
Figure 7. Empty Flag Timing
WCLK
tDS
tDS
D0
D0 –D17
D1
tENH
tENS
tENH
tENS
WEN
tFRL[19]
[19]
tFRL
RCLK
tREF
tSKEW2
tREF
tREF
tSKEW2
EF
REN
OE
tA
D0
Q0 –Q17
Figure 8. Full Flag Timing
NO WRITE
NO WRITE
WCLK
tSKEW1
[15]
tDS
tSKEW1 [15]
DATA WRITE
DATA WRITE
D0 –D17
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENS
tENH
tENS
tENH
REN
OE
LOW
tA
Q0 –Q17
DATA IN OUTPUT REGISTER
Document #: 38-06004 Rev. *E
tA
DATA READ
NEXT DATA READ
Page 9 of 23
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CY7C4255, CY7C4265, CY7C4265A
Switching Waveforms (continued)
Figure 9. Half-Full Flag Timing
tCLKH
tCLKL
WCLK
tENS tENH
WEN
tHF
HF
HALF FULL + 1
OR MORE
HALF FULL OR LESS
HALF FULLOR LESS
tHF
RCLK
tENS
REN
Figure 10. Programmable Almost Empty Flag Timing
tCLKH
tCLKL
WCLK
tENS tENH
WEN
tPAE
PAE [21]
N + 1 WORDS
IN FIFO
tPAE
n WORDS IN FIFO
RCLK
tENS
REN
Note
21. PAE is offset = n. Number of data words into FIFO already = n.
Document #: 38-06004 Rev. *E
Page 10 of 23
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CY7C4255, CY7C4265, CY7C4265A
Switching Waveforms (continued)
Figure 11. Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW))
tCLKL
tCLKH
WCLK
tENS tENH
WEN
WEN2
tENS tENH
PAE
tSKEW3
Note
22
[23]
N + 1 WORDS
INFIFO
tPAE synch
Note
24
tPAE synch
RCLK
tENS
tENS tENH
REN
Figure 12. Programmable Almost Full Flag Timing
tCLKL
tCLKH
WCLK
Note 25
tENS tENH
WEN
tPAF
PAF
FULL– M WORDS
[27]
INFIFO
[26]
tPAF
FULL– (M+1) WORDS
[28]
IN FIFO
RCLK
tENS
REN
Notes
22. PAE offset − n.
23. tSKEW3 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of
WCLK and the rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK.
24. If a read is preformed on this rising edge of the read clock, there are Empty + (n−1) words in the FIFO when PAE goes LOW.
25. PAF offset = m. Number of data words written into FIFO already = 8192 − (m + 1) for the CY7C4255 and 16384 − (m + 1) for the CY7C4265/65A.
26. PAF is offset = m.
27. 8192 − m words in CY7C4255 and 16384 – m words in CY7C4265/65A.
28. 8192 − (m + 1) words in CY7C4255 and 16384 – (m + 1) CY7C4265/65A.
Document #: 38-06004 Rev. *E
Page 11 of 23
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CY7C4255, CY7C4265, CY7C4265A
Switching Waveforms (continued)
Figure 13. Programmable Almost Full Flag Timing (applies only in SMODE (SMODE is LOW))
Note 29
tCLKL
tCLKH
WCLK
tENS tENH
WEN
Note
30
WEN2
tPAF
tENS tENH
PAF
FULL– M [27]
WORDS
IN FIFO
FULL– M + 1 WORDS
IN FIFO
tSKEW3[31]
tPAF synch
RCLK
tENS
tENS tENH
REN
Figure 14. Write Programmable Registers
tCLK
tCLKL
tCLKH
WCLK
tENS
tENH
LD
tENS
WEN
tDS
tDH
PAE OFFSET
D0 –D17
PAE OFFSET
PAF OFFSET
D0 – D11
Notes
29. If a write is performed on this rising edge of the write clock, there are Full − (m − 1) words of the FIFO when PAF goes LOW.
30. PAF offset = m.
31. tSKEW3 is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of
RCLK and the rising edge of WCLK is less than tSKEW3, then PAF may not change state until the next WCLK rising edge.
Document #: 38-06004 Rev. *E
Page 12 of 23
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CY7C4255, CY7C4265, CY7C4265A
Switching Waveforms (continued)
Figure 15. Read Programmable Registers
tCLK
tCLKL
tCLKH
RCLK
tENS
tENH
LD
tENS
WEN
tA
UNKNOWN
Q0 –Q17
PAE OFFSET
PAF OFFSET
PAE OFFSET
Figure 16. Write Expansion Out Timing
tCLKH
WCLK
Note 32
tXO
Note 32
WXO
tXO
tENS
WEN
Figure 17. Read Expansion Out Timing
tCLKH
WCLK
Note 33
tXO
RXO
tXO
tENS
REN
Figure 18. Write Expansion In Timing
tXI
WXI
WCLK
tXIS
Notes
32. Write to Last Physical Location.
33. Read from Last Physical Location.
Document #: 38-06004 Rev. *E
Page 13 of 23
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CY7C4255, CY7C4265, CY7C4265A
Switching Waveforms (continued)
Figure 19. Read Expansion In Timing
tXI
RXI
tXIS
RCLK
Figure 20. Retransmit Timing[34, 35, 36]
FL/RT
tPRT
tRTR
REN/WEN
EF/FF
and all
async flags
HF/PAE/PAF
Notes
34. Clocks are free-running in this case.
35. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags are valid at tRTR.
36. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after tRTR to update these flags.
Document #: 38-06004 Rev. *E
Page 14 of 23
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CY7C4255, CY7C4265, CY7C4265A
Architecture
read/write operation. When the LD pin is set LOW, and WEN is
LOW, the next offset register in sequence is written.
The CY7C4256/65 consists of an array of 8K/16K words of 18
bits each (implemented by a dual-port array of SRAM cells), a
read pointer, a write pointer, control signals (RCLK, WCLK, REN,
WEN, RS), and flags (EF, PAE, HF, PAF, FF). The
CY7C4255/65/65A also includes the control signals WXI, RXI,
WXO, RXO for depth expansion.
The contents of the offset registers can be read on the output
lines when the LD pin is set LOW and REN is set LOW; then,
data can be read on the LOW-to-HIGH transition of the Read
Clock (RCLK).
Resetting the FIFO
Upon power up, the FIFO must be reset with a Reset (RS) cycle.
This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs go LOW after the falling edge of
RS only if OE is asserted. For the FIFO to reset to its default
state, a falling edge must occur on RS and the user must not read
or write while RS is LOW.
FIFO Operation
When the WEN signal is active (LOW), data present on the D0–17
pins is written into the FIFO on each rising edge of the WCLK
signal. Similarly, when the REN signal is active LOW, data in the
FIFO memory are presented on the Q0–17 outputs. New data is
presented on each rising edge of RCLK while REN is active LOW
and OE is LOW. REN must set up tENS before RCLK for it to be
a valid read function. WEN must occur tENS before WCLK for it
to be a valid write function.
An output enable (OE) pin is provided to three-state the Q0–17
outputs when OE is deasserted. When OE is enabled (LOW),
data in the output register is available to the Q0–17 outputs after
tOE. If devices are cascaded, the OE function only outputs data
on the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional writes
when the FIFO is full, and under flow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0–17 outputs even
after additional reads occur.
Programming
The CY7C4255/65/65A devices contain two 14-bit offset
registers. Data present on D0–13 during a program write determines the distance from Empty (Full) that the Almost Empty
(Almost Full) flags become active. If the user elects not to
program the FIFO’s flags, the default offset values are used (see
Table 4). When the Load LD pin is set LOW and WEN is set
LOW, data on the inputs D0–13 is written into the Empty offset
register on the first LOW-to-HIGH transition of the Write Clock
(WCLK). When the LD pin and WEN are held LOW then data is
written into the Full offset register on the second LOW-to-HIGH
transition of the Write Clock (WCLK). The third transition of the
Write Clock (WCLK) again writes to the Empty offset register
(see Table 4). Writing all offset registers does not have to occur
at one time. One or two offset registers can be written and then,
by bringing the LD pin HIGH, the FIFO is returned to normal
Table 4. Write Offset Register
WCLK[37]
LD
WEN
0
0
Writing to offset registers:
Empty Offset
Full Offset
Selection
0
1
No Operation
1
0
Write Into FIFO
1
1
No Operation
Flag Operation
The CY7C4255/65/65A devices provide five flag pins to indicate
the condition of the FIFO contents. Empty and Full are
synchronous. PAE and PAF are synchronous if VCC/SMODE is
tied to VSS.
Full Flag
The Full Flag (FF) goes LOW when device is Full. Write operations are inhibited whenever FF is LOW regardless of the state
of WEN. FF is synchronized to WCLK: it is exclusively updated
by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) goes LOW when the device is empty. Read
operations are inhibited whenever EF is LOW, regardless of the
state of REN. EF is synchronized to RCLK, i.e., it is exclusively
updated by each rising edge of RCLK.
Programmable Almost Empty/Almost Full Flag
The CY7C4255/65/65A features programmable Almost Empty
and Almost Full Flags. Each flag can be programmed (described
in the Programming section) a specific distance from the corresponding boundary flags (Empty or Full). When the FIFO
contains the number of words or fewer for which the flags have
been programmed, the PAF or PAE are asserted, signifying that
the FIFO is either Almost Full or Almost Empty. See Table 5 on
page 16 for a description of programmable flags.
When the SMODE pin is tied LOW, the PAF flag signal transition
is caused by the rising edge of the write clock and the PAE flag
transition is caused by the rising edge of the read clock.
Note
37. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK.
Document #: 38-06004 Rev. *E
Page 15 of 23
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CY7C4255, CY7C4265, CY7C4265A
Retransmit
The retransmit feature is beneficial when transferring packets of
data. It enables the receipt of data to be acknowledged by the
receiver and retransmitted if necessary.
The Retransmit (RT) input is active in the stand-alone and width
expansion modes. The retransmit feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred and at least one word has been read since
the last RS cycle. A HIGH pulse on RT resets the internal read
pointer to the first physical location of the FIFO. WCLK and
RCLK may be free running but must be disabled during and tRTR
after the retransmit pulse. With every valid read cycle after
retransmit, previously accessed data is read and the read pointer
is incremented until it is equal to the write pointer. Flags are
governed by the relative locations of the read and write pointers
and are updated during a retransmit cycle. Data written to the
FIFO after activation of RT are transmitted also.
The full depth of the FIFO can be repeatedly retransmitted.
Table 5. Flag Truth Table
Number of Words in FIFO
CY7C4255 – 8K x 18
CY7C4265/65A – 16K x 18
FF
PAF
HF
PAE
EF
0
0
H
H
H
L
L
1 to n[38]
1 to n[38]
H
H
H
L
H
(n + 1) to 4096
(n + 1) to 8192
H
H
H
H
H
4097 to (8192 – (m + 1))
8193 to (16384 – (m + 1))
H
H
L
H
H
m)[39]
H
L
L
H
H
L
L
L
H
H
(8192 –
m)[39]
to 8191
8192
(16384 –
to 16383
16384
Notes
38. n = Empty Offset (Default Values: CY7C4255/CY7C4265/65A n = 127).
39. m = Full Offset (Default Values: CY7C4255/CY7C4265/65A n = 127).
Document #: 38-06004 Rev. *E
Page 16 of 23
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CY7C4255, CY7C4265, CY7C4265A
Width Expansion Configuration
The CY7C4255/65/65A can be expanded in width to provide word widths greater than 18 in increments of 18. During width expansion
mode all control line inputs are common and all flags are available. Empty (Full) flags should be created by ANDing the Empty (Full)
flags of every FIFO; the PAE and PAF flags can be detected from any one device. This technique avoids reading data from, or writing
data to the FIFO that is “staggered” by one clock cycle due to the variations in skew between RCLK and WCLK. Figure 21 demonstrates a 36-word width by using two CY7C4255/65/65As.
Figure 21. Block Diagram of 8K x18/16K x 18 Synchronous FIFO Memory Used in a Width Expansion Configuration
RESET (RS)
DATA IN (D) 36
RESET (RS)
18
18
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
READ ENABLE (REN)
WRITE ENABLE (WEN)
OUTPUT ENABLE (OE)
LOAD (LD)
PROGRAMMABLE(PAE)
7C4255
7C4265
7C4255
7C4265
HALF FULL FLAG (HF)
PROGRAMMABLE (PAF)
EMPTY FLAG (EF)
FF
FF
EF
EF
18
FULL FLAG (FF)
DATA OUT (Q)
36
18
FIRST LOAD (FL)
WRITE EXPANSION IN (WXI)
READ EXPANSION IN (RXI)
Depth Expansion Configuration
(with Programmable Flags)
The CY7C4255/65/65A can easily be adapted to applications requiring more than 8192/16384 words of buffering. Figure 22 shows
Depth Expansion using three CY7C42X5s. Maximum depth is limited only by signal loading. Follow these steps:
1. The first device must be designated by grounding the First Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device must be tied to the Write Expansion In (WXI) pin of the next device.
4. The Read Expansion Out (RXO) pin of each device must be tied to the Read Expansion In (RXI) pin of the next device.
5. All Load (LD) pins are tied together.
6. The Half-Full Flag (HF) is not available in the Depth Expansion Configuration.
7. EF, FF, PAE, and PAF are created with composite flags by ORing together these respective flags for monitoring. The composite
PAE and PAF flags are not precise.
Document #: 38-06004 Rev. *E
Page 17 of 23
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CY7C4255, CY7C4265, CY7C4265A
Figure 22. Block Diagram of 8Kx18/16Kx18 Synchronous FIFO Memory with Programmable Flags used in Depth Expansion
Configuration
WXO RXO
7C4255
7C4265
VCC
FL
FF
EF
PAE
PAF
WXI RXI
WXO RXO
7C4255
7C4265
DATA IN(D)
DATA OUT (Q)
VCC
FL
FF
EF
PAF
PAE
WXI RXI
WRITE CLOCK(WCLK)
WXO RXO
WRITE ENABLE(WEN)
READ ENABLE(REN)
7C4255
7C4265
RESET (RS)
READ CLOCK(RCLK)
OUTPUT ENABLE(OE)
LOAD (LD)
FF
FF
PAF
EF
EF
PAFWXI RXI PAE
PAE
FIRST LOAD (FL)
Document #: 38-06004 Rev. *E
Page 18 of 23
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CY7C4255, CY7C4265, CY7C4265A
Figure 23. Typical AC and DC Characteristics
NORMALIZED tA vs. AMBIENT
TEMPERATURE
NORMALIZED tA vs. SUPPLY
VOLTAGE
1.60
NORMALIZED tA
NORMALIZED tA
1.20
1.10
1.00
0.90
TA = 25°C
0.80
4.00
4.50
5.00
5.50
6.00
1.40
1.20
1.00
0.60
−55.00
1.00
VIN = 3.0V
TA = 25°C
f = 28 MHz
0.80
4.50
5.00
5.50
SUPPLY VOLTAGE (V)
Document #: 38-06004 Rev. *E
6.00
125.00
1.75
NORMALIZED ICC
NORMALIZED ICC
NORMALIZED ICC
1.20
1.20
65.00
NORMALIZED SUPPLY CURRENT
vs. FREQUENCY
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
1.40
0.60
4.00
5.00
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
VCC = 5.0V
0.80
1.10
1.00
VIN = 3.0V
VCC = 5.0V
f = 28 MHz
0.90
0.80
−55.00
5.00
65.00
125.00
AMBIENT TEMPERATURE (°C)
1.50
1.25
1.00
VCC = 5.0V
TA = 25°C
VIN = 3.0V
0.75
0.50
20.00
30.00
40.00
50.00 60.00
FREQUENCY (MHz)
Page 19 of 23
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CY7C4255, CY7C4265, CY7C4265A
Ordering Information
8Kx18 Deep Sync FIFO
Speed
(ns)
10
15
Ordering Code
CY7C4255–10AC
Package
Name
51-85046
Package
Type
64-Pin Thin Quad Flatpack
CY7C4255–10AXC
51-85046
64-Pin Thin Quad Flatpack (Pb-free)
CY7C4255–10ASC
51-85051
64-Pin Small Thin Quad Flatpack
CY7C4255–15AC
51-85046
64-Pin Thin Quad Flatpack
CY7C4255–15AXC
51-85046
64-Pin Thin Quad Flatpack (Pb-free)
Operating
Range
Commercial
Commercial
16Kx18 Deep Sync FIFO
Speed
(ns)
10
15
Ordering Code
Package
Diagram
Package
Type
CY7C4265–10AC
51-85046
64-Pin Thin Quad Flatpack
CY7C4265–10ASC
51-85051
64-Pin Small Thin Quad Flatpack
CY7C4265–10ASXC
51-85051
64-Pin Small Thin Quad Flatpack (Pb-free)
CY7C4265–10AI
51-85046
64-Pin Thin Quad Flatpack
CY7C4265–10AXI
51-85046
64-Pin Thin Quad Flatpack (Pb-free)
CY7C4265–15AC
51-85046
64-Pin Thin Quad Flatpack
CY7C4265–15AXC
51-85046
64-Pin Thin Quad Flatpack (Pb-free)
CY7C4265-15ASC
51-85051
64-Pin Small Thin Quad Flatpack
CY7C4265A–15ASI
51-85051
64-Pin Small Thin Quad Flatpack
Document #: 38-06004 Rev. *E
Operating
Range
Commercial
Industrial
Commercial
Industrial
Page 20 of 23
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CY7C4255, CY7C4265, CY7C4265A
Package Diagrams
Figure 24. 64-Pin Thin Plastic Quad Flat Pack (10 x 10 x 1.4 mm), 51-85051
51-85051 *A
Document #: 38-06004 Rev. *E
Page 21 of 23
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CY7C4255, CY7C4265, CY7C4265A
Package Diagrams (continued)
Figure 25. 64-Pin Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm), 51-85046
51-85046-*B
51-85046-*B
Document #: 38-06004 Rev. *E
Page 22 of 23
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CY7C4255, CY7C4265, CY7C4265A
Document History Page
Document Title: CY7C4255, CY7C4265, CY7C4265A 8K/16K X 18 Deep Sync FIFOs
Document Number: 38-06004
ECN NO.
Orig. of
Change
**
106465
SZV
*A
122257
*B
252889
*C
385985
*D
*E
REV.
Submission
Date
Description of Change
07/11/01
Change from Spec Number: 38-00468 to 38-06004
RBI
12/26/02
Power up requirements added to Maximum Ratings Information
YDT
See ECN
Removed PLCC package and pruned parts from Order Information
ESH
See ECN
Added Pb-Free logo to top of first page
Added CY7C4265-10ASXC, CY7C4265-10AXI, CY7C4265-15AXC,
CY7C4255-10AXC, CY7C4255-15AXC to ordering information
2623658
VKN/PYRS
12/17/08
Added CY7C4265A part
Updated Ordering information table
2714768
VKN/AESA
06/04/2009
Corrected defective Logic Block diagram, Pinouts, and Package diagrams
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
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Document #: 38-06004 Rev. *E
Revised June 03, 2009
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