Revised January 2005 MM74HCT05 Hex Inverter (Open Drain) General Description Features The MM74HCT05 is a logic function fabricated by using advanced silicon-gate CMOS technology, which provides the inherent benefits of CMOS—low quiescent power and wide power supply range. The device is also input and output characteristic and pinout compatible with standard DM74LS logic families. The MM74HCT05 open drain Hex Inverter requires the addition of an external resistor to perform a wire-NOR function. ■ Open drain for wire-NOR function ■ LS-TTL pinout and threshold compatible ■ Fanout of 10 LS-TTL loads ■ Typical propagation delays: tPZL (with 1 kΩ resistor) 10 ns tPLZ (with 1 kΩ resistor) 8 ns All inputs are protected from static discharge damage by internal diodes to VCC and ground. MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug-in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs. Ordering Code: Order Number MM74HCT05M MM74HCT05SJ MM74HCT05MTC MM74HCT05N Package Number Package Description M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC14 N14A 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Logic Diagram Typical Application Top View © 2005 Fairchild Semiconductor Corporation DS005358 www.fairchildsemi.com MM74HCT05 Hex Inverter (Open Drain) February 1984 MM74HCT05 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) −0.5 to +7.0V −1.5 to VCC +1.5V −0.5 to +7.0V Clamp Diode Current (IIK, IOK) ± 20 mA DC Output Current, per pin (IOUT) + 25 mA Storage Temperature Range (TSTG) Max 4.5 5.5 V DC Input Voltage (VIN) 0 VCC V Output Voltage (VOUT) Operating Temperature Range (TA) ± 50 mA DC VCC or GND Current, per pin (ICC) Min Supply Voltage (VCC) 600 mW 500 mW 5.5 V +85 °C 500 ns (tr, tf) Power Dissipation (PD) S.O. Package only 0 −40 Input Rise or Fall Times −65°C to +150°C (Note 3) Units Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. Lead Temperature (TL) 260°C (Soldering 10 seconds) DC Electrical Characteristics (VCC = 5V ± 10%,unless otherwise specified) Symbol Parameter Conditions TA = 25°C Typ TA = −40 to 85°C Guaranteed Limits Units VIH Minimum HIGH Level Input Voltage 2.0 2.0 V VIL Maximum LOW Level Input Voltage 0.8 0.8 V VOL IIN Maximum LOW VIN = VIH Level Voltage |IOUT| = 20 µA Maximum Input Current 0 0.1 0.1 |IOUT| = 4.0 mA, VCC = 4.5V 0.2 0.26 0.33 |IOUT| = 4.8 mA, VCC = 5.5V 0.2 0.26 0.33 ± 0.1 ± 1.0 µA 0.5 5.0 µA 2.0 20 µA 0.3 0.4 mA 10 µA VIN = VCC or GND, VIH or VIL ILKG ICC Maximum HIGH Level VIN = VIH or VIL, Output Leakage Current VOUT = VCC Maximum Quiescent VIN = VCC or GND Supply Current IOUT = 0µA VIN = 2.4V or 0.5V (Note 4) IOHZ Off State Current VCC = 4.5 - 5.5, VO = 5.5 Note 4: This is measured per input with all other inputs held at VCC or ground. www.fairchildsemi.com 2 V VCC = 5V, TA = 25°C,CL = 15 pF, tr = tf = 6 ns unless otherwise noted. Symbol Parameter Conditions Typ Guaranteed Limit Units tPZL Maximum Propagation Delay RL = 1 kΩ 8 15 ns tPLZ Maximum Propagation Delay RL = 1 kΩ 9 16 ns AC Electrical Characteristics VCC = 5V, ± 10%, CL = 50pF, tr = tf = 6 ns unless otherwise specified. Symbol Parameter Conditions TA=25°C Typ TA = −40 to 85°C Guaranteed Limits Units tPZL Maximum Propagation Delay RL = 1kΩ 10 22 28 ns tPLZ Maximum Propagation Delay RL = 1 kΩ 12 20 25 ns tTHL Maximum Output Fall Time 10 15 19 CPD Power Dissipation Capacitance (per gate) (Note 5) RL = ∞ CIN 20 Maximum Input Capacitance 5 ns pF 10 pF Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f+ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. 3 www.fairchildsemi.com MM74HCT05 AC Electrical Characteristics MM74HCT05 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A www.fairchildsemi.com 4 MM74HCT05 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5 www.fairchildsemi.com MM74HCT05 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 www.fairchildsemi.com 6 MM74HCT05 Hex Inverter (Open Drain) Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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