MITSUBISHI <Standard Linear IC> M62353AGP 8BIT 8CH D-A CONVERTER WITH BUFFER AMPLIFIERS DESCRIPTION M62353A is a CMOS structured semiconductor integrated ciruict integrating 8 channels of built-in D-A converters with high performance buffer operational amplifier for each channel output. Pin configuration(Top View) 3-wire serial interface (DI,CLK,LD) method is used for the taransfer format of digital data to allow connection with microcomputer with minimum wiring Vss (VrefL) Do terminal is provided to allow cascading serial use. 1 16 GND Built-in buffer operational amplifiers are designed to operate or full-swing in the AO2 2 15 AO1 whole voltage range from Vcc to GND for each input/output. And their higher stability AO3 3 14 DI for capacitive load perfectly fits in to the use for electronic volume (VCA) AO4 4 13 CLK or the replacement for semi-variable resistor for tuning. AO5 5 12 LD AO6 6 11 DO AO7 7 10 AO8 VDD (VrefU) 8 9 Vcc FEATURES 12 bit serial data input (3 wire serial data transfer method, DI, CLK, LD) Corresponds to TTL input for digital input (VINH ≥ 2V, VINL≤ 0.8V) R-2R+ segment method high performance 8 channel 8 bit D-A converters 8ch buffer operational amplifiers opperating in the whole voltage range from Vcc to Outline 16P2E-A GND Buffer operational amplifiers with high oscillation stability for capacitive load APPLICATION Adjustment or control of industrial or home-use electronic equipments such as VTR camera, VTR set, TV, and CRT display. GND AO1 16 15 DI CLK LD DO 14 13 12 11 D0 1 2 3 4 5 6 D7 D8 9 10 D11 AO8 VCC 10 9 8 8bit R-2R+ segment D-A converter D-A Ch1 (8) L ..... ..... (8) (8) L 3 Ch2 8bit R-2R+ segment D-A converter L 4 D-A (8) D-A L L 5 6 D-A L 7 D-A D-A Buffer Amp. 1 Vss (VrefL) 2 3 4 5 6 7 AO2 AO3 AO4 AO5 AO6 AO7 ( 1 / 6) 8 VDD (VrefU) 0107 MITSUBISHI <Standard Linear IC> M62353AGP 8BIT 8CH D-A CONVERTER WITH BUFFER AMPLIFIERS EXPLANATION OF TERMINALS Pin No. symbol Function 14 DI Serial data input terminal. 12bit serial data is input to this terminal. 11 DO Serial data output terminal. Serial data of 12bit shift register is output from this terminal. 13 CLK Serial clock input terminal.Input signal from DI terminal is input to 12bit shift register upon the rise 12 LD Data is loaded to register when 'H' is input to LD terminal. 15 AO1 AO2 2 3 AO3 AO4 4 5 8bit D-A converter output terminal. Built-in buffer amp.is connected to VCC. D-A converted voltage between VDD and VSS is output to each terminal. AO5 AO6 AO7 AO8 V CC GND V DD V SS 6 7 10 9 16 8 1 Power supply terminal. Digital and Analog common GND D-A converter High level reference voltage input terminal. D-A converter Low level reference voltage input terminal. BLOCK DIAGRAM FOR EXPLANATION OF TERMINALS V CC GND 9 DI CLK 16 14 12 BIT SHIFT REGISTER 13 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 DECODER (8) (8) D0 D7 DO 12 LD 7 8 D7 8bit Latch 8bit R-2R + segment D-A converter 8bit R-2R + segment D-A converter A1 V DD 4 5 6 D0 8bit Latch 8 1 2 3 11 D11 A8 15 AO1 ( 2 / 6) 10 1 AO8 V SS 0107 MITSUBISHI <Standard Linear IC> M62353AGP 8BIT 8CH D-A CONVERTER WITH BUFFER AMPLIFIERS DIGITAL DATA FORMAT Last LSB First MSB D0 D1 D2 D3 D4 DAC DATA D5 D6 D7 D8 D9 D10 D11 DAC SELECT DATA DAC DATA D0 D1 D2 D3 D4 D5 D6 D7 D-A output 0 0 0 0 0 0 0 0 (VrefU-VrefL)/256x1+VrefL[V] (1LSB) 1 0 0 0 0 0 0 0 (VrefU-VrefL)/256x2+VrefL[V] (2LSB) 0 1 0 0 0 0 0 0 (VrefU-VrefL)/256x3+VrefL[V] (3LSB) 1 1 0 0 0 0 1 0 (VrefU-VrefL)/256x4+VrefL[V] (3LSB) : : : : : : : 0 1 1 1 1 1 1 1 (VrefU-VrefL)/256x255+VrefL[V] (255LSB) 1 1 1 1 1 1 1 1 VrefU[V] (256LSB) : : VrefU=VDD VrefL=VSS DAC SELECT DATA D8 D9 D10 D11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DAC SELECTION Don't Care A01select A02select A03select A04select A05select A06select A07select A08select Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care TIMING CHART (model) CLK SI D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LD AO1~ AO8 ( 3 / 6) 0107 MITSUBISHI <Standard Linear IC> M62353AGP 8BIT 8CH D-A CONVERTER WITH BUFFER AMPLIFIERS ABSOLUTE MAXMUM RATING Parameter Symbol Conditions Supply voltage Vcc VDD V IN D-A converter High levelreference voltage Ratings Unit - 0.3 ~ 7.0 V - 0.3 ~ 7.0 V Digital input voltage - 0.3 ~ V CC +0.3 V Vout Output voltage - 0.3 ~ V CC +0.3 V Pd Topr Power dissipation Operating temperature - 20 ~ 85 mW °C Tstg Storage temperature - 40 ~ 125 °C 150 ELECTRIC CHARACTERISTICS <Digital part> (VCC, VrefU=5V ± 10% , VCC ≥ VrefU, GND, VrefL=0.0V, Ta=-20 ~ + 85 ºC unless otherwise specified.) Symbol Parameter Ratings Conditions Vcc Supply voltage Icc Supply current CLK=1MHz Operation IILK Input leak current VIN =0 ~ V CC VIL VIH Digital input Low voltage 4.5 V CC =5V, IAO =0 A Digital output Low voltage Digital output High voltage MAX 5.0 5.5 V 1.0 2.5 mA 10 A -10 2.0 V V IOL = 2.5mA IOH = - 400 A Unit TYP 0.8 Digital input High voltage VOL VOH MIN 0.4 VCC-0.4 V V Note2: Typical value is for Ta=25ºC Note3: Changes from M62353GP: Digital input voltage corresponds to TTL spec. <Analog Part> Symbol IrefU VDD (V refU ) VSS (V refL ) (VCC, VrefU=5V ± 10% , VCC ≥ VrefU, GND, VrefL=0.0V, Ta=-20 ~ + 85 ºC unless otherwise specified.) Parameter Reference voltage pin current D-A converter High level reference voltage range D-A converter Low level reference voltage range VAO IAO Buffer amplifier output drive range Buffer amplifier output drive range SDL SL Szero SFULL Co Ro Differential nonlinearity Nonlinearity Zero code error Full scale error Conditions Ratings MIN TYP MAX Unit VrefU =5V,VrefL =0V,IAO =0 A 0.9 Data condition: at Maxmum Current The output does not necessarily be the Values within the reference voltage setting range.The output value is determined by the buffer amplifier output voltage range(VAO). IAO = ± 100 A IAO = ± 500 A Upper side saturation voltage=0.3V Lower side saturation voltage=0.2V VrefU = 4.79V VrefL = 0.95V (15mV/LSB) VCC = 5.5V without load(I AO =+0 A) 1.7 3.5 VCC GND VCC - 3.5 0.1 VCC -0.1 0.2 VCC -0.2 V 1 -1.0 1.0 LSB -1.5 1.5 LSB -2.0 2.0 LSB -2.0 2.0 LSB F 0.1 5 ( 4 / 6) V -1 Output capacitative load Buffer Amp. output impedance mA mA ohm 0107 MITSUBISHI <Standard Linear IC> M62353AGP 8BIT 8CH D-A CONVERTER WITH BUFFER AMPLIFIERS (VCC, VrefU=5V ± 10% , VCC ≥ VrefU, GND, VrefL=0.0V, Ta=-20 ~ + 85 ºC unless otherwise specified.) <AC characteristics> Symbol Ratings Parameter Conditions MIN TYP MAX Unit tCKL Clock "L" pulse width 200 ns tCKH Clock "H" pulse width 200 ns tCR tCF Clock rise time Clock fall time tDCH Data setup time 30 ns tCHD Data hold time 60 ns tCHL LD setup time 200 ns tLDC LD hold time ns tLDH LD "H"hold time 100 100 tDO Data output delay time tLDD D-A output settling time 200 CL ≤ 100pF ns 70 CL ≤ 100pF,VAO:0.5 ns 350 4.5V 300 The time until the output becomes the final value of 1/2 LSB ns s Measurement circuit DUT input output CL <100pF = TIMING CHART tCR tCKH tCF tCHL CLK tCKL tLDC DI tDCH tLDH tCHD tCHL LD tLDD AO1 ~ AO8 output t DO tDO DO output ( 5 / 6) 0107 MITSUBISHI <Standard Linear IC> M62353AGP 8BIT 8CH D-A CONVERTER WITH BUFFER AMPLIFIERS TYPICAL APPLICATION 9 VCC MCU 8 VDD(VrefU) AO1 15 AO2 2 AO3 3 14 DI 13 CLK 12 LD AO4 4 11 DO AO5 5 AO6 6 AO7 7 AO8 10 GND 16 VSS(VrefL) 1 Note: M62353AGP has 3 terminals(VDD, VCC, and VSS) to which constant voltage is to be applied. Ripple voltage or spike noise to these terminals may worsen converting precision or cause erroneous operations. So be sure to use this device by putting cacpacitor between each terminal and GND to get D-A conversion operation stabilized. Output buffer amplifiers have high oscillation stability against capacitive load. This means that jitters by wirings around output terminals or capcitor between output and GND(0.1uF max.) do not cause any problems with DAC operations. Connect capacitor(0.1uF or around) between output and GND for protection from spark discharge when this device is used under such high electric field as that for instance of instruments with cathode ray tube. ( 6 / 6) 0107