PD - 94568A iP2002 Synchronous Buck Multiphase Optimized BGA Power Block Integrated Power Semiconductors, Drivers & Passives Features: • • • • • • • Output current 30A continuous with no derating up to TPCB = 90°C and TCASE = 90°C Operating frequency up to 1MHz Dual sided heatsink capable Very small 11mm x 11mm x 2.6mm profile iP2001 footprint compatible Internal features minimize layout sensitivity * Optimized for very low power losses iP2002 Power Block Description The iP2002 is a fully optimized solution for high current synchronous buck multiphase applications. Board space and design time are greatly reduced because most of the components required for each phase of a typical discrete-based multiphase circuit are integrated into a single 11mm x 11mm x 2.6mm BGA power block. The only additional components required for a complete multiphase converter are a PWM IC, the external inductors, and the input and output capacitors. iPOWIR technology offers designers an innovative board space saving solution for applications requiring high power densities. iPOWIR technology eases design for applications where component integration offers benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for layout, heat transfer and component selection. iP2002 Internal Block Diagram VIN PRDY ENABLE PWM VDD MOSFET Driver with dead time control SGND VSW PGND * All of the difficult PCB layout and bypassing issues have been addressed with the internal design of the iPOWIR Block. There are no concerns about double pulsing, unwanted shutdown, or other malfunctions which often occur in switching power supplies. The iPOWIR Block will function normally without any additional input power supply bypass capacitors. However, for reliable long term operation it is recommended that at least four 10uF ceramic input decoupling capacitors are provided to the VIN pin of each power block. No additional bypassing is required on the VDD pin. www.irf.com 03/20/03 1 iP2002 All specifications @ 25°C (unless otherwise specified) Absolute Maximum Ratings : Parameter Min Typ Max Units Conditions VIN to PGND VDD to SGND PWM to SGND Enable to SGND Output RMS Current - - 16 6.0 V V -0.3 -0.3 - - VDD+0.3 VDD+0.3 30 V V A Block Temperature -40 - 125 °C Symbol Min Typ Max Units Supply Voltage VDD 4.6 5.0 5.5 V Input Voltage Range VIN 3.0 - 13.2 V see Figs. 2 & 3 Output Voltage Range VOUT 0.9 - 3.3 V see Figs. 2, 4 & 8 Output Current Range IOUT - - 30 A see Fig. 2 Operating Frequency fsw 150 - 1000 kHz Operating Duty Cycle D - - 85 % not to exceed 6.0V not to exceed 6.0V Recommended Operating Conditions : Parameter Conditions see Figs. 2 & 5 Electrical Specifications @ VDD = 5V (unless otherwise specified) : Parameter Block Power Loss c Turn On Delay d Turn Off Delay d VIN Quiescent Current VDD Quiescent Current Under-Voltage Lockout Start Threshold Hysteresis Enable Input Voltage High Input Voltage Low Power Ready Logic Level High Logic Level Low PWM Input Logic Level High Logic Level Low Symbol P BLK td(on) td(off) IQ-VIN IQ-VDD UVLO VSTART VHys-UVLO Enable VIH VIL PRDY VOH VOL PWM VOH VOL Min - Typ 7.2 63 26 - Max 8.9 1.0 10 Units W 4.2 - 4.4 .05 4.5 - V 2.0 - - 0.8 V 4.5 - 4.6 0.1 0.2 V 2.0 - - 0.8 V ns mA µA Conditions VIN = 12V, VOUT = 1.3V, IOUT = 30A, fSW = 1MHz Enable = 0V, VIN = 12V Enable = 0V, VDD = 5V VDD = 4.6V, ILoad = 10mA VDD < UVLO Threshold, ILoad = 1mA c Measurement were made using four 10uF (TDK C3225X7R1C106M or equiv.) capacitors across the input (see Fig. 8). d Not associated with the rise and fall times. Does not affect Power Loss (see Fig. 9). 2 www.irf.com iP2002 Pin Description Table Pin Name VDD SGND Ball Designator A1 – A3, B1 – B3 A5 – A12, B5 – B12, C5 - C10 C11, C12, D11, D12, E11, E12, F6, F7, F12, G6, G7, G12, H6, H7, H12, J6, J7, J12, K5 – K7, K12, L5, L6, L12, M5 – M7, M12 D5 – D10, E5 – E10, F8 – F11, G8 – G11, H8 – H11, J8 – J11, K8 – K11, L8 – L11, M8 – M11 C1 – C3, D1 –D3, E1 –E3 ENABLE F1 VIN PGND VSW PRDY PWM NC www.irf.com K1 Pin Function Supply voltage for the internal circuitry. Input voltage for the DC-DC converter. Power Ground - connection to the ground of bulk and filter capacitors. Switching Node - connection to the output inductor. Signal Ground. When set to logic level high, internal circuitry of the device is enabled. When set to logic level low, the PRDY pin is forced low, the Control and Sychronous switches are turned off, and the supply current is less than 10µA. Power Ready - This pin indicates the status of ENABLE or VDD. This output will be driven low when ENABLE is logic low or when VDD is less than 4.4V (typ.). When ENABLE is logic high and VDD is greater than 4.4V (typ.), this output is driven high. This output has a 10mA source and 1mA sink capability. TTL-level input signal to MOSFET drivers. H1 B4, C4, D4, E4, F2 – F4, G2 – This pin is not for electrical connection. It G4, H2 – H4, J1, J2 – J4, K3, should be attached only to dead copper. L1, L2, M1 – M4 3 iP2002 11 VIN = 12V VOUT = 1.3V fSW = 1MHz TBLK = 125°C L = 0.30uH 10 9 8 Power Loss (W) 7 Maximum Typical 6 5 4 3 2 1 0 0 5 10 15 20 25 30 Output Current (A) Fig. 1: Power Loss vs. Current Case Temperature (ºC) 0 10 20 30 40 50 60 70 80 90 100 110 120 32 30 28 26 Safe Operating Area 24 Output Current (A) 22 20 18 16 14 TX 12 10 VIN = 12V VOUT = 1.3V fSW = 1MHz L = 0.30uH 8 6 4 2 0 0 10 20 30 40 50 60 70 80 90 100 110 120 PCB Temperature (ºC) Fig. 2: Safe Operating Area (SOA) vs. TPCB & TCASE 4 www.irf.com iP2002 Typical Performance Curves 1.30 1.40 10.5 13.5 1.25 10.5 9.5 8.5 7.5 1.20 6.5 5.5 1.15 4.5 1.10 3.5 2.5 1.05 1.5 0.5 1.00 -0.5 1.20 1.15 8.5 6.5 4.5 1.10 2.5 1.05 0.5 1.00 -1.5 0.95 -1.5 0.95 VIN = 12V IOUT = 30A fSW = 1MHz L = 0.30uH TBLK = 125°C 1.25 11.5 Power Loss (Normalized) 1.30 SOA Temp Adjustment (ºC) Power Loss (Normalized) 1.35 12.5 SOA Temp Adjustment (ºC) VOUT = 1.3V IOUT = 30A fSW = 1MHz L = 0.30uH TBLK = 125°C -2.5 0.90 -3.5 3 4 5 6 7 8 9 10 11 12 0.90 13 -3.5 0.8 1.2 1.6 Input Voltage (V) 3.2 3.6 1.10 -0.5 -4.5 0.85 -6.5 0.80 -8.5 0.75 Power Loss (Normalized) -2.5 3.5 VIN = 12V VOUT = 1.3V IOUT = 30A fSW = 1MHz TBLK = 125°C 1.08 1.06 3.0 2.5 2.0 1.04 1.5 1.02 1.0 0.5 1.00 -0.1 SOA Temp Adjustment (ºC) VIN = 12V VOUT = 1.3V IOUT = 30A L = 0.30uH TBLK = 125°C SOA Temp Adjustment (ºC) Power Loss (Normalized) 2.8 Fig. 4: Normalized Power Loss vs. VOUT 1.00 0.90 2.4 Output Voltage (V) Fig. 3: Normalized Power Loss vs. VIN 0.95 2.0 0.98 -0.6 0.70 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 -10.5 1000 0.96 -1.1 0.1 0.2 0.3 0.4 Switching Frequency (kHz) 0.5 0.6 0.7 0.8 0.9 1.0 Output Inductance (uH) Fig. 5: Normalized Power Loss vs. Frequency Fig. 6: Normalized Power Loss vs. Inductance 70 Average IDD (mA) 60 50 40 30 20 Does not include PRDY current TBLK = 25°C 10 0 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 Switching Frequency (kHz) Fig. 7: IDD vs. Frequency www.irf.com 5 iP2002 Applying the Safe Operating Area (SOA) Curve The SOA graph incorporates power loss and thermal resistance information in a way that allows one to solve for maximum current capability in a simplified graphical manner. It incorporates the ability to solve thermal problems where heat is drawn Case Temperature (ºC) out through the printed circuit board and the top of the case. 0 10 20 30 40 50 60 70 80 90 100 110 120 32 Procedure 30 28 3 26 2) Draw a vertical line from the TX axis intercept to the SOA curve. Safe Operating Area 24 22 Output Current (A) 1) Draw a line from Case Temp axis at TCASE to the PCB Temp axis at TPCB. 20 18 16 14 TX 12 10 VIN = 12V VOUT = 1.3V fSW = 1MHz L = 0.30uH 8 3) Draw a horizontal line from the intersection of the vertical line with the SOA curve to the Y axis. The point at which the horizontal line meets the y-axis is the SOA current. 1 2 6 4 2 0 0 10 20 30 40 50 60 70 80 90 100 110 120 PCB Temperature (ºC) Adjusting the Power Loss and SOA curves for different operating conditions To make adjustments to the power loss curves in Fig. 1, multiply the normalized value obtained from the curves in Figs. 3, 4, 5 or 6 by the value indicated on the power loss curve in Fig. 1. If multiple adjustments are required, multiply all of the normalized values together, then multiply that product by the value indicated on the power loss curve in Fig. 1. The resulting product is the final power loss based on all factors. See example no. 1. To make adjustments to the SOA curve in Fig. 2, determine your maximum PCB Temp & Case Temp at the maximum operating current of each iP2002. Then, add the correction temperature from the normalized curves in Figs. 3, 4, 5 or 6 to the TX axis intercept (see procedure no. 2 above) in Fig. 2. When multiple adjustments are required, add all of the temperatures together, then add the sum to the TX axis intercept in Fig. 2. See example no. 2. Operating Conditions for the following examples: Output Current = 30A Output Voltage = 3.3V Input Voltage = 10V Sw Freq= 900kHz Inductor = 0.2uH Example 1) Adjusting for Maximum Power Loss: (Fig. 1) (Fig. 3) (Fig. 4) (Fig. 5) (Fig. 6) Maximum power loss = 11W Normalized power loss for input voltage ≈ 0.98 Normalized power loss for output voltage ≈ 1.24 Normalized power loss for frequency ≈ 0.95 Normalized power loss for inductor value ≈ 1.02 Adjusted Power Loss = 11W x 0.98 x 1.24 x 0.95 x 1.02 ≈ 12.95W 6 www.irf.com iP2002 Example 2) Adjusting for SOA Temperature: (Fig. 3) (Fig. 4) (Fig. 5) (Fig. 6) Normalized Normalized Normalized Normalized SOA Temperature for input voltage ≈ -0.6°C SOA Temperature for output voltage ≈ 8.4°C SOA Temperature for frequency ≈ -1.8°C SOA Temperature for inductor value ≈ 1.1°C TX axis intercept temp adjustment = - 0.6°C + 8.4°C - 1.8°C + 1.1°C ≈ 7.1°C Assuming TCASE = 100°C & TPCB = 90°C: The following example shows how the SOA current is adjusted for a TX increase of 7.1°C. Case Temperature (ºC) 0 10 20 30 40 50 60 70 80 90 100 110 120 32 30 Unadjusted SOA Current 28 26 24 Adjusted SOA Current Output Current (A) 22 20 18 16 14 Safe Operating Area 12 10 VIN = 12V VOUT = 1.3V fSW = 1MHz L = 0.30uH 8 6 4 2 TX 0 0 10 20 30 40 50 60 70 80 90 100 110 120 PCB Temperature (ºC) 90% PIN = VIN Average x IIN Average PDD = VDD Average x IDD Average POUT = VOUT Average x IOUT Average PLOSS = (PIN + PDD) - POUT PRDY Average VDD Current Average VDD Voltage A V PWM A V iP2001 iP2002 PWM 10% Average Output Current VSW 90% A PGND Averaging Circuit V Fig 8. Power Loss Test Circuit www.irf.com Average Input Voltage VDD SGND DC VIN ENABLE DC Average Input Current Average Output Voltage (V OUT) Average Output Voltage VSW 10% td(on) td(off) Fig 9. Timing Diagram 7 C37 0.22uF 2 3 4.42k 2 8 open R36 8.2pF C25 3.92K ISL6558CB U1 GND FS/EN PGOOD VSEN +5V 10uF Vdd ISEN4 PWM4 PWM3 ISEN3 PWM2 ISEN2 PWM1 C29 Vin VCC ISEN1 6800pF C1 1uF U6 12V / 5V CONVERTER CMPD3003A 1 20K R4 7 2 PGOOD TP5 open C47 6 1800pF C26 R1 C27 Vin 0.22uF C38 D2 PRDY4 3 0.22uF 1 CMPD3003A D1 R3 4.42k R2 3.92k R32 3.92k R31 C36 PRDY2 PRDY3 0.22uF C35 PRDY1 0 200 R6 4 5 FB R35 3 COMP 8 DROOP VOUTS 15 16 9 10 12 11 13 14 1 open +5V 0 +5V 0 R12 R13 R29 open 0 R11 0 R18 R16 10K 10k R17 10k R23 10K R27 10k R25 10k open 10uF open R24 open R26 open R28 PRDY4 +5V PRDY3 +5V PRDY2 +5V PRDY1 R22 R10 10k R21 +5V C2 R30 +5V 10k R19 ENABLE4 +5V ENABLE3 +5V ENABLE2 +5V ENABLE1 +5V PRDY4 ENABLE4 PWM4 SGND4 VDD4 IP2002-4 PRDY3 ENABLE3 PWM3 SGND3 VDD3 IP2002-3 PRDY2 ENABLE2 PWM2 SGND2 VDD2 IP2002-2 PRDY1 ENABLE1 PWM1 SGND1 VDD1 IP2002-1 PGND4 VSW4 VIN4 PGND3 VSW3 VIN3 PGND2 VSW2 VIN2 PGND1 VSW1 VIN1 VSW4 VSW3 VSW2 VSW1 10uF C12 10uF C9 10uF C6 10uF C3 10uF C13 10uF C10 10uF C7 10uF C4 10uF C14 10uF C11 10uF C8 10uF C5 Vin 2.49k R7 2.49k R5 2.49k R9 10uF C32 2.49k R8 10uF C31 10uF C30 10uF C33 Vin Vin Vin VSW4 TP9 VSW3 TP8 VSW2 TP7 L1 L2 0.3uH L4 0.3uH L3 0.3uH 100uF Size Title C22 100uF 100uF C20 100uF C18 100uF C16 PGNDS TP17 330uF C41 C21 100uF C19 100uF C17 100uF C15 330uF 330uF 0.3uH VSW1 TP6 C40 C39 VINS TP13 0.1uF C34 10uF C46 PGNDS VOUTS PGND TP16 PGND TP15 PGND TP14 VOUT TP12 VOUT TP11 VOUT TP10 PGNDS TP22 VOUTS TP21 Number Revision IP2002_4 phase demo board open C45 open C44 open C43 open C42 VOUT PGND TP19 VIN TP18 iP2002 4-Phase Reference Design Schematic www.irf.com iP2002 Quantity 1 17 8 2 1 1 1 1 1 4 3 5 3 5 9 2 1 1 4 1 7 2 1 1 4 1 1 4 1 Designator C1 C10 C11 C12 C13 C14 C3 C30 C31 C32 C33 C4 C46 C5 C6 C7 C8 C9 C15 C16 C17 C18 C19 C20 C21 C22 C2 C29 C25 C26 C27 C28 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C47 R1 R2 R31 R10 R11 R12 R13 R35 R16 R17 R18 R19 R21 R23 R25 R27 R34 R3 R32 R33 R4 R5 R7 R8 R9 R6 R22 R24 R26 R28 R29 R30 R36 D1 D2 D5 D6 L1 L2 L3 L4 L5 U1 U2 U3 U4 U5 U6 Value 1 6800pF Value 2 50V Type 2 X7R Tolerance 10% Package 0805 Mfr. PHICOMP Mfr. Part No. 08052R682K9BB0 10.0uF 16V X5R 10% 1206 Murata GRM31CR61C106KC31B 100uF 6.3V X5R 20% 1210 TDK C3225X5R0J107M 10.0uF 8.20pF 1800pF 1.00uF 0.010uF 0.100uF 0.22uF 330uF Open 3.92K 0 6.3V 50V 50V 16V 50V 50V 6.3V 16V 1/8W 1/8W X5R NPO X7R X7R X7R X7R X5R WA series thin film thick film 10% 3% 10% 10% 10% 10% 10% 20% 0.10% <50m 1206 0805 0805 0805 0805 0805 0603 SMD 0805 0805 TDK PHICOMP PHICOMP MuRata TDK ROHM TDK Panasonic BC Component ROHM C3216X5R0J106K 0805CG829C9BB0 08052R182K9BB0 GRM40X7R105K016 C2012X7R1H103KT MCH215C104KP C1608X5R0J224K EEF-WA1C331P 2312-241-73922 MCR10EZHJ000 10.0K 1/8W thick film 1% 0805 KOA RK73H2A1002F 4.42K 30.1K 20.0K 2.49K 200 1/8W 1/8W 1/8W 1/8W 1/8W thin film thick film thick film thick film thick film 0.10% 1% 1% 1% 1% 0805 0805 0805 0805 0805 BC Component KOA KOA KOA KOA 2312-241-74422 RK73H2A3012F RK73H2A2002F RK73H2A2491F RK73H2A2000F Open - - - - - - 30V 40V 30V 0.3uH 15uH 4.5 - 5.5V 30A 4.7 - 25V 200mA schottky sot23 Central 2.1A schottky D-64 IRF 100mA schottky sot23 Central 36A ferrite 20% SMT Panasonic 0.70A ferrite 20% SMT Coilcraft 0.8 - 5V PWM controller 0 - 70°C 16 Ld SOIC Intersil Power Block 11mm x 11mm International Rect 1.8 - 5V PWM controller -40 to +85°C S6 Linear Technology CMPD3003A 10MQ040N CMPSH-3 ETQP2H0R3BFA 1008PS-153M ISL6558CB iP2002 LT1616 4-Phase Reference Design Bill of Materials Refer to the following application notes for detailed guidelines and suggestions when implementing iPOWIR Technology products: AN-1028: Recommended Design, Integration and Rework Guidelines for International Rectifier’s iPOWIR Technology BGA Packages This paper discusses the assembly considerations that need to be taken when mounting iPOWIR BGA’s on printed circuit boards. This includes soldering, pick and place, reflow, inspection, cleaning and reworking recommendations. AN-1029: Optimizing a PCB Layout for an iPOWIR Technology Design This paper describes how to optimize the PCB layout design for both thermal and electrical performance. This includes placement, routing, and via interconnect suggestions. AN-1030: Applying iPOWIR Products in Your Thermal Environment This paper explains how to use the Power Loss and SOA curves in the data sheet to validate if the operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product. AN-1047: Graphical solution for two branch heatsinking Safe Operating Area Detailed explanation of the dual axis SOA graph and how it is derived. www.irf.com 9 iP2002 VDD NC VIN NC SGND PGND NC NC ENABLE NC NC PWM NC NC NC NC NC PRDY NC NC VSW PGND NC Dimensions shown in inches (millimeters) Recommended PCB Footprint (Top View) 10 www.irf.com iP2002 0.15 [.006] C 2X 11.00 [.433] 6 B A 5 C 0.45 [.0177] 0.35 [.0138] NOTES: 0.12 [.005] C BALL A1 CORNER ID 1. 2. 3. 4. 5 11.00 [.433] 6 7 0.15 [.006] C TOP VIEW 2X 133X Ø 4X 0.80 [.032] BOTTOM VIEW 22X 6 0.55 [.0216] 0.45 [.0178] 0.15 [.006] 0.08 [.003] 0.40 [.016] DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES]. CONTROLLING DIMENSION: MILLIMETER SOLDER BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. PRIMARY DATUM C (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE PACKAGE BODY. SOLDER BALL DIAMETER IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, IN A PLANE PARALLEL TO DATUM C. 7 C A B C 2.31 [.0909] 2.11 [.0831] (4X 1.1 [.043]) 2.76 [.1087] 2.46 [.0969] SIDE VIEW Mechanical Drawing www.irf.com 11 iP2002 0123 XXXX iP2002 Part Marking 0123 601000 iP2002 0123 601000 iP2002 16mm 24mm FEED DIRECTION NOTES: 1. OUTLINE CONFORMS TO EIA-481 & EIA-541. Tape & Reel Information Data and specifications subject to change without notice. This product has been designed and qualified for the industrial market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.8/01 12 www.irf.com