T ODUC MENT TE P R E CE L A O L S P t OB RE D E enter a D N ME port C m/tsc M p O u C S l E a o NO R echnic tersil.c t our T IL or www.in c a t n o c S INTER 1-888- CD22202, CD22203 ® November 2002 5V Low Power DTMF Receiver Features Description • Central Office Quality The CD22202 and CD22203 complete dual-tone multiple frequency (DTMF) receivers detect a selectable group of 12 or 16 standard digits. No front-end pre-filtering is needed. The only externally required components are an inexpensive 3.579545MHz TV “colorburst’’ crystal (for frequency reference) and a bias resistor. Extremely high system density is possible through the use of the clock output of a crystal connected CD22202/CD22203 receiver to drive the time bases of additional receivers. This is a monolithic integrated circuit fabricated with low-power, complementary symmetry CMOS processing. It only requires a single low tolerance power supply. • No Front End Band Splitting Filters Required • Single, Low Tolerance, 5V Supply • Detects Either 12 or 16 Standard DTMF Digits • Uses Inexpensive 3.579545MHz Crystal for Reference • Excellent Speech Immunity • Output in Either 4-Bit Hexadecimal Code or Binary Coded 2-of-8 • Synchronous or Handshake Interface The CD22202 and CD22203 employ state-of-the-art circuit technology to combine the digital and analog functions on the same CMOS chip using a standard digital semiconductor process. The analog input is preprocessed by 60Hz reject and band splitting filters and then hard limited to provide AGC. Eight Bandpass filters detect the individual tones. The digital post processor times the tone durations and provides the correctly coded digital outputs. Outputs interface directly to standard CMOS circuitry and are three-state enabled to facilitate bus oriented architectures. • Three-State Outputs • Excellent Latch-Up Immunity Part Number Information PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. CD22202E 0 to 70 18 Ld PDIP E18.3 CD22203E 0 to 70 18 Ld PDIP E18.3 Functional Diagram Pinout 1 18 D2 HEX/B28 2 17 D4 EN 3 16 D8 IN1633 4 15 CLRDV VDD 5 6 13 ATB 7 12 XIN XEN 8 11 XOUT ANALOG IN 9 10 VSS 15 CLRDV HIGH B/P FILTERS 13 ATB 14 DV ED (203 ONLY), NC (202) VSS XEN 8 CHIP CLOCKS XIN 12 11 XOUT 1 DV 2 HEX/B28 1 D1 18 D2 17 D4 16 D8 3 VOLTAGE REG./REF. 5 VDD CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved ED-203 NC-202 14 CLOCK GENERATOR D1 LOW B/P FILTERS DETECTORS AND SIGNALPROCESSING CIRCUITS ANALOG IN 9 PREPROCESSOR/ BANDSPLIT FILTER 6 CD22202, CD22203 (PDIP) TOP VIEW 10 VSS EN 7 4 INI633 FN1695.4 CD22202, CD22203 Absolute Maximum Ratings Thermal Information DC Supply Voltage (VDD)(Referenced to VSS Terminal) . . . . . . . 7V Power Dissipation TA = 25oC (Derate above TA = 25oC at 6.25mW/oC . . . . . . . 65mW Input Voltage Range All Inputs Except Analog In . . . . . . . . . . . . . . (VDD +0.5V) to -0.5V Analog in Voltage Range . . . . . . . . . . . . (VDD +0.5V) to (VDD -10V) DC Current into any Input or Output . . . . . . . . . . . . . . . . . . . . . . ±20mA Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Junction Temperature (Plastic). . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC NOTE: Unused inputs must be connected to VDD or VSS as appropriate. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications PARAMETER 0oC ≤ TA ≤ +70oC, VDD = 5V ±10% TEST CONDITIONS Frequency Detect Bandwidth MIN TYP MAX ±(1.5 + 2Hz) ±2.3 ±3.5 UNITS % of fO Amplitude for Detection Each Tone -32 - -2 Minimum Acceptable Twist High Tone Twist = ---------------------------Low Tone -10 - +10 dB - - 0.8 VRMS 60Hz Tolerance dBm Referenced to 600Ω Dial Tone Tolerance “Precise” Dial Tone - - 0 dB Referenced to Lower Amplitude Tone Talk Off MITEL Tape #CM7291 - 2 - Hits Digital Outputs (except XOUT) “0” Level, 400µA Load 0 - 0.5 V “1” Level, 200µA Load VDD -0.5 - VDD V “0” Level 0 - 0.3VDD V “1” Level 0.7VDD - VDD V Digital Inputs Supply Current TA = +25oC - 10 16 mA Noise Tolerance MITEL Tape #CM7291 (Note 1) - - -12 dB Referenced to Lowest Amplitude Tone Input Impedance VDD ≥ VIN ≥ (VDD -10) 100kΩ//15pF 300kΩ - NOTE: 1. Bandwidth limited (3kHz) Gaussian noise. 2 CD22202, CD22203 Functional Block Diagram CD22202 CD22203 BANDPASS FILTERS ANALOG IN BAND SPLIT FILTERS PREPROCESSOR 60Hz REJECT 9 PRE EMP 697 ZERO CROSSING DETECTORS 770 BS1 AMPLITUDE DETECTORS EARLY DETECT OUTPUT 852 6 941 BS2 CLRDV TIMING CIRCUITRY 1209 15 1336 CLR ATB 13 1477 8 XEN DV STROBE 1633 DV F.F DV 14 DATA STROBE ÷8 12 CLOCK GENERATOR H/B28 CHIP CLOCKS 2 XIN 1 D1 1MΩ 18 D2 OUTPUT DECODER XOUT 11 OUTPUT REGISTER 17 D4 VOLTAGE REF POWER REGULATOR 16 D8 DATA CLEAR 5 10 7 VDD VSS VSS IN1633 3 EN 4 NOTE: Pin 6: Early detect output on CD22203 only. System Functions Analog In FIGURE 1. ANALOG IN The Analog In pin accepts the analog input. It is internally biased so that the input signal may be either AC or DC coupled, as long as it does not exceed the positive supply voltage. Proper input coupling is illustrated below. The CD22202 and CD22203 are designed to accept sinusoidal input waveforms, but will operate satisfactorily with any input that has the correct fundamental frequency with harmonics that are at least 20dB below the fundamental. Crystal Oscillator CD22202, CD22203 VDD 0.01µF AUDIO INPUT (+4dBm MAXIMUM) 270kΩ 9 1500pF The CD22202 and CD22203 contain an on-board inverter with sufficient gain to provide oscillation when connected to a low cost television “color-burst” (3.579545MHz) crystal. The crystal oscillator is enabled by tying XEN high. The crystal is connected between XIN and XOUT. A 1MΩ resistor is also connected between these pins in this mode. ATB is a clock frequency output. Other CD22202 and CD22203 devices may use the same frequency reference by tying their ATB pins to the ATB output of a crystal connected device. XIN and XEN of the auxiliary devices must then be tied high and low, respectively. Up to ten devices may be run from a single crystal connected CD22202 and CD22203 as shown in Figure 2. 33kΩ ANALOG IN 10pF (ON CHIP) >100kΩ VSS OPTIONAL HIGH FREQUENCY NOISE FILTER (fC = 3.9kHz) 3 CD22202, CD22203 sensed and decoded at the output pins D1, D2, D4, and D8. DV remains high until a valid pause occurs or CLRDV is raised high, whichever is sooner. This handshake can save microprocessor time. 3.579545MHz 1M 12 ATB VDD XOUT XIN 8 CD22202/22203 13 DTMF Dialing Matrix 11 XIN CONNECTED TO VDD 12 XEN CD22202/22203 13 COL 0 1209Hz COL 1 1336Hz COL 2 1477Hz COL 3 1633Hz ROW 0 697Hz 1 2 3 A ROW 1 770Hz 4 5 6 B ROW 2 852Hz 7 8 9 C ROW 3 941Hz * 0 # D XEN 8 UP TO 10 DEVICES FIGURE 2. CRYSTAL OSCILLATOR NOTE: Column 3 is for special applications and is not normally used in telephone dialing. HEX/B28 IN1633 This pin selects the format of the digital output code. When HEX/B28 is tied high, the output is hexadecimal. When tied low, the output is binary coded 2-of-8. The following table describes the two output codes. When tied high, this pin inhibits detection of tone pairs containing the 1633Hz component. For detection of all 16 standard digits, IN1633 must be tied low. TABLE 1. OUTPUT CODES N/C Pin HEXADECIMAL BINARY CODED 2-OF-8 This pin has no internal connection and should be left floating. DIGIT D8 D4 D2 D1 D8 D4 D2 D1 1 0 0 0 1 0 0 0 0 Digital Inputs and Outputs 2 0 0 1 0 0 0 0 1 3 0 0 1 1 0 0 1 0 4 0 1 0 0 0 1 0 0 5 0 1 0 1 0 1 0 1 All digital inputs and outputs of the DTMF receivers are represented by the schematic below. Only the “analog in” pin is different, and is described above. Care must be exercised not to exceed the voltage or current ratings on these pins as listed in the “maximum ratings” section. 6 0 1 1 0 0 1 1 0 7 0 1 1 1 1 0 0 0 8 1 0 0 0 1 0 0 1 9 1 0 0 1 1 0 1 0 0 1 0 1 0 1 1 0 1 * 1 0 1 1 1 1 0 0 # 1 1 0 0 1 1 1 0 A 1 1 0 1 0 0 1 1 B 1 1 1 0 0 1 1 1 C 1 1 1 1 1 0 1 1 D 0 0 0 0 1 1 1 1 VDD CMOS DIGITAL CIRCUITRY DIGITAL INPUT DIGITAL OUTPUT VSS FIGURE 3. DIGITAL INPUTS AND OUTPUTS ED Input Filter This pin, on the CD22203 only, indicates the presence of frequencies which are likely to be DTMF digits, but have not yet been verified by a DV signal. It is comparable to a “buttondown” output, and it is useful as an EARLY DETECT signal to interrupt a microprocessor for digit storage and validation. The CD22202 and CD22203 will tolerate total input noise of a maximum of 12dB below the lowest amplitude tone. For most telephone applications, the combination of the high frequency attenuation of the telephone line and internal band limiting make special circuitry at the input to these receivers unnecessary. However, noise near the 56kHz internal sampling frequency will be aliased (folded back) DV and CLRDV DV signals a detection by going high after a valid tone pair is 4 CD22202, CD22203 into the audio spectrum, so if excessive noise is present above 28kHz, the simple RC filter shown below may be used to band limit the incoming signal. The cut off frequency is 3.9kHz. NOISY SIGNAL ANALOG IN 270kΩ PARAMETER Noise will also be reduced by placing a grounded trace around XIN and XOUT pins on the circuit board layout when using a crystal. It is important to note that XOUT is not intended to drive an additional device. XIN may be driven externally; in this case, leave XOUT floating. Timing Waveforms TONE BURST 1 tOFF PAUSE ANALOG INPUT TONE BURST 2 tR tD D1, D2 D4, D8 tSU tH tCL MAX UNITS For Detection tON 40 - - ms For Rejection tON - - 20 ms For Detection tOFF 40 - - ms For Rejection tOFF - - 20 ms Detect Time tD 25 - 46 ms Release Time tR 35 50 ms Data Setup Time tSU 7 - - µs Data Hold Time tH 4.2 - 5 ms DV Clear Time tCL - 160 250 ns CLRDV Pulse Width tPW 200 - - ns ED Detect Time tED 7 - 22 ms ED Release Time tER 2 - 18 ms Output Enable Time CL = 50pF, RL = 1kΩ - - 200 300 ns Output Disable Time CL = 35pF, RL = 500Ω - - 150 200 ns Output Rise Time CL = 50pF - - 200 300 ns Output Fall Time CL = 50pF - - 160 250 ns Guard Time DV tPW Whenever the DTMF receiver is continually monitoring a voice channel containing distorted or musical voices or tones, additional guard time may be added in order to prevent false decoding. This may be done in software by verifying that both ED and DV are present simultaneously for about 55ms. An appropriate guard time should be selected to balance the fastest expected dialing speed against the rejection of distorted or musical voices or tones (most autodialers operate in the 65ms to 75ms range although a few generate 50ms tones). A hardware guard time circuit is shown in Figure 6. R3 and R4 should keep the voice amplitude as low as practical, while R2 and R5 adjust detection speed. CLRDV tED TYP Pause Time CD22202 CD22203 FIGURE 4. FILTER FOR USE IN EXTREME HIGH FREQUENCY INPUT NOISE ENVIRONMENT tON MIN Tone Time 33kΩ 0.0015µF SYMBOL tER ED (NOTE) NOTE: Early Detect output is available only on the CD22203. FIGURE 5. 5 CD22202, CD22203 +5V R2 10µF ≈ 240K D1 (55ms) HEX/B28 EN 1 18 2 17 3 16 4 15 5 14 6 13 7 12 8 11 IN1633 VDD IN4148 ED VSS C2 0.15µF XEN ANALOG IN 10 9 D2 D4 D8 CLRDV DV ATB XIN XOUT 3.58 MHz VSS R1 1M R5 1.8M R6 100K R4 33K R3 ≈ 390K AUDIO IN C1 4700pF D8 D4 D2 D1 HEX DATA OUT ENABLE INPUT 1/3 CD74HC04 DV OUT (BUFFERS OPTIONAL) FIGURE 6. CD22203 DTMF RECEIVER WITH GUARD TIME CIRCUIT TO PROVIDE EXCEPTIONAL TALK-OFF PERFORMANCE Operating and Handling Considerations Handling Input Signals All inputs and outputs of CMOS devices have a network for electrostatic protection during handling. Recommended handling practices for CMOS devices are described in ICAN-6525 “Guide to Better Handling and Operation of CMOS Integrated Circuits”. To prevent damage to the input protection circuit, input signals should never be greater than VDD nor less than VSS. Input currents must not exceed 20mA even when the power supply is off. Operating A connection must be provided at every input terminal. All unused input terminals must be connected to either VDD or VSS, whichever is appropriate. Unused Inputs Operating Voltage Output Short Circuits During operation near the maximum supply voltage limit, care should be taken to avoid or suppress power supply turn-on and turnoff transients, power supply ripple, or ground noise; any of these conditions must not cause VDD - VSS to exceed the absolute maximum rating. Shorting of outputs to VDD or VSS may damage CMOS devices by exceeding the maximum device dissipation. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 6