LODEV LF2242JC33 12/16-bit half-band interpolating/ decimating digital filter Datasheet

LF2242
LF2242
DEVICES INCORPORATED
12/16-bit Half-Band Interpolating/
Decimating Digital Filter
12/16-bit Half-Band Interpolating/
Decimating Digital Filter
DEVICES INCORPORATED
FEATURES
DESCRIPTION
❑ 40 MHz Clock Rate
❑ Passband (0 to 0.22fS)
Ripple: ±0.02 dB
❑ Stopband (0.28fS to 0.5fS)
Rejection: 59.4 dB
❑ User-Selectable 2:1 Decimation or
1:2 Interpolation
❑ 12-bit Two’s Complement Input
and 16-bit Output with
User-Selectable Rounding, 8- to
16-Bits
❑ User-Selectable Two’s Complement
or Inverted Offset Binary Output
Formats
❑ Three-State Outputs
❑ Replaces TRW/ Raytheon/
Fairchild TMC2242
❑ Package Styles Available:
• 44-pin PLCC, J-Lead
• 44-pin PQFP
The LF2242 is a linear-phase, halfband (low pass) interpolating/
decimating digital filter that, unlike
intricate analog filters, requires no
tuning. The LF2242 can also significantly reduce the complexity of
traditional analog anti-aliasing prefilters without compromising the
signal bandwidth or attenuation. This
can be achieved by using the LF2242
as a decimating post-filter with an
A/D converter and by sampling the
signal at twice the rate needed.
Likewise, by using the LF2242 as an
interpolating pre-filter with a D/A
converter, the corresponding analog
reconstruction post-filter circuitry can
be simplified.
The coefficients of the LF2242 are
fixed, and the only user programming
required is the selection of the mode
(interpolate, decimate, or passthrough) and rounding. The asynchronous three-state output enable
control simplifies interfacing to a bus.
Data can be input into the LF2242 at a
rate of up to 40 million samples per
second. Within the 40 MHz I/O limit,
the output sample rate can be onehalf, equal to, or two times the input
sample rate. Once data is clocked in,
the 55-value output response begins
after 7 clock cycles and ends after 61
clock cycles. The pipeline latency
from the input of an impulse response
to its corresponding output peak is 34
clock cycles.
The output data may be in either
two’s complement format or inverted
offset binary format. To avoid
truncation errors, the output data is
always internally rounded before it is
latched into the output register.
Rounding is user-selectable, and the
output data can be rounded from 16
bit values down to 8 bit values.
DC gain of the LF2242 is 1.0015
(0.0126 dB) in pass-through and
decimate modes and 0.5007 (–3.004
dB) in interpolate mode. Passband
ripple does not exceed ±0.02 dB from
0 to 0.22fS with stopband attenuation
greater than 59.4 dB from 0.28fS to
0.5fS (Nyquist frequency). The
response of the filter is –6 dB at 0.25fS.
Full compliance with CCIR Recommendation 601 (–12 dB at 0.25fS) can
be achieved by cascading two devices
serially.
LF2242 BLOCK DIAGRAM
TCO
RND2–0
3
3
SI11–0
12
INTERPOLATION 12
CIRCUIT
55-TAP
FIR
FILTER
ROUND
AND LIMIT
CIRCUIT
3
CLK
16
16
DECIMATION
CIRCUIT
SO15–0
3
OE
TO ALL REGISTERS
INT DEC SYNC
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LF2242
DEVICES INCORPORATED
FIGURE 1.
12/16-bit Half-Band Interpolating/
Decimating Digital Filter
Controls
FREQUENCY RESPONSE OF FILTER
INT — Interpolation Control
0
When INT is LOW and DEC is HIGH
(Table 1), the device internally forces
every other incoming data sample to
zero. This effectively halves the input
data rate and the output amplitude.
–10
GAIN (dB)
–20
–30
–40
DEC — Decimation Control
–50
When DEC is LOW and INT is HIGH
(Table 1), the output register is strobed on
every other rising edge of CLK (driven at
half the clock rate), decimating the output
data stream.
–60
–70
–80
0
0.1ƒS
0.2ƒS
0.3ƒS
0.4ƒS
0.5ƒS
FREQUENCY (NORMALIZED)
SIGNAL DEFINITIONS
Power
TABLE 1.
INT
DEC
MODE SELECTION
MODE
0
0
Pass-through*
Inputs
0
1
Interpolate
SI11–0 — Data Input
1
0
Decimate
1
1
Pass-through*
12-bit two’s complement data input
port. Data is latched into the register on
+5 V power supply. All pins must be the rising edge of CLK. The LSB is SI0
(Figure 2).
connected.
VCC and GND
Clock
Outputs
CLK — Master Clock
SO15-0 Data Output
*Input and output registers run at full
clock rate
The rising edge of CLK strobes all regis- The current 16-bit result is available on
ters. All timing specifications are refer- the SO15-0 outputs. The LF2242’s limiter
ensures that a valid full-scale (7FFF
enced to the rising edge of CLK.
positive or 8000 negative) output will be
generated in the event of an internal
SYNC — Synchronization Control
overflow. The LSB is SO0 (Figure 2).
Incoming data is synchronized by holding SYNC HIGH on CLKN, and then by
bringing SYNC LOW on CLKN+1 with
the first word of input data. SYNC is held
LOW until resynchronization is desired,
or it can be toggled at half the clock rate.
For interpolation (INT = LOW), input
data should be presented at the first rising edge of CLK for which SYNC is LOW
and then at every alternate rising edge of
CLK thereafter. SYNC is inactive if DEC
and INT are equal (pass-through mode).
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LF2242
DEVICES INCORPORATED
FIGURE 2.
12/16-bit Half-Band Interpolating/
Decimating Digital Filter
RND2-0 — Rounding Control
INPUT AND OUTPUT FORMATS
The rounding control inputs set the position of the effective LSB of the output data
by adding a rounding bit to the internal
bit position that is one below that specified by RND2-0. All bits below the effective LSB position are subsequently zeroed (Table 2).
Two’s Complement Input Format
11 10 9 8
–20 2–1 2–2 2–3
3 2 1 0
2–8 2–9 2–10 2–11
(Sign)
Two’s Complement Output Format (TCO = 1, Non-interpolate)
15 14 13 12
–20 2–1 2–2 2–3
3 2 1 0
2–12 2–13 2–14 2–15
TCO — Two’s Complement Format
Control
(Sign)
The TCO input determines the format of
the output data. When TCO is HIGH, the
output data is presented in two’s complement format. When TCO is LOW, the
data is in inverted offset binary format
(all output bits are inverted except the
MSB — the MSB is unchanged).
Two’s Complement Output Format (TCO = 1, Interpolate)
15 14 13 12
–21 20 2–1 2–2
3 2 1 0
2–11 2–12 2–13 2–14
(Sign)
Inverted Offset Binary Output Format (TCO = 0, Non-interpolate)
15 14 13 12
20 2–1 2–2 2–3
3 2 1 0
2–12 2–13 2–14 2–15
OE — Output Enable
(Sign)
When the OE signal is LOW, the current
data in the output register is available on
the SO15-0 pins. When OE is HIGH, the
outputs are in a high-impedance state.
Inverted Offset Binary Output Format (TCO = 0, Interpolate)
15 14 13 12
21 20 2–1 2–2
3 2 1 0
2–11 2–12 2–13 2–14
(Sign)
TABLE 2.
ROUNDING FORMAT
RND2-0
SO15
SO14
SO13
SO12
•••
SO8
SO7
SO6
SO5
SO4
SO3
SO2
SO1
SO0
000
X
X
X
X
•••
X
X
X
X
X
X
X
X
R
001
X
X
X
X
•••
X
X
X
X
X
X
X
R
0
010
X
X
X
X
•••
X
X
X
X
X
X
R
0
0
011
X
X
X
X
•••
X
X
X
X
X
R
0
0
0
100
X
X
X
X
•••
X
X
X
X
R
0
0
0
0
101
X
X
X
X
•••
X
X
X
R
0
0
0
0
0
110
X
X
X
X
•••
X
X
R
0
0
0
0
0
0
111
X
X
X
X
•••
X
R
0
0
0
0
0
0
0
'R' indicates the half-LSB rounded bit (effective LSB position)
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LF2242
DEVICES INCORPORATED
12/16-bit Half-Band Interpolating/
Decimating Digital Filter
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature ........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ............................................................................... –0.5 V to V CC + 0.5 V
Signal applied to high impedance output ...................................................................... –0.5 V to VCC + 0.5 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode
Temperature Range (Ambient)
Active Operation, Commercial
Active Operation, Industrial
Supply Voltage
0°C to +70°C
4.75 V ≤ VCC ≤ 5.25 V
-40°C to +85°C
4.75 V ≤ VCC ≤ 5.25 V
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol
Parameter
Test Condition
Min
VOH
Output High Voltage
VCC = Min., IOH = –2.0 mA
VOL
Output Low Voltage
VCC = Min., IOL = 4.0 mA
VIH
Input High Voltage
VIL
Input Low Voltage
(Note 3)
IIX
Input Current
IOZ
Typ
Max
2.4
Unit
V
0.4
V
2.0
VCC
V
0.0
0.8
V
Ground ≤ VIN ≤ VCC (Note 12)
±10
µA
Output Leakage Current
(Note 12)
±10
µA
ICC1
VCC Current, Dynamic
(Notes 5, 6)
80
mA
ICC2
VCC Current, Quiescent
(Note 7)
10
mA
CIN
Input Capacitance
TA = 25°C, f = 1 MHz
10
pF
COUT
Output Capacitance
TA = 25°C, f = 1 MHz
10
pF
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LF2242
DEVICES INCORPORATED
12/16-bit Half-Band Interpolating/
Decimating Digital Filter
SWITCHING CHARACTERISTICS
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)
LF2242–
33
25
Symbol
Parameter
Min
tCYC
Cycle Time
33
Max
Min
25
Max
tPW
Clock Pulse Width
10
10
tS
Input Setup Time
10
8
tH
Input Hold Time
0
0
tD
Output Delay
20
16
tDIS
Three-State Output Disable Delay (Note 11)
15
15
tENA
Three-State Output Enable Delay (Note 11)
15
15
SWITCHING WAVEFORMS: PASS-THROUGH MODE (INT = DEC)
1
2
3
7
8
9
10
CLK
tPW
tPW
SYNC
tH
SI11-0
N
N+1
N+2
tD
tS
HIGH IMPEDANCE
SO15-0
f(N)
tDIS
f(N+1)
f(N+2)
tENA
OE
Video Imaging Products
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LF2242
DEVICES INCORPORATED
12/16-bit Half-Band Interpolating/
Decimating Digital Filter
SWITCHING WAVEFORMS: INTERPOLATE MODE (INT = 0, DEC = 1)
1
2
3
7
8
9
10
CLK
tPW
tS
tPW
SYNC
SI11-0
N
N+2
tD
tH
HIGH IMPEDANCE
SO15-0
f(N)
tDIS
f(N+1)
f(N+2)
tENA
OE
SWITCHING WAVEFORMS: DECIMATE MODE (INT = 1, DEC = 0)
1
2
3
7
8
9
10
CLK
tPW
tS
tPW
SYNC
SI11-0
N
N+1
N+2
tD
tH
HIGH IMPEDANCE
SO15-0
f(N)
tDIS
f(N+2)
tENA
OE
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LF2242
DEVICES INCORPORATED
12/16-bit Half-Band Interpolating/
Decimating Digital Filter
NOTES
1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond
those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tDIS test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified IOH and IOL at an output
voltage of VOH min and VOL max
2. The products described by this spec- respectively. Alternatively, a diode
ification include internal circuitry de- bridge with upper and lower current
signed to protect the chip from damag- sources of I OH and I OL respectively,
ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be
cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF
less, conventional precautions should minimum, and may be distributed.
be observed during storage, handling,
and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current
stress values.
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
3. This device provides hard clamping of testing of this device. The following
transient undershoot and overshoot. In- measures are recommended:
put levels below ground or above VCC
will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be
VCC + 0.6 V. The device can withstand installed between VCC and Ground
indefinite operation with inputs in the leads as close to the Device Under Test
range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors
tion will not be adversely affected, how- should be installed between device VCC
ever, input current levels will be well in and the tester common, and device
excess of 100 mA.
ground and tester common.
4. Actual test conditions may vary from b. Ground and VCC supply planes
those designated but operation is guar- must be brought directly to the DUT
anteed as specified.
socket or contactor fingers.
5. Supply current for a given applica- c. Input voltages should be adjusted to
tion can be accurately approximated by: compensate for inductive ground and VCC
noise to maintain required DUT input
NCV2 F
levels relative to the DUT ground pin.
4
where
10. Each parameter is shown as a min-
11. For the tENA test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the tDIS test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
S1
DUT
IOL
VTH
CL
IOH
FIGURE B. THRESHOLD LEVELS
tENA
OE
Z
tDIS
1.5 V
1.5 V
3.5V Vth
0
1.5 V
1.5 V
Z
1
VOL*
VOH*
0.2 V
0.2 V
0
Z
1
Z
0V Vth
VOL* Measured VOL with IOH = –10mA and IOL = 10mA
VOH* Measured VOH with IOH = –10mA and IOL = 10mA
imum or maximum value. Input requirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter6. Tested with all outputs changing ev- nal system must supply at least that
ery cycle and no load, at a 20 MHz clock much time to meet the worst-case requirements of all parts. Responses from
rate.
the internal circuitry are specified from
7. Tested with all inputs within 0.1 V of the point of view of the device. Output
VCC or Ground, no load.
delay, for example, is specified as a
8. These parameters are guaranteed maximum since worst-case operation of
any device always provides data within
but not 100% tested.
that time.
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
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LF2242
DEVICES INCORPORATED
12/16-bit Half-Band Interpolating/
Decimating Digital Filter
ORDERING INFORMATION
44-pin
6 5 4 3 2 1 44 43 42 41 40
39
8
38
9
37
10
36
11
12
13
Top
View
35
34
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
GND
VCC
SI10
SI9
SI8
SI7
SI6
SI5
SI4
SI3
VCC
SO12
SO11
SO10
SO9
SO8
GND
VCC
SO7
SO6
SO5
SO4
Speed
1
2
3
4
5
6
7
8
9
10
11
Top
View
33
32
31
30
29
28
27
26
25
24
23
GND
VCC
SI10
SI9
SI8
SI7
SI6
SI5
SI4
SI3
VCC
12
13
14
15
16
17
18
19
20
21
22
7
SO3
SO2
SO1
SO0
RND2
RND1
RND0
SI0
SI1
SI2
GND
SO3
SO2
SO1
SO0
RND2
RND1
RND0
SI0
SI1
SI2
GND
SO12
SO11
SO10
SO9
SO8
GND
VCC
SO7
SO6
SO5
SO4
44
43
42
41
40
39
38
37
36
35
34
SO13
SO14
SO15
OE
TCO
DEC
INT
SYNC
CLK
GND
SI11
SO13
SO14
SO15
OE
TCO
DEC
INT
SYNC
CLK
GND
SI11
44-pin
Plastic J-Lead Chip Carrier
(J1)
Plastic Quad Flatpack
(Q4)
0°C to +70°C — COMMERCIAL SCREENING
33 ns
25 ns
LF2242JC33
LF2242JC25
LF2242QC33
LF2242QC25
–40°C to +85°C — COMMERCIAL SCREENING
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