Infineon HYS72D64020GR-7-A 2.5 v 184-pin registered ddr-i sdram module Datasheet

HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
2.5 V 184-pin Registered DDR-I SDRAM Modules
256MB, 512MB &1GByte Modules
PC1600 & PC2100
• 184-pin Registered 8-Byte Dual-In-Line
DDR-I SDRAM Module for PC and Server
main memory applications
• Auto Refresh (CBR) and Self Refresh
• One bank 32M × 72, 64M x 72, and two bank
64M x 72, 128M × 72 organization
• Re-drive for all input signals using register
and PLL devices.
• All inputs and outputs SSTL_2 compatible
• Serial Presence Detect with E2PROM
• JEDEC standard Double Data Rate
Synchronous DRAMs (DDR-I SDRAM) with a
single + 2.5 V (± 0.2 V) power supply
• Jedec standard MO-206 form factor:
133.35 mm (nom.) × 43.18 mm (nom.) × 4.00
mm (max.)
(6,80 mm max. with stacked components)
• Built with 256Mbit DDR-I SDRAMs in 66Lead TSOPII package
• Jedec standard reference layout:
Raw Cards A, B and C
• Programmable CAS Latency, Burst Length,
and Wrap Sequence (Sequential &
Interleave)
• Gold plated contacts
• Performance:
-7
-8
Component Speed Grade
DDR266A DDR200
Module Speed Grade
PC2100
Unit
PC1600
fCK
Clock Frequency (max.) @ CL = 2.5
143
125
MHz
fCK
Clock Frequency (max.) @ CL = 2
133
100
MHz
Description
The HYS 72Dxx0x0GR are industry standard 184-pin 8-byte Dual in-line Memory Modules (DIMMs)
organized as 32M × 72 (256MB), 64M × 72 (512MB) and 128M × 72 (1GB). The memory array is
designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and
address signals are re-driven on the DIMM using register devices and a PLL for the clock
distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM
timing. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial
presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes
are programmed with configuration data and the second 128 bytes are available to the customer.
INFINEON Technologies
1
2002-05-08 (revision 1.0)
HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
Ordering Information
Type
Compliance Code
Description
SDRAM
Technology
HYS 72D32000GR-7-A
PC2100R-20330-A1
one bank 256 MB Reg. DIMM
256 MBit (x8)
HYS 72D64000GR-7-A
PC2100R-20330-B1
one bank 512 MB Reg. DIMM
256 Mbit (x4)
HYS 72D64020GR-7-A
PC2100R-20330-A1
two banks 512 MB Reg. DIMM
256 MBit (x8)
HYS 72D128020GR-7-A
PC2100R-20330-C1
two banks 1 GByte Reg. DIMM
256 MBit (x4)
(stacked)
PC1600R-20220-A1
one bank 256 MB Reg. DIMM
256 MBit (x8)
PC2100 (CL=2):
PC1600 (CL=2):
HYS 72D32000GR-8-A
HYS 72D64000GR-8-A
PC1600R-20220-B1
one bank 512 MB Reg. DIMM
256 Mbit (x4)
HYS 72D64020GR-8-A
PC1600R-20220-A1
two banks 512 MB Reg. DIMM
256 MBit (x8)
HYS 72D128020GR-8-A
PC1600R-20220-C1
two banks 1 GByte Reg. DIMM
256 MBit (x4)
(stacked)
Note:
All part numbers end with a place code (not shown), designating the silicon-die revision. Reference
information available on request. Example: HYS 72D32000GR-8-A, indicating Rev.A die are used for
SDRAM components
The Compliance Code is printed on the module labels and describes the speed sort fe. “PC2100R”, the
latencies (f.e. “20330” means CAS latency = 2, trcd latency = 3 and trp latency =3 ) and the Raw Card
used for this module.
INFINEON Technologies
2
2002-05-08 (revision 1.0)
HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
Pin Definitions and Functions
A0 - A11,A12
Address Inputs
VDD
Power (+ 2.5 V)
(A12 for 256Mb & 512Mb based modules)
BA0, BA1
Bank Selects
VSS
Ground
DQ0 - DQ63
Data Input/Output
VDDQ
I/O Driver power supply
CB0 - CB7
Check Bits (x72 organization only)
VDDID
VDD Indentification flag
RAS
Row Address Strobe
VDDSPD
EEPROM power supply
CAS
Column Address Strobe
VREF
I/O reference supply
WE
Read/Write Input
SCL
Serial bus clock
CKE0, CKE1
Clock Enable
SDA
Serial bus data line
DQS0 - DQS8
SDRAM low data strobes
SA0 - SA2
slave address select
CK0, CK0
Differential Clock Input
NC
no connect
DM0 - DM8
DQS9 - DQS17
SDRAM low data mask/
high data strobes
DU
don’t use
CS0 - CS1
Chip Selects
RESET
Reset pin (forces register
inputs low) *)
*) for detailed description of the Power Up and Power Management on DDR Registered DIMMs see the
Application Note at the end of this datasheet
Address Format
Density
Organization
Memory
Banks
SDRAMs
# of
SDRAMs
# of row/bank/
columns bits
Refresh
Period
Interval
256 MB
32M x 72
1
32M x 8
9
13/2/10
8k
64 ms
7.8 µs
512 MB
64M × 72
1
64M × 4
18
13/2/11
8k
64 ms
7.8 µs
512 MB
64M x 72
2
32M x 8
18
13/2/10
8k
64 ms
7.8 µs
1 GB
128M × 72
2
64M × 4
36
13/2/11
8k
64 ms
7.8 µs
INFINEON Technologies
3
2002-05-08 (revision 1.0)
HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
Pin Configuration
PIN# Symbol
PIN#
Symbol
PIN#
1
VREF
48
A0
93
2
DQ0
49
CB2
94
3
VSS
50
VSS
95
4
DQ1
51
CB3
96
5
DQS0
52
BA1
97
6
DQ2
KEY
98
7
VDD
53
DQ32
99
8
DQ3
54
VDDQ
100
9
NC
55
DQ33
101
10
RESET
56
DQS4
102
11
VSS
57
DQ34
103
12
DQ8
58
VSS
104
13
DQ9
59
BA0
105
14
DQS1
60
DQ35
106
15
VDDQ
61
DQ40
107
16
DU
62
VDDQ
108
17
DU
63
WE
109
18
VSS
64
DQ41
110
19
DQ10
65
CAS
111
20
DQ11
66
VSS
112
21
CKE0
67
DQS5
113
22
VDDQ
68
DQ42
114
23
DQ16
69
DQ43
115
24
DQ17
70
VDD
116
25
DQS2
71
NC
117
26
VSS
72
DQ48
118
27
A9
73
DQ49
119
28
DQ18
74
VSS
120
29
A7
75
DU
121
30
VDDQ
76
DU
122
31
DQ19
77
VDDQ
123
32
A5
78
DQS6
124
33
DQ24
79
DQ50
125
34
VSS
80
DQ51
126
35
DQ25
81
VSS
127
36
DQS3
82
VDDID
128
37
A4
83
DQ56
129
38
VDD
84
DQ57
130
39
DQ26
85
VDD
131
40
DQ27
86
DQS7
132
41
A2
87
DQ58
133
42
VSS
88
DQ59
134
43
A1
89
VSS
135
44
CB0
90
NC
136
45
CB1
91
SDA
137
46
VDD
92
SCL
138
47
DQS8
139
Note: A12 is used for 256Mbit and 512Mbit based modules only
INFINEON Technologies
4
Symbol
VSS
DQ4
DQ5
VDDQ
DM0/DQS9
DQ6
DQ7
VSS
NC
NC
NC
VDDQ
DQ12
DQ13
DM1/DQS10
VDD
DQ14
DQ15
CKE1
VDDQ
NC
DQ20
NC / A12
VSS
DQ21
A11
DM2/DQS11
VDD
DQ22
A8
DQ23
VSS
A6
DQ28
DQ29
VDDQ
DM3/DQS12
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
CK0
VSS
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Symbol
DM8/DQS17
A10
CB6
VDDQ
CB7
KEY
VSS
DQ36
DQ37
VDD
DM4/DQS13
DQ38
DQ39
VSS
DQ44
RAS
DQ45
VDDQ
CS0
CS1
DM5/DQS14
VSS
DQ46
DQ47
NC
VDDQ
DQ52
DQ53
NC
VDD
DM6/DQS15
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7/DQS16
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
2002-05-08 (revision 1.0)
HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
RS0
DQS0
DM0/DQS9
DQS4
DM4/DQS13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D0
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
D2
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
RAS
CAS
CKE0
WE
PCK
PCK
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS
D5
CS
DQS
D6
CS
DQS
D3
CS DQS
D7
VDDSPD
EEPROM
VDD, V DDQ
D0 - D8
VREF
D0 - D8
Serial PD
R
E
G
I
S
T
E
R
A0-A12
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS
DQS7
DM7/DQS16
DQS8
DM8/DQS17
CS0
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D4
DQS6
DM6/DQS15
DQS3
DM3/DQS12
BA0-BA1
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
CS DQS
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS5
DM5/DQS14
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS
CS
D0 - D8
DQS
SDA
SCL
D8
A0
A1
A2
D0 - D8
V DDID
RS0 -> CS : SDRAMs D0-D8
Strap: see Note 4
Notes:
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D8
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, Adress and control resistors: 22 Ohms.
4. VDDID strap connections
STRAP OUT (OPEN): VDD = VDDQ
RA0-RA12 -> A0-A12: SDRAMs D0 - D8
RRAS -> RAS : SDRAMs D0 - D8
RCAS -> CAS : SDRAMs D0 - D8
RCKE0 -> CKE: SDRAMs D0 - D8
RWE -> WE : SDRAMs D0 - D8
CK0, CK 0 --------- PLL*
RESET
V SS
SA0 SA1 SA2
5. SDRAM placement alternates between the back
and front of the DIMM.
* Wire per Clock Loading Table/Wiring Diagrams
Block Diagram: One Bank 32Mb x 72 DDR-I SDRAM DIMM Module
HYS72D32000GR using x8 organized SDRAMs on Raw Card Version A
INFINEON Technologies
5
2002-05-08 (revision 1.0)
HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
RS1
RS0
DQS0
DM0/DQS9
DQS4
DM4/DQS13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
D0
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS
D9
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
CS
D4
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
D13
DQS5
DM5/DQS14
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS
D1
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS
D10
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
D2
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS8
DM8/DQS17
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D11
CS
DQS
D6
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
D3
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D12
CS DQS
D7
Serial PD
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CS DQS
D14
CS
DQS
D15
DQS7
DM7/DQS16
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS6
DM6/DQS15
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CS DQS
D5
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D8
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS
D16
V DDSPD
DQS
EEPROM
SDA
SCL
A0
A1
A2
D17
SA0 SA1 SA2
V DD, V DDQ
D0 - D17
VREF
D0 - D17
V SS
D0 - D17
V DDID
Strap: see Note 4
CK0, CK 0 --------- PLL*
CS0
CS1
BA0-BA1
A0-A12
RAS
CAS
CKE0
CKE1
WE
R
E
G
I
S
T
E
R
PCK
PCK
* Wire per Clock Loading Table/Wiring Diagrams
RS0 -> CS : SDRAM D0-D8
RS1 -> CS : SDRAM D9-D17
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D17
RA0-RA12 -> A0-A12: SDRAMs D0 - D17
RRAS -> RAS : SDRAMs D0 - D17
RCAS -> CAS : SDRAMs D0 - D17
RCKE0 -> CKE: SDRAMs D0 - D8
RCKE1 -> CKE: SDRAMs D9 - D17
RWE -> WE : SDRAMs D0 - D17
RESET
Notes:
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, Adress and control resistors: 22 Ohms.
4. VDDID strap connections
STRAP OUT (OPEN): VDD = VDDQ
5. SDRAM placement alternates between the back
and front of the DIMM.
Block Diagram: Two Bank 64Mb x 72 DDR-I SDRAM DIMM Modules
HYS 72D64020GR Using x8 Organized SDRAMs on Raw Card Version A
INFINEON Technologies
6
2002-05-08 (revision 1.0)
HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
VSS
RS0B
RS0A
DQS0
DM0/DQS9
DQS
DQ0
DQ1
DQ2
DQ3
I/O
I/O
I/O
I/O
DQ8
DQ9
DQ10
DQ11
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQ16
DQ17
DQ18
DQ19
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQ24
DQ25
DQ26
DQ27
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQ32
DQ33
DQ34
DQ35
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQ40
DQ41
DQ42
DQ43
CS
DQ48
DQ49
DQ50
DQ51
DQS
I/O 0
I/O 1
I/O 2
I/O 3
0
1
2
3
DM
CS
DQ4
DQ5
DQ6
DQ7
D0
DQS
CS
I/O 0
I/O 1
D9
I/O 2
I/O 3
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
DM1/DQS10
DQS1
DM
CS
DQ12
DQ13
DQ14
DQ15
D1
DQS2
CS
D10
DM2/DQS11
DQS
DM
DQ20
DQ21
DQ22
DQ23
D2
DQS3
CS
I/O 0
I/O 1
I/O 2
I/O 3
D11
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D12
DQS
CS
DM
DM3/DQS12
DM
DQ28
DQ29
DQ30
DQ31
D3
DQS4
DM4/DQS13
DM
DQ36
DQ37
DQ38
DQ39
D4
DQS5
DM
DM5/DQS14
DQ44
DQ45
DQ46
DQ47
D5
DQS6
DM6/DQS15
DM
DQ52
DQ53
DQ54
DQ55
D6
DQS7
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
DM
D13
VDDSPD
EEPROM
VDD, VDDQ
D0 - D17
VREF
D0 - D17
V SS
CS
DM
D0 - D17
V DDID
Strap: see Note 4
D14
Serial PD
CS
DQS
I/O 0
I/O 1
D15
I/O 2
I/O 3
DM
SDA
SCL
A0
A1
A2
SA0 SA1 SA2
DM7/DQS16
DQS
DQ56
DQ57
DQ58
DQ59
DQS8
I/O
I/O
I/O
I/O
CS0
WE
PCK
PCK
R
E
G
I
S
T
E
R
CS
DM
DQ60
DQ61
DQ62
DQ63
D7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CB0
CB1
CB2
CB3
BA0-BA1
A0-A11,A12
RAS
CAS
CKE0
0
1
2
3
CS
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM8/DQS17
D8
CB4
CB5
CB6
CB7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
Notes:
D16
CS
D17
DM
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, Adress and control resistors: 22 Ohms.
4. VDDID strap connections
STRAP OUT (OPEN): VDD = VDDQ
5. SDRAM placement alternates between the back
and front of the DIMM.
RS 0 -> CS : SDRAMs D0-D17
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D17
RA0-RA11,RA12 -> A0-A11,A12: SDRAMs D0 - D17
RRAS -> RAS : SDRAMs D0 - D17
RCAS -> CAS : SDRAMs D0 - D17
RCKE0A -> CKE: SDRAMs D0 - D8
RCKEB -> CKE: SDRAMs D9 - D17
CK0, CK 0 --------- PLL*
RWE -> WE : SDRAMs D0 - D17
* Wire per Clock Loading Table/Wiring Diagrams
RESET
Block Diagram: One Bank 64Mb x 72 DDR-I SDRAM DIMM Modules
HYS 72D64000GR Using x4 Organized SDRAMs on Raw Card Version B
INFINEON Technologies
7
2002-05-08 (revision 1.0)
HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
V SS
RS1
RS0
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQ8
DQ9
DQ10
DQ11
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
CS
D0
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
CS
DQ4
DQ5
DQ6
DQ7
D18
DQS1
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
D9
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
D27
DM1/DQS10
CS
DM
D1
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
DQ12
DQ13
DQ14
DQ15
D19
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
CS
D10
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
D28
DM2/DQS11
DQS2
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQ16
DQ17
DQ18
DQ19
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQ24
DQ25
DQ26
DQ27
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQ32
DQ33
DQ34
DQ35
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQ40
DQ41
DQ42
DQ43
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQ48
DQ49
DQ50
DQ51
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQ56
DQ57
DQ58
DQ59
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
CB0
CB1
CB2
CB3
DM
D2
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
DQ20
DQ21
DQ22
DQ23
D20
DQS3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
CS
D11
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D29
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D30
CS
DM
DM3/DQS12
DM
D3
DM
DQ28
DQ29
DQ30
DQ31
D21
DQS4
DM4/DQS13
DM
D4
DM
DQ36
DQ37
DQ38
DQ39
D22
DQS5
DM
D5
DM5/DQS14
DM
DQ44
DQ45
DQ46
DQ47
D23
DQS6
DM
D6
DM6/DQS15
DM
DQ52
DQ53
DQ54
DQ55
D24
DQS7
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
D12
DQS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D7
DM
DQ60
DQ61
DQ62
DQ63
D25
DQS8
D8
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
CS
D15
DM
CS
CB4
CB5
CB6
CB7
D26
CK0, CK 0 --------- PLL*
DQS
I/O 0
I/O 1
I/O 2
I/O 3
Serial PD
DM
CS
D17
CS
S
D32
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D33
DQS
I/O 0
I/O 1
I/O 2
I/O 3
V DDSPD
DM
DM
D31
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D16
DM8/DQS17
DM
DQS
DM
S
D14
DM7/DQS16
DM
DQS
DM
D13
CS
CS
CS
DM
DM
DM
D34
CS
DM
D35
EEPROM
* Wire per Clock Loading Table/Wiring Diagrams
SDA
CS0
RS0 -> CS : SDRAMs D0-D17
CS1
BA0-BA1
A0-A12
RAS
CAS
CKE0
CKE1
WE
PC
K
PC
K
R
E
G
I
S
T
E
R
SCL
A0
A1
A2
RS1 -> CS : SDRAMs D18 -D35
SA0 SA1 SA2
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D35
VDD,VDDQ
D0 - D35
VREF
D0 - D35
V SS
RA0-RA12 -> A0-A12: SDRAMs D0 - D35
RRAS -> RAS : SDRAMs D0 - D35
RCAS -> CAS : SDRAMs D0 - D35
Notes:
D0 - D35
V DDID
Strap: see Note 4
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, Adress and control resistors: 22 Ohms.
4. VDDID strap connections
STRAP OUT (OPEN): VDD = VDDQ
RCKE0 -> CKE: SDRAMs D0 - D17
RCKE1 -> CKE: SDRAMs D18 - D35
RWE -> WE : SDRAMs D0 - D35
RESET
5. SDRAM placement alternates between the back
and front of the DIMM.
Block Diagram: Two Bank 128Mb x 72 DDR-I SDRAM DIMM Modules
HYS 72D128020GR using x4 Organized SDRAMs on Raw Card Version C
INFINEON Technologies
8
2002-05-08 (revision 1.0)
HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
min.
max.
Unit
Input / Output voltage relative to VSS
VIN, VOUT
– 0.5
3.6
V
Power supply voltage on VDD /VDDQ to VSS
VDD, VDDQ
– 0.5
3.6
V
Storage temperature range
TSTG
-55
+150
o
Power dissipation (per SDRAM component)
PD
–
1
W
Data out current (short circuit)
IOS
–
50
mA
C
Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended operation conditions.
Exposure to higher than recommended voltage for extended periods of time affect device reliability
Supply Voltage Levels
Parameter
Symbol
Limit Values
min.
nom.
Unit
Notes
max.
Device Supply Voltage
VDD
2.3
2.5
2.7
V
-
Output Supply Voltage
VDDQ
2.3
2.5
2.7
V
1)
Input Reference Voltage
VREF
0.49 x VDDQ
0.5 x VDDQ
0.51 x VDDQ
V
2)
Termination Voltage
VTT
VREF – 0.04
VREF
VREF + 0.04
V
3)
EEPROM supply voltage
VDDSPD
2.3
2.5
3.6
V
1 Under all conditions, VDDQ must be less than or equal to VDD
2 Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).
VREF is also expected to track noise variations in VDDQ .
3 VTT of the transmitting device must track VREF of the receiving device.
DC Operating Conditions (SSTL_2 Inputs)
(VDDQ = 2.5 V, TA = 70 °C, Voltage Referenced to VSS)
Parameter
Symbol
Limit Values
min.
Unit
Notes
max.
DC Input Logic High
VIH (DC)
VREF + 0.15
VDDQ + 0.3
V
1)
DC Input Logic Low
VIL (DC)
– 0.30
VREF – 0.15
V
–
Input Leakage Current
IIL
–5
5
µA
1)
Output Leakage Current
IOL
–5
5
µA
2)
1) The relationship between the VDDQ of the driving device and the VREF of the receiving device is what
determines noise margins. However, in the case of VIH (max) (input overdrive), it is the VDDQ of the receiving
device that is referenced. In the case where a device is implemented such that it supports SSTL_2 inputs but
has no SSTL_2 outputs (such as a translator), and therefore no VDDQ supply voltage connection, inputs must
tolerate input overdrive to 3.0 V (High corner VDDQ + 300 mV).
2) For any pin under test input of 0 V ≤ VIN ≤ VDDQ + 0.3 V. Values are shown per DDR-SDRAM component.
INFINEON Technologies
9
2002-05-08 (revision 1.0)
HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
Operating, Standby and Refresh Currents (PC1600)
256MB
x72
1bank
-8
512MB
x72
1bank
-8
512MB
x72
2bank
-8
1GB
x72
2bank
-8
Unit
Notes
Symbol
Parameter/Condition
MAX
MAX
MAX
MAX
IDD0
Operating Current: one bank; active / precharge; tRC = tRC MIN; tCK =
tCK MIN; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles
810
1620
1305
2610
mA
1, 4
IDD1
Operating Current: one bank; active/read/precharge; Burst = 4;
Refer to the following page for detailed test conditions.
900
1800
1395
2790
mA
1, 3, 4
IDD2P
Precharge Power-Down Standby Current: all banks idle; power-down
mode; CKE <= VIL MAX; tCK = tCK MIN
135
270
270
540
mA
2, 4
IDD2F
Precharge Floating Standby Current: /CS >= VIH MIN, all banks idle;
CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs
changing once per clock cycle, VIN = VREF for DQ, DQS and DM.
315
630
630
1260
mA
2, 4
IDD2Q
Precharge Quiet Standby Current: /CS >= VIH MIN, all banks idle;
CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs
stable at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM.
315
630
630
1260
mA
2, 4
IDD3P
Active Power-Down Standby Current: one bank active; power-down
mode; CKE <= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and
DM.
135
270
270
540
mA
2, 4
IDD3N
Active Standby Current: one bank active; active / precharge;CS >= VIH
MIN; CKE >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ, DM, and
DQS inputs changing twice per clock cycle; address and control inputs
changing once per clock cycle
495
990
990
1980
mA
2, 4
IDD4R
Operating Current: one bank active; Burst = 2; reads; continuous burst;
address and control inputs changing once per clock cycle; 50% of data
outputs changing on every clock edge; CL = 2 for DDR200, and
DDR266A, CL=3 for DDR333; tCK = tCK MIN; IOUT = 0mA
1350
2700
1845
3690
mA
1, 3, 4
IDD4W
Operating Current: one bank active; Burst = 2; writes; continuous burst;
address and control inputs changing once per clock cycle; 50% of data
outputs changing on every clock edge; CL = 2 for DDR200, and
DDR266A, CL=3 for DDR333; tCK = tCK MIN
1170
2340
1665
3330
mA
1, 4
5
IDD5
Auto-Refresh Current: tRC = tRFC MIN, distributed refresh
1620
3240
2115
4230
mA
1, 4
IDD6
Self-Refresh Current: CKE <= 0.2V; external clock on; tCK = tCK MIN
27
54
54
108
mA
2, 4
IDD7
Operating Current: four bank; four bank interleaving with BL=4;
Refer to the following page for detailed test conditions.
2025
4050
2520
5040
mA
1, 3, 4
1. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component]
for single bank modules (n: number of components per module bank)
n * IDDx[component] + n * IDD3N[component]
for two bank modules (n: number of components per module bank)
2. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component]
for single bank modules (n: number of components per module bank)
2 * n * IDDx[component]
for two bank modules (n: number of components per module bank)
3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions
4. DRAM component currents only: module IDD will be measured differently depending upon register and PLL operation currents
5. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C
INFINEON Technologies
10
2002-05-08 (revision 1.0)
HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
Operating, Standby and Refresh Currents (PC2100)
256MB
x72
1bank
-7
512MB
x72
1bank
-7
512MB
x72
2bank
-7
1GB
x72
2bank
-7
Unit
Notes
Symbol
Parameter/Condition
MAX
MAX
MAX
MAX
IDD0
Operating Current: one bank; active / precharge; tRC = tRC MIN; tCK =
tCK MIN; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles
900
1800
1485
2970
mA
1, 4
IDD1
Operating Current: one bank; active/read/precharge; Burst = 4;
Refer to the following page for detailed test conditions.
1080
2160
1665
3330
mA
1, 3, 4
IDD2P
Precharge Power-Down Standby Current: all banks idle; power-down
mode; CKE <= VIL MAX; tCK = tCK MIN
180
360
360
720
mA
2, 4
IDD2F
Precharge Floating Standby Current: /CS >= VIH MIN, all banks idle;
CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs
changing once per clock cycle, VIN = VREF for DQ, DQS and DM.
360
720
720
1440
mA
2, 4
IDD2Q
Precharge Quiet Standby Current: /CS >= VIH MIN, all banks idle;
CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs
stable at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM.
360
720
720
1440
mA
2, 4
IDD3P
Active Power-Down Standby Current: one bank active; power-down
mode; CKE <= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and
DM.
180
360
360
720
mA
2, 4
IDD3N
Active Standby Current: one bank active; active / precharge;CS >= VIH
MIN; CKE >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ, DM, and
DQS inputs changing twice per clock cycle; address and control inputs
changing once per clock cycle
585
1170
1170
2340
mA
2, 4
IDD4R
Operating Current: one bank active; Burst = 2; reads; continuous burst;
address and control inputs changing once per clock cycle; 50% of data
outputs changing on every clock edge; CL = 2 for DDR200, and
DDR266A, CL=3 for DDR333; tCK = tCK MIN; IOUT = 0mA
1710
3420
2295
4590
mA
1, 3, 4
IDD4W
Operating Current: one bank active; Burst = 2; writes; continuous burst;
address and control inputs changing once per clock cycle; 50% of data
outputs changing on every clock edge; CL = 2 for DDR200, and
DDR266A, CL=3 for DDR333; tCK = tCK MIN
1530
3060
2115
4230
mA
1, 4
5
IDD5
Auto-Refresh Current: tRC = tRFC MIN, distributed refresh
1710
3420
2295
4590
mA
1, 4
IDD6
Self-Refresh Current: CKE <= 0.2V; external clock on; tCK = tCK MIN
27
54
54
108
mA
2, 4
IDD7
Operating Current: four bank; four bank interleaving with BL=4;
Refer to the following page for detailed test conditions.
2205
4410
2790
5580
mA
1, 3, 4
1. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component]
for single bank modules (n: number of components per module bank)
n * IDDx[component] + n * IDD3N[component]
for two bank modules (n: number of components per module bank)
2. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component]
for single bank modules (n: number of components per module bank)
2 * n * IDDx[component]
for two bank modules (n: number of components per module bank)
3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions
4. DRAM component currents only: module IDD will be measured differently depending upon register and PLL operation currents
5. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C
INFINEON Technologies
11
2002-05-08 (revision 1.0)
HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
Electrical Characteristics & AC Timing for DDR-I components
(for reference only)
(0 °C ≤ TA ≤ 70 °C; V DDQ = 2.5V ± 0.2V; V DD = 2.5V ± 0.2V)
Symbol
tAC
tDQSCK
DDR266A
-7
Parameter
DDR200
-8
Unit
Notes
+ 0.8
ns
1-4
+ 0.8
ns
1-4
Min
Max
Min
Max
DQ output access time from CK/CK
− 0.75
+ 0.75
− 0.8
DQS output access time from CK/CK
− 0.75
+ 0.75
− 0.8
tCH
CK high-level width
0.45
0.55
0.45
0.55
tCK
1-4
tCL
CK low-level width
0.45
0.55
0.45
0.55
tHP
Clock Half Period
tCK
tCK
Clock cycle time
tCK
1-4
min (tCL, tCH)
min (tCL, tCH)
ns
1-4
CL = 2.5
7
12
8
12
ns
1-4
CL = 2.0
7.5
12
10
12
ns
1-4
tDH
DQ and DM input hold time
0.5
0.6
ns
1-4
tDS
DQ and DM input setup time
0.5
0.6
ns
1-4
tIPW
Control and Addr. input pulse width (each
input)
2.2
2.5
ns
1, 10
tDIPW
DQ and DM input pulse width (each input)
1.75
2
ns
1-4,
11
tHZ
Data-out high-impedence time from CK/CK
− 0.75
+ 0.75
− 0.8
+ 0.8
ns
1-4, 5
tLZ
Data-out low-impedence time from CK/CK
− 0.75
+ 0.75
− 0.8
+ 0.8
ns
1-4, 5
0.75
1.25
0.75
1.25
tCK
1-4
+ 0.5
+ 0.6
ns
1-4
+ 0.75
+ 1.0
ns
1-4
tDQSS
Write command to 1st DQS latching transition
tDQSQ
DQS-DQ skew
(for DQS & associated DQ signals)
tQHS
Data hold skew factor
tQH
Data Output hold time from DQS
tDQSL,H DQS input low (high) pulse width (write cycle)
tHP-t QHS
tHP-tQHS
ns
1-4
0.35
0.35
tCK
1-4
tDSS
DQS falling edge to CK setup time (write
cycle)
0.2
0.2
tCK
1-4
tDSH
DQS falling edge hold time from CK (write
cycle)
0.2
0.2
tCK
1-4
tMRD
Mode register set command cycle time
14
16
ns
1-4
tWPRES
Write preamble setup time
0
0
ns
1-4, 7
tWPST
Write postamble
0.40
tCK
1-4, 6
tWPRE
Write preamble
0.25
0.25
tCK
1-4
fast slew rate
0.9
1.1
ns
slow slew rate
1.0
1.1
ns
fast slew rate
0.9
1.1
ns
tIS
tIH
Address and control
input setup time
Address and control
input hold time
slow slew rate
0.60
1.0
0.40
0.60
1.1
2-4,
10,11
ns
tRPRE
Read preamble
0.9
1.1
0.9
1.1
tCK
1-4
tRPST
Read postamble
0.40
0.60
0.40
0.60
tCK
1-4
tRAS
Active to Precharge command
45
120,000
50
120,000
ns
1-4
tRC
Active to Active/Auto-refresh command period
65
ns
1-4
INFINEON Technologies
12
70
2002-05-08 (revision 1.0)
HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
Electrical Characteristics & AC Timing for DDR-I components
(for reference only)
(0 °C ≤ TA ≤ 70 °C; V DDQ = 2.5V ± 0.2V; V DD = 2.5V ± 0.2V)
Symbol
Parameter
DDR266A
-7
Min
Max
DDR200
-8
Min
Unit
Notes
ns
1-4
Max
tRFC
Auto-refresh to Active/Auto-refresh
command period
tRCD
Active to Read or Write delay
20
20
ns
1-4
tRP
Precharge command period
20
20
ns
1-4
tRRD
Active bank A to Active bank B command
15
15
ns
1-4
tWR
Write recovery time
15
15
ns
1-4
tDAL
Auto precharge write recovery
+ precharge time
tCK
1-4,9
1-4
75
80
(twr/tck) + (trp/tck)
tWTR
Internal write to read command delay
1
1
tCK
tXSNR
Exit self-refresh to non-read command
75
80
ns
1-4
tXSRD
Exit self-refresh to read command
200
200
tCK
1-4
tREFI
Average Periodic
Refresh Interval
µs
1-4, 8
7.8
256Mbit based
7.8
1. Input slew rate >=1V/ns for DDR266 and = 1V/ns for DDR200.
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross:
the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are >= 1.0 V/ns.
3. Inputs are not recognized as valid until VREF stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT.
5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or
begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for
this parameter, but system performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or
before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning
from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning
from HIGH to LOW at this time, depending on tDQSS.
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the
actual system clock cycle time.
10. These parameters guarantee device timing, but they are not necessarily tested on each device
11. Fast slew rate >= 1.0 V/ns , slow slew rate >= 0.5 V/ns and < 1V/ns for command/address and CK & CK
slew rate >1.0 V/ns, measured between VOH(ac) and VOL(ac)
INFINEON Technologies
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Registered DDR-I SDRAM-Modules
SPD Codes
Byte#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Description
Number of SPD Bytes
Total Bytes in Serial PD
Memory Type
Number of Row Addresses
Number of Column Addresses
Number of DIMM Banks
Module Data Width
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL = 2.5
Access Time from Clock at CL = 2.5
DIMM Config
Refresh Rate/Type
SDRAM Width, Primary
Error Checking SDRAM Data Width
Minimum Clock Delay for Back-to-Back
Random Column Address
Burst Length Supported
Number of SDRAM Banks
Supported CAS Latencies
CS Latencies
WE Latencies
SDRAM DIMM Module Attributes
22
SDRAM Device Attributes: General
23
24
25
26
27
28
29
30
31
32
33
34
35
36-40
41
42
43
44
45
46-61
62
63
64
Min. Clock Cycle Time at CAS Latency = 2
Access Time from Clock for CL = 2
Minimum Clock Cycle Time at CL = 1.5
Access Time from Clock at CL = 1.5
Minimum Row Precharge Time
Minimum Row Act. to Row Act. Delay tRRD
Minimum RAS to CAS Delay tRCD
Minimum RAS Pulse Width tRAS
Module Bank Density (per bank)
Addr. and Command Setup Time
Addr. and Command Hold Time
Data Input Setup Time
Data Input Hold Time
Superset Information
Minimum Core Cycle Time tRC
Min. Auto Refresh Cmd Cycle Time tRFC
Maximum Clock Cycle Time tck
Max. DQS-DQ Skew tDQSQ
X-Factor tQHS
Superset Information
SPD Revision
Checksum for Bytes 0 - 62
Manufacturers JEDEC ID Code
128
256
DDR-SDRAM
13
10 / 11
1 /2
x72
0
SSTL_2.5
7ns / 8ns
0.75ns / 0.8ns
ECC
Self-Refresh, 7.8ms
x8 / x4
na
1GB
x72
2bank
-8
HEX
80
08
07
0D
0B
02
48
00
04
80
80
02
82
04
04
tccd = 1 CLK
01
01
01
01
01
01
01
01
2, 4 & 8
4
CAS latency = 2 & 2.5
CS latency = 0
Write latency = 1
registered
Concurrent Auto
Precharge
7.5ns / 10ns
0.75ns / 0.8ns
not supported
not supported
20ns
15ns
20ns
45ns / 50ns
256MByte / 512MByte
0.9ns / 1.1ns
0.9ns / 1.1ns
0.5ns / 0.6ns
0.5ns / 0.6ns
–
65ns / 70ns
75ns / 80ns
12ns
0.5ns / 0.6ns
0.75ns / 1.0ns
–
Revision 0.0
–
–
0E
04
0C
01
02
26
0E
04
0C
01
02
26
0E
04
0C
01
02
26
0E
04
0C
01
02
26
0E
04
0C
01
02
26
0E
04
0C
01
02
26
0E
04
0C
01
02
26
0E
04
0C
01
02
26
C0
C0
C0
C0
C0
C0
C0
C0
75
75
00
00
50
3C
50
2D
40
90
90
50
50
00
41
4B
30
32
75
00
00
CA
C1
INFINEON
A0
80
00
00
50
3C
50
32
40
B0
B0
60
60
00
46
50
30
3C
A0
00
00
BF
C1
INFINEON
75
75
00
00
50
3C
50
2D
80
90
90
50
50
00
41
4B
30
32
75
00
00
03
C1
INFINEON
A0
80
00
00
50
3C
50
32
80
B0
B0
60
60
00
46
50
30
3C
A0
00
00
F8
C1
INFINEON
75
75
00
00
50
3C
50
2D
40
90
90
50
50
00
41
4B
30
32
75
00
00
CB
C1
INFINEON
A0
80
00
00
50
3C
50
32
40
B0
B0
60
60
00
46
50
30
3C
A0
00
00
C0
C1
INFINEON
75
75
00
00
50
3C
50
2D
80
90
90
50
50
00
41
4B
30
32
75
00
00
04
C1
INFINEON
A0
80
00
00
50
3C
50
32
80
B0
B0
60
60
00
46
50
30
3C
A0
00
00
F9
C1
INFINEON
65-71
Manufacturer
–
72
73-90
91-92
93-94
95-98
99-127
Module Assembly Location
Module Part Number
Module Revision Code
Module Manufacturing Date
Module Serial Number
–
–
–
–
–
–
–
INFINEON Technologies
256MB 256MB 512MB 512MB 512MB 512MB 1GB
x72
x72
x72
x72
x72
x72
x72
1bank 1bank 1bank 1bank 2bank 2bank 2bank
-7
-8
-7
-8
-7
-8
-7
HEX
HEX
HEX
HEX
HEX
HEX
HEX
80
80
80
80
80
80
80
08
08
08
08
08
08
08
07
07
07
07
07
07
07
0D
0D
0D
0D
0D
0D
0D
0A
0A
0B
0B
0A
0A
0B
01
01
01
01
02
02
02
48
48
48
48
48
48
48
00
00
00
00
00
00
00
04
04
04
04
04
04
04
70
80
70
80
70
80
70
75
80
75
80
75
80
75
02
02
02
02
02
02
02
82
82
82
82
82
82
82
08
08
04
04
08
08
04
08
08
04
04
08
08
04
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2002-05-08 (revision 1.0)
HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
Package Outlines Raw Card A (one memory bank)
Module Package
DDR-I Registered DIMM Modules Raw Card A
256MByte Modules (one physical bank, 9 components)
Front View
4.0 max.
43.43 +- 0.13
133.35 -+ 0.15
4.0
2.3 typ.
Register
PLL
Register
53
52
pin 1
92
64.77
1.27 -+ 0.1
49.53
2.3 typ.
6.62
Backside View
144
145
184
2.5D
10.0
17.80
pin 93
3
3
Detail of Contacts B
Detail of Contacts A
2.5 -+ 0.20
0.20 +- 0.15
6.35
3.8 typ.
0.9R
1+- 0.05
1.27
1.8
2.175
L-DIM-184-10, Raw Card A, one
bank
INFINEON Technologies
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2002-05-08 (revision 1.0)
HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
Package Outlines Raw Card A (two memory banks)
Module Package
DDR-I Registered DIMM Modules Raw Card A
512MByte Module (two physical banks, 18 components)
Front View
4.0 max.
43.43 +- 0.13
133.35 +- 0.15
4.0
2.3 typ.
Register
PLL
Register
52
pin 1
92
53
64.77
1.27 -+ 0.1
49.53
2.3 typ.
6.62
Backside View
144
145
184
2.5D
10.0
17.80
pin 93
3
3
Detail of Contacts B
6.35
2.5 +- 0.20
0.20 -+ 0.15
Detail of Contacts A
3.8 typ.
0.9R
1 -+ 0.05
1.27
1.8
2.175
L-DIM-184-10, Raw Card A, two
banks
INFINEON Technologies
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HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
Package Outlines Raw Card B
Module Package
DDR-I Registered DIMM Modules Raw Card B
512MByte Modules
(one physical bank, 18 components)
Front View
4.0 max.
43.43 -+ 0.13
133.35 -+ 0.15
4.0
2.3 typ.
Register
PLL
Register
52
pin 1
92
53
64.77
1.27 +- 0.1
49.53
2.3 typ.
6.62
Backside View
144
145
184
2.5D
10.0
17.80
pin 93
3
3
Detail of Contacts B
6.35
2.5 +- 0.20
0.20 -+ 0.15
Detail of Contacts A
3.8 typ.
0.9R
1 -+ 0.05
1.27
1.8
2.175
L-DIM-184-8, Raw Card
B
INFINEON Technologies
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2002-05-08 (revision 1.0)
HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
Package Outlines Raw Card C
Module Package
DDR-I Registered DIMM Modules Raw Card C
1 GByte Modules (two physical banks, 36 components)
Front View
6.8 max.
43.43 -+ 0.13
133.35 +- 0.15
4.0
2.3 typ.
Register
PLL
Register
52
pin 1
92
53
64.77
1.27 -+ 0.1
49.53
2.3 typ.
6.62
Backside View
144
145
184
2.5D
10.0
17.80
pin 93
3
3
Detail of Contacts B
6.35
2.5 +- 0.20
0.20 -+ 0.15
Detail of Contacts A
3.8 typ.
0.9R
1 -+ 0.05
1.27
1.8
2.175
L-DIM-184-11, Raw Card
C
INFINEON Technologies
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2002-05-08 (revision 1.0)
HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
APPLICATION NOTE:
Power Up and Power Management on DDR Registered DIMMs
(according to JEDEC ballot JC-42.5 Item 1173)
184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up
and to minimize power consumption during low power mode. One feature is externally controlled via a systemgenerated RESET signal; the second is based on module detection of the input clocks. These enhancements
permit the modules to power up with SDRAM outputs in a High-Z state (eliminating risk of high current dissipations and/or dotted I/Os), and result in the powering-down of module support devices (registers and PhaseLocked Loop) when the memory is in Self-Refresh mode.
The new RESET pin controls power dissipation on the module’s registers and ensures that CKE and other
SDRAM inputs are maintained at a valid ‘low’ level during power-up and self refresh. When RESET is at a low
level, all the register outputs are forced to a low level, and all differential register input receivers are powered
down, resulting in very low register power consumption. The RESET pin, located on DIMM tab #10, is driven
from the system as an asynchronous signal according to the attached details. Using this function also permits the
system and DIMM clocks to be stopped during memory Self Refresh operation, while ensuring that the SDRAMs
stay in Self Refresh mode.
The function for RESET is as follows:
Register
Outputs
Register Inputs
RESET
CK
CK
Data in (D)
Data out (Q)
H
Rising
Falling
H
H
H
Rising
Falling
L
L
H
L or H
L or H
X
Qo
H
High Z
High Z
X
Illegal input
conditions
L
X or Hi-Z
X or Hi-Z
X or Hi-Z
L
X : Don’t care, Hi-Z : High Impedance, Qo: Data latched at the previous of CK
risning and CK falling
As described in the table above, a low on the RESET input ensures that the Clock Enable (CKE) signal(s) are
maintained low at the SDRAM pins (CKE being one of the 'Q' signals at the register output). Holding CKE low
maintains a high impedance state on the SDRAM DQ, DQS and DM outputs — where they will remain until activated by a valid ‘read’ cycle. CKE low also maintains SDRAMs in Self Refresh mode when applicable.
The DDR PLL devices automatically detect clock activity above 20MHz. When an input clock frequency of
20MHz or greater is detected, the PLL begins operation and initiates clock frequency lock (the minimum operating frequency at which all specifications will be met is 95MHz). If the clock input frequency drops below 20MHz
(actual detect frequency will vary by vendor), the PLL VCO (Voltage Controlled Oscillator) is stopped, outputs are
INFINEON Technologies
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HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
made High-Z, and the differential inputs are powered down — resulting in a total PLL current consumption of less
than 1mA. Use of this low power PLL function makes the use of the PLL RESET (or G pin) unnecessary, and it is
tied inactive on the DIMM.
This application note describes the required and optional system sequences associated with the DDR Registered DIMM 'RESET' function. It is important to note that all references to CKE refer to both CKE0 and CKE1 for
a 2-bank DIMM. Because RESET applies to all DIMM register devices, it is therefore not possible to uniquely
control CKE to one physical DIMM bank through the use of the RESET pin.
Power-Up Sequence with RESET — Required
1. The system sets RESET at a valid low level.
This is the preferred default state during power-up. This input condition forces all register outputs to a low
state independent of the condition on the register inputs (data and clock), ensuring that CKE is at a stable
low-level at the DDR SDRAMs.
2. The power supplies should be initialized according to the JEDEC-approved initialization sequence for DDR
SDRAMs.
3. Stabilization of Clocks to the SDRAM
The system must drive clocks to the application frequency (PLL operation is not assured until the input clock
reaches 20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices,
and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM
PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. When
a stable clock is present at the SDRAM input (driven from the PLL), the DDR SDRAM requires 200 µsec prior
to SDRAM operation.
4. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector).
CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command (with
CKE low), as this is the first command defined by the JEDEC initialization sequence (ideally this would be a
‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs to be consistent
with the state of the register outputs.
5. The system switches RESET to a logic ‘high’ level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
setting the RESET timing in relation to a specific clock edge is not required (during this period, register inputs
must remain stable).
6. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows their clock receivers, data input receivers, and output drivers
sufficient time to be turned on and become stable. During this time the system must maintain the valid logic
levels described in step 5. It is also a functional requirement that the registers maintain a low state at the CKE
outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time
(t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to
accept an input signal, is specified in the register and DIMM do-umentation.
7. The system can begin the JEDEC-defined DDR SDRAM power-up sequence (according to the JEDECpproved initialization sequence).
Self Refresh Entry (RESET low, clocks powered off) — Optional
Self Refresh can be used to retain data in DDR SDRAM DIMMs even if the rest of the system is powered down
and the clocks are off. This mode allows the DDR SDRAMs on the DIMM to retain data without external clocking.
Self Refresh mode is an ideal time to utilize the RESET pin, as this can reduce register power consumption
(RESET low deactivates register CK and CK, data input receivers, and data output drivers).
INFINEON Technologies
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Registered DDR-I SDRAM-Modules
1. The system applies Self Refresh entry command.
(CKE→Low, CS→Low, RAS → Low, CAS→ Low, WE→ High)
Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a
Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input
conditions to the SDRAM are Don’t Cares— with the exception of CKE.
2. The system sets RESET at a valid low level.
This input condition forces all register outputs to a low state, independent of the condition on the registerm
inputs (data and clock), and ensures that CKE, and all other control and address signals, are a stable lowlevel at the DDR SDRAMs. Since the RESET signal is asynchronous, setting the RESET timing in relation to
a specific clock edge is not required.
3. The system turns off clock inputs to the DIMM. (Optional)
a. In order to reduce DIMM PLL current, the clock inputs to the DIMM are turned off, resulting in High-Z clock
inputs to both the SDRAMs and the registers. This must be done after the RESET deactivate time of the register (t (INACT) ). The deactivate time defines the time in which the clocks and the control and address signals must maintain valid levels after RESET low has been applied and is specified in the register and DIMM
documentation.
b. The system may release DIMM address and control inputs to High-Z.
This can be done after the RESET deactivate time of the register. The deactivate time defines the time in
which the clocks and the control and the address signals must maintain valid levels after RESET low has
been applied. It is highly recommended that CKE continue to remain low during this operation.
4. The DIMM is in lowest power Self Refresh mode.
Self Refresh Exit (RESET low, clocks powered off) — Optional
1. Stabilization of Clocks to the SDRAM.
The system must drive clocks to the application frequency (PLL operation is not assured until the input clock
reaches ~20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices,
and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM
PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds.
2. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector).
CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command (with
CKE low), as this is the first command defined by the JEDEC Self Refresh Exit sequence (ideally this would
be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs, to be consistent with the state of the register outputs.
3. The system switches RESET to a logic ‘high’ level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
RESET timing relationship to a specific clock edge is not required (during this period, register inputs must
remain stable).
4. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels
described in Step 2. It is also a functional requirement that the registers maintain a low state at the CKE outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time (t
(ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to
accept an input signal, is specified in the register and DIMM do-umentation.
5. System can begin the JEDEC-defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry (RESET low, clocks running) — Optional
INFINEON Technologies
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Registered DDR-I SDRAM-Modules
Although keeping the clocks running increases power consumption from the on-DIMM PLL during self refresh,
this is an alternate operating mode for these DIMMs.
1. System enters Self Refresh entry command.
(CKE→ Low, CS→ Low, RAS→ Low, CAS→ Low, WE→ High)
Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a
Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input
conditions to the SDRAM are Don’t Cares — with the exception of CKE.
2. The system sets RESET at a valid low level.
This input condition forces all register outputs to a low state, independent of the condition on the data and
clock register inputs, and ensures that CKE is a stable low-level at the DDR SDRAMs.
3. The system may release DIMM address and control inputs to High-Z.
This can be done after the RESET deactivate time of the register (t (INACT) ). The deactivate time describes
the time in which the clocks and the control and the address signals must maintain valid levels after RESET
low has been applied. It is highly recommended that CKE continue to remain low during the operation.
4. The DIMM is in a low power, Self Refresh mode.
Self Refresh Exit (RESET low, clocks running) — Optional
1. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector).
CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command (with
CKE low), as this is the first command defined by the Self Refresh Exit sequence (ideally this would be a
‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs to be consistent
with the state of the register outputs.
2. The system switches RESET to a logic 'high' level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
it does not need to be tied to a particular clock edge (during this period, register inputs must continue to
remain stable).
3. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels
described in Step 1. It is also a functional requirement that the registers maintain a low state at the CKE outputs in order to guarantee that the DDR SDRAMs continue to receive a low level on CKE. This activation
time, from asynchronous switching of RESET from low to high, until the registers are stable and ready to
accept an input signal, is t (ACT ) as specified in the register and DIMM documentation.
4. The system can begin JEDEC defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry/Exit (RESET high, clocks running) — Optional
As this sequence does not involve the use of the RESET function, the JEDEC standard SDRAM specification
explains in detail the method for entering and exiting Self Refresh for this case.
Self Refresh Entry (RESET high, clocks powered off) — Not Permissible
In order to maintain a valid low level on the register output, it is required that either the clocks be running and the
system drive a low level on CKE, or the clocks are powered off and RESET is asserted low according to the
INFINEON Technologies
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Registered DDR-I SDRAM-Modules
sequence defined in this application note. In the case where RESET remains high and the clocks are powered
off, the PLL drives a High-Z clock input into the register clock input. Without the low level on RESET an unknown
DIMM state will result.
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Registered DDR-I SDRAM-Modules
INFINEON Technologies
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Registered DDR-I SDRAM-Modules
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