Holt HI-8282ACDT Arinc 429 serial transmitter and dual receiver Datasheet

HI-8282A
July 2013
ARINC 429
Serial Transmitter and Dual Receiver
FEATURES
GENERAL DESCRIPTION
The HI-8282A is a silicon gate CMOS device for interfacing
the ARINC 429 serial data bus to a 16-bit parallel data bus.
Two receivers and an independent transmitter are
provided. The receiver input circuitry and logic are
designed to meet the ARINC 429 specifications for loading,
level detection, timing, and protocol. The transmitter
section provides the ARINC 429 communication protocol.
Additional interface circuitry such as the Holt HI-8585,
HI-8586 or HI-3182 is required to translate the 5 volt logic
outputs to ARINC 429 drive levels.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The data bus interfaces with
CMOS and TTL.
• ARINC specification 429 compliant
• Alternate source to Intersil HS-3282 in all
ARINC 429 applications
• Small footprint 44-pin QFP package option
• 16-Bit parallel data bus
• Direct receiver interface to ARINC bus
• Timing control 10 times the data rate
• Selectable data clocks
• Automatic transmitter data timing
• 8 word transmit FIFO
• Receiver error rejection per ARINC
specification 429
Timing of all the circuitry begins with the master clock input,
CLK. For ARINC 429 applications, the master clock
frequency is 1 MHz.
• Self test mode
Each independent receiver monitors the data stream with a
sampling rate 10 times the data rate. The sampling rate is
software selectable at either 1MHz or 125KHz. The results
of a parity check are available as the 32nd ARINC bit. The
HI-8282A examines the null and data timings and will reject
erroneous patterns. For example, with a 125 KHz clock
selection, the data frequency must be between 10.4 KHz
and 15.6 KHz.
• Industrial & extended temperature ranges
APPLICATIONS
• Low power, single 5 volt supply
- N/C
- 429DI2(B)
- 429DI2(A)
- 429DI1(B)
- 429DI1(A)
- VCC
- N/C
- MR
- TXCLK
- CLK
- N/C
PIN CONFIGURATION (Top View)
44
43
42
41
40
39
38
37
36
35
34
The transmitter has a First In, First Out (FIFO) memory to
store 8 ARINC words for transmission. The data rate of the
transmitter is software selectable by dividing the master
clock, CLK, by either 10 or 80. The master clock is used to
set the timing of the ARINC transmission within the required
resolution.
• Parity functions
N/C - 1
D/R1 - 2
D/R2 - 3
SEL - 4
EN1 - 5
EN2 - 6
BD15 - 7
BD14 - 8
BD13 - 9
BD12 - 10
BD11 - 11
HI-8282APQI
HI-8282APQT
HI-8282APQM
33 - N/C
32 - N/C
31 - CWSTRX
30 - ENTX
29 - 429DO
28 - 429DO
27 - TX/R
26 - PL2
25 - PL1
24 - BD00
23 - BD01
N/C - 12
BD10 - 13
BD09 - 14
BD08 - 15
BD07 - 16
BD06 - 17
GND - 18
BD05 - 19
BD04 - 20
BD03 - 21
BD02 - 22
• Avionics data communication
• Serial to parallel conversion
• Parallel to serial conversion
44-Pin Plastic Quad Flat Pack (PQFP)
(See page 10 for additional Package Pin Configurations)
((DS8282A Rev. H)
HOLT INTEGRATED CIRCUITS
www.holtic.com
07/13
HI-8282A
PIN DESCRIPTION
SYMBOL
FUNCTION
DESCRIPTION
VCC
POWER
429DI1 (A)
INPUT
+5V ±5%
ARINC receiver 1 positive input
429DI1 (B)
INPUT
ARINC receiver 1 negative input
429DI2 (A)
INPUT
ARINC receiver 2 positive input
429DI2 (B)
INPUT
ARINC receiver 2 negative input
D/R1
OUTPUT
Receiver 1 data ready flag
D/R2
OUTPUT
Receiver 2 data ready flag
SEL
INPUT
Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2)
EN1
INPUT
Data Bus control, enables receiver 1 data to outputs
EN2
INPUT
Data Bus control, enables receiver 2 data to outputs if EN1 is high
BD15
I/O
Data Bus
BD14
I/O
Data Bus
BD13
I/O
Data Bus
BD12
I/O
Data Bus
BD11
I/O
Data Bus
BD10
I/O
Data Bus
BD09
I/O
Data Bus
BD08
I/O
Data Bus
BD07
I/O
Data Bus
BD06
I/O
Data Bus
GND
POWER
BD05
I/O
Data Bus
0V
BD04
I/O
Data Bus
BD03
I/O
Data Bus
BD02
I/O
Data Bus
BD01
I/O
Data Bus
BD00
I/O
Data Bus
PL1
INPUT
Latch enable for byte 1 entered from data bus to transmitter FIFO.
PL2
INPUT
TX/R
OUTPUT
Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow PL1.
Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high
after transmission and FIFO empty.
429DO
OUTPUT
"ONES" data output from transmitter.
429DO
OUTPUT
"ZEROES" data output from transmitter.
ENTX
INPUT
Enable Transmission
CWSTR
INPUT
Clock for control word register
CLK
INPUT
Master Clock input
TX CLK
OUTPUT
MR
INPUT
Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80.
Master Reset, active low
HOLT INTEGRATED CIRCUITS
2
HI-8282A
FUNCTIONAL DESCRIPTION
ARINC 429 DATA FORMAT
The following table shows the bit positions in exchanging data with the
receiver or transmitter. ARINC bit 1 is the first bit transmitted or
received.
CONTROL WORD REGISTER
The HI-8282A contains 10 data flip flops whose D inputs are connected to the data bus and clocks connected to CWSTR. Each
flip flop provides options to the user as follows:
BYTE 1
DATA
BUS
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ARINC
BIT
13 12 11 10
DATA
BUS
PIN
FUNCTION CONTROL
BDO5
SELF TEST
0 = ENABLE
If enabled, an internal connection
is made passing 429DO and
429DO to the receiver logic inputs
BDO6
RECEIVER 1
DECODER
1 = ENABLE
If enabled, ARINC bits 9 and,
10 must match the next two
control word bits
BDO7
-
-
If Receiver 1 Decoder is
enabled, the ARINC bit 9
must match this bit
THE RECEIVERS
Figure 1 shows the input circuit for each receiver. The ARINC 429
specification requires the following detection levels:
DESCRIPTION
BDO8
-
-
If Receiver 1 Decoder is
enabled, the ARINC bit 10
must match this bit
BDO9
RECEIVER 2
DECODER
1 = ENABLE
If enabled, ARINC bits 9 and
10 must match the next two
control word bits
BD10
-
-
If Receiver 2 Decoder is
enabled, then ARINC bit 9
must match this bit
BD11
-
-
BD12
INVERT
XMTR
PARITY
1 = ENABLE
Logic 0 enables normal odd parity
and Logic 1 enables even parity
output in transmitter 32nd bit
XMTR DATA
CLK SELECT
0 = ÷10
1 = ÷80
CLK is divided either by 10 or
80 to obtain XMTR data clock
RCVR DTA
CLK SELECT
0 = ÷10
1 = ÷80
CLK is divided either by 10 or
80 to obtain RCVR data clock
BD13
BD14
vcc
If Receiver 2 Decoder is
enabled, then ARINC bit 10
must match this bit
DIFFERENTIAL
AMPLIFIERS
429DI1(A)
OR
429DI2(A)
COMPARATORS
ONES
vcc
GND
NULL
ZEROES
429DI1(B)
OR
429DI2(B)
GND
FIGURE 1. ARINC RECEIVER INPUT
9
31 30 32
1
2
3
4
5
6
7
8
BYTE 2
DATA
BUS
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ARINC
BIT
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
ARINC BUS INTERFACE
STATE
ONE
NULL
ZERO
DIFFERENTIAL VOLTAGE
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
The HI-8282A guarantees recognition of these levels with a common
mode Voltage with respect to GND less than ±5V for the worst case
condition (4.75V supply and 13v signal level).
Design tolerances guarantee detection of the above levels, so the
actual acceptance ranges are slightly larger. If the ARINC signal is
out of the actual acceptance ranges, including the nulls, the chip
rejects the data.
HI-8282A-10
The HI-8282A-10 option is similar to the HI-8282A with the exception
that it allows an external 10K to 15K ohm resistor to be added in
series with each ARINC input without affecting the ARINC input
thresholds. This option is especially useful in applications where
lightning protection circuitry is also required.
Each side of the ARINC bus must be connected through a 10K to 15K
ohm series resistor in order for the chip to detect the correct ARINC
levels. The typical 10 volt differential signal is translated and input to
a window comparator and latch. The comparator levels are set so
that with the external 10K to 15K ohm resistors, they are just below
the standard 6.5 V minimum ARINC data threshold and just above
the 2.5 V maximum ARINC null threshold.
The receivers of the HI-8282A-10, when used with external
15K ohm resistors, will withstand DO-160F, Level 3, waveforms 3,
4, 5A and 5B pin injection. No additional lightning protection circuit
is necessary.
Please refer to the Holt AN-300 Application Note for additional
information and recommendations on lightning protection of Holt
Line Drivers and Receivers.
HOLT INTEGRATED CIRCUITS
3
HI-8282A
FUNCTIONAL DESCRIPTION (cont.)
RECEIVER LOGIC OPERATION
Figure 2 is a block diagram showing each receiver’s logic.
4. The Word Gap timer samples the Null shift register every
10 input clocks (80 for low speed) after the last data bit of a
valid reception. If the Null is present, the Word Gap counter
is incremented. A count of 3 enables the next reception.
RECEIVER PARITY
BIT TIMING
ARINC 429 specifies the following timing for received data:
HIGH SPEED
100K BPS ± 1%
1.5 ± 0.5 µsec
1.5 ± 0.5 µsec
5 µsec ± 5%
BIT RATE
PULSE RISE TIME
PULSE FALL TIME
PULSE WIDTH
LOW SPEED
12K -14.5K BPS
10 ± 5 µsec
10 ± 5 µsec
34.5 - 41.7 µsec
The HI-8282A accepts signals meeting these specifications and rejects signals outside these tolerances using the method described
here:
1. The timing logic requires an accurate 1.0 MHz clock
source. Less than 0.1% error is recommended.
2. The sampling shift registers are 10 bits long and must
show three consecutive Ones, Zeros or Nulls to be considered valid data. To qualify data bits, One or Zero in the upper
bits of the sampling shift register must be followed by Null in
the lower bits within the data bit time. A word gap Null requires three consecutive Nulls in both the upper and lower
bits of the sampling shift register. This guarantees the minimum pulse width.
3. Each data bit must follow its predecessor by not less than
8 samples and not more than 12 samples. In this manner the
bit rate is checked. With exactly 1 MHz input clock frequency,
the acceptable data bit rates are as follows:
HIGH SPEED
LOW SPEED
83K BPS
125K BPS
10.4K BPS
15.6K BPS
DATA BIT RATE MIN
DATA BIT RATE MAX
The 32nd bit of received ARINC words stored in the receive FIFO
is used as a Parity Flag indicating whether good Odd parity is received from the incoming ARINC word.
Odd Parity Received
The parity bit is reset to indicate correct parity was received
and the resulting word is then written to the receive FIFO.
Even Parity Received
The receiver sets the 32nd bit to a “1”, indicating a parity error
and the resulting word is then written to the receive FIFO.
Therefore, the 32nd bit retrieved from the receiver FIFO will always be a “0” when valid (odd parity) ARINC 429 words are received.
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). If the receiver decoder is enabled and
the 9th and 10th ARINC bits match the control word program bits
or if the receiver decoder is disabled, then EOS clocks the data
ready flag flip flop to a "1", D/R1 or D/R2 (or both) will go low. The
data flag for a receiver remains low until after both ARINC bytes
from that receiver are retrieved. This is accomplished by first activating EN with SEL, the byte selector, low to retrieve the first byte
and then activating EN with SEL high to retrieve the second byte.
EN1 retrieves data from receiver 1 and EN2 retrieves data from receiver 2.
If another ARINC word is received and a new EOS occurs before
the two bytes are retrieved, the data is overwritten by the new
word.
TO PINS
SEL
MUX
CONTROL
EN
32 TO 16 DRIVER
CLOCK
OPTION
CONTROL
BIT BD14
D/R
DECODER
CONTROL
BITS
/
CLOCK
LATCH
ENABLE
CONTROL
32 BIT LATCH
BITS 9 & 10
32 BIT SHIFT REGISTER
DATA
PARITY
CHECK
32ND
BIT
BIT
COUNTER
AND
END OF
SEQUENCE
BIT CLOCK
EOS
ONES
CLK
EOS
WORD GAP
WORD GAP
TIMER
SHIFT REGISTER
BIT CLOCK
END
START
NULL
SHIFT REGISTER
ZEROS
SHIFT REGISTER
SEQUENCE
CONTROL
ERROR
ERROR
DETECTION
FIGURE 2. RECEIVER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
4
CLOCK
HI-8282A
FUNCTIONAL DESCRIPTION (cont.)
BD12 control word bit is set low, the 32nd bit transmitted will
make parity odd. If the control bit is high, the parity is even.
TRANSMITTER
SELF TEST
A block diagram of the transmitter section is shown in Figure 3.
If the BD05 control word bit is set low, 429DO or 429DO are
internally connected to the receivers inputs, bypassing the
interface circuitry. Data to Receiver 1 is as transmitted and data to
Recevier 2 is the complement. 429DO and 429DO outputs remain
active during self test.
FIFO OPERATION
The FIFO is loaded sequentially by first pulsing PL1 to load byte 1
and then PL2 to load byte 2. The control logic automatically loads
the 31 bit word in the next available position of the FIFO. If TX/R,
the transmitter ready flag, is high (FIFO empty), then 8 words,
each 31 bits long, may be loaded. If TX/R is low, then only the
available positions may be loaded. If all 8 positions are full, the
FIFO ignores further attempts to load data.
DATA TRANSMISSION
When ENTX goes high, enabling transmission, the FIFO
positions are incremented with the top register loading into the
data transmission shift register. Within 2.5 data clocks the first
data bit appears at either 429DO or 429DO. The 31 bits in the
data transmission shift register are presented sequentially to the
outputs in the ARINC 429 format with the following timing:
ARINC DATA BIT TIME
DATA BIT TIME
NULL BIT TIME
WORD GAP TIME
HIGH SPEED
10 Clocks
5 Clocks
5 Clocks
40 Clocks
LOW SPEED
80 Clocks
40 Clocks
40 Clocks
320 Clocks
The word counter detects when all loaded positions are transmitted and sets the transmitter ready flag, TX/R, high.
TRANSMITTER PARITY
The parity generator counts the ONES in the 31-bit word. If the
SYSTEM OPERATION
The two receivers are independent of the transmitter. Therefore,
control of data exchanges is strictly at the option of the user. The
only restrictions are:
1. The received data may be overwritten if not retrieved
within one ARINC word cycle.
2. The FIFO can store 8 words maximum and ignores
attempts to load addition data if full.
3. Byte 1 of the transmitter data must be loaded first.
4. Either byte of the received data may be retrieved first.
Both bytes must be retrieved to clear the data ready flag.
5. After ENTX, transmission enable, goes high it cannot go
low until TX/R, transmitter ready flag, goes high. Otherwise,
one ARINC word is lost during transmission.
MASTER RESET (MR)
Upon Master Reset, data transmission and reception are
immediately terminated, the transmit FIFO and receivers
cleared as are the transmit and receive flags. The Control Word
register is not affected by a Master Reset.
BIT BD12
31 BIT PARALLEL
LOAD SHIFT REGISTER
BIT CLOCK
DATA AND
NULL TIMER
SEQUENCER
PARITY
GENERATOR
429DO
BIT
AND
WORD GAP
COUNTER
WORD CLOCK
8 X 31 FIFO
429DO
START
SEQUENCE
ADDRESS
WORD COUNTER
AND
FIFO CONTROL
LOAD
TX/R
ENTX
INCREMENT
WORD COUNT
FIFO
LOADING
SEQUENCER
PL1
PL2
DATA BUS
DATA
CLOCK
DATA CLOCK
DIVIDER
CONTROL BIT BD13
FIGURE 3. TRANSMITTER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
5
CLK
TX CLK
HI-8282A
FUNCTIONAL DESCRIPTION (cont.)
word byte onto the data bus. By strobing PL2 at the same time as
EN, the second data word byte is also transferred to the Transmit
FIFO. The data word is now ready for transmission, according to
the parity programmed into the Control Word register.
REPEATER OPERATION
Repeater mode of operation allows a data word received by the
HI-8282 to be placed directly into the Transmit FIFO for
transmission. After a 32-bit word has been shifted into the
receiver shift register, the D/R flag goes low. A logic "0" is placed
on the SEL line and EN is strobed. This is the same procedure as
for normal receiver operation, placing the lower byte (16) of the
data word on the data bus. By strobing PL1 at the same time as
EN, the byte is also transferred into the Transmit FIFO. SEL is
then taken high and EN is strobed again to place the upper data
In normal (non-repeater) operation, either byte of the received
data word may be read first by using the SEL input. During
repeater operation however, data word lower byte must always be
read first. While the data is being read, it is loading concurrently
into the Transmit FIFO, which always loads lower byte first.
TIMING DIAGRAMS
DATA RATE - EXAMPLE PATTERN
429DO
ARINC BIT
429DO
DATA
NULL
DATA
DATA
NULL
BIT 1
NEXT WORD
WORD GAP
BIT 32
BIT 31
BIT 30
NULL
LOADING CONTROL WORD
VALID
DATA BUS
tCWSET
tCWHLD
CWSTR
tCWSTR
RECEIVER OPERATON
ARINC DATA
BIT 31
DATA READY FLAG
BIT 32
D/R
tEND/R
tD/R
BYTE SELECT
SEL
DON'T CARE
DON'T CARE
tSELEN
ENABLE BYTE ON BUS
tENSEL
DON'T CARE
tEN
tSELEN
tENSEL
EN
tENEN
tDATAEN
tD/REN
tDATAEN
BYTE 1 VALID
DATA BUS
tENDATA
HOLT INTEGRATED CIRCUITS
6
BYTE 2 VALID
tENDATA
HI-8282A
TIMING DIAGRAMS (cont.)
TRANSMITTER OPERATION
BYTE 2 VALID
BYTE 1 VALID
DATA BUS
tDWSET
tDWSET
tDWHLD
tDWHLD
PL1
tPL12
tPL
PL2
tPL12
tPL
tTX/R
TX/R
TRANSMITTING DATA
PL2
tDTX/R
tPL2EN
TX/R
ENTX
ARINC BIT
tENDAT
429DO
or
429DO
tENTX/R
DATA
BIT 1
DATA
BIT 32
DATA
BIT 2
REPEATER OPERATION TIMING
429DI
BIT 32
tEND/R
D/R
tD/R
tD/REN
tEN
tENEN
tEN
EN
tSELEN
SEL
tENSEL
DON'T CARE
DON'T CARE
tENPL
tSELEN
tPLEN
tENSEL
PL1
tPLEN
tENPL
PL2
tTX/R
TX/R
tTX/REN
tENTX/R
ENTX
tDTX/R
tENDAT
BIT 1
429DO
BIT 32
tNULL
HOLT INTEGRATED CIRCUITS
7
HI-8282A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Vcc
Voltage at ARINC Inputs
Voltage at any other pin
-0.3V to +7V
Power Dissipation
500mW
-120V to +120V Operating Temperature Range: (Industrial)
(Extended)
-0.3V to Vcc +0.3V
DC Current Drain per input pin
10mA
Storage Temperature Range:
-40°C to +85°C
-55°C to +125°C
-65°C to +150°C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Vcc = 5V ±5%, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
ARINC INPUTS
-
CONDITIONS
SYMBOL
LIMITS
UNIT
MIN
TYP
MAX
6.5
-13.0
-2.5
10.0
-10.0
0
13.0
-6.5
2.5
27
27
429DI1 (A), 429DI1 (B), 429DI2 (A) & 429DI2 (B)
Differential Input Voltage:
ONE
ZERO
NULL
Input Resistance:
Input Current:
VIH
VIL
VNUL
ARINC Input Pins: Common
mode voltage less than ±5V
with respect to GND
Differential
To GND
To Vcc
RI
RG
RH
12
12
12
Input Sink
Input Source
IIH
IIL
-450
Differential
To GND
To Vcc
CI
CG
CH
Input Voltage HI
Input Voltage LO
VIH
VIL
Input Sink
Input Source
IIH
IIL
Input Capacitance:
(Guaranteed but not tested)
Pins 2 to 3, 4 to 5
V
V
V
KW
KW
KW
200
µA
µA
20
20
20
pF
pF
pF
0.7
V
V
BI-DIRECTIONAL INPUTS - BD00 through BD15
Input Voltage:
Input Current:
2.1
1.5
-1.5
µA
µA
ALL OTHER INPUTS - SEL, EN1, EN2, PL1, PL2, ENTX, CWSTR, CLK & MR
Input Voltage:
Input Current:
Input Voltage HI
Input Voltage LO
VIH
VIL
Input Sink
Input Source
IIH
IIL
3.5
0.7
10
-20
V
V
µA
µA
OUTPUTS - D/R1, D/R2, BD00 through BD15, TX/R, 429DO, 429DO & TX CLK
Output Voltage:
Logic "1" Output Voltage
Logic "0" Output Voltage
VOH
VOL
IOH = -1.5mA
IOL = 2.6mA
2.7
Output Current:
(Bi-directional Pins)
Output Sink
Output Source
IOL
IOH
VOUT = 0.4V
VOUT = VCC - 0.4V
3.0
1.1
mA
mA
Output Current:
(All Other Outputs)
Output Sink
Output Source
IOL
IOH
VOUT = 0.4V
VOUT = VCC - 0.4V
2.6
1.1
mA
mA
Output Capacitance:
0.4
V
V
CO
15
pF
Standby Supply Current:
ICC1
20
mA
Operating Supply Current:
ICC2
20
mA
SUPPLY INPUT - VCC
HOLT INTEGRATED CIRCUITS
8
HI-8282A
AC ELECTRICAL CHARACTERISTICS
Vcc = 5V, GND = 0V, TA = Operating Temperature Range and fclk = 1MHz +0.1% with 60/40 duty cycle
PARAMETER
SYMBOL
LIMITS
MIN
TYP
MAX
UNITS
CONTROL WORD TIMING
Pulse Width - CWSTR
Setup - DATA BUS Valid to CWSTR HIGH
Hold - CWSTR HIGH to DATA BUS Hi-Z
tCWSTR
tCWSET
tCWHLD
130
130
0
ns
ns
ns
RECEIVER TIMING
Delay - Start ARINC 32nd Bit to D/R LOW: High Speed
Low Speed
tD/R
tD/R
16
128
µs
µs
200
ns
ns
Delay - D/R LOW to EN L0W
Delay - EN LOW to D/R HIGH
tD/REN
tEND/R
0
Setup - SEL to EN L0W
Hold - SEL to EN HIGH
tSELEN
tENSEL
20
20
Delay - EN L0W to DATA BUS Valid
Delay - EN HIGH to DATA BUS Hi-Z
tENDATA
tDATAEN
Pulse Width - EN1 or EN2
Spacing - EN HIGH to next EN L0W
tEN
tENEN
200
50
ns
ns
tPL
200
ns
tDWSET
tDWHLD
110
10
ns
ns
Spacing - PL1 or PL2
tPL12
0
ns
Delay - PL2 HIGH to TX/R LOW
tTX/R
Spacing - PL2 HIGH to ENTX HIGH
tPL2EN
ns
ns
200
30
ns
ns
FIFO TIMING
Pulse Width - PL1 or PL2
Setup - DATA BUS Valid to PL HIGH
Hold - PL HIGH to DATA BUS Hi-Z
840
ns
TRANSMISSION TIMING
Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): High Speed
Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): Low Speed
0
tENDAT
tENDAT
µs
25
200
400
µs
µs
Delay - 32nd ARINC Bit to TX/R HIGH
tDTX/R
Spacing - TX/R HIGH to ENTX L0W
tENTX/R
0
ns
ns
Delay - EN LOW to PL LOW
tENPL
0
ns
Hold - PL HIGH to EN HIGH
tPLEN
0
ns
tTX/REN
0
ns
tMR
200
ns
REPEATER OPERATION TIMING
Delay - TX/R LOW to ENTX HIGH
Master Reset Pulse Width
ARINC Data Rate and Bit Timing
± 1%
HOLT INTEGRATED CIRCUITS
9
HI-8282A
ADDITIONAL HI-8282A PIN CONFIGURATIONS
(See page 1 for the 44-pin Plastic Quad Flat Pack )
44-PIN PLASTIC PLCC
44-PIN J-LEAD CERQUAD
HI-8282APJI
HI-8282APJT
HI-8282APJM
44-PIN CERAMIC LCC
HI-8282ACJI
HI-8282ACJT
HI-8282ACJM
40-PIN CERAMIC SIDE BRAZED DIP
Vcc
1
40
NC
(REC. 1 INPUT) 429DI1(A)
2
39
MR
(REC.1 INPUT) 429DI1(B)
3
38
TX CLK (XMIT CLOCK OUT)
(REC. 2 INPUT) 429DI2(A)
4
37
CLK
(REC. 2 INPUT) 429DI2(B)
5
36
NC
(REC.1 DATA FLAG) D/R1
6
35
NC
(REC.2 DATA FLAG) D/R2
7
34
CWSTR (CONTROL WORD STROBE)
8
33
ENTX
(REC. BYTE SELECT)
SEL
(MASTER RESET)
(MASTER CLK IN)
(ENABLE XMIT)
(REC. 1 OUTPUT ENABLE) EN1
9
32
429DO (XMIT DATA)
(REC. 2 OUTPUT ENABLE) EN2
10
31
429DO (XMIT DATA)
BD15
11
30
TX/R
BD14
12
29
PL2
(XMIT BYTE 2 LE)
BD13
13
28
PL1
(XMIT BYTE 1 LE)
BD12
14
27
BD00
HI-8282ACLI
HI-8282CLT
HI-8282CLM
BD11
15
26
BD01
BD10
16
25
BD02
BD09
17
24
BD03
BD08
18
23
BD04
BD07
19
22
BD05
20
21
GND
BD06
(XMIT READY FLAG)
HI-8282ACDI / CDT / CDM
HOLT INTEGRATED CIRCUITS
10
HI-8282A
ORDERING INFORMATION
HI - 8282A Cx x -xx (Ceramic)
PART
NUMBER
INPUT SERIES RESISTANCE
BUILT-IN
REQUIRED EXTERNALLY
No dash number
35 Kohm
0
-10 (Note 1)
25 Kohm
10K to 15K ohm
PART
NUMBER
TEMPERATURE
RANGE
FLOW
BURN
IN
LEAD
FINISH
I
-40°C TO +85°C
I
NO
Gold
T
-55°C TO +125°C
T
NO
Gold
M
-55°C TO +125°C
M
YES
PART
NUMBER
Tin / Lead (Sn / Pb) Solder
PACKAGE
DESCRIPTION
CD
40 PIN CERAMIC SIDE BRAZED DIP (40C)
CJ
44 PIN J-LEAD CERQUAD (44U)
CL
44 PIN CERAMIC LEADLESS CHIP CARRIER (44S)
HI - 8282A Px x x -xx (Plastic)
PART
NUMBER
INPUT SERIES RESISTANCE
BUILT-IN
REQUIRED EXTERNALLY
No dash number
35 Kohm
0
-10 (Note 1)
25 Kohm
10K to 15K ohm
PART
NUMBER
Blank
F
PART
NUMBER
LEAD
FINISH
Tin / Lead (Sn / Pb) Solder
100% Matte Tin (Pb-free, RoHS compliant)
TEMPERATURE
RANGE
FLOW
BURN
IN
I
-40°C TO +85°C
I
NO
T
-55°C TO +125°C
T
NO
M
-55°C TO +125°C
M
YES
PART
NUMBER
PACKAGE
DESCRIPTION
PJ
44 PIN PLASTIC J-LEAD PLCC (44J)
PQ
44 PIN PLASTIC QUAD FLAT PACK (44PTQS)
NOTES:
1. The -10 configuration requires an external 10K to 15K ohm resistor in series with each ARINC input to
guarantee specified voltage thresholds. The 15K ohm resistors are required to withstand DO-160F, Level 3,
Waveforms 3, 4 , 5A & 5B pin injection.
HOLT INTEGRATED CIRCUITS
11
HI-8282A
REVISION HISTORY
Revision
Date
Description of Change
DS8282A, Rev. G
Rev. H
02/01/09 Clarified the “T” temperature range. Clarified series resistance values for “-10” devices.
07/30/13 Updated Bit Timing, Receiver Parity and QFP package information. Changed “hi-temp”
operating conditions to “extended”. Update Voltage at ARINC input pins from +/-29V to
+/-120V.
HOLT INTEGRATED CIRCUITS
12
HI-8282A PACKAGE DIMENSIONS
inches (millimeters)
40-PIN CERAMIC SIDE-BRAZED DIP
Package Type: 40C
2.020
max
(51.308)
.595 ±.010
(15.113 ±.254)
.610 ±.010
(15.494 ±.254)
.050
typ
(1.270)
.225
max
(5.715)
.085 ±.009
(2.159 ±.229)
.600 ±.010
(15.240 ±.254)
.125 min
(3.175)
.100
BSC
(2.54)
.018
typ
(.457)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
.010 +.002/-.001
(.254 +.051/-.025)
inches (millimeters)
44-PIN J-LEAD CERQUAD
Package Type: 44U
2 1 44 43
.620 ±.012
(15.748 ±.305)
.688 ±.005 max
(17.475 ±.127) SQ.
.650 ±.010
(16.510 ±.254)
SQ.
.200
max
(5.080)
.039 ±.005
(.990 ±.127)
.019 ±.002
(.483 ± .051)
.050
BSC
(1.270)
.100 ±.007
(2.540 ±.178)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
HOLT INTEGRATED CIRCUITS
13
HI-8282A PACKAGE DIMENSIONS
inches (millimeters)
44-PIN PLASTIC PLCC
Package Type: 44J
PIN NO. 1
PIN NO. 1 IDENT
.045 x 45°
.045 x 45°
.050
(1.27) BSC
.690 ±.005
(17.526 ±.127)
SQ.
.653 ±.004
(16.586 ±.102)
SQ.
.031±.005
(.787 ±.127)
.017 ±.004
(.432 ±.102)
See Detail A
.010 ± .001
(.254 ± .03)
.173 ±.008
(4.394 ±.203)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
.020
(.508) min
.610 ±.020
(15.494±.508)
DETAIL A
R .035±.010
(.889 ±.254)
inches (millimeters)
44-PIN PLASTIC QUAD FLAT PACK (PQFP)
Package Type:
44PMQS
.009 MAX.
(.23)
.0315
BSC
(.80)
.394 ± .004
(10.0 ± .10)
SQ.
.520 ± .010
(13.20 ± .25)
SQ.
.014 ± .003
(.37 ± .08)
.035 ± .006
(.88 ± .15)
.012
R MAX.
(.30)
See Detail A
.096
MAX.
(2.45)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
.079 ± .008
(2.0 ± .20)
.005
R MIN. Detail A
(.13)
HOLT INTEGRATED CIRCUITS
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0° £ Q £ 7°
HI-8282A PACKAGE DIMENSIONS
inches (millimeters)
44-PIN CERAMIC LEADLESS CHIP CARRIER
Package Type: 44S
.020
INDEX
(.508)
.040 x 45°
3 PLCS
(1.016 x 45°)
PIN 1
.075 ±.004
(1.905 ±.101)
.050 ± 0. 05
(1.270 ±.127)
.651 ±.011
(16.535 ±.279)
SQ.
.050
BSC
(1.270)
.025 ±.003
(.635 ±.076)
.009R ± .006
(.229R ±.152)
.092 ± 0. 28
(2.336 ±.711)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
HOLT INTEGRATED CIRCUITS
15
.326 ±.006
(8.280 ±.152)
PIN 1