Infineon HYB25D256161CE 16m x 16 double data rate graphics dram Datasheet

D a t a s h e et , R e v . 1 . 0 , F e b . 2 00 4
HYB25D256161CE-5
HYB25D256161CE-4
1 6 M x 1 6 D o u b l e D a t a R a t e G r a p h ic s D R A M
D D R SG R A M
Green Product
M e m or y P r o du c t s
N e v e r
s t o p
t h i n k i n g .
Edition 2004-02
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
D a t a s h e et , R e v . 1 . 0 , F e b . 2 00 4
HYB25D256161CE-5
HYB25D256161CE-4
1 6 M x 1 6 D o u b l e D a t a R a t e G r a p h ic s D R A M
D D R SG R A M
Green Product
M e m or y P r o du c t s
N e v e r
s t o p
t h i n k i n g .
HYB25D256161CE-5
HYB25D256161CE-4
Revision History:
Rev.1.0
Previous Version:
V0.92
Page
Subjects (major changes since last revision)
all
Editorial changes
2004-02
2003-12-22
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Template: mp_a4_v2.0_2003-06-06.fm
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.3
3.3.1
3.3.2
3.4
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.6
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DLL Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bank/Row Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
14
14
15
15
16
17
17
17
18
21
21
22
27
41
42
47
4
4.1
4.2
4.3
4.4
4.4.1
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Normal Strength Pull-down and Pull-up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Weak Strength Pull-down and Pull-up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDD Current Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
48
50
52
54
58
5
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Datasheet
5
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Datasheet
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Input/Output Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Burst Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Truth Table 1a: Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Truth Table 1b: DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Truth Table 2: Clock Enable (CKE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Truth Table 3: Current State Bank n - Command to Bank n (same bank) . . . . . . . . . . . . . . . . . . . 43
Truth Table 4: Current State Bank n - Command to Bank m (different bank). . . . . . . . . . . . . . . . . 45
Truth Table 5: Concurrent Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Input and Output Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Electrical Characteristics and DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Normal Strength Pull-down and Pull-up Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Evaluation Conditions for I/O Driver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Weak Strength Driver Pull-down and Pull-up Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Electrical Characteristics and AC Timing - Absolute Specifications –4/–5 . . . . . . . . . . . . . . . . . . 55
IDD Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
IDD Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Datasheet
Pin Configuration P-TSOPII-66-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram (16 Mbit × 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Required CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
tRCD and tRRD Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Consecutive Read Bursts (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Non-Consecutive Read Bursts (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Random Read Accesses (Burst Length = 2, 4 or 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Terminating a Read Burst (Burst Length = 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read to Write (Burst Length = 4 or 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read to Precharge (Burst Length = 4 or 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Burst (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write to Write (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write to Write: Max. DQSS, Non-Consecutive (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . .
Random Write Cycles (Burst Length = 2, 4 or 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write to Read: Non-Interrupting (CAS Latency = 3; Burst Length = 4). . . . . . . . . . . . . . . . . . . . . .
Write to Read: Interrupting (CAS Latency = 3; Burst Length = 8). . . . . . . . . . . . . . . . . . . . . . . . . .
Write to Read: Min. DQSS, Odd Number of Data (3-bit Write), Interrupting (CL3; BL8) . . . . . . . .
Write to Read: Nominal DQSS, Interrupting (CAS Latency = 3; Burst Length = 8) . . . . . . . . . . . .
Write to Precharge: Non-Interrupting (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write to Precharge: Interrupting (Burst Length = 4 or 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write to Precharge: Minimum DQSS, Odd Number of Data (1-bit Write), Interrupting (BL 4 or 8).
Write to Precharge: Nominal DQSS (2-bit Write), Interrupting (Burst Length = 4 or 8) . . . . . . . . .
Precharge Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Normal Strength Pull-down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Normal Strength Pull-up Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Weak Strength Pull-down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Weak Strength Pull-up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Output Load Circuit Diagram / Timing Reference Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Input (Write), Timing Burst Length = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Output (Read), Timing Burst Length = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialize and Mode Register Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto Refresh Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read without Auto Precharge (Burst Length = 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read with Auto Precharge (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bank Read Access (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write without Auto Precharge (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write with Auto Precharge (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bank Write Access (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write DM Operation (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
P-TSOPII-66-1 (Plastic Thin Small Outline Package Type II). . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
10
12
16
21
21
22
23
23
24
25
26
26
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
47
50
50
52
52
54
59
59
60
61
62
63
64
65
66
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71
Rev.1.0, 2004-02
16M x 16 Double Data Rate Graphics DRAM
DDR SGRAM
1
Overview
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
HYB25D256161CE-5
HYB25D256161CE-4
Double data rate architecture: two data transfers per clock cycle
Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the
receiver
DQS is edge-aligned with data for reads and is center-aligned with data for writes
Differential clock inputs (CK and CK)
Four internal banks for concurrent operation
Data mask (DM) for write data
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Burst Lengths: 2, 4, or 8
CAS Latency: 3
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
7.8 µs Maximum Average Periodic Refresh Interval
2.5 V (SSTL_2 compatible) I/O
VDDQ = 2.6 V ± 0.1 V
VDD = 2.6 V ± 0.1 V
P-TSOPII-66-1 package
Lead- and halogene-free = green product
Table 1
Performance
Part Number Speed Code
max. Clock Frequency
1.2
@CL3
fCK3
–4
–5
Unit
250
200
MHz
Description
The 16M x 16 Double Data Rate Graphics DRAM is a high-speed CMOS, dynamic random-access memory
containing 268,435,456 bits. It is internally configured as a quad-bank DRAM.
The 16M x 16 Double Data Rate Graphics DRAM uses a double-data-rate architecture to achieve high-speed
operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to
transfer two data words per clock cycle at the I/O pins. A single read or write access for the 16M x 16 Double Data
Rate Graphics DRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal
DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver.
DQS is a strobe transmitted by the DDR SGRAM during Reads and by the memory controller during Writes. DQS
is edge-aligned with data for Reads and center-aligned with data for Writes.
The 16M x 16 Double Data Rate Graphics DRAM operates from a differential clock (CK and CK; the crossing of
CK going HIGH and CK going LOW is referred to as the positive edge of CK). Commands (address and control
signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output
data is referenced to both edges of DQS, as well as to both edges of CK.
Datasheet
8
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Overview
Read and write accesses to the DDR SGRAM are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration
of an Active command, which is then followed by a Read or Write command. The address bits registered
coincident with the Active command are used to select the bank and row to be accessed. The address bits
registered coincident with the Read or Write command are used to select the bank and the starting column location
for the burst access.
The DDR SGRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto
Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst
access.
As with standard SDRAMs, the pipelined, multibank architecture of DDR SGRAMs allows for concurrent
operation, thereby providing high effective bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with the
JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible.
Note: The functionality described and the timing specifications included in this data sheet are for the DLL Enabled
mode of operation.
Table 2
Ordering Information
Part Number1)
Organisation
Clock (MHz)
Package
HYB25D256161CE–4
×16
250
P-TSOPII-66-1
HYB25D256161CE–5
200
1) HYB: designator for memory components
25D: DDR SGRAMs at VDDQ = 2.5 V / 2.6 V
256: 256-Mbit density
C: Die revision C
Datasheet
9
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Pin Configuration
2
Pin Configuration
VDD
1
66
VSS
DQ0
VDDQ
DQ1
2
3
4
65
64
63
DQ15
VSSQ
DQ14
DQ2
5
62
DQ13
VSSQ
DQ3
DQ4
VDDQ
DQ5
6
7
8
9
10
61
60
59
58
57
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ6
11
56
DQ9
VSSQ
12
55
VDDQ
DQ7
NC
13
14
15
16
17
18
19
20
54
53
52
51
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
RAS
21
22
23
46
45
44
CK
CK
CKE
CS
NC
24
25
43
42
NC
A12
BA0
BA1
A10/AP
26
27
28
29
41
40
39
38
A11
A9
A8
A7
30
31
37
36
A6
A5
32
33
35
34
A4
VSS
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
A0
A1
A2
A3
VDD
50
49
48
47
UDM
16Mb x 16
Figure 1
Datasheet
Pin Configuration P-TSOPII-66-1
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Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Pin Configuration
Table 3
Input/Output Functional Description
Symbol
Type
Function
CK, CK
Input
Clock: CK and CK are differential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK and negative
edge of CK. Output (read) data is referenced to the crossings of CK and CK
(both directions of crossing).
CKE
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock
signals and device input buffers and output drivers. Taking CKE Low provides
Precharge Power-Down and Self Refresh operation (all banks idle), or Active
Power-Down (row Active in any bank). CKE is synchronous for power down
entry and exit, and for self refresh entry. CKE is asynchronous for self refresh
exit. CKE must be maintained high throughout read and write accesses. Input
buffers, excluding CK, CK and CKE are disabled during power-down. Input
buffers, excluding CKE, are disabled during self refresh.
CS
Input
Chip Select: All commands are masked when CS is registered HIGH. CS
provides for external bank selection on systems with multiple banks. CS is
considered part of the command code. The standard pinout includes one CS
pin.
RAS, CAS, WE Input
Command Inputs: RAS, CAS and WE (along with CS) define the command
being entered.
DM
Input
Input Data Mask: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH coincident with that input data during a
Write access. DM is sampled on both edges of DQS. Although DM pins are
input only, the DM loading matches the DQ and DQS loading.
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read,
Write or Precharge command is being applied. BA0 and BA1 also determines
if the mode register or extended mode register is to be accessed during a
MRS or EMRS cycle.
A0 - A12
Input
Address Inputs: Provide the row address for Active commands, and the
column address and Auto Precharge bit for Read/Write commands, to select
one location out of the memory array in the respective bank. A10 is sampled
during a Precharge command to determine whether the Precharge applies to
one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be
precharged, the bank is selected by BA0, BA1. The address inputs also
provide the op-code during a Mode Register Set command.
DQ
Input/Output
Data Input/Output: Data bus.
DQS
Input/Output
Data Strobe: Output with read data, input with write data. Edge-aligned with
read data, centered in write data. Used to capture data.
NC
–
No Connect: No internal electrical connection is present.
VDDQ
VSSQ
VDD
VSS
VREF
Supply
DQ Power Supply: 2.6 V ± 0.1 V.
Supply
DQ Ground
Supply
Power Supply: 2.6 V ± 0.1 V.
Supply
Ground
Supply
SSTL_2 Reference Voltage: VDDQ/2
Datasheet
11
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
2
Bank0
Memory
Array
(8192 x 512x 32)
32
2
16
16
16384
Sense Amplifiers
COL0
I/O Gating
DM Mask Logic
32
32
512
(x32)
Column
Decoder
Column-Address
Counter/Latch
1
Figure 2
CK,
CK
COL0
16
1
DQS
Generator
Input
Register
Write Mask 1
FIFO
1
&
2
Drivers
16
32
16
clk clk
out in Data
8
9
Drivers
Data
DQS
1
1
16
16
DQ0-DQ15,
DM
LDQS, UDQS
1
Receivers
8192
Bank Control Logic
Refresh Counter
15
Address Register
A0-A12,
BA0, BA1
CK, CK
DLL
13
13
Bank3
MUX
15
13
Bank2
Read Latch
Mode
Registers
Bank0
Row-Address Latch
& Decoder
Bank1
Row-Address MUX
Command
Decode
CKE
CK
CK
CS
WE
CAS
RAS
Control Logic
Pin Configuration
16
COL0
2
Block Diagram (16 Mbit × 16)
Notes
1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does
not represent an actual circuit implementation.
2. UDM and LDM are unidirectional signals (input only), but is internally loaded to match the load of the
bidirectional DQ, UDQS and LDQS signals.
Datasheet
12
Rev.1.0, 2004-02
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256-Mbit Double Data Rate SGRAM
Functional Description
3
Functional Description
The 16M x 16 Double Data Rate Graphics DRAM is a high-speed CMOS, dynamic random-access memory
containing 268,435,456 bits. The 16M x 16 Double Data Rate Graphics DRAM is internally configured as a quadbank DRAM.
The 16M x 16 Double Data Rate Graphics DRAM uses a double-data-rate architecture to achieve high-speed
operation. The double-data-rate architecture is essentially a 2n prefetch architecture, with an interface designed
to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 16M x 16 Double
Data Rate Graphics DRAM consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM
core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.
Read and write accesses to the DDR SGRAM are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration
of an Active command, which is then followed by a Read or Write command. The address bits registered
coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1 select the
bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command are used
to select the starting column location for the burst access.
Prior to normal operation, the DDR SGRAM must be initialized. The following sections provide detailed information
covering device initialization, register definition, command descriptions and device operation.
3.1
Initialization
DDR SGRAMs must be powered up and initialized in a predefined manner. Operational procedures other than
those specified may result in undefined operation. The following criteria must be met:
No power sequencing is specified during power up or power down given the following criteria:
•
•
•
VDD and VDDQ are driven from a single power converter output
VTT meets the specification
A minimum resistance of 42 Ω limits the input current from the VTT supply into any pin and VREF tracks VDDQ/2
or the following relationship must be followed:
•
•
•
VDDQ is driven after or with VDD such that VDDQ < VDD + 0.3 V
VTT is driven after or with VDDQ such that VTT < VDDQ + 0.3 V
VREF is driven after or with VDDQ such that VREF < VDDQ + 0.3 V
The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a read
access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SGRAM
requires a 200 µs delay prior to applying an executable command.
Once the 200 µs delay has been satisfied, a Deselect or NOP command should be applied, and CKE should be
brought HIGH. Following the NOP command, a Precharge ALL command should be applied. Next a Mode
Register Set command should be issued for the Extended Mode Register, to enable the DLL, then a Mode
Register Set command should be issued for the Mode Register, to reset the DLL, and to program the operating
parameters. 200 clock cycles are required between the DLL reset and any executable command. During the
200 cycles of clock for DLL locking, a Deselect or NOP command must be applied. After the 200 clock cycles, a
Precharge ALL command should be applied, placing the device in the “all banks idle” state.
Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a Mode Register Set
command for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without
resetting the DLL) must be performed. Following these cycles, the DDR SGRAM is ready for normal operation.
Datasheet
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Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
3.2
Mode Register Definition
The Mode Register is used to define the specific mode of operation of the DDR SGRAM. This definition includes
the selection of a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is
programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 0) and retains the stored information
until it is programmed again or the device loses power (except for bit A8, which is self-clearing).
Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4A6 specify the CAS latency, and A7-A12 specify the operating mode.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these requirements results in unspecified operation.
MR
Mode Register Definition
BA1
BA0
0
0
A12
A11
(BA[1:0] = 00B)
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
MODE
CL
BT
BL
w
w
w
w
reg. addr
A0
Field
Bits
Type
Description
BL
[2:0]
w
Burst Length
Number of sequential bits per DQ related to one read/write command; see Chapter 3.2.1.
Note: All other bit combinations are RESERVED.
001 2
010 4
011 8
BT
3
w
Burst Type
See Table 4 for internal address sequence of low order address bits; see Chapter 3.2.2.
0
Sequential
1
Interleaved
CL
[6:4]
w
CAS Latency
Number of full clocks from read command to first data valid window; see Chapter 3.2.3.
Note: All other bit combinations are RESERVED.
011 3
MODE [12:7] w
Operating Mode
See Chapter 3.2.4.
Note: All other bit combinations are RESERVED.
000000
000010
3.2.1
Normal Operation without DLL Reset
Normal Operation with DLL Reset
Burst Length
Read and write accesses to the DDR SGRAM are burst oriented, with the burst length being programmable. The
burst length determines the maximum number of column locations that can be accessed for a given Read or Write
command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is
reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length
is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit
Datasheet
14
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HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting
location within the block. The programmed burst length applies to both Read and Write bursts.
3.2.2
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the
burst type and the starting column address, as shown in Table 4.
Table 4
Burst
Length
Burst Definition
Starting Column Address
A2
A1
A0
Type = Sequential
Type = Interleaved
0
0-1
0-1
1
1-0
1-0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
2
4
8
Order of Accesses Within a Burst
Notes
1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the
block.
3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access within
the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps
within the block.
3.2.3
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and
the availability of the first burst of output data. The latency can be programmed 2, 2.5 and 3 clocks. CAS latency
of 1.5 is supported for DDR200 components only.
If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally
coincident with clock edge n + m (see Figure 3)
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Datasheet
15
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
3.2.4
Operating Mode
The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 set to zero,
and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with
bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode Register
Set command issued to reset the DLL should always be followed by a Mode Register Set command to select
normal operating mode.
All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and
reserved states should not be used as unknown operation or incompatibility with future versions may result.
CAS Latency = 3, BL = 4
CK
CK
Command
Read
NOP
NOP
NOP
NOP
NOP
CL=3
DQS
DQ
Don’t Care
Shown with nominal tAC, tDQSCK, and tDQSQ.
Figure 3
Datasheet
Required CAS Latency
16
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256-Mbit Double Data Rate SGRAM
Functional Description
3.3
Extended Mode Register
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional
functions include DLL enable/disable, and output drive strength selection (optional). These functions are controlled
via the bits shown in the Extended Mode Register Definition. The Extended Mode Register is programmed via the
Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored information until it is programmed
again or the device loses power. The Extended Mode Register must be loaded when all banks are idle, and the
controller must wait the specified time before initiating any subsequent operation. Violating either of these
requirements result in unspecified operation.
3.3.1
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon
returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is
automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self
refresh operation. Any time the DLL is enabled, 200 clock cycles must occur before a Read command can be
issued. This is the reason 200 clock cycles must occur before issuing a Read or Write command upon exit of self
refresh operation.
3.3.2
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. In addition this design version
supports a weak driver mode for lighter load and/or point-to-point environments which can be activated during
mode register set. I-V curves for the normal and weak drive strength are included in this document.
EMR
Extended Mode Register Definition
BA1
BA0
0
1
A12
A11
A10
(BA[1:0] = 01B)
A9
A8
A7
A1
A0
MODE
DS
DLL
w
w
w
reg. addr
A6
A5
A4
Field
Bits
Type
Description
DLL
0
w
DLL Status
See Chapter 3.3.1.
0
Enabled
1
Disabled
DS
1
w
Drive Strength
See Chapter 3.3.2, Chapter 4.2 and Chapter 4.3.
0
Normal
1
Weak
MODE
[12:2]
w
Operating Mode
A3
A2
Note: All other bit combinations are RESERVED.
0
Datasheet
Normal Operation
17
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256-Mbit Double Data Rate SGRAM
Functional Description
3.4
Commands
Deselect
The Deselect function prevents new commands from being executed by the DDR SGRAM. The DDR SGRAM is
effectively deselected. Operations already in progress are not affected.
No Operation (NOP)
The No Operation (NOP) command is used to perform a NOP to a DDR SGRAM. This prevents unwanted
commands from being registered during idle or wait states. Operations already in progress are not affected.
Mode Register Set
The mode registers are loaded via inputs A0-A12, BA0 and BA1. See mode register descriptions in Chapter 3.2.
The Mode Register Set command can only be issued when all banks are idle and no bursts are in progress. A
subsequent executable command cannot be issued until tMRD is met.
Active
The Active command is used to open (or activate) a row in a particular bank for a subsequent access. The value
on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row. This row
remains active (or open) for accesses until a Precharge (or Read or Write with Auto Precharge) is issued to that
bank. A Precharge (or Read or Write with Auto Precharge) command must be issued and completed before
opening a different row in the same bank.
Read
The Read command is used to initiate a burst read access to an active (open) row. The value on the BA0, BA1
inputs selects the bank, and the address provided on inputs A0-A8 selects the starting column location. The value
on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being
accessed is precharged at the end of the Read burst; if Auto Precharge is not selected, the row remains open for
subsequent accesses.
Write
The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0, BA1
inputs selects the bank, and the address provided on inputs A0-A8 selects the starting column location. The value
on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being
accessed is precharged at the end of the Write burst; if Auto Precharge is not selected, the row remains open for
subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input
logic level appearing coincident with the data. If a given DM signal is registered low, the corresponding data is
written to memory; if the DM signal is registered high, the corresponding data inputs are ignored, and a Write is
not executed to that byte/column location.
Precharge
The Precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all
banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the Precharge
command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where
only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t
Care”. Once a bank has been precharged, it is in the idle state and must be activated prior to any Read or Write
commands being issued to that bank. A precharge command is treated as a NOP if there is no open row in that
bank, or if the previously open row is already in the process of precharging.
Datasheet
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256-Mbit Double Data Rate SGRAM
Functional Description
Auto Precharge
Auto Precharge is a feature which performs the same individual-bank precharge functions described above, but
without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction
with a specific Read or Write command. A precharge of the bank/row that is addressed with the Read or Write
command is automatically performed upon completion of the Read or Write burst. Auto Precharge is nonpersistent
in that it is either enabled or disabled for each individual Read or Write command. Auto Precharge ensures that
the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to
the same bank until the precharge (tRP) is completed. This is determined as if an explicit Precharge command was
issued at the earliest possible time, as described for each burst type in Chapter 3.5.
Burst Terminate
The Burst Terminate command is used to truncate read bursts (with Auto Precharge disabled). The most recently
registered Read command prior to the Burst Terminate command is truncated, as shown in Chapter 3.5.
Auto Refresh
Auto Refresh is used during normal operation of the DDR SGRAM and is analogous to CAS Before RAS (CBR)
Refresh in previous DRAM types. This command is nonpersistent, so it must be issued each time a refresh is
required.
The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care”
during an Auto Refresh command. The 16M x 16 Double Data Rate Graphics DRAM requires Auto Refresh cycles
at an average periodic interval of 7.8 µs (maximum).
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh
interval is provided. A maximum of eight Auto Refresh commands can be posted in the system, meaning that the
maximum absolute interval between any Auto Refresh command and the next Auto Refresh command is
9 × 7.8 µs (70.2 µs). This maximum absolute interval is short enough to allow for DLL updates internal to the
DDR SGRAM to be restricted to Auto Refresh cycles, without allowing too much drift in tAC between updates.
Self Refresh
The Self Refresh command can be used to retain data in the DDR SGRAM, even if the rest of the system is
powered down. When in the self refresh mode, the DDR SGRAM retains data without external clocking. The Self
Refresh command is initiated as an Auto Refresh command coincident with CKE transitioning low. The DLL is
automatically disabled upon entering Self Refresh, and is automatically enabled upon exiting Self Refresh
(200 clock cycles must then occur before a Read command can be issued). Input signals except CKE (low) are
“Don’t Care” during Self Refresh operation.
The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable prior to CKE
returning high. Once CKE is high, the SDRAM must have NOP commands issued for tXSNR because time is
required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and
DLL requirements is to apply NOPs for 200 clock cycles before applying any other command.
Datasheet
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256-Mbit Double Data Rate SGRAM
Functional Description
Table 5
Truth Table 1a: Commands
Name (Function)
CS
RAS CAS WE Address
MNE
Notes
Deselect (NOP)
H
X
X
X
X
NOP
1)2)
No Operation (NOP)
L
H
H
H
X
NOP
1)2)
Active (Select Bank And Activate Row)
L
L
H
H
Bank/Row ACT
1)3)
Read (Select Bank And Column, And Start Read Burst)
L
H
L
H
Bank/Col
Read
1)4)
Write (Select Bank And Column, And Start Write Burst)
L
H
L
L
Bank/Col
Write
1)4)
Burst Terminate
L
H
H
L
X
BST
1)5)
Precharge (Deactivate Row In Bank Or Banks)
L
L
H
L
Code
PRE
1)6)
Auto Refresh Or Self Refresh (Enter Self Refresh Mode)
L
L
L
H
X
AR/SR
1)7)8)
Mode Register Set
L
L
L
L
Op-Code
MRS
1)9)
1) CKE is HIGH for all commands shown except Self Refresh.
2) Deselect and NOP are functionally interchangeable.
3) BA0-BA1 provide bank address and A0-A12 provide row address.
4) BA0, BA1 provide bank address; A0-A8 provide column address;
A10 HIGH enables the Auto Precharge feature (nonpersistent), A10 LOW disables the Auto Precharge feature.
5) Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read
bursts with Auto Precharge enabled or for write bursts.
6) A10 LOW: BA0, BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
7) This command is Auto Refresh if CKE is HIGH; Self Refresh if CKE is LOW.
8) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
9) BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1,
BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to
be written to the selected Mode Register).
Table 6
Truth Table 1b: DM Operation
Name (Function)
DM
DQs
Notes
Write Enable
L
Valid
1)
Write Inhibit
H
X
1)
1) Used to mask write data; provided coincident with the corresponding data.
Datasheet
20
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
3.5
Operations
3.5.1
Bank/Row Activation
Before any Read or Write commands can be issued to a bank within the DDR SGRAM, a row in that bank must
be “opened” (activated). This is accomplished via the Active command and addresses A0-A12, BA0 and BA1 (see
Figure 4), which decode and select both the bank and the row to be activated. After opening a row (issuing an
Active command), a Read or Write command may be issued to that row, subject to the tRCD specification. A
subsequent Active command to a different row in the same bank can only be issued after the previous active row
has been “closed” (precharged). The minimum time interval between successive Active commands to the same
bank is defined by tRC. A subsequent Active command to another bank can be issued while the first bank is being
accessed, which results in a reduction of total row-access overhead. The minimum time interval between
successive Active commands to different banks is defined by tRRD.
CK
CK
HIGH
CKE
CS
RAS
CAS
WE
Figure 4
A0-A12
RA
BA0, BA1
BA
RA = row address.
BA = bank address.
Don’t Care
Activating a Specific Row in a Specific Bank
CK
CK
ACT
Command
NOP
ACT
NOP
NOP
RD/WR
A0-A12
ROW
ROW
COL
BA0, BA1
BA x
BA y
BA y
tRRD
NOP
NOP
tRCD
Don’t Care
Figure 5
Datasheet
tRCD and tRRD Definition
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HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
3.5.2
Reads
Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are
initiated with a Read command, as shown on Figure 6.
The starting column and bank addresses are provided with the Read command and Auto Precharge is either
enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed starts precharge
at the completion of the burst, provided tRAS has been satisfied. For the generic Read commands used in the
following illustrations, Auto Precharge is disabled.
During Read bursts, the valid data-out element from the starting column address is available following the CAS
latency after the Read command. Each subsequent data-out element is valid nominally at the next positive or
negative clock edge (i.e. at the next crossing of CK and CK). (Figure 10) shows general timing for each supported
CAS latency setting. DQS is driven by the DDR SGRAM along with output data. The initial low state on DQS is
known as the read preamble; the low state coincident with the last data-out element is known as the read
postamble. Upon completion of a burst, assuming no other commands have been initiated, the DQs goes High-Z.
Data from any Read burst may be concatenated with or truncated with data from a subsequent Read command.
In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either
the last element of a completed burst or the last desired data element of a longer burst which is being truncated.
The new Read command should be issued x cycles after the first Read command, where x equals the number of
desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown on Figure 7. A Read
command can be initiated on any clock cycle following a previous Read command. Nonconsecutive Read data is
illustrated on Figure 8. Full-speed Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8) within a
page (or pages) can be performed as shown on Figure 9.
CK
CK
CKE
HIGH
CS
RAS
CAS
WE
A0-A8
CA
EN AP
A10
DIS AP
BA0, BA1
CA = column address
BA = bank address
EN AP = enable Auto Precharge
DIS AP = disable Auto Precharge
BA
Don’t Care
Figure 6
Datasheet
Read Command
22
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
CAS Latency = 3
CK
CK
Command
Address
Read
NOP
Read
BAa, COL n
NOP
NOP
NOP
BAa, COL b
CL=3
DQS
DQ
DOa-b
DOa-n
DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).
When burst length = 4, the bursts are concatenated.
When burst length = 8, the second burst interrupts the first.
3 subsequent elements of data out appear in the programmed order following DO a-n.
3 (or 7) subsequent elements of data out appear in the programmed order following DO a-b.
Shown with nominal tAC, tDQSCK, and tDQSQ.
Figure 7
Don’t Care
Consecutive Read Bursts (Burst Length = 4)
CAS Latency = 3
CK
CK
Command
Address
Read
Read
BAa, COL n
NOP
NOP
NOP
BAa, COL b
CL=3
DQS
DO a-n
DQ
DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).
3 subsequent elements of data out appear in the programmed order following DO a-n (and following DO a-b).
Shown with nominal tAC, tDQSCK, and tDQSQ.
Figure 8
Datasheet
DOa- b
Don’t Care
Non-Consecutive Read Bursts (Burst Length = 4)
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HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
CAS Latency = 3
CK
CK
Command
Address
Read
Read
Read
Read
NOP
BAa, COL n
BAa, COL x
BAa, COL b
BAa, COL g
NOP
CL=3
DQS
DQ
DOa-n
DO a-n, etc. = data out from bank a, column n etc.
n' etc. = odd or even complement of n, etc. (i.e., column address LSB inverted).
Reads are to active rows in any banks.
Shown with nominal tAC, tDQSCK, and tDQSQ.
Figure 9
Datasheet
DOa-n’
DOa-x
DOa-x’
DOa-b
Don’t Care
Random Read Accesses (Burst Length = 2, 4 or 8)
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256-Mbit Double Data Rate SGRAM
Functional Description
Data from any Read burst may be truncated with a Burst Terminate command, as shown on Figure 10. The Burst
Terminate latency is equal to the read (CAS) latency, i.e. the Burst Terminate command should be issued x cycles
after the Read command, where x equals the number of desired data element pairs.
Data from any Read burst must be completed or truncated before a subsequent Write command can be issued. If
truncation is necessary, the Burst Terminate command must be used, as shown on Figure 11. The example is
shown for tDQSS(min). The tDQSS(max) case, not shown here, has a longer bus idle time. tDQSS(min) and tDQSS(max) are
defined in Chapter 3.5.3.
A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that Auto
Precharge was not activated). The Precharge command should be issued x cycles after the Read command,
where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). This
is shown on Figure 12 for Read latencies of 2 and 2.5. Following the Precharge command, a subsequent
command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden
during the access of the last data elements.
In the case of a Read being executed to completion, a Precharge command issued at the optimum time (as
described above) provides the same operation that would result from the same Read burst with Auto Precharge
enabled. The disadvantage of the Precharge command is that it requires that the command and address busses
be available at the appropriate time to issue the command. The advantage of the Precharge command is that it
can be used to truncate bursts.
CAS Latency = 3
CK
CK
Command
Address
Read
NOP
BST
NOP
NOP
NOP
BAa, COL n
CL=3
DQS
DQ
DOa-n
No further output data after this point.
DQS tristated.
DO a-n = data out from bank a, column n.
Cases shown are bursts of 8 terminated after 4 data elements.
3 subsequent elements of data out appear in the programmed order following DO a-n.
Shown with nominal tAC, tDQSCK, and tDQSQ.
Figure 10
Datasheet
Don’t Care
Terminating a Read Burst (Burst Length = 8)
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Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
CAS Latency = 3
CK
CK
Command
Address
Read
BST
NOP
BAa, COL n
NOP
Write
NOP
BAa, COL b
CL=3
tDQSS (min)
DQS
DQ
DI a-b
DOa-n
DM
Don’t Care
DO a-n = data out from bank a, column n
.DI a-b = data in to bank a, column b
1 subsequent elements of data out appear in the programmed order following DO a-n.
Data In elements are applied following Dl a-b in the programmed order, according to burst length.
Shown with nominal tAC, tDQSCK, and tDQSQ.
Figure 11
Read to Write (Burst Length = 4 or 8)
CAS Latency = 3
CK
CK
Command
Read
NOP
PRE
NOP
NOP
ACT
tRP
Address
BA a, COL n
BA a or all
BA a, ROW
CL=3
DQS
DQ
DOa-n
DO a-n = data out from bank a, column n.
Cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8.
3 subsequent elements of data out appear in the programmed order following DO a-n.
Shown with nominal tAC, tDQSCK, and tDQSQ.
Figure 12
Read to Precharge (Burst Length = 4 or 8)
Datasheet
26
Don’t Care
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
3.5.3
Writes
Write bursts are initiated with a Write command, as shown in Figure 13.
The starting column and bank addresses are provided with the Write command, and Auto Precharge is either
enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the
completion of the burst. For the generic Write commands used in the following illustrations, Auto Precharge is
disabled.
During Write bursts, the first valid data-in element is registered on the first rising edge of DQS following the write
command, and subsequent data elements are registered on successive edges of DQS. The Low state on DQS
between the Write command and the first rising edge is known as the write preamble; the Low state on DQS
following the last data-in element is known as the write postamble. The time between the Write command and the
first corresponding rising edge of DQS (tDQSS) is specified with a relatively wide range (from 75% to 125% of one
clock cycle), so most of the Write diagrams that follow are drawn for the two extreme cases (i.e. tDQSS(min) and
tDQSS(max)). Figure 14 shows the two extremes of tDQSS for a burst of four. Upon completion of a burst, assuming
no other commands have been initiated, the DQs and DQS enters High-Z and any additional input data is ignored.
Data for any Write burst may be concatenated with or truncated with a subsequent Write command. In either case,
a continuous flow of input data can be maintained. The new Write command can be issued on any positive edge
of clock following the previous Write command. The first data element from the new burst is applied after either
the last element of a completed burst or the last desired data element of a longer burst which is being truncated.
The new Write command should be issued x cycles after the first Write command, where x equals the number of
desired data element pairs (pairs are required by the 2n prefetch architecture). Figure 15 shows concatenated
bursts of 4. An example of non-consecutive Writes is shown in Figure 16. Full-speed random write accesses
within a page or pages can be performed as shown in Figure 17. Data for any Write burst may be followed by a
subsequent Read command. To follow a Write without truncating the write burst, tWTR (Write to Read) should be
met as shown in Figure 18.
Data for any Write burst may be truncated by a subsequent Read command, as shown in Figure 19 to Figure 21.
Note that only the data-in pairs that are registered prior to the tWTR period are written to the internal array, and any
subsequent data-in must be masked with DM, as shown in the diagrams noted previously.
Data for any Write burst may be followed by a subsequent Precharge command. To follow a Write without
truncating the write burst, tWR should be met as shown in Figure 22.
Data for any Write burst may be truncated by a subsequent Precharge command, as shown in Figure 23 to
Figure 25. Note that only the data-in pairs that are registered prior to the tWR period are written to the internal array,
and any subsequent data in should be masked with DM. Following the Precharge command, a subsequent
command to the same bank cannot be issued until tRP is met.
In the case of a Write burst being executed to completion, a Precharge command issued at the optimum time (as
described above) provides the same operation that would result from the same burst with Auto Precharge. The
disadvantage of the Precharge command is that it requires that the command and address busses be available at
the appropriate time to issue the command. The advantage of the Precharge command is that it can be used to
truncate bursts.
Datasheet
27
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
CK
CK
CKE
HIGH
CS
RAS
CAS
WE
A0-A8
CA
EN AP
A10
DIS AP
BA0, BA1
CA = column address
BA = bank address
EN AP = enable Auto Precharge
DIS AP = disable Auto Precharge
BA
Don’t Care
Figure 13
Datasheet
Write Command
28
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HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
Maximum DQSS
T1
T2
T3
T4
CK
CK
Write
Command
NOP
NOP
NOP
BA a, COL b
Address
tDQSS (max)
DQS
DQ
Dla-b
DM
Minimum DQSS
T1
T2
T3
T4
CK
CK
Command
Address
Write
NOP
NOP
NOP
BA a, COL b
tDQSS (min)
DQS
Dla-b
DQ
DM
DI a-b = data in for bank a, column b.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
A non-interrupted burst is shown.
A10 is Low with the Write command (Auto Precharge is disabled).
Don’t Care
Figure 14
Datasheet
Write Burst (Burst Length = 4)
29
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
Maximum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Write
Command
Address
NOP
Write
BAa, COL b
NOP
NOP
NOP
BAa, COL n
tDQSS (max)
DQS
DQ
DI a-b
DI a-n
DM
Minimum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Write
Command
Address
NOP
BA, COL b
Write
NOP
NOP
NOP
BA, COL n
tDQSS (min)
DQS
DQ
DI a-b
DI a-n
DM
DI a-b = data in for bank a, column b, etc.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
3 subsequent elements of data in are applied in the programmed order following DI a-n.
A non-interrupted burst is shown.
Each Write command may be to any bank.
Figure 15
Datasheet
Don’t Care
Write to Write (Burst Length = 4)
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Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
T1
T2
T3
T4
T5
CK
CK
Write
Command
Address
NOP
NOP
BAa, COL b
Write
NOP
BAa, COL n
tDQSS (max)
DQS
DQ
DI a-b
DI a-n
DM
DI a-b, etc. = data in for bank a, column b, etc.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
3 subsequent elements of data in are applied in the programmed order following DI a-n.
A non-interrupted burst is shown.
Each Write command may be to any bank.
Figure 16
Datasheet
Don’t Care
Write to Write: Max. DQSS, Non-Consecutive (Burst Length = 4)
31
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
Maximum DQSS
T1
T2
T3
T4
T5
CK
CK
Write
Command
Address
Write
BAa, COL b
Write
BAa, COL x
BAa, COL n
Write
Write
BAa, COL a
BAa, COL g
tDQSS (max)
DQS
DQ
DI a-b
DI a-b’
DI a-x
DI a-x’
DI a-n
DI a-n’
DI a-a
DI a-a’
DM
Minimum DQSS
T1
T2
T3
T4
T5
CK
CK
Write
Command
Address
Write
BAa, COL b
Write
BAa, COL x
BAa, COL n
Write
Write
BAa, COL a
BAa, COL g
tDQSS (min)
DQS
DQ
DI a-b
DI a-b’
DI a-x
DI a-x’
DI a-n
DI a-n’
DI a-a
DI a-a’
DI a-g
DM
DI a-b, etc. = data in for bank a, column b, etc.
b', etc. = odd or even complement of b, etc. (i.e., column address LSB inverted).
Each Write command may be to any bank.
Figure 17
Datasheet
Don’t Care
Random Write Cycles (Burst Length = 2, 4 or 8)
32
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HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
Maximum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Write
Command
NOP
NOP
NOP
Read
NOP
tWTR
Address
BAa, COL b
BAa, COL n
CL = 3
tDQSS (max)
DQS
DQ
DI a-b
DM
Minimum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Write
Command
NOP
NOP
NOP
Read
NOP
tWTR
Address
BAa, COL n
BAa, COL b
CL = 3
tDQSS (min)
DQS
DQ
DI a-b
DM
DI a-b = data in for bank a, column b.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
A non-interrupted burst is shown.
tWTR is referenced from the first positive CK edge after the last data in pair.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands may be to any bank.
Figure 18
Datasheet
Don’t Care
Write to Read: Non-Interrupting (CAS Latency = 3; Burst Length = 4)
33
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
Maximum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
Read
NOP
tWTR
Address
BAa, COL n
BAa, COL b
CL = 3
tDQSS (max)
DQS
DQ
DIa- b
1
DM
1
Minimum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
Read
NOP
tWTR
Address
BAa, COL n
BAa, COL b
CL = 3
tDQSS (min)
DQS
DQ
DI a-b
1
DM
1
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 4 data elements are written.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
tWTR is referenced from the first positive CK edge after the last data in pair.
The Read command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands are not necessarily to the same bank.
1 = These bits are incorrectly written into the memory array if DM is low.
Figure 19
Datasheet
Don’t Care
Write to Read: Interrupting (CAS Latency = 3; Burst Length = 8)
34
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
Read
NOP
tWTR
Address
BAa, COL n
BAa, COL b
CL = 3
tDQSS (min)
DQS
DQ
DI a-b
DM
1
2
2
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 3 data elements are written.
2 subsequent elements of data in are applied in the programmed order following DI a-b.
tWTR is referenced from the first positive CK edge after the last desired data in pair (not the last desired data in element)
The Read command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands are not necessarily to the same bank.
1 = This bit is correctly written into the memory array if DM is low.
2 = These bits are incorrectly written into the memory array if DM is low.
Figure 20
Datasheet
Don’t Care
Write to Read: Min. DQSS, Odd Number of Data (3-bit Write), Interrupting (CL3; BL8)
35
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
T1
T2
T3
T4
T5
T6
CK
CK
Write
Command
NOP
NOP
NOP
Read
NOP
tWTR
Address
BAa, COL n
BAa, COL b
CL = 3
tDQSS (nom)
DQS
DQ
DI a-b
DM
1
1
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 4 data elements are written.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
tWTR is referenced from the first positive CK edge after the last desired data in pair.
The Read command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands are not necessarily to the same bank.
1 = These bits are incorrectly written into the memory array if DM is low.
Figure 21
Datasheet
Don’t Care
Write to Read: Nominal DQSS, Interrupting (CAS Latency = 3; Burst Length = 8)
36
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
Maximum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Write
Command
NOP
NOP
NOP
NOP
PRE
tWR
Address
BA (a or all)
BA a, COL b
tRP
tDQSS (max)
DQS
DQ
DI a-b
DM
Minimum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
NOP
PRE
tWR
Address
BA (a or all)
BA a, COL b
tRP
tDQSS (min)
DQS
DQ
DI a-b
DM
DI a-b = data in for bank a, column b.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
A non-interrupted burst is shown.
tWR is referenced from the first positive CK edge after the last data in pair.
A10 is Low with the Write command (Auto Precharge is disabled).
Figure 22
Datasheet
Don’t Care
Write to Precharge: Non-Interrupting (Burst Length = 4)
37
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
Maximum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Write
Command
NOP
NOP
NOP
PRE
NOP
tWR
Address
BA (a or all)
BA a, COL b
tDQSS (max)
tRP
2
DQS
DQ
DI a-b
3
DM
1
3
1
Minimum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Write
Command
NOP
NOP
NOP
PRE
NOP
tWR
BA a, COL b
Address
BA (a or all)
tDQSS (min)
tRP
2
DQS
DQ
DM
DI a-b
3
3
1
1
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 2 data elements are written.
1 subsequent element of data in is applied in the programmed order following DI a-b.
tWR is referenced from the first positive CK edge after the last desired data in pair.
The Precharge command masks the last 2 data elements in the burst, for burst length = 8.
A10 is Low with the Write command (Auto Precharge is disabled).
1 = Can be don't care for programmed burst length of 4.
2 = For programmed burst length of 4, DQS becomes don't care at this point.
3 = These bits are incorrectly written into the memory array if DM is low.
Figure 23
Datasheet
Don’t Care
Write to Precharge: Interrupting (Burst Length = 4 or 8)
38
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
T1
T2
T3
T4
T5
T6
CK
CK
Write
Command
NOP
NOP
NOP
PRE
NOP
tWR
Address
BA (a or all)
BA a, COL b
tDQSS (min)
tRP
2
DQS
DQ
DM
DI a-b
3
4
4
1
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 1 data element is written.
tWR is referenced from the first positive CK edge after the last desired data in pair.
The Precharge command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
1 = Can be don't care for programmed burst length of 4.
2 = For programmed burst length of 4, DQS becomes don't care at this point.
3 = This bit is correctly written into the memory array if DM is low.
4 = These bits are incorrectly written into the memory array if DM is low.
Figure 24
Datasheet
1
Don’t Care
Write to Precharge: Minimum DQSS, Odd Number of Data (1-bit Write), Interrupting (BL 4 or 8)
39
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
T1
T2
T3
T4
T5
T6
CK
CK
Write
Command
NOP
NOP
NOP
PRE
NOP
tWR
BA a, COL b
Address
BA (a or all)
tDQSS (nom)
tRP
2
DQS
DQ
DM
DI a-b
3
3
1
DI a-b = Data In for bank a, column b.
An interrupted burst is shown, 2 data elements are written.
1 subsequent element of data in is applied in the programmed order following DI a-b.
tWR is referenced from the first positive CK edge after the last desired data in pair.
The Precharge command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
1 = Can be don't care for programmed burst length of 4.
2 = For programmed burst length of 4, DQS becomes don't care at this point.
3 = These bits are incorrectly written into the memory array if DM is low.
Figure 25
Datasheet
1
Don’t Care
Write to Precharge: Nominal DQSS (2-bit Write), Interrupting (Burst Length = 4 or 8)
40
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
3.5.4
Precharge
The Precharge command is used to deactivate the open row in a particular bank or the open row in all banks. The
bank(s) will be available for a subsequent row access some specified time (tRP) after the Precharge command is
issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank
is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are
treated as “Don’t Care”. Once a bank has been precharged, it is in the idle state and must be activated prior to any
Read or Write commands being issued to that bank.
CK
CK
CKE
HIGH
CS
RAS
CAS
WE
A0-A9, A11, A12
All Banks
A10
BA0, BA1
One Bank
BA
BA = bank address
(if A10 is Low, otherwise Don’t Care).
Don’t Care
Figure 26
Datasheet
Precharge Command
41
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
3.5.5
Power-Down
Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down occurs
when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a
row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input
and output buffers, excluding CK, CK and CKE. The DLL is still running in Power Down mode, so for maximum
power savings, the user has the option of disabling the DLL prior to entering Power-down. In that case, the DLL
must be enabled after exiting power-down, and 200 clock cycles must occur before a Read command can be
issued. In power-down mode, CKE Low and a stable clock signal must be maintained at the inputs of the
DDR SGRAM, and all other input signals are “Don’t Care”. However, power-down duration is limited by the refresh
requirements of the device, so in most applications, the self refresh mode is preferred over the DLL-disabled
power-down mode.
The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or Deselect
command). A valid, executable command may be applied one clock cycle later.
CK
CK
tIS
CKE
Command
VALID
tIS
NOP
NOP
No column
access in
progress
Exit
power down
mode
Don’t Care
Enter Power Down mode
(Burst Read or Write operation
must not be in progress)
Figure 27
Datasheet
VALID
Power Down
42
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
Table 7
Truth Table 2: Clock Enable (CKE)
Current State CKE n-1
CKEn
Command n
Action n
Notes
Previous
Cycle
Current
Cycle
Self Refresh
L
L
X
Maintain Self-Refresh
–
Self Refresh
L
H
Deselect or NOP
Exit Self-Refresh
1)
Power Down
L
L
X
Maintain Power-Down
–
Power Down
L
H
Deselect or NOP
Exit Power-Down
–
All Banks Idle
H
L
Deselect or NOP
Precharge Power-Down Entry –
All Banks Idle
H
L
AUTO REFRESH
Self Refresh Entry
–
Bank(s) Active H
L
Deselect or NOP
Active Power-Down Entry
–
H
H
See Table 8
–
–
1) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A
minimum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
1.
2.
3.
4.
CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
Current state is the state of the DDR SGRAM immediately prior to clock edge n.
COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.
All states and sequences not shown are illegal or reserved.
Table 8
Truth Table 3: Current State Bank n - Command to Bank n (same bank)
Current State CS
Any
Idle
Row Active
Read (Auto
Precharge
Disabled)
Write (Auto
Precharge
Disabled)
RAS CAS WE
Command
Action
Notes
H
X
X
X
Deselect
NOP. Continue previous operation.
1)2)3)4)5)6)
L
H
H
H
No Operation
NOP. Continue previous operation.
1) to 6)
L
L
H
H
Active
Select and activate row
1) to 6)
L
L
L
H
AUTO REFRESH
–
1) to 7)
L
L
L
L
MODE
REGISTER SET
–
1) to 7)
L
H
L
H
Read
Select column and start Read burst
1) to 6), 8)
L
H
L
L
Write
Select column and start Write burst
1) to 6), 8)
L
L
H
L
Precharge
Deactivate row in bank(s)
1) to 6), 9)
L
H
L
H
Read
Select column and start new Read
burst
1) to 6), 8)
L
L
H
L
Precharge
Truncate Read burst, start
Precharge
1) to 6), 9)
L
H
H
L
BURST
TERMINATE
BURST TERMINATE
1) to 6), 10)
L
H
L
H
Read
Select column and start Read burst
1) to 6), 8), 11)
L
H
L
L
Write
Select column and start Write burst
1) to 6), 8)
L
L
H
L
Precharge
Truncate Write burst, start Precharge
1) to 6), 9), 11)
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 7 and after tXSNR/tXSRD has been met (if the
previous state was self refresh).
2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are
those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
Datasheet
43
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
3) Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register
accesses are in progress.
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
4) The following states must not be interrupted by a command issued to the same bank.
Precharging: Starts with registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank is in
the idle state.
Row Activating: Starts with registration of an Active command and ends when tRCD is met. Once tRCD is met, the bank is in
the “row active” state.
Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when
tRP has been met. Once tRP is met, the bank is in the idle state.
Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when
tRP has been met. Once tRP is met, the bank is in the idle state.
Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring
during these states. Allowable commands to the other bank are determined by its current state and according to Table 9.
5) The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied
on each positive clock edge during these states.
Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. Once tRFC is met, the
DDR SGRAM is in the “all banks idle” state.
Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when tMRD has been met.
Once tMRD is met, the DDR SGRAM is in the “all banks idle” state.
Precharging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks
is in the idle state.
6) All states and sequences not shown are illegal or reserved.
7) Not bank-specific; requires that all banks are idle.
8) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads
or Writes with Auto Precharge disabled.
9) May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.
10) Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank.
11) Requires appropriate DM masking.
Datasheet
44
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
Table 9
Truth Table 4: Current State Bank n - Command to Bank m (different bank)
Current State
CS
RAS CAS WE
Command
Action
Notes
H
X
X
X
Deselect
NOP. Continue previous operation.
1)2)3)4)5)6)
L
H
H
H
No Operation
NOP. Continue previous operation.
1) to 6)
Idle
X
X
X
X
Any Command
Otherwise Allowed
to Bank m
–
1) to 6)
Row Activating,
Active, or
Precharging
L
L
H
H
Active
Select and activate row
1) to 6)
L
H
L
H
Read
Select column and start Read burst
1) to 7)
L
H
L
L
Write
Select column and start Write burst
1) to 7)
L
L
H
L
Precharge
–
1) to 6)
L
L
H
H
Active
Select and activate row
1) to 6)
L
H
L
H
Read
Select column and start new Read
burst
1) to 7)
L
L
H
L
Precharge
–
1) to 6)
L
L
H
H
Active
Select and activate row
1) to 6)
L
H
L
H
Read
Select column and start Read burst
1) to 8)
L
H
L
L
Write
Select column and start new Write
burst
1) to 7)
L
L
H
L
Precharge
–
1) to 6)
Read (With Auto L
Precharge)
L
L
H
H
Active
Select and activate row
1) to 6)
H
L
H
Read
Select column and start new Read
burst
1) to 7), 9)
L
H
L
L
Write
Select column and start Write burst
1) to 7), 9), 10)
L
L
H
L
Precharge
–
1) to 6)
Write (With Auto L
Precharge)
L
L
H
H
Active
Select and activate row
1) to 6)
H
L
H
Read
Select column and start Read burst
1) to 7), 9)
L
H
L
L
Write
Select column and start new Write
burst
1) to 7), 9)
L
L
H
L
Precharge
–
1) to 6)
Any
Read (Auto
Precharge
Disabled)
Write (Auto
Precharge
Disabled)
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 7: Clock Enable (CKE) and after tXSNR/tXSRD
has been met (if the previous state was self refresh).
2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands
shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is
allowable). Exceptions are covered in the notes below.
3) Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register
accesses are in progress.
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Read with Auto Precharge Enabled: See 10).
Write with Auto Precharge Enabled: See 10).
4) AUTO REFRESH and Mode Register Set commands may only be issued when all banks are idle.
5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state
only.
6) All states and sequences not shown are illegal or reserved.
Datasheet
45
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
7) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads
or Writes with Auto Precharge disabled.
8) Requires appropriate DM masking.
9) Concurrent Auto Precharge:
This device supports “Concurrent Auto Precharge”. When a read with auto precharge or a write with auto precharge is
enabled any command may follow to the other banks as long as that command does not interrupt the read or write data
transfer and all other limitations apply (e.g. contention between READ data and WRITE data must be avoided). The
minimum delay from a read or write command with auto precharge enable, to a command to a different banks is
summarized in Table 10.
10) A Write command may be applied after the completion of data output.
Table 10
Truth Table 5: Concurrent Auto Precharge
From Command
To Command (different bank)
Minimum Delay with Concurrent
Auto Precharge Support
Unit
WRITE w/AP
Read or Read w/AP
1 + (BL/2) + tWTR
Write to Write w/AP
BL/2
Precharge or Activate
1
Read or Read w/AP
BL/2
Write or Write w/AP
CL (rounded up) + BL/2
Precharge or Activate
1
tCK
tCK
tCK
tCK
tCK
tCK
Read w/AP
Datasheet
46
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
3.6
Simplified State Diagram
Power
Applied
Power
On
Self
Refresh
Precharge
PREALL
REFS
REFSX
MRS
EMRS
MRS
CKEH
Active
Power
Down
Auto
Refresh
REFA
Idle
CKEL
ACT
Precharge
Power
Down
CKEH
CKEL
Burst Stop
Row
Active
Write
Write A
Read
Read A
Write
Read
Read
Read A
Write A
PRE
Write
A
PRE
PRE
PRE
Read
A
Read
A
Precharge
PREALL
Automatic Sequence
Command Sequence
PREALL = Precharge All Banks
MRS = Mode Register Set
EMRS = Extended Mode Register Set
REFS = Enter Self Refresh
REFSX = Exit Self Refresh
REFA = Auto Refresh
Figure 28
Datasheet
CKEL = Enter Power Down
CKEH = Exit Power Down
ACT = Active
Write A = Write with Autoprecharge
Read A = Read with Autoprecharge
PRE = Precharge
Simplified State Diagram
47
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Electrical Characteristics
4
Electrical Characteristics
4.1
Operating Conditions
Table 11
Absolute Maximum Ratings
Parameter
Symbol
Voltage on I/O pins relative to VSS
VIN, VOUT
VIN
VDD
VDDQ
TA
TSTG
PD
IOUT
Voltage on Inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating Temperature (Ambient)
Storage Temperature (Plastic)
Power Dissipation
Short Circuit Output Current
Values
Unit Note/
Test Condition
Min.
Typ.
Max.
–0.5
—
VDDQ + 0.5 V
—
–0.5
—
+3.6
V
—
–0.5
—
+3.6
V
—
–0.5
—
+3.6
V
—
0
—
+70
°C
—
–55
—
+150
°C
—
—
1.5
—
W
—
—
50
—
mA
—
Attention: Stresses above those listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values may cause
irreversible damage to the integrated circuit.
Table 12
Input and Output Capacitances
Parameter
Input Capacitance: CK, CK
Delta Input Capacitance
Input Capacitance:
All other input-only pins
Delta Input Capacitance:
All other input-only pins
Symbol
Values
Unit
Note/
Test Condition
Min.
Typ.
Max.
CI1
CdI1
CI2
2.0
—
3.0
pF
P-TSOPII-66-11)
—
—
0.25
pF
1)
2.0
—
3.0
pF
P-TSOPII-66-1 1)
CdIO
—
—
0.5
pF
1)
4.0
—
5.0
pF
P-TSOPII-66-1
Input/Output Capacitance: DQ, DQS, DM CIO
2)1)2)
Delta Input/Output Capacitance:
DQ, DQS, DM
CdIO
—
—
0.5
pF
1)
1) These values are guaranteed by design and are tested on a sample base only. VDDQ = VDD = 2.5 V ± 0.2 V, f = 100 MHz,
TA = 25 °C, VOUT(DC) = VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins are tied to ground.
2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace
matching at the board level.
Datasheet
48
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Electrical Characteristics
Table 13
Electrical Characteristics and DC Operating Conditions 1)
Parameter
Symbol
VDD
I/O Supply Voltage
VDDQ
Supply Voltage, I/O Supply
VSS,
Voltage
VSSQ
I/O Reference Voltage
VREF
I/O Termination Voltage (System) VTT
Input High (Logic1) Voltage
VIH(DC)
Input Low (Logic0) Voltage
VIL(DC)
Input Voltage Level,
VIN(DC)
Supply Voltage
Values
Unit Note/Test Condition 2)
Min.
Max.
2.5
2.7
V
DDR400 2)
2.5
2.7
V
DDR400 2)
0
0
V
—
0.49 × VDDQ 0.51 × VDDQ V
2)3)
VREF – 0.04 VREF + 0.04
VREF + 0.15 VDDQ + 0.3
–0.3
VREF – 0.15
–0.3
VDDQ + 0.3
V
2)4)
V
2)
V
2)
V
2)
CK and CK Inputs
Input Differential Voltage,
CK and CK Inputs
VID(DC)
0.36
VDDQ + 0.6
V
2)5)
VI-Matching Pull-up Current to
Pull-down Current
VIRatio
0.71
1.4
—
6)
Input Leakage Current
II
–2
2
µA
Any input 0 V ≤ VIN ≤ VDD; 2)
All other pins not under test = 0 V
Output Leakage Current
IOZ
–5
5
µA
DQs are disabled;
0 V ≤ VOUT ≤ VDDQ 2)
Output High Current, Normal
Strength Driver
IOH
—
–16.2
mA
VOUT = 1.95 V 2)
Output Low Current, Normal
Strength Driver
IOL
16.2
—
mA
VOUT = 0.35 V 2)
1) 0 °C ≤ TA ≤ 70 °C
2) VREF is expected to be equal to 0.5 x VDDQ of the transmitting device, and to track variations in the DC level of the same.
Peak-to-peak noise on VREF may not exceed ± 2% of the DC value.
3) VREF is expected to be equal to 0.5 x VDDQ of the transmitting device, and to track variations in the DC level of the same.
Peak-to-peak noise on VREF may not exceed ± 2% of the DC value.
4) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF, and must track variations in the DC level of VREF.
5) VID is the magnitude of the difference between the input level on CK and the input level on CK.
6) The ration of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the
maximum difference between pull-up and pull-down drivers due to process variation.
Datasheet
49
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Electrical Characteristics
4.2
Normal Strength Pull-down and Pull-up Characteristics
1. The nominal pull-down V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve.
2. The full variation in driver pull-down current from minimum to maximum process, temperature, and voltage lie
within the outer bounding lines of the V-I curve.
3. The nominal pull-up V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the inner
bounding lines of the V-I curve.
4. The full variation in driver pull-up current from minimum to maximum process, temperature, and voltage lie
within the outer bounding lines of the V-I curve.
5. The full variation in the ratio of the maximum to minimum pull-up and pull-down current does not exceed 1.7,
for device drain to source voltages from 0.1 to 1.0.
6. The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device drain
to source voltages from 0.1 to 1.0 V.
140
Maximum
IOUT (mA)
120
100
Nominal High
80
60
Nominal Low
40
Minimum
20
0
0
0.5
1
1.5
2
2.5
VDDQ - VOUT (V)
Figure 29
Normal Strength Pull-down Characteristics
0
-20
Minimum
IOUT (mA)
-40
Nominal Low
-60
-80
-100
-120
-140
Nominal High
-160
Maximum
0
Figure 30
Datasheet
0.5
1
1.5
VDDQ - VOUT (V)
2
2.5
Normal Strength Pull-up Characteristics
50
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Electrical Characteristics
Table 14
Normal Strength Pull-down and Pull-up Currents
Voltage (V)
Pulldown Current (mA)
Pullup Current (mA)
Nominal
Low
Nominal
High
Min.
Max.
Nominal
Low
Nominal
High
Min.
Max.
0.1
6.0
6.8
4.6
9.6
-6.1
-7.6
-4.6
-10.0
0.2
12.2
13.5
9.2
18.2
-12.2
-14.5
-9.2
-20.0
0.3
18.1
20.1
13.8
26.0
-18.1
-21.2
-13.8
-29.8
0.4
24.1
26.6
18.4
33.9
-24.0
-27.7
-18.4
-38.8
0.5
29.8
33.0
23.0
41.8
-29.8
-34.1
-23.0
-46.8
0.6
34.6
39.1
27.7
49.4
-34.3
-40.5
-27.7
-54.4
0.7
39.4
44.2
32.2
56.8
-38.1
-46.9
-32.2
-61.8
0.8
43.7
49.8
36.8
63.2
-41.1
-53.1
-36.0
-69.5
0.9
47.5
55.2
39.6
69.9
-43.8
-59.4
-38.2
-77.3
1.0
51.3
60.3
42.6
76.3
-46.0
-65.5
-38.7
-85.2
1.1
54.1
65.2
44.8
82.5
-47.8
-71.6
-39.0
-93.0
1.2
56.2
69.9
46.2
88.3
-49.2
-77.6
-39.2
-100.6
1.3
57.9
74.2
47.1
93.8
-50.0
-83.6
-39.4
-108.1
1.4
59.3
78.4
47.4
99.1
-50.5
-89.7
-39.6
-115.5
1.5
60.1
82.3
47.7
103.8
-50.7
-95.5
-39.9
-123.0
1.6
60.5
85.9
48.0
108.4
-51.0
-101.3
-40.1
-130.4
1.7
61.0
89.1
48.4
112.1
-51.1
-107.1
-40.2
-136.7
1.8
61.5
92.2
48.9
115.9
-51.3
-112.4
-40.3
-144.2
1.9
62.0
95.3
49.1
119.6
-51.5
-118.7
-40.4
-150.5
2.0
62.5
97.2
49.4
123.3
-51.6
-124.0
-40.5
-156.9
2.1
62.9
99.1
49.6
126.5
-51.8
-129.3
-40.6
-163.2
2.2
63.3
100.9
49.8
129.5
-52.0
-134.6
-40.7
-169.6
2.3
63.8
101.9
49.9
132.4
-52.2
-139.9
-40.8
-176.0
2.4
64.1
102.8
50.0
135.0
-52.3
-145.2
-40.9
-181.3
2.5
64.6
103.8
50.2
137.3
-52.5
-150.5
-41.0
-187.6
2.6
64.8
104.6
50.4
139.2
-52.7
-155.3
-41.1
-192.9
2.7
65.0
105.4
50.5
140.8
-52.8
-160.1
-41.2
-198.2
Table 15
Evaluation Conditions for I/O Driver Characteristics
Parameter
Nominal
Minimum
Maximum
Operating Temperature
25 °C
0 °C
70 °C
VDD/VDDQ
2.5 V
2.3 V
2.7 V
Process Corner
typical
slow-slow
fast-fast
Datasheet
51
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Electrical Characteristics
4.3
Weak Strength Pull-down and Pull-up Characteristics
1. The weak pull-down V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the inner
bounding lines of the V-I curve.
2. The weak pull-up V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the inner
bounding lines of the V-I curve.
3. The full variation in driver pull-up current from minimum to maximum process, temperature, and voltage lie
within the outer bounding lines of the V-I curve.
4. The full variation in the ratio of the maximum to minimum pull-up and pull-down current does not exceed 1.7,
for device drain to source voltages from 0.1 to 1.0.
5. The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device drain
to source voltages from 0.1 to 1.0 V.
80
Maximum
70
Iout [mA]
60
Typical high
50
Typical low
40
30
Minimum
20
10
0
0,0
0,5
1,0
1,5
2,0
2,5
Vout [V]
Figure 31
Weak Strength Pull-down Characteristics
0,0
0,0
0,5
1,0
1,5
2,0
2,5
-10,0
Minimum
-20,0
Iout [V]
-30,0
Typical low
-40,0
-50,0
Typical high
-60,0
-70,0
Maximum
-80,0
Vout [V]
Figure 32
Datasheet
Weak Strength Pull-up Characteristics
52
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Electrical Characteristics
Table 16
Weak Strength Driver Pull-down and Pull-up Characteristics
Voltage (V)
Pulldown Current (mA)
Pullup Current (mA)
Nominal
Low
Nominal
High
Min.
Max.
Nominal
Low
Nominal
High
Min.
Max.
0.1
3.4
3.8
2.6
5.0
-3.5
-4.3
-2.6
-5.0
0.2
6.9
7.6
5.2
9.9
-6.9
-8.2
-5.2
-9.9
0.3
10.3
11.4
7.8
14.6
-10.3
-12.0
-7.8
-14.6
0.4
13.6
15.1
10.4
19.2
-13.6
-15.7
-10.4
-19.2
0.5
16.9
18.7
13.0
23.6
-16.9
-19.3
-13.0
-23.6
0.6
19.6
22.1
15.7
28.0
-19.4
-22.9
-15.7
-28.0
0.7
22.3
25.0
18.2
32.2
-21.5
-26.5
-18.2
-32.2
0.8
24.7
28.2
20.8
35.8
-23.3
-30.1
-20.4
-35.8
0.9
26.9
31.3
22.4
39.5
-24.8
-33.6
-21.6
-39.5
1.0
29.0
34.1
24.1
43.2
-26.0
-37.1
-21.9
-43.2
1.1
30.6
36.9
25.4
46.7
-27.1
-40.3
-22.1
-46.7
1.2
31.8
39.5
26.2
50.0
-27.8
-43.1
-22.2
-50.0
1.3
32.8
42.0
26.6
53.1
-28.3
-45.8
-22.3
-53.1
1.4
33.5
44.4
26.8
56.1
-28.6
-48.4
-22.4
-56.1
1.5
34.0
46.6
27.0
58.7
-28.7
-50.7
-22.6
-58.7
1.6
34.3
48.6
27.2
61.4
-28.9
-52.9
-22.7
-61.4
1.7
34.5
50.5
27.4
63.5
-28.9
-55.0
-22.7
-63.5
1.8
34.8
52.2
27.7
65.6
-29.0
-56.8
-22.8
-65.6
1.9
35.1
53.9
27.8
67.7
-29.2
-58.7
-22.9
-67.7
2.0
35.4
55.0
28.0
69.8
-29.2
-60.0
-22.9
-69.8
2.1
35.6
56.1
28.1
71.6
-29.3
-61.2
-23.0
-71.6
2.2
35.8
57.1
28.2
73.3
-29.5
-62.4
-23.0
-73.3
2.3
36.1
57.7
28.3
74.9
-29.5
-63.1
-23.1
-74.9
2.4
36.3
58.2
28.3
76.4
-29.6
-63.8
-23.2
-76.4
2.5
36.5
58.7
28.4
77.7
-29.7
-64.4
-23.2
-77.7
2.6
36.7
59.2
28.5
78.8
-29.8
-65.1
-23.3
-78.8
2.7
36.8
59.6
28.6
79.7
-29.9
-65.8
-23.3
-79.7
Datasheet
53
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Electrical Characteristics
4.4
AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating
Conditions, IDD Specifications and Conditions, and Electrical Characteristics and AC Timing.)
Notes
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal
reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full
voltage range specified.
3. Figure 33 represents the timing reference load used in defining the relevant timing parameters of the part. It
is not intended to be either a precise representation of the typical system environment nor a depiction of the
actual load presented by a production tester. System designers will use IBIS or other simulation tools to
correlate the timing reference load to a system environment. Manufacturers will correlate to their production
test conditions (generally a coaxial transmission line terminated at the tester electronics).
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is
still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for
the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is
1 V/ns in the range between VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively
switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal
does not ring back above (below) the DC input LOW (HIGH) level).
6. For System Characteristics like Setup & Holdtime Derating for Slew Rate, I/O Delta Rise/Fall Derating, DDR
SDRAM Slew Rate Standards, Overshoot & Undershoot specification and Clamp V-I characteristics see the
latest JEDEC specification for DDR components.
VTT
50 Ω
Output
(VOUT)
Timing Reference Point
30 pF
Figure 33
Datasheet
AC Output Load Circuit Diagram / Timing Reference Load
54
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Electrical Characteristics
Table 17
AC Operating Conditions1)
Parameter
Symbol
Values
Min.
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
Input High (Logic 1) Voltage, DQ, DQS and DM Signals
Input Low (Logic 0) Voltage, DQ, DQS and DM Signals
Input Differential Voltage, CK and CK Inputs
Input Closing Point Voltage, CK and CK Inputs
Unit Note/
Test
Condition
Max.
VREF + 0.31 —
—
VREF – 0.31
0.7
VDDQ + 0.6
0.5 × VDDQ 0.5 × VDDQ
– 0.2
V
2)3)
V
2)3)
V
2)3)4)
V
2)3)5)
+ 0.2
1) VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V ; 0 °C ≤ TA ≤ 70 °C
2) Input slew rate = 1 V/ns.
3) Inputs are not recognized as valid until VREF stabilizes.
4) VID is the magnitude of the difference between the input level on CK and the input level on CK.
5) The value of VIX is expected to equal 0.5 × VDDQ of the transmitting device and must track variations in the DC level of the
same.
Table 18
Electrical Characteristics and AC Timing - Absolute Specifications –4/–5 1)
Parameter
Symbol
–4
–5
Unit Note/Test Condition
Min.
Max.
Min.
Max.
tAC
tDQSCK
tCH
tCL
tHP
tCK
tDH
tDS
tIPW
–0.6
+0.6
–0.65
+0.65
ns
2)3)4)5)
–0.65
+0.65
–0.65
+0.65
ns
2)3)4)5)
0.45
0.55
0.45
0.55
2)3)4)5)
0.45
0.55
0.45
0.55
tCK
tCK
min. (tCL, tCH) ns
2)3)4)5)
DQ and DM input pulse width (each
input)
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock Half Period
min. (tCL, tCH)
2)3)4)5)
4
12
5
12
ns
CL = 3.02)3)4)5)
0.4
—
0.4
—
ns
2)3)4)5)
0.4
—
0.4
—
ns
2)3)4)5)
2.2
—
2.2
—
ns
2)3)4)5)6)
tDIPW
1.75
—
1.75
—
ns
2)3)4)5)6)
Data-out high-impedance time from
CK/CK
tHZ
–0.7
0.7
–0.7
+0.7
ns
2)3)4)5)7)
Data-out low-impedance time from
CK/CK
tLZ
–0.7
0.7
–0.7
+0.7
ns
2)3)4)5)7)
Write command to 1st DQS latching
transition
tDQSS
0.85
1.15
0.75
1.25
tCK
2)3)4)5)
DQS-DQ skew (DQS and associated
DQ signals)
tDQSQ
—
0.5
—
0.5
ns
P-TSOPII-66-1
Data hold skew factor
tQHS
—
DQ/DQS output hold time
tQH
tHP –
tQHS
—
tHP –
tQHS
—
ns
2)3)4)5)
DQS input low (high) pulse width (write
cycle)
tDQSL,H
0.35
—
0.35
—
tCK
2)3)4)5)
Clock cycle time
DQ and DM input hold time
DQ and DM input setup time
Control and Addr. input pulse width
(each input)
Datasheet
2)3)4)5)
0.4
—
0.5
ns
P-TSOPII-66-1
2)3)4)5)
55
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Electrical Characteristics
Table 18
Electrical Characteristics and AC Timing - Absolute Specifications –4/–5 1) (cont’d)
Parameter
Symbol
–4
–5
Unit Note/Test Condition
Min.
Max.
Min.
Max.
DQS falling edge to CK setup time (write tDSS
cycle)
0.2
—
0.2
—
tCK
2)3)4)5)
tDSH
0.2
—
0.2
—
tCK
2)3)4)5)
2
—
2
—
tCK
2)3)4)5)
0
—
0
—
ns
2)3)4)5)8)
0.40
0.60
0.40
0.60
2)3)4)5)9)
0.25
—
0.25
—
tCK
tCK
0.6
—
0.6
—
ns
2)4)5)6)10)
0.6
—
0.6
—
ns
2)4)5)6)10)
0.9
1.1
0.9
1.1
2)3)4)5)
0.4
0.6
0.4
0.6
tCK
tCK
36
70E+3 40
70E+3 ns
2)3)4)5)
52
—
55
—
ns
2)3)4)5)
DQS falling edge hold time from CK
(write cycle)
tMRD
Write preamble setup time
tWPRES
Write postamble
tWPST
Write preamble
tWPRE
Address and control input setup time
tIS
Address and control input hold time
tIH
Read preamble
tRPRE
Read postamble
tRPST
Active to Precharge command
tRAS
Active to Active/Auto-refresh command tRC
Mode register set command cycle time
2)3)4)5)
2)3)4)5)
period
Auto-refresh to Active/Auto-refresh
command period
tRFC
60
—
65
—
ns
2)3)4)5)
Active to Read delay
tRCDRD
tRCDWR
tRP
tRAP
tRRD
16
—
20
—
ns
2)3)4)5)
12
—
15
—
16
—
20
—
ns
2)3)4)5)
16
—
20
—
ns
2)3)4)5)
8
—
10
—
ns
2)3)4)5)
tWR
tDAL
15
—
15
—
ns
2)3)4)5)
28
—
35
—
tCK
2)3)4)5)10)
tWTR
tXSNR
tXSRD
tREFI
1
—
1
—
tCK
2)3)4)5)
Active to Write delay
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B
command
Write recovery time
Auto precharge write recovery +
precharge time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
75
—
75
—
ns
2)3)4)5)
200
—
200
—
tCK
2)3)4)5)
—
7.8
—
7.8
µs
2)3)4)5)11)
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V
2) Input slew rate ≥ 1 V/ns
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
Datasheet
56
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Electrical Characteristics
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
11) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Table 19
IDD Conditions
Parameter
Symbol
IDD0
Operating Current 0
one bank; active/ precharge; tRC = tRC,MIN;
DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
Operating Current 1
IDD1
one bank; active/read/precharge; Burst Length = 4; Refer to Chapter 4.4.1 for detailed test conditions.
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE £ VIL,MAX
IDD2P
Precharge Floating Standby Current
CS Š VIH,,MIN, all banks idle; CKE Š VIH,MIN;
address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.
IDD2F
Precharge Quiet Standby Current
IDD2Q
CS Š VIHMIN, all banks idle; CKE Š VIH,MIN;
address and other control inputs stable at Š VIH,MIN or £ VIL,MAX; VIN = VREF for DQ, DQS and DM.
Active Power-Down Standby Current
one bank active; power-down mode; CKE £ VILMAX; VIN = VREF for DQ, DQS and DM.
IDD3P
Active Standby Current
one bank active; CS Š VIH,MIN; CKE Š VIH,MIN; tRC = tRAS,MAX;
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
IDD3N
Operating Current Read
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 3 ; IOUT = 0 mA
IDD4R
Operating Current Write
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 3
IDD4W
Auto-Refresh Current
tRC = tRFCMIN, distributed refresh
IDD5
Self-Refresh Current
CKE £ 0.2 V; external clock on
IDD6
Operating Current 7
four bank interleaving with Burst Length = 4; Refer to Chapter 4.4.1 for detailed test conditions.
IDD7
Datasheet
57
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Electrical Characteristics
Table 20
IDD Specification
Parameter
Symbol
–4
–5
Unit Note/ Test Condition 1)
Typ. Max. Typ. Max.
IDD0
Operating Current 1
IDD1
Precharge Power-Down Standby Current IDD2P
Precharge Floating Standby Current
IDD2F
Precharge Quiet Standby Current
IDD2Q
Active Power-Down Standby Current
IDD3P
Active Standby Current
IDD3N
Operating Current Read
IDD4R
Operating Current Write
IDD4W
Auto-Refresh Current
IDD5
Self-Refresh Current
IDD6
Operating Current 7
IDD7
Operating Current 0
–
115
75
90
mA
2)3)3)
–
135
95
110
mA
3)3)
–
6
4
5
mA
3)3)
–
45
30
36
mA
3)3)
–
35
20
28
mA
3)3)
–
23
13
18
mA
3)3)
–
65
43
54
mA
3)3)
–
150
100
120
mA
–
160
100
130
mA
3)3)
–
240
140
190
mA
3)3)
–
2.8
1.4
2.8
mA
3)4)
–
315
210
250
mA
3)
3)3)
1) Test conditions for typical values: VDD = 2.6 V , TA = 25 °C, test conditions for maximum values: VDD = 2.7 V, TA = 10 °C
2) IDD specifications are tested after the device is properly initialized and measured at 200 MHz.
3) Input slew rate = 1 V/ns.
4) Enables on-chip refresh and address counters.
4.4.1
IDD Current Measurement Conditions
Legend: A = Activate, R = Read, RA = Read with Autoprecharge, P = Precharge, N = NOP or DESELECT
IDD1: Operating Current: One Bank Operation
1. General test condition
a) Only one bank is accessed with tRC,MIN.
b) Burst Mode, Address and Control inputs are changing once per NOP and DESELECT cycle.
c) 50% of data changing at every transfer
d) IOUT = 0 mA.
2. Timing patterns
a) (200 MHz, CL = 3): tCK = 5 ns, BL = 4, tRCD = 3 × tCK, tRC = 11 × tCK, tRAS = 8 × tCK
Setup:A0 N N R0 N N N N P0 N N
Read: A0 N N R0 N N N N P0 N N -repeat the same timing with random address changing
IDD7: Operating Current: Four Bank Operation
1. General test condition
a) Four banks are being interleaved with tRCMIN.
b) Burst Mode, Address and Control inputs on NOP edge are not changing.
c) 50% of data changing at every transfer
d) IOUT = 0 mA.
2. Timing patterns
a) (200 MHz, CL = 3): tCK = 5 ns, BL = 4, tRRD = 2 × tCK, tRCD = 3 *× tCK, tRAS = 8 × tCK
Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N
Read: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N - repeat the same timing with random address
Datasheet
58
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Timing Diagrams
5
Timing Diagrams
All Timing diagrams are based on DDR400 Time settings. For Time settings based on DDR500 see Table 18.
W '64/
W '46+
'46
W '+
W '6
'4
',Q
'0
PSWG
Figure 34
Data Input (Write), Timing Burst Length = 4
Note:
1. DI n = Data In for column n.
2. 3 subsequent elements of data in are applied in programmed order following DI n.
'46
W 4+
W'464B0$;
'4
PSWG
Figure 35
Data Output (Read), Timing Burst Length = 4
Note:
1. tQH (Data output hold time from DQS)
2. tDQSQ and tQH are only shown once and are shown referenced to different edges of DQS, only for clarify of
illustration.
3. tDQSQ and tQH both apply to each of the four relevant edges of DQS.
4. tDQSQ max. is used to determine the worst case setup time for controller data capture.
5. tQH is used to determine the worst case hold time for controller data capture.
Datasheet
59
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
PSWG
/RDG
0RGH
5HJLVWHU
ZLWK$ %$
5$
&2'(
$5
W5)&
/RDG0RGH
5HJLVWHU
5HVWHW'//
$//%$1.6
([WHQGHG
0RGH
5HJLVWHU
6HW
&2'(
&2'(
$
$//%$1.6
&2'(
$$>@
3RZHUXS
9''DQG
&.VWDEOH
+LJK=
'4
'46
+LJK=
%$>@
'0
&RPPDQG
&.(
&.
&.
95()
977 6\VWHP
9''
Figure 36
9''4
W97'
/9&026/2:/(9(/
—V
W,6
123
W,+
W&+
W&.
W&/
W,6
35(
W,+
W,6
(056
W,+
W05'
056
&2'(
W05'
W,6
35(
W,+
W53
$5
W5)&
F\FOHVRI&.
056
&2'(
W05'
5$
$&7
Timing Diagrams
Initialize and Mode Register Sets
Note:
1. * VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device
latchup.
2. ** tMRD is required before any command can be applied and 200 cycles of CK are required before a Read
command can be applied.
3. The two Autorefresh commands may be moved to follow the first MRS, but precede the second Precharge All
command.
4. The Timing reference is shown with respect to Vref-Crossing.
Datasheet
60
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
([LW3RZHU
'RZQ0RGH
9$/,'
Figure 37
'0
'4
'46
9$/,'
$''5
&RPPDQG
&.(
&.
&.
W,6
9$/,'
W,+
W&.
W,6
123
W&+
(QWHU3RZHU
'RZQ0RGH
W&/
W,6
123
9$/,'
PSWG
Timing Diagrams
Power Down Mode
Note:
1. No column accesses are allowed to be in progress at the time power down is entered.
2. * = If this command is a Precharge (or if the device is already in the idle state) then the power down mode
shown is Precharge power down. If this command is an Active (or if at least one row is already active), then
the power down mode shown is Active power down.
3. The Timing reference is shown with respect to Vref-Crossing.
Datasheet
61
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
PSWG
%$
5$
5$
123
9$/,'
123
&.(
&RPPDQG
Figure 38
%$
21(%$1.
$//%$1.6
'0
'4
'46
%$>@
$
$>@$>@
&.
&.
W,6
123
W,+
W,6
35(
W,+
W&.
W&+
W&/
W53
123
123
$5
W5)&
123
$5
9$/,'
W5)&
123
$&7
Timing Diagrams
Auto Refresh Mode
Note:
1.
2.
3.
4.
PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address; AR = Autorefresh.
NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
DM, DQ, and DQS signals are all don't care/high-Z for operations shown.
The Timing reference is shown with respect to Vref-Crossing.
Datasheet
62
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
PSWG
)LUVW5HDG
DIWHU6HOI
5HIUHVK([LW
SRVVLEOH
9$/,'
W,+
W,6
Figure 39
1RQ5'
([LW6HOI
5HIUHVK0RGH
123
(QWHU6HOI
5HIUHVK0RGH
'0
'4
'46
$''5
123
&RPPDQG
&.(
&.
&.
W,6
W53
W,+
W&+
W&.
W&/
W,6
$5
W,6
123
W;615
W;65'
F\FOHV
1RQ5'
9$/,'
Timing Diagrams
Self Refresh Mode
Note:
1. * = Device must be in the all banks idle state before entering Self Refresh Mode.
2. ** = tXSNR is required before any non-read command can be applied, and tXSRD (200 cycles of CK) are
required before a Read command can be applied.
3. The Timing reference is shown with respect to Vref-Crossing.
Datasheet
63
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
W$&PD[
4
W/=0$;
4
4
W5367
W'46&.PD[
4
W$&0,1
W5367
4
4
W535(
&/ %$
W/=0$;
4
W/=0,1
Figure 40
%$
',6$3
&$
5($'
'4
'46
'4
'46
'0
%$>@
$
$$$>@
&RPPDQG
&.(
&.
&.
W,6
123
W,+
W,6
W,+
W&.
123
21(%$1.
$//%$1.6
123
35(
W&/
W&+
4
W'46&.0,1
W535(
W53
123
W/=0,1
123
W,+
W+=0,1
W+=PD[
%$
5$
5$
$&7
123
9$/,'
123
9$/,'
123
9$/,'
PSWG
Timing Diagrams
Read without Auto Precharge (Burst Length = 4)
Note:
1.
2.
3.
4.
5.
DIS AP = Disable Auto Precharge.
Don't care if A10 is High at this point.
PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address.
NOP commands are shown for ease of illustration; other commands may be valid at these times.
The Timing reference is shown with respect to Vref-Crossing.
Datasheet
64
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
PSWG
123
W$&PD[
4
4
W5367
W'46&.PD[
4
W$&0,1
W5367
W/=0$;
4
4
Figure 41
W535(
%$
(1$3
&$
'4
'46
'4
'46
'0
%$>@
$
$$$>@
&.
&.
W,6
123
W,+
W,6
5($'
W,+
W&.
123
W&+
W&/
123
W/=0$;
4
123
W/=0,1
4
4
W'46&.0,1
W535(
W53
123
W/=0,1
123
W,+
W+=0,1
W+=PD[
%$
5$
5$
123
123
&RPPDQG
$&7
9$/,'
&.(
9$/,'
9$/,'
Timing Diagrams
Read with Auto Precharge (Burst Length = 4)
Note:
1.
2.
3.
4.
EN AP = enable Auto Precharge.
ACT = active; RA = row address.
NOP commands are shown for ease of illustration; other commands may be valid at these times.
The Timing reference is shown with respect to Vref-Crossing.
Datasheet
65
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
PSWG
%$
5$
5$
123
W+=PD[
W$&PD[
4
4
W5367
W'46&.PD[
W+=0,1
4
W$&0,1
Figure 42
W535(
%$
',6$3
&$
5$
5$
%$
$$$$
$
%$%$
'4
'46
'4
'46
'0
&RPPDQG
&.(
&.
&.
W,6
123
W,+
W,6
$&7
W,+
W&.
123
W&+
W5&'5'
W&/
123
W,6
5HDG
W,+
W5$6
&/ W/=0$;
W/=0,1
123
W535(
W/=0$;
4
4
W/=0,1
123
W5&
4
4
4
W5367
W'46&.0,1
%$
21(%$1.
$//%$1.6
123
35(
W53
123
$&7
9$/,'
Timing Diagrams
Bank Read Access (Burst Length = 4)
Note:
1.
2.
3.
4.
5.
DIS AP = disable Auto Precharge.
Don't care if A10 is High at this point.
PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address.
NOP commands are shown for ease of illustration; other commands may be valid at these times.
The Timing reference is shown with respect to Vref-Crossing.
Datasheet
66
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
PSWG
%$
5$
5$
Figure 43
W:367
',Q
W:35(6
W'46+
%$
',6$3
&$
'0
'4
'46
%$>@
$
$$$>@
&.
&.
W,6
123
W,+
W,6
:ULWH
W,+
W'466
W&.
W:35(
123
W&+
W'46/
W&/
123
W'6+
123
W,+
123
W:5
123
%$
21(%$1.
$//%$1.6
123
&RPPDQG
35(
9$/,'
&.(
W53
123
$&7
Timing Diagrams
Write without Auto Precharge (Burst Length = 4)
Note:
1.
2.
3.
4.
5.
DIS AP = Disable Auto Precharge.
Don't care if A10 is High at this point.
PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address.
NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
The Timing reference is shown with respect to Vref-Crossing.
Datasheet
67
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
%$
%$[
PSWG
5$
(1$3
5$
123
123
123
9$/,'
123
&RPPDQG
Figure 44
&$
W:367
',Q
W:35(6
W'46+
'0
'4
'46
%$>@
$
$$$>@
&.
&.
W,6
123
W,+
W,6
:ULWH
W,+
W'466
W&.
W:35(
123
W&+
W'46/
W&/
123
W'6+
123
9$/,'
&.(
W:5
9$/,'
W'$/
9$/,'
W53
123
$&7
Timing Diagrams
Write with Auto Precharge (Burst Length = 4)
Note:
1.
2.
3.
4.
EN AP = Enable Auto Precharge.
ACT = Active; RA = Row address; BA = Bank address.
NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
The Timing reference is shown with respect to Vref-Crossing.
Datasheet
68
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
PSWG
W:367
',Q
W'46/
W'466
W:35(6
W:35(
%$
Figure 45
5$
5$
%$
$$$>@
$
%$>@
'0
'4
'46
&.
&.
W,6
123
W,+
W,6
$&7
W,+
W&.
123
W&+
W5&':5
W&/
123
&$
:ULWH
W,+
W,6
',6$3
W5$6
123
W'46+
123
W'6+
123
123
W:5
%$
21(%$1.
$//%$1.6
123
&RPPDQG
35(
9$/,'
&.(
Timing Diagrams
Bank Write Access (Burst Length = 4)
Note:
1.
2.
3.
4.
5.
DIS AP = Disable Auto Precharge.
Don't care if A10 is High at this point.
PRE = Precharge; ACT = Active; RA = Row address.
NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
The Timing reference is shown with respect to Vref-Crossing.
Datasheet
69
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
PSWG
%$
5$
5$
%$
21(%$1.
$//%$1.6
123
Figure 46
W:367
W'46+
W'466
',Q
W:35(6
%$
',6$3
&$
'0
'4
'46
%$>@
$
$$$>@
123
&200$1'
&.(
&.
&.
W,6 W,+
:ULWH
W,6 W,+
W&.
123
W&+
W'46/
W&/
123
W'6+
123
123
W:5
123
35(
9$/,'
W53
123
123
$&7
Timing Diagrams
Write DM Operation (Burst Length = 4)
Note:
1.
2.
3.
4.
DIS AP = Disable Auto Precharge.
Don't care if A10 is High at this point.
PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address.
NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
tDQSS = min.
5. The Timing reference is shown with respect to Vref-Crossing.
Datasheet
70
Rev.1.0, 2004-02
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Package Outlines
Gage Plane
0.65 Basic
0.35 +0.1
-0.05
0.805 REF
10.16 ±0.13
0.25 Basic
1.20 MAX.
Package Outlines
0.05 MIN.
6
0.1
Seating Plane
0.5 ±0.1
11.76 ±0.2
22.22 ±0.13
Lead 1
GPX09261
Figure 47
P-TSOPII-66-1 (Plastic Thin Small Outline Package Type II)
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
SMD = Surface Mounted Device
Datasheet
Dimensions in mm
71
Rev.1.0, 2004-02
www.infineon.com
Published by Infineon Technologies AG