IRF IR3629A High frequency synchronous pwm buck controller with power good output Datasheet

Data Sheet No. PD94726
IR3629/IR3629A MPbF
HIGH FREQUENCY SYNCHRONOUS PWM BUCK CONTROLLER
WITH POWER GOOD OUTPUT
Features
Description
•
•
•
•
The
•
•
•
•
•
•
Internal 600kHz Oscillator (300kHz “A version”)
Operates with Single 5V or 12V Supply
Programmable Over Current Protection
Hiccup Current Limit Using MOSFET RDS(on)
sensing
Precision Reference Voltage (0.6V)
Programmable Soft-Start
Programmable PGood output
Pre-Bias Start-up
Thermal Protection
12-Lead MLP Package
IR3629/IR3629A
is
a
PWM
controller
designed for high performance synchronous Buck
DC/DC applications. The IR3629/IR3629A drives
a pair of external N-MOSFETs using a fixed
600kHz (300kHz “A version”) switching frequency
allowing the use of small external components.
The output voltage can be precisely regulated
using the internal 0.6V reference voltage for low
voltage applications. Protection such as Pre-Bias
startup, hiccup current limit and thermal shutdown
Applications
provide the required system level security in the
•
•
•
•
•
•
•
event of fault conditions.
Distributed Point-of-Loads
Embedded Systems
Storage Systems
DDR Applications
Graphics Cards
Computing Peripheral Voltage Regulators
General DC-DC Converters
Fig. 1: Typical application Circuit
ORDERING INFORMATION
PKG
DESIG
M
M
11/26/2007
PACKAGE
PIN
DESCRIPTION
COUNT
IR3629/IR3629AMPBF
12
IR3629/IR3629AMTRPBF 12
PARTS
PARTS
T&R
PER TUBE PER REEL ORIENTATION
122
-------------3000
Figure A
IR3629/IR3629A MPbF
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND)
•
Vcc Supply Voltage ................................................… -0.5V to 16V
•
Vc Supply Voltage …………………………………….. -0.5V to 30V
•
PGood ………………………………………………… -0.5V to 16V
•
Fb, Comp, SS ……………………..………………….. -0.3V to 3.5V
•
OCset
•
AGnd to PGnd ………………………………….…….. -0.3V to +0.3V
•
Storage Temperature Range ..................................... -65°C To 150°C
•
Operating Junction Temperature Range ................... -40°C To 150°C
•
ESD Classification …………………………………..… JEDEC, JESD22-A114
•
Moisture Sensitivity Level ……………………………. JEDEC Level 2 @ 260oC
………………………………………………… 10mA
Caution: Stresses beyond those listed under “Absolute Maximum Rating” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other conditions beyond
those indicated in the operational sections of the specifications is not implied. Exposure to “Absolute Maximum
Rating” conditions for extended periods may affect device reliability.
Package Information
PGood
1
12
OCSet
VCC
2
11
SS/SD
LDrv
3
10
Gnd
PGnd
4
9
Comp
HDrv
5
8
Fb
VC
6
7
Vsns
Exposed Pad
12-Lead MLPD, 3x4mm
ΘJA = 30o C/W *
ΘJC = 2o C/W
*Exposed pad on underside is connected to a copper
pad through vias for 4-layer PCB board design
11/26/2007
2
IR3629/IR3629A MPbF
Block Diagram
Fig. 2: Simplified block diagram of the IR3629/IR3629A
11/26/2007
3
IR3629/IR3629A MPbF
Pin Description
Pin Name
1
PGood
2
Vcc
3
LDrv
4
PGnd
5
HDrv
6
Vc
7
Vsns
8
Fb
9
Comp
10
Gnd
11
SS/SD
12
OCSet
11/26/2007
Description
Power Good status pin. Output is open collector. Connect a pull up
resistor from this pin to Vcc.
This pin provides biasing voltage for the internal blocks of the IC. It also
biases the low side driver. A minimum of 0.1uF, high frequency capacitor
must be connected from this pin to power ground.
Output driver for the low side MOSFET
Power Ground. This pin serves as a separate ground for the MOSFET
drivers and should be connected to the system’s power ground plane.
Output driver for the high side MOSFET
This pin powers the high side driver and must be connected to a voltage
higher than bus voltage. A minimum of 0.1uF, high frequency capacitor
must be connected from this pin to power ground.
PGood sense pin
Inverting input to the error amplifier. This pin is connected directly to the
output of the regulator via resistor divider to set the output voltage and
provide feedback to the error amplifier.
Output of the error amplifier.
Signal ground for internal reference and control circuitry.
Soft start / shutdown. This pin provides user programmable soft-start
function. Connect an external capacitor from this pin to ground to set the
start up time of the output voltage. The converter can be shutdown by
pulling this pin below 0.3V.
Current limit set point. A resistor from this pin to drain of the low side
MOSFET will set the current limit threshold.
4
IR3629/IR3629A MPbF
Recommended Operating Conditions
Symbol
Definition
Min
Max
Units
Vcc
Vc
Tj (Note1)
Supply Voltage
Supply Voltage
Junction Temperature
4.5
Converter voltage + 5V
-40
14
28
125
V
V
o
C
Note1:
The junction temperature for 5V application is 0oC-125oC
Electrical Specifications
Unless otherwise specified, these specification apply over Vcc=Vc=12V, 0oC<Tj< 105oC
Typical value are specified at Ta=25oC
Parameter
SYM
Test Condition
Min
TYP
MAX
Units
Accuracy
Feedback Voltage
VFB
0.6
o
Accuracy
o
0 C<Tj<125 C
o
o
-40 C<Tj<105 C, Note2
-1.5
-2.5
V
+1.5
+1.5
%
Supply Current
VCC Supply Current
ICC(Static)
SS=0V, No Switching
10
13
VCC Supply Current
ICC(Dynamic)
IR3629, CLOAD=1.5nF
15
25
IR3629A, CLOAD=1.5nF
15
19
SS=0V, No Switching
4.5
7
(Static)
(Dynamic)
VC Supply Current
IC(Static)
VC Supply Current
(Dynamic)
IC(Dynamic)
(Static)
IR3629, CLOAD=1.5nF
17
25
IR3629A, CLOAD=1.5nF
10
15
mA
Under Voltage Lockout
VCC-Start-Threshold
VCC-Stop-Threshold
VCC-Hysteresis
VC-Start-Threshold
VC-Stop-Threshold
VC-Hysteresis
VCC_UVLO(R)
VCC_UVLO(F)
VCC_Hys
VC_UVLO(R)
VC_UVLO(F)
VC_Hys
Supply ramping up
Supply ramping down
Supply ramping up and down
Supply ramping up
Supply ramping down
Supply ramping up and down
4.0
3.7
0.15
3.1
2.85
0.15
4.2
3.9
0.25
3.3
3.05
0.2
4.4
4.1
0.3
3.5
3.25
0.25
IR3629A
270
300
330
IR3629
540
600
660
V
Oscillator
Frequency
FS
Ramp Amplitude
Vramp
Note3
Min Duty Cycle
Dmin
Fb=1V
0
IR3629, Note3
80
Min Pulse Width
Dmin(ctrl)
IR3629A , Note3
160
Max Duty Cycle
Dmax
11/26/2007
1.25
IR3629, Fb=0.5V
71
IR3629A, Fb=0.5V
78
kHz
V
%
ns
%
5
IR3629/IR3629A MPbF
Parameter
SYM
Test Condition
Min
TYP
MAX
-0.1
-0.5
20
35
50
Units
Error Amplifier
Input Bias Current
IFB1
SS=3V
Input Bias Current
IFB2
SS=0V
Source/Sink Current
I(source/Sink)
50
70
90
Transconductance
gm
1000
1300
1600
μmho
15
20
28
μA
0.25
V
μA
Soft Start/SD
Soft Start Current
ISS
Shutdown
Threshold
SD
Output
SS=0V
Over Current Protection
OCSET Current
Hiccup Current
Hiccup Duty Cycle
IOCSET
IHiccup
Hiccup(duty)
15
20
3
15
26
0.35
0.38
0.41
V
15
27.5
40
mV
0.25
0.5
V
0.3
1
μA
Note3
IHiccup / ISS , Note3
μA
%
Power Good
Vsns Lower Trip Point
Vsns(trip)
Hysteresis
PGood(Hys)
Pgood Output Low
Voltage
Input Bias Curent
PG(voltage)
Vsns ramping Down
IPgood =4mA
ISns
0
Thermal Shutdown
Thermal
Threshold
Thermal
Hysteresis
Shutdown
TD
Note3
140
Shutdown
TD(Hys)
Note3
20
o
C
Output Drivers
LO, Drive Rise Time
Tr(Lo)
CL=1.5nF, See Fig 3
30
60
HI Drive Rise Time
Tr(Hi)
CL=1.5nF, See Fig 3
30
60
LO Drive Fall Time
Tf(Lo)
CL=1.5nF, See Fig 3
30
60
HI Drive Fall Time
Tf(Hi)
CL=1.5nF, See Fig 3
30
60
Dead Band Time
Tdead
See Fig 3
50
100
10
ns
Note2: Cold temperature performance is guaranteed via correlation using statistical quality control.
Not tested in production.
Note3: Guaranteed by Design but not tested in production.
Tr
Tf
9V
High Side Driver
(HDrv)
2V
Tr
Tf
9V
Low Side Driver
(LDrv)
2V
Deadband
H_to_L
Deadband
L_to_H
Fig. 3: Definition of Rise/Fall time and Deadband Time
11/26/2007
6
IR3629/IR3629A MPbF
TYPICAL OPERATING CHARACTERISTICS
Iss(mA)
601.0
25.0
600.5
24.0
600.0
23.0
599.5
22.0
[uA]
[mV]
Vfb(mV)
599.0
21.0
20.0
598.5
19.0
598.0
18.0
597.5
17.0
597.0
-40
-20
0
20
40
60
80
100
-40
120
-20
0
20
12.0
6.0
11.0
5.5
10.0
5.0
9.0
80
100
120
60
80
100
120
4.5
8.0
4.0
7.0
3.5
3.0
6.0
-40
-20
0
20
40
60
80
100
-40
120
-20
0
20
40
Temp[oC]
Temp[oC]
Iocset(uA)
Transconductance (gm)[mMHO]
1.5
22.0
1.4
21.5
1.4
21.0
1.3
20.5
1.3
[uA]
[mMHO]
60
Ic(Static)(mA)
[mA]
[mA]
Icc(static)(mA)
1.2
20.0
19.5
1.2
1.1
19.0
1.1
18.5
1.0
18.0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
Temp[oC]
40
60
80
100
120
140
80
100
120
140
Temp[oC]
Frequency (kHz)(IR3629)
Frequency(kHz)(IR3629A)
615.0
310.0
610.0
305.0
605.0
300.0
600.0
295.0
595.0
[kHz]
[kHz]
40
Temp[oC]
Temp[oC]
590.0
290.0
285.0
585.0
580.0
280.0
575.0
275.0
570.0
270.0
-40
-20
0
20
40
60
Temp[oC]
11/26/2007
80
100
120
140
-40
-20
0
20
40
60
Temp[oC]
7
IR3629/IR3629A MPbF
Circuit Description
THEORY OF OPEARTION
Introduction
The IR3629/29A is a voltage mode PWM
synchronous controller and operates with a fixed
600kHz (300kHz for IR3629A) switching
frequency, allowing the use of small external
components. The output voltage is set by a
feedback pin (Fb) and the internal reference
voltage (0.6V). These are the two inputs to the
error amplifier. The error signal between these
two inputs is amplified and it is compared to a
fixed frequency linear sawtooth ramp and
generates fixed frequency pulses of variable
duty-cycle (D) which drivers N-channel external
MOSFETs.
The internal oscillator circuit uses an on-chip
capacitor to set the switching frequency.
The IR3629/29A operates with single input
voltage from 4.5V to 12V allowing an extended
operating input voltage range.
The current limit is programmable and uses onresistance of the low-side MOSFET, eliminating
the need for an external current sense resistor.
Under-Voltage Lockout
The under-voltage lockout circuit monitors the
two input supplies (Vcc and Vc) and ensures that
the MOSFET driver outputs remain in the off
state whenever the supply voltage drops below
set thresholds. Lockout occurs if Vc or Vcc fall
below 3.3V and 4.2V respectively. Normal
operation resumes once Vc and Vcc rise above
the set values.
Thermal Shutdown
Temperature sensing is provided inside the
IR3629/29A. The trip threshold is typically set to
145oC. When the trip threshold is exceeded,
thermal shutdown discharges the Soft Start
voltage and turns off both MOSFETs. Thermal
shutdown is not latched and automatic restart is
initiated when the sensed temperature drops
within the operating range. There is a 20oC
hysteresis in the thermal shutdown threshold.
11/26/2007
Power Good
The IR3629/29A provides an open collector
power good signal which reports the status of the
output. The output is sensed through the
dedicated Vsns pin. The power good threshold
can be externally programmed using two external
resistors. The power good comparator is
internally set to 0.38V (typical).
Shutdown
The output can be shutdown by pulling the softstart pin below 0.3V. This can easily be done by
using an external small signal transistor. During
shutdown both MOSFET drivers will be turned
off. Normal operation will resume by cycling the
soft start pin.
Pre-Bias Startup
The IR3629/29A is able to start up into precharged output, which prevents oscillation and
disturbances of the output voltage.
The output starts in asynchronous fashion and
keeps the synchronous MOSFET off until the first
gate signal for control MOSFET is generated.
Figure 4 shows a typical Pre-Bias condition at
startup.
Depending on the system configuration, specific
amount of output capacitors may be required to
prevent discharging the output voltage.
Volt
Vo
Pre-Bias Voltage
(Output Voltage before startup)
Time
Fig. 4: Pre-Bias startup
Minimum Pulse Width
The time required for turning on and off the high
side MOSFET is defined as “Minimum Pulse
Width”. To ensure that a reliable operation is
achieved the following condition needs to be met:
Vout
Ton(min) <
Vin(max) * Fs
8
IR3629/IR3629A MPbF
Soft-Start
The IR3629/29A has a programmable soft-start
to control the output voltage rise and limit the
inrush current during start-up.
To ensure correct start-up, the soft-start
sequence initiates when Vcc and Vc rise above
their threshold and generate the Power On
Ready (POR) signal. The soft-start function
operates by sourcing current to charge an
external capacitor to about 3V.
Initially, the soft-start function clamps the output
of error amplifier by injecting a current (35uA)
into the Fb pin and generates a voltage about
0.84V (35ux24K) across the negative input of
error amplifier (see figure 5).
The magnitude of the injected current is inversely
proportional to the voltage at the soft-start pin. As
the soft-start voltage ramps up, the injected
current decreases linearly and so does the
voltage at the negative input of error amplifier.
When the soft-start capacitor voltage is around
1V, the voltage at the positive input of the error
amplifier is approximately 0.6V.
The output of the error amplifier will start
increasing and generating the first PWM signal.
As the soft-start capacitor voltage continues to
rise up, the current flowing into the Fb pin will
keep decreasing.
The feedback voltage increases linearly as the
soft-start voltage ramps up. When soft-start
voltage is around 2V the output voltage reaches
the steady state and the injected current is zero.
Figure 6 shows the theoretical
waveforms during soft-start.
operating
The output voltage start-up time is the time
period when soft-start capacitor voltage
increases from 1V to 2V.
The start-up time will be dependent on the size of
the external soft-start capacitor and can be
estimated by:
20μA ∗
3V
20uA
SS/SD
35uA
40uA
POR
Comp
0.6V
Fb
Error Amp
24K
24K
Fig. 5: Soft-Start circuit for IR3629/29A
Output of UVLO
POR
3V
≅2V
Soft-Start
Voltage
≅1V
0V
35uA
40uA
Current flowing
into Fb pin
0uA
Voltage at negative input ≅0.96V
of Error Amp
0.84V
0.6V
0.6V
Voltage at Fb pin
0V
Fig. 6: Theoretical operation waveforms
during soft-start
Tstart
= 2V −1V
Css
For a given start-up time, the soft-start capacitor
(nF) can be estimated as:
CSS ≅ 20μA * Tstart (ms)
11/26/2007
--(1)
9
IR3629/IR3629A MPbF
Over-Current Protection
28uA
The over current protection is performed by
sensing current through the RDS(on) of the lowside MOSFET. This method enhances the
converter’s efficiency and reduces cost by
eliminating a current sense resistor. As shown in
figure 7, an external resistor (RSET) is connected
between OCSet pin and the drain of the low-side
MOSFET (Q2) which determines the current limit
set point.
The internal current source develops a voltage
across RSET. When the low-side MOSFET is
turned on, the inductor current flows through the
Q2 and results in a voltage which is given by:
VOCSet = (IOCSet ∗ ROCSet ) − (RDS(on) ∗ IL )
--(2 )
IOCSET
IR3624
IR3629/29A
Q1
L1
OCSet RSET
VOUT
OCP
20uA
SS1 / SD
20
3uA
Fig. 8: 3uA current source for discharging
soft-start capacitor during hiccup
The OCP circuit starts sampling current when the
low gate drive is about 3V. The OCSet pin is
internally clamped during deadtime to prevent
false trigging. Figure 9 shows the OCSet pin
during one switching cycle. As shown, there is
about 150ns delay to mask the deadtime. Since
this node contains switching noises, this delay
also functions as a filter.
Q2
Hiccup
Control
Fig. 7: Connection of over current sensing resistor
Deadtime
The critical inductor current can be calculated by
setting:
VOCSet = (IOCSet ∗ ROCSet ) − (RDS(on) ∗ IL ) = 0
ISET = IL(critical) =
ROCSet ∗ IOCSet
RDS(on)
Blanking time
Clamp voltage
--(3 )
An over-current is detected if the OCSet pin goes
below ground. This trips the OCP comparator
and cycles the soft start function in hiccup mode.
The hiccup is performed by charging and
discharging the soft-start capacitor in a certain
slope rate. As shown in figure 8, a 3uA current
source is used to discharge the soft-start
capacitor.
The OCP comparator resets after every soft start
cycle. The converter stays in this mode until the
overload or short circuit is removed. The
converter will automatically recover.
11/26/2007
IOCSet*ROCSet
Fig. 9: OCset pin during normal condition
Ch1: Inductor point, Ch2:Ldrv, Ch3:OCSet
The value of RSET should be checked in an actual
circuit to ensure that the over-current protection
circuit activates as expected. The IR3629 current
limit is designed primarily as a disaster
preventing, "no blow up" circuit, and does not
operate as a precision current regulator.
10
IR3629/IR3629A MPbF
Soft-Start Programming
Application Information
Design Example:
The following example is a typical application for
IR3629. The application circuit is shown on page
18.
Vin=12V,(13.2V, max )
Vo=1.5V
Io=12 A
ΔVo≤30 mV(output voltage ripple)
Fs=600 kHz
The soft-start timing can be programmed by
selecting the soft-start capacitance value. The
start-up time of the converter can be calculated
by using:
CSS ≅ 20μA * Tstart
--(1)
Where Tstart is the desired start-up time (ms).
For a start-up time of 10ms, the soft-start
capacitor will be 0.2uF. Choose a ceramic
capacitor at 0.22uF.
Vc supply for single input voltage
Output Voltage Programming
Output voltage is programmed by reference
voltage and external voltage divider. The Fb pin
is the inverting input of the error amplifier, which
is internally referenced to 0.6V. The divider is
ratioed to provide 0.6V at the Fb pin when the
output is at its desired value. The output voltage
is defined by using the following equation:
⎛
R ⎞
Vo = Vref ∗ ⎜⎜1 + 8 ⎟⎟
R9 ⎠
⎝
--( 4 )
When an external resistor divider is connected to
the output as shown in figure 10.
VOUT
IR3629
IR3624
R8
Fb
R9
Fig. 10: Typical application of the IR3629 for
programming the output voltage
To drive the high side switch, it is necessary to
supply a gate voltage at least 4V greater than the
bus voltage. This is achieved by using a charge
pump configuration as shown in figure 11. This
method is simple and inexpensive. The operation
of the circuit is as follows: when the lower
MOSFET is turned on, the capacitor (C1) is
pulled down to ground and charges, up to VBUS
value, through the diode (D1). The bus voltage
will be added to this voltage when the upper
MOSFET turns on in the next cycle, and
providing supply voltage (Vc) through diode (D2).
Vc is approximately:
VC ≅ 2 ∗Vbus − (VD1 + VD2 )
--(6 )
A capacitors in the range of 0.1uF is generally
adequate for most applications. Fast recovery
diodes must be used to minimize the amount of
charge fed back from the charge pump capacitor
into VBUS. The diodes need to be able to block
the full power rail voltage, which is seen when
the high-side MOSFET is switched on. For lowvoltage applications, schottky diodes can be
used to minimize forward drop.
VBUS
Equation (4) can be rewritten as:
D1
C3
D2
⎛ V
R9 = R8 ∗ ⎜⎜ ref
⎝ V O−Vref
⎞
⎟⎟
⎠
For the calculated values of R8 and R9 see
feedback compensation section.
VBUS
Vc
--( 5 )
C2
C1
Q1
L
IR3629/29A
IR3624
HDrv
Q2
Fig. 11: Charge pump circuit to generate
Vc voltage
11/26/2007
11
IR3629/IR3629A MPbF
Input Capacitor Selection
The ripple current generated during the on time
of upper the MOSFET should be provided by the
input capacitor. The RMS value of this ripple is
expressed by:
IRMS = Io ∗ D ∗ (1 − D )
--(7 )
V
D= o
Vin
Where:
D is the Duty Cycle
IRMS is the RMS value of the input capacitor
current.
Io is the output current.
For Io=10A and D=0.125, the IRMS=3.3A.
Ceramic capacitors are recommended due to
their peak current capabilities, they also feature
low ESR and ESL at higher frequency which
enables better efficiency.
Use 4x22uF, 16V ceramic capacitors from
Panasonic.
If Δi ≈ 37%(Io ) , then the output inductor will be:
L = 0.6uH
The MPL104-0R6 from Delta provides a
compact, low profile inductor suitable for this
application.
Output Capacitor Selection
The voltage ripple and transient requirements
determine the output capacitors type and values.
The criteria is normally based on the value of the
Effective Series Resistance (ESR). However the
actual capacitance value and the Equivalent
Series Inductance (ESL) are other contributing
components. These components can be
described as:
ΔVo = ΔVo(ESR) + ΔVo(ESL) + ΔVo(C )
ΔVo(ESR) = ΔIL * ESR
- -(9)
⎛Vin ⎞
⎟ * ESL
⎝L⎠
ΔVo(ESL) = ⎜
Inductor Selection
The inductor is selected based on output power,
operating frequency and efficiency requirements.
A low inductor value causes large ripple current,
resulting in the smaller size, faster response to a
load transient but poor efficiency and high output
noise. Generally, the selection of the inductor
value can be reduced to the desired maximum
ripple current in the inductor ( Δi ) . The optimum
point is usually found between 20% and 50%
ripple of the output current.
For the buck converter, the inductor value for the
desired operating ripple current can be
determined using the following relation:
Vin − Vo = L ∗
Δi
1
; Δt = D ∗
Fs
Δt
Where:L = (Vin − Vo ) ∗
Vo
Vin ∗ Δi * Fs
Vin = Maximum input voltage
Vo = Output Voltage
Δi = Inductor ripple current
F s= Switching frequency
Δt = Turn on time
D = Duty cycle
11/26/2007
--(8 )
ΔVo(C ) =
ΔIL
8 * Co * Fs
ΔVo = Output voltage ripple
ΔIL = Inductor ripple current
Since the output capacitor has a major role in the
overall performance of the converter and
determines the result of transient response,
selection of the capacitor is critical. The IR3629
can perform well with all types of capacitor.
As a rule, the capacitor must have low enough
ESR to meet output ripple and load transient
requirements.
The goal for this design is to meet the voltage
ripple requirement in the smallest possible
capacitor size. Therefore a ceramic capacitor is
selected due to low ESR and small size. Five of
the Panasonic ECJ2FB0J226M (22uF, 6.3V, X5R
and EIA 0805 case size) is a good choice.
In the case of tantalum or low ESR electrolytic
capacitors, the ESR dominates the output
voltage ripple, equation (9) can be used to
calculate the required ESR for the specific
voltage ripple.
12
IR3629/IR3629A MPbF
Power MOSFET Selection
The IR3629 uses two N-Channel MOSFETs per
channel. The selection criteria to meet power
transfer requirements are based on maximum
drain-source voltage (VDSS), gate-source drive
voltage (Vgs), maximum output current, Onresistance RDS(on), and thermal management.
The MOSFET must have a maximum operating
voltage (VDSS) exceeding the maximum input
voltage (Vin).
The gate drive requirement is almost the same
for both MOSFETs. A logic-level transistor can
be used and caution should be taken with
devices at very low gate threshold voltage (Vgs)
to
prevent
undesired
turn-on
of
the
complementary MOSFET, which results in a
shoot-through current.
The total power dissipation for MOSFETs
includes conduction and switching losses. For
the Buck converter the average inductor current
is equal to the DC load current. The conduction
loss is defined as:
switching losses in a synchronous Buck
converter. The synchronous MOSFET turns on
under zero voltage conditions, therefore, the turn
on losses for synchronous MOSFET can be
neglected. With a linear approximation, the total
switching loss can be expressed as:
Psw =
Vds(off ) tr + tf
*
* Iload - - - (10)
2
T
Where:
V ds(off) = Drain to source voltage at the off time
tr = Rise time
tf = Fall time
T = Switching period
Iload = Load current
The switching time waveforms is shown in
figure12.
VDS
90%
2
Pcond = (upper switch)= Iload
∗ Rds(on) ∗ D ∗ ϑ
2
Pcond = (lower switch)= Iload
∗ Rds(on) ∗ (1 − D) ∗ϑ
ϑ = Rds(on) temperature dependency
The RDS(on) temperature dependency should be
considered for the worst case operation. This is
typically given in the MOSFET datasheet. Ensure
that the conduction losses and switching losses
do not exceed the package ratings or violate the
overall thermal budget.
For this design, the IRF7823 is selected for
control FET and IRF7832Z is selected for the
synchronous FET. These devices provide low on
resistance in a cost effective SO8 package.
The MOSFETs have the following data:
ControlFET(IRF7823):
Vds = 30V,Qg = 14nC
SyncFET(IRF7832Z):
Vds = 30V,Qg = 45nC
Rds(on) = 8.7mΩ @Vgs = 10V
Rds(on) = 3.8mΩ @Vgs = 10V
The conduction losses will be: Pcon=0.44W. The
switching loss is more difficult to calculate, even
though the switching transition is well
understood. The reason is the effect of the
parasitic components and switching times during
the switching procedures such as turn-on / turnoff delays and rise and fall times. The control
MOSFET contributes to the majority of the
11/26/2007
10%
VGS
td(ON)
tr
td(OFF)
tf
Fig. 12: switching time waveforms
From IRF7832Z data sheet:
tr = 13ns
tf = 14ns
These values are taken under a certain test
condition. For more details please refer to the
IRF7832Z data sheet.
By using equation (10), we can calculate the
switching losses. Psw=0.74W
The reverse recovery loss is also another
contributing factor in control FET switching
losses. This is equivalent to extra current
required to remove the minority charges from the
synchronous FET. The reverse recovery loss can
be expressed as:
PQrr = Qrr*trr*Fs
Qrr : Reverse Recovery Charge
trr : Reverse Recovery Time
Fs: Switching Frequency
13
IR3629/IR3629A MPbF
Feedback Compensation
The IR3629 is a voltage mode controller. The
control loop is a single voltage feedback path
including error amplifier and error comparator. To
achieve fast transient response and accurate
output regulation, a compensation circuit is
necessary. The goal of the compensation
network is to provide a closed-loop transfer
function with the highest 0dB crossing frequency
and adequate phase margin (greater than 45o).
The output LC filter introduces a double pole, –
40dB/decade gain slope above its corner
resonant frequency, and a total phase lag of 180o
(see figure 13). The resonant frequency of the LC
filter is expressed as follows:
FLC =
1
- - - (11)
2 ∗ π Lo ∗ Co
Phase
0
0dB
-180
E/A
R9
Comp
Ve
C4
VREF
R3
CPOLE
Gain(dB)
H(s) dB
Frequency
Fig. 14: TypeII compensation network
and its asymptotic gain plot
The transfer function (Ve/Vo) is given by:
⎛
R9 ⎞ 1 + sR3C4
⎟*
H(s) = ⎜⎜ gm *
- - - (13)
R9 + R8 ⎟⎠
sC4
⎝
[H(s)] = ⎛⎜⎜ g
FLC
⎝
Frequency
Fig. 13: Gain and Phase of LC filter
The IR3629/29A’s error amplifier is a differentialinput transconductance amplifier. The output is
available for DC gain control or AC phase
compensation.
The error amplifier can be compensated either in
type II or type III compensation. When it is used
in type II compensation the transconductance
properties of the error amplifier become evident
and can be used to cancel one of the output filter
poles. This will be accomplished with a series RC
circuit from Comp pin to ground as shown in
figure 14.
This method requires the output capacitor should
have enough ESR to satisfy stability
requirements. In general the output capacitor’s
ESR generates a zero typically at 5kHz to 50kHz
which is essential for an acceptable phase
margin.
11/26/2007
Fb
The (s) indicates that the transfer function varies
as a function of frequency. This configuration
introduces a gain and zero, expressed by:
-40dB/decade
FLC Frequency
R8
FZ
Figure 13 shows gain and phase of the LC filter.
Since we already have 180o phase shift from the
output filter a lone , the system risks being
unstable.
Gain
The ESR zero of the output capacitor expressed
as follows:
1
FESR =
- - - (12)
2 ∗ π * ESR * Co
VOUT
Fz =
m
*
R9 ⎞
⎟ * R3 - - - (14)
R9 + R8 ⎟⎠
1
2π * R3 * C4
- - - (15)
The gain is determined by the voltage divider and
error amplifier’s transconductance gain.
First select the desired zero-crossover frequency
(Fo):
Fo > FESR and Fo ≤ (1/5 ~ 1/10) * Fs
Use the following equation to calculate R3:
R3 =
Vosc * Fo * FESR * (R8 + R9 ) * 1.28
2
Vin * FLC
* R9 * gm
- - - (15A)
Where:
Vin = Maximum Input Voltage
Vosc = Oscillator Ramp Voltage
Fo = Crossover Frequency
FESR = Zero Frequency of the Output Capacitor
FLC = Resonant Frequency of the Output Filter
R8 and R9 = Feedback Resistor Dividers
gm = Error Amplifier Transconductance
1.28 = Empirical number to compensate thermal,
process variations and components tolerances
14
IR3629/IR3629A MPbF
To cancel one of the LC filter poles, place the
zero before the LC filter resonant frequency pole:
VOUT
ZIN
Fz = 75%FLC
C7
1
Fz = 0.75 *
2π Lo * Co
- - - (16)
Using equations (15) and (16) to calculate C9.
One more capacitor is sometimes added in
parallel with C4 and R3. This introduces one
more pole which is mainly used to suppress the
switching noise.
The additional pole is given by:
1
FP =
C *C
2π * R3 * 4 POLE
C4 + CPOLE
1
1
π * R3 * Fs −
C4
≅
R3
R10
1
π * R 3 * Fs
For a general solution for unconditional stability
for any type of output capacitors, in a wide range
of ESR values we should implement local
feedback with a compensation network (type III).
The typically used compensation network for
voltage-mode controller is shown in figure 15.
In such configuration, the transfer function is
given by:
C4
R8
Zf
Fb
R9
E/A
Comp
H(s) dB
FZ2
FP2
FP3
As known, the transconductance amplifier has a
high impedance (current source) output,
therefore, consideration should be taken when
loading the error amplifier output. It may exceed
its source/sink output current capability, so that
the amplifier will not be able to swing its output
voltage over the necessary range.
The compensation network has three poles and
two zeros and they are expressed as follows:
FP1 = 0
FP 2 =
1
2π * R10 * C7
FP 3 =
The error amplifier gain is independent of the
transconductance under the following condition:
Fz1 =
1
2π * R3 * C4
Fz 2 =
1
1
≅
2π * C7 * (R8 + R10 ) 2π * C7 * R8
- - - (17)
Frequency
Fig.15: Compensation network with local
feedback and its asymptotic gain plot
Ve 1 − g m Zf
=
Vo 1 + g m ZIN
gm * Z f >> 1 and gm * Z in >> 1
Ve
VREF
Gain(dB)
FZ1
The pole sets to one half of the switching
frequency which results in the capacitor CPOLE:
CPOLE =
C3
1
1
≅
⎛ C * C3 ⎞ 2π * R3 * C3
⎟⎟
2π * R3 ⎜⎜ 4
⎝ C4 + C3 ⎠
Cross over frequency is expressed as:
By replacing Zin and Zf according to figure 15, the
transfer function can be expressed as:
H (s ) =
Fo = R3 * C7 *
Vin
1
*
Vosc 2π * Lo * Co
(1 + sR3C4 ) * [1 + sC7 (R8 + R10 )]
1
*
sR8 (C4 + C3 ) ⎡
⎛ C4 * C3 ⎞⎤
⎟⎟⎥ * (1 + sR10C7 )
⎢1 + sR3 ⎜⎜
⎝ C4 + C3 ⎠⎦
⎣
11/26/2007
15
IR3629/IR3629A MPbF
Based on the frequency of the zero generated by
the output capacitor and its ESR versus
crossover frequency, the compensation type can
be different. The table below shows the
compensation types and location of the
crossover frequency.
Compensator
type
FESR vs. Fo
Output
capacitor
TypII(PI)
FLC<FESR<Fo<Fs/2
Electrolytic
, Tantalum
TypeIII(PID)
Method A
FLC<Fo<FESR<Fs/2
Tantalum,
ceramic
TypeIII(PID)
Method B
FLC<Fo<Fs/2<FESR
Ceramic
The following design rules will give a crossover
frequency approximately one-tenth of the
switching frequency. The higher the band width,
the potentially faster the load transient response.
The DC gain will be large enough to provide high
DC-regulation accuracy (typically -5dB to -12dB).
The phase margin should be greater than 45o for
overall stability.
Desired Phase Margin:
Θmax =
π
3
1 SinΘ
FZ 2 = Fo *
1 + SinΘ
FZ 2 = 16kHz
Table1- The compensation type and location
of FESR versus Fo
1 + SinΘ
1 SinΘ
FP 2 = 224kHz
The details of these compensation types are
discussed in application note AN-1043 which can
be downloaded from IR’s website at www.irf.com.
Select : FZ1 = 0.5 * FZ 2 and FP3 = 0.5 * Fs
For this design we have:
R3 ≥
Vin=12V
Vo=0.9V
Vosc=1.25V
Vref=0.6V
gm=1000umoh
Lo=0.56uH
Co=5x22uF, ESR=2mOhm
Note: Use 15uF instead of 22uF for calculation,
this is due to derating of ceramic capacitor
Fs=600kHz
These result to:
FLC=24.6kHz
FESR=1MHz
Fs/2=300kHz
Select crossover frequency:
FP 2 = Fo *
2
; R ≥ 2KΩ; Select : R3 = 10KΩ
gm 3
Calculate C4 , C3 and C7 :
C4 =
1
; C = 1.98nF, Select : C4 = 2.2nF
2π * FZ1 * R 3 4
C3 =
1
; C = 65.8 pF, Select : C3 = 12pF
2π * FP 3 * R3 3
C7 =
2π * Fo * Lo * Co * Vosc * 1.28
; C7 = 0.22nF,
R3 * Vin
Select : C7 = 0.22nF
Calculate R10 , R8 and R9 :
Fo < FESR and Fo ≤ (1/5 ~ 1/10) * Fs
R10 =
Fo=60kHz
Since: FLC<Fo<Fs/2<FESR, typeIII method B is
selected to place the pole and zeros.
11/26/2007
1
; R = 3.23KΩ, Select : R10 = 3.24KΩ
2π * C7 * FP 2 10
R8 =
1
2π * C7 * FZ 2
R9 =
Vref
* R8 ; R9 = 27.47KΩ, Select : R9 = 27.4KΩ
Vo Vref
R10 ; R8 = 41.76KΩ, Select : R8 = 42.20KΩ
16
IR3629/IR3629A MPbF
Programming the Current-Limit
The Current-Limit threshold can be set by
connecting a resistor (RSET) from the drain of the
low-side MOSFET to the OCSet pin. The
resistor can be calculated by using equation (3).
The RDS(on) has a positive temperature
coefficient and it should be considered for the
worst case operation. This resistor must be
placed close to the IC, place a small ceramic
capacitor from this pin to ground for noise
rejection purposes.
ISET = IL( critical) =
ROCSet ∗ IOCSet
RDS( on )
--(3 )
RDS( on ) = 3.8 mΩ *1.5 = 5.7 mΩ
ISET
Io( LIM ) = 12 A *1.5 = 18 A
(50% over nominal output current)
ROCSet = 5.13KΩ Select
R7 = 5.23KΩ
Setting the Power Good Threshold
Power Good threshold can be programmed by
using two external resistors (R1, R2 in figure 16).
The following formulas can be used to set the
threshold:
R2 =
0.38V
*R1
0.9*Vout − 0.38V
--(18 )
Where;
0.38V is reference of the internal comparator
0.9*Vout is selectable threshold for power good,
for this design it is 1.35V.
Layout Consideration
The layout is very important when designing high
frequency switching converters. Poor layout will
affect noise pickup and can cause a good design
to perform with less than expected results.
Start to place the power components, making all
the connection in the top layer with wide, copper
filled areas. The inductor, output capacitors and
the MOSFETS should be as close to each other
as possible. This helps to reduce the EMI
radiated by the power traces due to the high
switching currents through them. Place input
capacitor very close to the drain of the high-side
MOSFET, to reduce the ESR replace the single
input capacitor with two parallel units.
The feedback part of the system should be kept
away from the inductor and other noise sources.
The critical bypass components such as
capacitors for Vcc and Vc should be close to the
respective pins. It is important to place the
feedback components including feedback
resistors and compensation components close to
Fb and Comp pins.
In a multilayer PCB use one layer as a power
ground plane and have a control circuit ground
(analog ground), to which all signals are
referenced. The goal is to localize the high
current path to a separate loop that does not
interfere with the more sensitive analog control
function. These two grounds must be connected
together on the PC board layout at a single point.
The MLPD is a thermally enhanced package.
Based
on
thermal
performance
it
is
recommended to use 4-layers PCB. To
effectively remove heat from the device the
exposed pad should be connected to ground
plane using vias.
Select R1=10KOhm
Using (18): R2=3.91KOhm
Select R2=3.92K
Use a pull up resistor (4.99K) from PGood pin to
Vcc.
11/26/2007
17
IR3629/IR3629A MPbF
Fig.16: Application circuit for 12V to 1.5V
11/26/2007
18
IR3629/IR3629A MPbF
PCB Metal and Components Placement
ƒ The lead land width should be equal to the nominal part lead width. The minimum lead to lead
spacing should be ≥ 0.2mm to minimize shorting.
ƒ The lead land length should be equal to maximum part lead length + 0.3 mm outboard extension +
0.05mm inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the
inboard extension will accommodate any part misalignment and ensure a fillet.
ƒ The center pad land length and width should be equal to maximum part pad length and width.
However, the minimum metal to metal spacing should be ≥ 0.17mm for 2 oz. Copper (≥ 0.1mm for 1 oz.
Copper and ≥ 0.23mm for 3 oz. Copper).
ƒ Two 0.30mm diameter via should be placed in the center of the pad land and connected to ground to
minimize the noise effect on the IC.
11/26/2007
19
IR3629/IR3629A MPbF
Solder Resist
ƒ The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The
solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all
Non Solder Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always ensure NSMD pads.
ƒ The minimum solder resist width is 0.13mm.
At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide
a fillet so a solder resist width of ≥ 0.17mm remains.
ƒ The land pad should be Non Solder Mask Defined (NSMD), with a minimum pullback of the solder
resist off the copper of 0.06mm to accommodate solder resist mis-alignment.
ƒEnsure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high
aspect ratio of the solder resist strip separating the lead lands from the pad land.
ƒEach via in the land pad should be tented or plugged from bottom boardside with solder resist.
11/26/2007
20
IR3629/IR3629A MPbF
Stencil Design
ƒ The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands.
Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm
pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower;
openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release.
ƒ The stencil lead land apertures should therefore be shortened in length by 80% and centered on the
lead land.
ƒ The land pad aperture should deposit approximately 50% area of solder on the center pad. If too
much solder is deposited on the center pad the part will float and the lead lands will be open.
ƒ The maximum length and width of the land pad stencil aperture should be equal to the solder resist
opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the
lead lands when the part is pushed into the solder paste.
11/26/2007
21
IR3629/IR3629A MPbF
(IR3629/IR3629A M) MLPD Package
3x4-12Lead
D
E/2
E
S
Y
M
B
O
L
A
A3
SEATING PLANE
A1
D2
E2
Terminal 1
Identifier
A
A1
A3
b
D2
D
E
E2
L
e
N
ND
VGED-4
MILLIMETERS
MIN NOM
MAX
0.80
0.90
1.00
0.00
0.02
0.05
0.20 REF
0.18
0.25
0.30
INCHES
NOM
MAX
.035
.039
.0008
.0019
.008 REF
.0118
.0071 .0096
3.0
.118
3.70
_
4.00 BSC
3.00 BSC
1.40
_
1.80
0.30
0.40
0.50
0.50 PITCH
12
6
MIN
.032
.000
_
.145
.157 BSC
.118 BSC
.070
.055
_
.012
.019
.016
.020 PITCH
10
6
Leads on 2 sides
e
b
L
(ND-1) x e
TAPE & REEL ORIENTATION
Figure A
11/26/2007
22
IR3629/IR3629A MPbF
(IR3629M) MLPD Package
3x4-12Lead
D
E/2
E
S
Y
M
B
O
L
A
A3
A
A1
A3
b
SEATING PLANE
D2
D
E
E2
L
e
N
ND
A1
D2
E2
Terminal 1
Identifier
VEED-5
MILLIMETERS
MIN NOM
MAX
0.80
0.90
1.00
0.00
0.02
0.05
0.20 REF
0.18
0.25
0.30
INCHES
NOM
MAX
.035
.039
.0008
.0019
.008 REF
.0118
.0071 .0098
2.20
.087
2.70
_
3.00 BSC
3.00 BSC
1.40
_
1.75
0.30
0.40
0.50
0.50 PITCH
10
5
MIN
.032
.000
_
.106
.118 BSC
.118 BSC
.068
.055
_
.012
.019
.016
.020 PITCH
10
5
Leads on 2 sides
e
b
L
(ND-1) x e
TAPE & REEL ORIENTATION
1
1
1
Figure A
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
This product has been designed and qualified for the Industrial market.
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 11/2007
11/26/2007
23