TI MSP430F5513IRGC Mixed signal microcontroller Datasheet

MSP430F551x
MSP430F552x
www.ti.com
SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
MIXED SIGNAL MICROCONTROLLER
FEATURES
1
•
•
•
•
•
•
Low Supply-Voltage Range: 1.8 V to 3.6 V
Ultralow Power Consumption
– Active Mode (AM):
All System Clocks Active
290 µA/MHz at 8 MHz, 3.0 V, Flash Program
Execution (Typical)
150 µA/MHz at 8 MHz, 3.0 V, RAM Program
Execution (Typical)
– Standby Mode (LPM3):
Real Time Clock With Crystal , Watchdog,
and Supply Supervisor Operational, Full
RAM Retention, Fast Wake-Up:
1.9 µA at 2.2 V, 2.1 µA at 3.0 V (Typical)
Low-Power Oscillator (VLO),
General-Purpose Counter, Watchdog, and
Supply Supervisor Operational, Full RAM
Retention, Fast Wake-Up:
1.4 µA at 3.0 V (Typical)
– Off Mode (LPM4):
Full RAM Retention, Supply Supervisor
Operational, Fast Wake-Up:
1.1 µA at 3.0 V (Typical)
– Shutdown Mode (LPM4.5):
0.18 µA at 3.0 V (Typical)
Wake-Up From Standby Mode in Less Than
5 µs
16-Bit RISC Architecture, Extended Memory,
up to 25-MHz System Clock
Flexible Power Management System
– Fully Integrated LDO With Programmable
Regulated Core Supply Voltage
– Supply Voltage Supervision, Monitoring,
and Brownout
Unified Clock System
– FLL Control Loop for Frequency
Stabilization
– Low Power/Low Frequency Internal Clock
Source (VLO)
– Low Frequency Trimmed Internal Reference
Source (REFO)
– 32-kHz Watch Crystals (XT1)
– High-Frequency Crystals up to 32 MHz
(XT2)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16-Bit Timer TA0, Timer_A With Five
Capture/Compare Registers
16-Bit Timer TA1, Timer_A With Three
Capture/Compare Registers
16-Bit Timer TA2, Timer_A With Three
Capture/Compare Registers
16-Bit Timer TB0, Timer_B With Seven
Capture/Compare Shadow Registers
Two Universal Serial Communication
Interfaces
– USCI_A0 and USCI_A1 Each Supporting
– Enhanced UART supporting
Auto-Baudrate Detection
– IrDA Encoder and Decoder
– Synchronous SPI
– USCI_B0 and USCI_B1 Each Supporting
– I2CTM
– Synchronous SPI
Full-Speed Universal Serial Bus (USB)
– Integrated USB-PHY
– Integrated 3.3-V/1.8-V USB Power System
– Integrated USB-PLL
– Eight Input, Eight Output Endpoints
12-Bit Analog-to-Digital (A/D) Converter
(MSP430F552x Only) With Internal Reference,
Sample-and-Hold, and Autoscan Feature
Comparator
Hardware Multiplier Supporting 32-Bit
Operations
Serial Onboard Programming, No External
Programming Voltage Needed
Three Channel Internal DMA
Basic Timer With Real-Time Clock Feature
Family Members are Summarized in Table 1
For Complete Module Descriptions, See the
MSP430x5xx Family User's Guide (SLAU208)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2010, Texas Instruments Incorporated
MSP430F551x
MSP430F552x
SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
www.ti.com
DESCRIPTION
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with extensive
low-power modes, is optimized to achieve extended battery life in portable measurement applications. The
device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to
maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to
active mode in less than 5 µs.
The MSP430F5529, MSP430F5527, MSP430F5525, and MSP430F5521 are microcontroller configurations with
integrated USB and PHY supporting USB 2.0, four 16-bit timers, a high-performance 12-bit analog-to-digital
converter (ADC), two universal serial communication interfaces (USCI), hardware multiplier, DMA, real-time clock
module with alarm capabilities, and 63 I/O pins. The MSP430F5528, MSP430F5526, MSP430F5524, and
MSP430F5522 include all of these peripherals but have 47 I/O pins.
The MSP430F5519, MSP430F5517, and MSP430F5515 are microcontroller configurations with integrated USB
and PHY supporting USB 2.0, four 16-bit timers, two universal serial communication interfaces (USCI), hardware
multiplier, DMA, real time clock module with alarm capabilities, and 63 I/O pins. The MSP430F5514 and
MSP430FF5513 include all of these peripherals but have 47 I/O pins.
Typical applications include analog and digital sensor systems, data loggers, etc. that require connectivity to
various USB hosts.
Family members available are summarized in Table 1.
Table 1. Family Members
USCI
(1)
(2)
(3)
2
Device
Flash
(KB)
SRAM
(KB) (1)
Timer_A (2)
Timer_B (3)
Channel A:
UART/IrDA/
SPI
Channel B:
SPI/I2C
ADC12_A
(Ch)
Comp_B
(Ch)
I/O
Package
Type
MSP430F5529
128
8+2
5, 3, 3
7
2
2
14 ext / 2 int
12
63
80 PN
64 RGC,
80 ZQE
MSP430F5528
128
8+2
5, 3, 3
7
2
2
10 ext / 2 int
8
47
MSP430F5527
96
6+2
5, 3, 3
7
2
2
14 ext / 2 int
12
63
80 PN
64 RGC,
80 ZQE
MSP430F5526
96
6+2
5, 3, 3
7
2
2
10 ext / 2 int
8
47
MSP430F5525
64
4+2
5, 3, 3
7
2
2
14 ext / 2 int
12
63
80 PN
MSP430F5524
64
4+2
5, 3, 3
7
2
2
10 ext / 2 int
8
47
64 RGC,
80 ZQE
MSP430F5522
32
8+2
5, 3, 3
7
2
2
10 ext / 2 int
8
47
64 RGC,
80 ZQE
MSP430F5521
32
6+2
5, 3, 3
7
2
2
14 ext/ 2 int
12
63
80 PN
MSP430F5519
128
8+2
5, 3, 3
7
2
2
-
12
63
80 PN
MSP430F5517
96
6+2
5, 3, 3
7
2
2
-
12
63
80 PN
MSP430F5515
64
4+2
5, 3, 3
7
2
2
-
12
63
80 PN
MSP430F5514
64
4+2
5, 3, 3
7
2
2
-
8
47
64 RGC,
80 ZQE
MSP430F5513
32
4+2
5, 3, 3
7
2
2
-
8
47
64 RGC,
80 ZQE
The additional 2 KB USB SRAM that is listed can be used as general purpose SRAM when USB is not in use.
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
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Copyright © 2009–2010, Texas Instruments Incorporated
MSP430F551x
MSP430F552x
www.ti.com
SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
ORDERING INFORMATION (1)
PACKAGED DEVICES (2)
TA
PLASTIC 80-PIN LQFP (PN)
PLASTIC 64-PIN VQFN (RGC)
PLASTIC 80-BALL BGA (ZQE)
MSP430F5529IPN
MSP430F5528IRGC
MSP430F5528IZQE
MSP430F5527IPN
MSP430F5526IRGC
MSP430F5526IZQE
MSP430F5525IPN
MSP430F5524IRGC
MSP430F5524IZQE
MSP430F5521IPN
MSP430F5522IRGC
MSP430F5522IZQE
MSP430F5519IPN
MSP430F5514IRGC
MSP430F5514IZQE
MSP430F5517IPN
MSP430F5513IRGC
MSP430F5513IZQE
–40°C to 85°C
MSP430F5515IPN
(1)
(2)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Functional Block Diagram – MSP430F5529IPN, MSP430F5527IPN, MSP430F5525IPN,
MSP430F5521IPN
XIN XOUT RST/NMI DVCC DVSS VCORE
AVCC AVSS
P1.x
XT2IN
XT2OUT
Unified
Clock
System
ACLK
SMCLK
128KB
96KB
64KB
32KB
8KB+2KB
6KB+2KB
4KB+2KB
MCLK
Flash
CPUXV2
and
Working
Registers
RAM
Power
Management
LDO
SVM/SVS
Brownout
SYS
Watchdog
Port Map
Control
(P4)
PA
P2.x
P3.x
PB
P4.x
P5.x
PC
P6.x
P7.x
PD
P8.x
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
I/O Ports
P3/P4
2×8 I/Os
I/O Ports
P5/P6
2×8 I/Os
I/O Ports
P7/P8
1×8 I/Os
1×3 I/Os
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
PD
1×11 I/Os
DP,DM,PUR
Full-speed
USB
USB-PHY
USB-LDO
USB-PLL
MAB
DMA
MDB
3 Channel
EEM
(L: 8+2)
JTAG/
SBW
Interface
MPY32
TA0
TA1
TA2
TB0
Timer_A
5 CC
Registers
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
Timer_B
7 CC
Registers
Copyright © 2009–2010, Texas Instruments Incorporated
RTC_A
CRC16
USCI0,1
ADC12_A
USCI_Ax:
UART,
IrDA, SPI
12 Bit
200 KSPS
USCI_Bx:
SPI, I2C
16 Channels
(14 ext/2 int)
Autoscan
REF
COMP_B
12 Channels
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MSP430F551x
MSP430F552x
SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
www.ti.com
Pin Designation – MSP430F5529IPN, MSP430F5527IPN, MSP430F5525IPN, MSP430F5521IPN
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
P6.3/CB3/A3
P6.2/CB2/A2
P6.1/CB1/A1
P6.0/CB0/A0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
P5.3/XT2OUT
P5.2/XT2IN
AVSS2
V18
VUSB
VBUS
PU.1/DM
PUR
PU.0/DP
VSSU
PN PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
MSP430F5529IPN
MSP430F5527IPN
MSP430F5525IPN
MSP430F5521IPN
P7.7/TB0CLK/MCLK
P7.6/TB0.4
P7.5/TB0.3
P7.4/TB0.2
P5.7/TB0.1
P5.6/TB0.0
P4.7/PM_NONE
P4.6/PM_NONE
P4.5/PM_UCA1RXD/PM_UCA1SOMI
P4.4/PM_UCA1TXD/PM_UCA1SIMO
DVCC2
DVSS2
P4.3/PM_UCB1CLK/PM_UCA1STE
P4.2/PM_UCB1SOMI/PM_UCB1SCL
P4.1/PM_UCB1SIMO/PM_UCB1SDA
P4.0/PM_UCB1STE/PM_UCA1CLK
P3.7/TB0OUTH/SVMOUT
P3.6/TB0.6
P3.5/TB0.5
P3.4/UCA0RXD/UCA0SOMI
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/TA1CLK/CBOUT
P1.7/TA1.0
P2.0/TA1.1
P2.1/TA1.2
P2.2/TA2CLK/SMCLK
P2.3/TA2.0
P2.4/TA2.1
P2.5/TA2.2
P2.6/RTCCLK/DMAE0
P2.7/UCB0STE/UCA0CLK
P3.0/UCB0SIMO/UCB0SDA
P3.1/UCB0SOMI/UCB0SCL
P3.2/UCB0CLK/UCA0STE
P3.3/UCA0TXD/UCA0SIMO
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P6.4/CB4/A4
P6.5/CB5/A5
P6.6/CB6/A6
P6.7/CB7/A7
P7.0/CB8/A12
P7.1/CB9/A13
P7.2/CB10/A14
P7.3/CB11/A15
P5.0/A8/VREF+/VeREF+
P5.1/A9/VREF−/VeREF−
AVCC1
P5.4/XIN
P5.5/XOUT
AVSS1
P8.0
P8.1
P8.2
DVCC1
DVSS1
VCORE
4
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Copyright © 2009–2010, Texas Instruments Incorporated
MSP430F551x
MSP430F552x
www.ti.com
SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
Functional Block Diagram – MSP430F5528IRGC, MSP430F5526IRGC, MSP430F5524IRGC,
MSP430F5522IRGC, MSP430F5528IZQE, MSP430F5526IZQE, MSP430F5524IZQE,
MSP430F5522IZQE
XIN XOUT RST/NMI DVCC DVSS VCORE
AVCC AVSS
P1.x
XT2IN
XT2OUT
Unified
Clock
System
ACLK
SMCLK
128KB
96KB
64KB
32KB
8KB+2KB
6KB+2KB
4KB+2KB
MCLK
Flash
CPUXV2
and
Working
Registers
RAM
Power
Management
LDO
SVM/SVS
Brownout
SYS
Watchdog
Port Map
Control
(P4)
PA
P2.x
P3.x
PB
P4.x
P5.x
PC
P6.x
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
I/O Ports
P3/P4
1×5 I/Os
1×8 I/Os
I/O Ports
P5/P6
1×6 I/Os
1×8 I/Os
PA
1×16 I/Os
PB
1×13 I/Os
PC
1×14 I/Os
DP,DM,PUR
Full-speed
USB
USB-PHY
USB-LDO
USB-PLL
MAB
DMA
MDB
3 Channel
EEM
(L: 8+2)
JTAG/
SBW
Interface
MPY32
TA0
TA1
TA2
TB0
Timer_A
5 CC
Registers
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
Timer_B
7 CC
Registers
Copyright © 2009–2010, Texas Instruments Incorporated
RTC_A
CRC16
USCI0,1
ADC12_A
USCI_Ax:
UART,
IrDA, SPI
12 Bit
200 KSPS
USCI_Bx:
SPI, I2C
12 Channels
(10 ext/2 int)
Autoscan
REF
COMP_B
8 Channels
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MSP430F551x
MSP430F552x
SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
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Pin Designation – MSP430F5528IRGC, MSP430F5526IRGC, MSP430F5524IRGC,
MSP430F5522IRGC
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
P5.3/XT2OUT
P5.2/XT2IN
AVSS2
V18
VUSB
VBUS
PU.1/DM
PUR
PU.0/DP
VSSU
RGC PACKAGE
(TOP VIEW)
P6.0/CB0/A0
P6.1/CB1/A1
P6.2/CB2/A2
P6.3/CB3/A3
P6.4/CB4/A4
P6.5/CB5/A5
P6.6/CB6/A6
P6.7/CB7/A7
P5.0/A8/VREF+/VeREF+
P5.1/A9/VREF−/VeREF−
AVCC1
2
47
3
46
4
45
5
44
6
43
7
8
9
10
MSP430F5528IRGC
MSP430F5526IRGC
MSP430F5524IRGC
MSP430F5522IRGC
42
41
40
39
11
38
12
37
13
36
14
35
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P4.7/PM_NONE
P4.6/PM_NONE
P4.5/PM_UCA1RXD/PM_UCA1SOMI
P4.4/PM_UCA1TXD/PM_UCA1SIMO
P4.3/PM_UCB1CLK/PM_UCA1STE
P4.2/PM_UCB1SOMI/PM_UCB1SCL
P4.1/PM_UCB1SIMO/PM_UCB1SDA
P4.0/PM_UCB1STE/PM_UCA1CLK
DVCC2
DVSS2
P3.4/UCA0RXD/UCA0SOMI
P3.3/UCA0TXD/UCA0SIMO
P3.2/UCB0CLK/UCA0STE
P3.1/UCB0SOMI/UCB0SCL
P3.0/UCB0SIMO/UCB0SDA
P2.7/UCB0STE/UCA0CLK
VCORE
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/TA1CLK/CBOUT
P1.7/TA1.0
P2.0/TA1.1
P2.1/TA1.2
P2.2/TA2CLK/SMCLK
P2.3/TA2.0
P2.4/TA2.1
P2.5/TA2.2
P2.6/RTCCLK/DMAE0
P5.4/XIN
P5.5/XOUT
AVSS1
DVCC1
DVSS1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
6
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Copyright © 2009–2010, Texas Instruments Incorporated
MSP430F551x
MSP430F552x
www.ti.com
SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
Functional Block Diagram – MSP430F5519IPN, MSP430F5517IPN, MSP430F5515IPN
XIN XOUT RST/NMI DVCC DVSS VCORE
AVCC AVSS
P1.x
XT2IN
XT2OUT
Unified
Clock
System
ACLK
SMCLK
MCLK
CPUXV2
and
Working
Registers
128KB
96KB
64KB
4KB+2KB
Flash
RAM
Power
Management
LDO
SVM/SVS
Brownout
SYS
Watchdog
Port Map
Control
(P4)
PA
P2.x
P3.x
PB
P4.x
P5.x
PC
P6.x
P7.x
PD
P8.x
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
I/O Ports
P3/P4
2×8 I/Os
I/O Ports
P5/P6
2×8 I/Os
I/O Ports
P7/P8
1×8 I/Os
1×3 I/Os
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
PD
1×11 I/Os
DP,DM,PUR
Full-speed
USB
USB-PHY
USB-LDO
USB-PLL
MAB
DMA
MDB
3 Channel
EEM
(L: 8+2)
USCI0,1
JTAG/
SBW
Interface
MPY32
TA0
TA1
TA2
TB0
Timer_A
5 CC
Registers
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
Timer_B
7 CC
Registers
Copyright © 2009–2010, Texas Instruments Incorporated
RTC_A
CRC16
USCI_Ax:
UART,
IrDA, SPI
COMP_B
12 Channels
USCI_Bx:
SPI, I2C
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MSP430F551x
MSP430F552x
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Pin Designation – MSP430F5519IPN, MSP430F5517IPN, MSP430F5515IPN
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
P6.3/CB3
P6.2/CB2
P6.1/CB1
P6.0/CB0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
P5.3/XT2OUT
P5.2/XT2IN
AVSS2
V18
VUSB
VBUS
PU.1/DM
PUR
PU.0/DP
VSSU
PN PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MSP430F5519IPN
MSP430F5517IPN
MSP430F5515IPN
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P7.7/TB0CLK/MCLK
P7.6/TB0.4
P7.5/TB0.3
P7.4/TB0.2
P5.7/TB0.1
P5.6/TB0.0
P4.7/PM_NONE
P4.6/PM_NONE
P4.5/PM_UCA1RXD/PM_UCA1SOMI
P4.4/PM_UCA1TXD/PM_UCA1SIMO
DVCC2
DVSS2
P4.3/PM_UCB1CLK/PM_UCA1STE
P4.2/PM_UCB1SOMI/PM_UCB1SCL
P4.1/PM_UCB1SIMO/PM_UCB1SDA
P4.0/PM_UCB1STE/PM_UCA1CLK
P3.7/TB0OUTH/SVMOUT
P3.6/TB0.6
P3.5/TB0.5
P3.4/UCA0RXD/UCA0SOMI
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/TA1CLK/CBOUT
P1.7/TA1.0
P2.0/TA1.1
P2.1/TA1.2
P2.2/TA2CLK/SMCLK
P2.3/TA2.0
P2.4/TA2.1
P2.5/TA2.2
P2.6/RTCCLK/DMAE0
P2.7/UCB0STE/UCA0CLK
P3.0/UCB0SIMO/UCB0SDA
P3.1/UCB0SOMI/UCB0SCL
P3.2/UCB0CLK/UCA0STE
P3.3/UCA0TXD/UCA0SIMO
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P6.4/CB4
P6.5/CB5
P6.6/CB6
P6.7/CB7
P7.0/CB8
P7.1/CB9
P7.2/CB10
P7.3/CB11
P5.0
P5.1
AVCC1
P5.4/XIN
P5.5/XOUT
AVSS1
P8.0
P8.1
P8.2
DVCC1
DVSS1
VCORE
8
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Functional Block Diagram – MSP430F5514IRGC, MSP430F5513IRGC, MSP430F5514IZQE,
MSP430F5513IZQE
XIN XOUT RST/NMI DVCC DVSS VCORE
AVCC AVSS
P1.x
XT2IN
XT2OUT
Unified
Clock
System
ACLK
SMCLK
MCLK
CPUXV2
and
Working
Registers
64KB
32KB
Flash
4KB+2KB
RAM
Power
Management
LDO
SVM/SVS
Brownout
SYS
Watchdog
Port Map
Control
(P4)
PA
P2.x
P3.x
PB
P4.x
P5.x
PC
P6.x
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
I/O Ports
P3/P4
1×5 I/Os
1×8 I/Os
I/O Ports
P5/P6
1×6 I/Os
1×8 I/Os
PA
1×16 I/Os
PB
1×13 I/Os
PC
1×14 I/Os
DP,DM,PUR
Full-speed
USB
USB-PHY
USB-LDO
USB-PLL
MAB
DMA
MDB
3 Channel
EEM
(L: 8+2)
USCI0,1
JTAG/
SBW
Interface
MPY32
TA0
TA1
TA2
TB0
Timer_A
5 CC
Registers
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
Timer_B
7 CC
Registers
Copyright © 2009–2010, Texas Instruments Incorporated
RTC_A
CRC16
USCI_Ax:
UART,
IrDA, SPI
COMP_B
8 Channels
USCI_Bx:
SPI, I2C
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Pin Designation – MSP430F5514IRGC, MSP430F5513IRGC
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
P5.3/XT2OUT
P5.2/XT2IN
AVSS2
V18
VUSB
VBUS
PU.1/DM
PUR
PU.0/DP
VSSU
RGC PACKAGE
(TOP VIEW)
P6.0/CB0
P6.1/CB1
P6.2/CB2
P6.3/CB3
P6.4/CB4
P6.5/CB5
P6.6/CB6
P6.7/CB7
P5.0
P5.1
AVCC1
2
47
3
46
4
45
5
44
6
43
7
8
9
42
MSP430F5514IRGC
MSP430F5513IRGC
41
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P4.7/PM_NONE
P4.6/PM_NONE
P4.5/PM_UCA1RXD/PM_UCA1SOMI
P4.4/PM_UCA1TXD/PM_UCA1SIMO
P4.3/PM_UCB1CLK/PM_UCA1STE
P4.2/PM_UCB1SOMI/PM_UCB1SCL
P4.1/PM_UCB1SIMO/PM_UCB1SDA
P4.0/PM_UCB1STE/PM_UCA1CLK
DVCC2
DVSS2
P3.4/UCA0RXD/UCA0SOMI
P3.3/UCA0TXD/UCA0SIMO
P3.2/UCB0CLK/UCA0STE
P3.1/UCB0SOMI/UCB0SCL
P3.0/UCB0SIMO/UCB0SDA
P2.7/UCB0STE/UCA0CLK
VCORE
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/TA1CLK/CBOUT
P1.7/TA1.0
P2.0/TA1.1
P2.1/TA1.2
P2.2/TA2CLK/SMCLK
P2.3/TA2.0
P2.4/TA2.1
P2.5/TA2.2
P2.6/RTCCLK/DMAE0
P5.4/XIN
P5.5/XOUT
AVSS1
DVCC1
DVSS1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
10
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MSP430F552x
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SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
Pin Designation – MSP430F5528IZQE, MSP430F5526IZQE, MSP430F5524IZQE,
MSP430F5522IZQE, MSP430F5514IZQE, MSP430F5513IZQE
ZQE PACKAGE
(TOP VIEW)
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C1
C2
C4
C5
C6
C7
C8
C9
D1
D2
D3
D4
D5
D6
D7
D8
D9
E1
E2
E3
E4
E5
E6
E7
E8
E9
F1
F2
F3
F4
F5
F6
F7
F8
F9
G1
G2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
H6
H7
H8
H9
J1
J2
J3
J4
J5
J6
J7
J8
J9
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Table 2. TERMINAL FUNCTIONS
TERMINAL
NAME
I/O (1)
NO.
PN
DESCRIPTION
RGC ZQE
P6.4/CB4/A4
1
5
C1
I/O
General-purpose digital I/O
Comparator_B input CB4
Analog input A4 – ADC (not available on '551x devices)
P6.5/CB5/A5
2
6
D2
I/O
General-purpose digital I/O
Comparator_B input CB5
Analog input A5 – ADC (not available on '551x devices)
P6.6/CB6/A6
3
7
D1
I/O
General-purpose digital I/O
Comparator_B input CB6
Analog input A6 – ADC (not available on '551x devices)
P6.7/CB7/A7
4
8
D3
I/O
General-purpose digital I/O
Comparator_B input CB7
Analog input A7 – ADC (not available on '551x devices)
I/O
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,
'5513 devices)
Comparator_B input CB8 (not available on '5528, '5526, '5524, '5522, '5514,
'5513 devices)
Analog input A12 – ADC (not available on '551x devices)
I/O
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,
'5513 devices)
Comparator_B input CB9 (not available on '5528, '5526, '5524, '5522, '5514,
'5513 devices)
Analog input A13 – ADC (not available on '551x devices)
I/O
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,
'5513 devices)
Comparator_B input CB10 (not available on '5528, '5526, '5524, '5522, '5514,
'5513 devices)
Analog input A14 – ADC (not available on '551x devices)
I/O
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,
'5513 devices)
Comparator_B input CB11 (not available on '5528, '5526, '5524, '5522, '5514,
'5513 devices)
Analog input A15 – ADC (not available on '551x devices)
I/O
General-purpose digital I/O
Output of reference voltage to the ADC (not available on '551x devices)
Input for an external reference voltage to the ADC (not available on '551x
devices)
Analog input A8 – ADC (not available on '551x devices)
I/O
General-purpose digital I/O
Negative terminal for the ADC's reference voltage for both sources, the
internal reference voltage, or an external applied reference voltage (not
available on '551x devices)
Analog input A9 – ADC (not available on '551x devices)
P7.0/CB8/A12
P7.1/CB9/A13
P7.2/CB10/A14
P7.3/CB11/A15
P5.0/A8/VREF+/VeREF+
5
6
7
8
9
N/A
N/A
N/A
N/A
9
N/A
N/A
N/A
N/A
E1
P5.1/A9/VREF-/VeREF-
10
10
E2
AVCC1
11
11
F2
P5.4/XIN
12
12
F1
I/O
General-purpose digital I/O
Input terminal for crystal oscillator XT1
P5.5/XOUT
13
13
G1
I/O
General-purpose digital I/O
Output terminal of crystal oscillator XT1
AVSS1
14
14
G2
P8.0
15
N/A
N/A
I/O
General-purpose digital I/O
P8.1
16
N/A
N/A
I/O
General-purpose digital I/O
P8.2
17
N/A
N/A
I/O
General-purpose digital I/O
DVCC1
18
15
H1
Digital power supply
DVSS1
19
16
J1
Digital ground supply
(1)
I = input, O = output, N/A = not available
12
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Analog power supply
Analog ground supply
Copyright © 2009–2010, Texas Instruments Incorporated
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MSP430F552x
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SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
Table 2. TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
VCORE
(2)
I/O (1)
NO.
PN
DESCRIPTION
RGC ZQE
Regulated core power supply output (internal usage only, no external current
loading)
20
17
J2
P1.0/TA0CLK/ACLK
21
18
H2
I/O
General-purpose digital I/O with port interrupt
TA0 clock signal TA0CLK input ; ACLK output (divided by 1, 2, 4, or 8)
P1.1/TA0.0
22
19
H3
I/O
General-purpose digital I/O with port interrupt
TA0 CCR0 capture: CCI0A input, compare: Out0 output
BSL transmit output
P1.2/TA0.1
23
20
J3
I/O
General-purpose digital I/O with port interrupt
TA0 CCR1 capture: CCI1A input, compare: Out1 output
BSL receive input
P1.3/TA0.2
24
21
G4
I/O
General-purpose digital I/O with port interrupt
TA0 CCR2 capture: CCI2A input, compare: Out2 output
P1.4/TA0.3
25
22
H4
I/O
General-purpose digital I/O with port interrupt
TA0 CCR3 capture: CCI3A input compare: Out3 output
P1.5/TA0.4
26
23
J4
I/O
General-purpose digital I/O with port interrupt
TA0 CCR4 capture: CCI4A input, compare: Out4 output
P1.6/TA1CLK/CBOUT
27
24
G5
I/O
General-purpose digital I/O with port interrupt
TA1 clock signal TA1CLK input
Comparator_B output
P1.7/TA1.0
28
25
H5
I/O
General-purpose digital I/O with port interrupt
TA1 CCR0 capture: CCI0A input, compare: Out0 output
P2.0/TA1.1
29
26
J5
I/O
General-purpose digital I/O with port interrupt
TA1 CCR1 capture: CCI1A input, compare: Out1 output
P2.1/TA1.2
30
27
G6
I/O
General-purpose digital I/O with port interrupt
TA1 CCR2 capture: CCI2A input, compare: Out2 output
P2.2/TA2CLK/SMCLK
31
28
J6
I/O
General-purpose digital I/O with port interrupt
TA2 clock signal TA2CLK input ; SMCLK output
P2.3/TA2.0
32
29
H6
I/O
General-purpose digital I/O with port interrupt
TA2 CCR0 capture: CCI0A input, compare: Out0 output
P2.4/TA2.1
33
30
J7
I/O
General-purpose digital I/O with port interrupt
TA2 CCR1 capture: CCI1A input, compare: Out1 output
P2.5/TA2.2
34
31
J8
I/O
General-purpose digital I/O with port interrupt
TA2 CCR2 capture: CCI2A input, compare: Out2 output
P2.6/RTCCLK/DMAE0
35
32
J9
I/O
General-purpose digital I/O with port interrupt
RTC clock output for calibration
DMA external trigger input
P2.7/UCB0STE/UCA0CLK
36
33
H7
I/O
General-purpose digital I/O
Slave transmit enable – USCI_B0 SPI mode
Clock signal input – USCI_A0 SPI slave mode
Clock signal output – USCI_A0 SPI master mode
P3.0/UCB0SIMO/UCB0SDA
37
34
H8
I/O
General-purpose digital I/O
Slave in, master out – USCI_B0 SPI mode
I2C data – USCI_B0 I2C mode
P3.1/UCB0SOMI/UCB0SCL
38
35
H9
I/O
General-purpose digital I/O
Slave out, master in – USCI_B0 SPI mode
I2C clock – USCI_B0 I2C mode
P3.2/UCB0CLK/UCA0STE
39
36
G8
I/O
General-purpose digital I/O
Clock signal input – USCI_B0 SPI slave mode
Clock signal output – USCI_B0 SPI master mode
Slave transmit enable – USCI_A0 SPI mode
P3.3/UCA0TXD/UCA0SIMO
40
37
G9
I/O
General-purpose digital I/O
Transmit data – USCI_A0 UART mode
Slave in, master out – USCI_A0 SPI mode
(2)
VCORE is for internal usage only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE.
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Table 2. TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
I/O (1)
NO.
PN
DESCRIPTION
RGC ZQE
P3.4/UCA0RXD/UCA0SOMI
41
38
G7
I/O
General-purpose digital I/O
Receive data – USCI_A0 UART mode
Slave out, master in – USCI_A0 SPI mode
P3.5/TB0.5
42
N/A
N/A
I/O
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,
'5513 devices)
TB0 CCR5 capture: CCI5A input, compare: Out5 output
P3.6/TB0.6
43
N/A
N/A
I/O
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,
'5513 devices)
TB0 CCR6 capture: CCI6A input, compare: Out6 output
I/O
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,
'5513 devices)
Switch all PWM outputs high impedance input – TB0 (not available on '5528,
'5526, '5524, '5522, '5514, '5513 devices)
SVM output (not available on '5528, '5526, '5524, '5522, '5514, '5513 devices)
P3.7/TB0OUTH/SVMOUT
44
N/A
N/A
P4.0/PM_UCB1STE/
PM_UCA1CLK
45
41
E8
I/O
General-purpose digital I/O with reconfigurable port mapping secondary
function
Default mapping: Slave transmit enable – USCI_B1 SPI mode
Default mapping: Clock signal input – USCI_A1 SPI slave mode
Default mapping: Clock signal output – USCI_A1 SPI master mode
P4.1/PM_UCB1SIMO/
PM_UCB1SDA
46
42
E7
I/O
General-purpose digital I/O with reconfigurable port mapping secondary
function
Default mapping: Slave in, master out – USCI_B1 SPI mode
Default mapping: I2C data – USCI_B1 I2C mode
P4.2/PM_UCB1SOMI/
PM_UCB1SCL
47
43
D9
I/O
General-purpose digital I/O with reconfigurable port mapping secondary
function
Default mapping: Slave out, master in – USCI_B1 SPI mode
Default mapping: I2C clock – USCI_B1 I2C mode
I/O
General-purpose digital I/O with reconfigurable port mapping secondary
function
Default mapping: Clock signal input – USCI_B1 SPI slave mode
Default mapping: Clock signal output – USCI_B1 SPI master mode
Default mapping: Slave transmit enable – USCI_A1 SPI mode
P4.3/PM_UCB1CLK/
PM_UCA1STE
48
44
D8
DVSS2
49
39
F9
Digital ground supply
DVCC2
50
40
E9
Digital power supply
P4.4/PM_UCA1TXD/
PM_UCA1SIMO
51
45
D7
I/O
General-purpose digital I/O with reconfigurable port mapping secondary
function
Default mapping: Transmit data – USCI_A1 UART mode
Default mapping: Slave in, master out – USCI_A1 SPI mode
P4.5/PM_UCA1RXD/
PM_UCA1SOMI
52
46
C9
I/O
General-purpose digital I/O with reconfigurable port mapping secondary
function
Default mapping: Receive data – USCI_A1 UART mode
Default mapping: Slave out, master in – USCI_A1 SPI mode
P4.6/PM_NONE
53
47
C8
I/O
General-purpose digital I/O with reconfigurable port mapping secondary
function
Default mapping: no secondary function.
P4.7/PM_NONE
54
48
C7
I/O
General-purpose digital I/O with reconfigurable port mapping secondary
function
Default mapping: no secondary function.
P5.6/TB0.0
55
N/A
N/A
I/O
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,
'5513 devices)
TB0 CCR0 capture: CCI0A input, compare: Out0 output (not available on
'5528, '5526, '5524, '5522, '5514, '5513 devices)
P5.7/TB0.1
56
N/A
N/A
I/O
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,
'5513 devices)
TB0 CCR1 capture: CCI1A input, compare: Out1 output (not available on
'5528, '5526, '5524, '5522, '5514, '5513 devices)
14
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Table 2. TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PN
RGC ZQE
P7.4/TB0.2
57
N/A
N/A
I/O
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,
'5513 devices)
TB0 CCR2 capture: CCI2A input, compare: Out2 output (not available on
'5528, '5526, '5524, '5522, '5514, '5513 devices)
P7.5/TB0.3
58
N/A
N/A
I/O
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,
'5513 devices)
TB0 CCR3 capture: CCI3A input, compare: Out3 output (not available on
'5528, '5526, '5524, '5522, '5514, '5513 devices)
I/O
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,
'5513 devices)
TB0 CCR4 capture: CCI4A input, compare: Out4 output (not available on
'5528, '5526, '5524, '5522, '5514, '5513 devices)
I/O
General-purpose digital I/O (not available on '5528, '5526, '5524, '5522, '5514,
'5513 devices)
TB0 clock signal TBCLK input (not available on '5528, '5526, '5524, '5522,
'5514, '5513 devices)
MCLK output (not available on '5528, '5526, '5524, '5522, '5514, '5513
devices)
P7.6/TB0.4
59
N/A
N/A
P7.7/TB0CLK/MCLK
60
N/A
N/A
VSSU
61
49
B8,
B9
PU.0/DP
62
50
A9
I/O
General-purpose digital I/O - controlled by USB control register
USB data terminal DP
PUR
63
51
B7
I/O
USB pullup resistor pin (open drain)
PU.1/DM
64
52
A8
I/O
General-purpose digital I/O - controlled by USB control register
USB data terminal DM
VBUS
65
53
A7
USB LDO input (connect to USB power source)
VUSB
66
54
A6
USB LDO output
V18
67
55
B6
USB regulated power (internal usage only, no external current loading)
AVSS2
68
56
A5
Analog ground supply
P5.2/XT2IN
69
57
B5
I/O
General-purpose digital I/O
Input terminal for crystal oscillator XT2
P5.3/XT2OUT
70
58
B4
I/O
General-purpose digital I/O
Output terminal of crystal oscillator XT2
TEST/SBWTCK (3)
71
59
A4
I
PJ.0/TDO (4)
72
60
C5
I/O
General-purpose digital I/O
JTAG test data output port
PJ.1/TDI/TCLK (4)
73
61
C4
I/O
General-purpose digital I/O
JTAG test data input or test clock input
PJ.2/TMS (4)
74
62
A3
I/O
General-purpose digital I/O
JTAG test mode select
PJ.3/TCK (4)
75
63
B3
I/O
General-purpose digital I/O
JTAG test clock
RST/NMI/SBWTDIO (3)
76
64
A2
I/O
Reset input active low
Non-maskable interrupt input
Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated.
P6.0/CB0/A0
77
1
A1
I/O
General-purpose digital I/O
Comparator_B input CB0
Analog input A0 – ADC (not available on '551x devices)
P6.1/CB1/A1
78
2
B2
I/O
General-purpose digital I/O
Comparator_B input CB1
Analog input A1 – ADC (not available on '551x devices)
(3)
(4)
USB PHY ground supply
Test mode pin – Selects four wire JTAG operation.
Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated
Please refer to Bootstrap Loader (BSL) and JTAG Operation for usage with BSL and JTAG functions
Please refer to JTAG Operation for usage with JTAG function.
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Table 2. TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
I/O (1)
NO.
PN
DESCRIPTION
RGC ZQE
P6.2/CB2/A2
79
3
B1
I/O
General-purpose digital I/O
Comparator_B input CB2
Analog input A2 – ADC (not available on '551x devices)
P6.3/CB3/A3
80
4
C2
I/O
General-purpose digital I/O
Comparator_B input CB3
Analog input A3 – ADC (not available on '551x devices)
Reserved
N/A
N/A
(5)
16
(5)
C6, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6, F7, F8, G3 are reserved and should be connected to ground.
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SHORT-FORM DESCRIPTION
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
The CPU is integrated with 16 registers that provide
reduced
instruction
execution
time.
The
register-to-register operation execution time is one
cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data.
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Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
Constant Generator
SR/CG1/R2
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
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Operating Modes
The MSP430 has one active mode and six software selectable low-power modes of operation. An interrupt event
can wake up the device from any of the low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following seven operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
• Low-power mode 1 (LPM1)
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and FLL loop control and DCOCLK are disabled
– DCO's dc-generator remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc generator is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc generator is disabled
– Crystal oscillator is stopped
– Complete data retention
• Low-power mode 4.5 (LPM4.5)
– Internal regulator disabled
– No data retention
– Wakeup from RST/NMI, P1, and P2
18
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Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 3. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
System Reset
Power-Up
External Reset
Watchdog Timeout, Password
Violation
Flash Memory Password Violation
INTERRUPT FLAG
WDTIFG, KEYV (SYSRSTIV) (1)
(2)
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
Reset
0FFFEh
63, highest
System NMI
PMM
Vacant Memory Access
JTAG Mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,
JMBOUTIFG (SYSSNIV) (1)
(Non)maskable
0FFFCh
62
User NMI
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG, OFIFG, ACCVIFG, BUSIFG
(SYSUNIV) (1) (2)
(Non)maskable
0FFFAh
61
Maskable
0FFF8h
60
Maskable
0FFF6h
59
TB0
TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,
TB0IFG (TB0IV) (1) (3)
Maskable
0FFF4h
58
Watchdog Timer_A Interval Timer
Mode
WDTIFG
Maskable
0FFF2h
57
Maskable
0FFF0h
56
Maskable
0FFEEh
55
Maskable
0FFECh
54
Comp_B
Comparator B interrupt flags (CBIV) (1)
TB0
USCI_A0 Receive/Transmit
TB0CCR0 CCIFG0
UCA0RXIFG, UCA0TXIFG (UCA0IV) (1)
UCB0RXIFG, UCB0TXIFG (UCAB0IV)
ADC12_A
ADC12IFG0 to ADC12IFG15 (ADC12IV) (1)
(3) (4)
TA0
TA0CCR0 CCIFG0 (3)
Maskable
0FFEAh
53
TA0
TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,
TA0IFG (TA0IV) (1) (3)
Maskable
0FFE8h
52
Maskable
0FFE6h
51
DMA
USB interrupts (USBIV) (1)
(3)
DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)
(1) (3)
Maskable
0FFE4h
50
TA1
TA1CCR0 CCIFG0 (3)
Maskable
0FFE2h
49
TA1
TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG (TA1IV) (1) (3)
Maskable
0FFE0h
48
I/O Port P1
P1IFG.0 to P1IFG.7 (P1IV) (1)
Maskable
0FFDEh
47
USCI_A1 Receive/Transmit
UCA1RXIFG, UCA1TXIFG (UCA1IV) (1)
(3)
Maskable
0FFDCh
46
USCI_B1 Receive/Transmit
UCB1RXIFG, UCB1TXIFG (UCB1IV) (1)
(3)
Maskable
0FFDAh
45
Maskable
0FFD8h
44
Maskable
0FFD6h
43
Maskable
0FFD4h
42
Maskable
0FFD2h
41
0FFD0h
40
TA2
TA2
I/O Port P2
RTC_A
TA2CCR0 CCIFG0
(3)
(3)
TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,
TA2IFG (TA2IV) (1) (3)
P2IFG.0 to P2IFG.7 (P2IV) (1)
(3)
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG (RTCIV) (1) (3)
Reserved
(3)
(4)
(5)
(3)
(1) (3)
USCI_B0 Receive/Transmit
USB_UBM
(1)
(2)
(3)
(3)
Reserved
(5)
⋮
⋮
0FF80h
0, lowest
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
Interrupt flags are located in the module.
Only on devices with ADC, otherwise reserved.
Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, it is recommended to reserve these locations.
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Memory Organization
Table 4. Memory Organization (1)
Memory (flash)
Main: interrupt vector
MSP430F5522
MSP430F5521
MSP430F5513
MSP430F5525
MSP430F5524
MSP430F5515
MSP430F5514
MSP430F5527
MSP430F5526
MSP430F5517
MSP430F5529
MSP430F5528
MSP430F5519
32 KB
00FFFFh–00FF80h
64 KB
00FFFFh–00FF80h
96 KB
00FFFFh–00FF80h
128 KB
00FFFFh–00FF80h
N/A
N/A
N/A
32 KB
0243FFh–01C400h
N/A
N/A
32 KB
01C3FFh–014400h
32 KB
01C3FFh–014400h
Bank 1
15 KB
00FFFFh–00C400h
32 KB
0143FFh–00C400h
32 KB
0143FFh–00C400h
32 KB
0143FFh–00C400h
Bank 0
17 KB
00C3FFh–008000h
32 KB
00C3FFh–004400h
32 KB
00C3FFh–004400h
32 KB
00C3FFh–004400h
Sector 3
2 KB (2)
0043FFh–003C00h
N/A
N/A
2 KB
0043FFh–003C00h
Sector 2
2 KB (3)
003BFFh–003400h
N/A
2 KB
003BFFh–003400h
2 KB
003BFFh–003400h
Sector 1
2 KB
0033FFh–002C00h
2 KB
0033FFh–002C00h
2 KB
0033FFh–002C00h
2 KB
0033FFh–002C00h
Sector 0
2 KB
002BFFh–002400h
2 KB
002BFFh–002400h
2 KB
002BFFh–002400h
2 KB
002BFFh–002400h
Sector 7
2 KB
0023FFh–001C00h
2 KB
0023FFh–001C00h
2 KB
0023FFh–001C00h
2 KB
0023FFh–001C00h
Info A
128 B
0019FFh–001980h
128 B
0019FFh–001980h
128 B
0019FFh–001980h
128 B
0019FFh–001980h
Info B
128 B
00197Fh–001900h
128 B
00197Fh–001900h
128 B
00197Fh–001900h
128 B
00197Fh–001900h
Info C
128 B
0018FFh–001880h
128 B
0018FFh–001880h
128 B
0018FFh–001880h
128 B
0018FFh–001880h
Info D
128 B
00187Fh–001800h
128 B
00187Fh–001800h
128 B
00187Fh–001800h
128 B
00187Fh–001800h
BSL 3
512 B
0017FFh–001600h
512 B
0017FFh–001600h
512 B
0017FFh–001600h
512 B
0017FFh–001600h
BSL 2
512 B
0015FFh–001400h
512 B
0015FFh–001400h
512 B
0015FFh–001400h
512 B
0015FFh–001400h
BSL 1
512 B
0013FFh–001200h
512 B
0013FFh–001200h
512 B
0013FFh–001200h
512 B
0013FFh–001200h
BSL 0
512 B
0011FFh–001000h
512 B
0011FFh–001000h
512 B
0011FFh–001000h
512 B
0011FFh–001000h
4 KB
000FFFh–0h
4 KB
000FFFh–0h
4 KB
000FFFh–0h
4 KB
000FFFh–0h
Total Size
Bank 3
Bank 2
Main: code memory
RAM
USB RAM (4)
Information memory
(flash)
Bootstrap loader (BSL)
memory (flash)
Peripherals
(1)
(2)
(3)
(4)
20
Size
N/A = Not available
'F5522 only
'F5522, 'F5521 only
USB RAM can be used as general purpose RAM when not used for USB operation.
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Bootstrap Loader (BSL)
The BSL enables users to program the flash memory or RAM using various serial interfaces. Access to the
device memory via the BSL is protected by an user-defined password. For complete description of the features of
the BSL and its implementation, see the MSP430 Memory Programming User's Guide, literature number
SLAU265.
USB BSL
All devices come pre-programmed with the USB BSL. Usage of the USB BSL requires external access to the six
pins shown in Table 5. In addition to these pins, the application must support external components necessary for
normal USB operation e.g. proper crystal on XT2IN and XT2OUT, proper decoupling, etc.
Table 5. USB BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
PU.0/DP
USB data terminal DP
PU.1/DM
USB data terminal DM
PUR
USB pullup resistor terminal
VBUS
USB bus power supply
VSSU
USB ground supply
UART BSL
A UART BSL is also available that can be programmed by the user into the BSL memory by replacing the
pre-programmed, factory supplied, USB BSL. Usage of the UART BSL requires external access to the six pins
shown in Table 6.
Table 6. UART BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P1.1
Data transmit
P1.2
Data receive
VCC
Power supply
VSS
Ground supply
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JTAG Operation
JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430
development tools and device programmers. The JTAG pin requirements are shown in Table 7. For further
details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's
Guide, literature number SLAU278.
Table 7. JTAG Pin Requirements and Functions
DEVICE SIGNAL
DIRECTION
FUNCTION
PJ.3/TCK
IN
JTAG clock input
PJ.2/TMS
IN
JTAG state control
PJ.1/TDI/TCLK
IN
JTAG data input/TCLK input
PJ.0/TDO
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
VCC
Power supply
VSS
Ground supply
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface.
Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire
interface pin requirements are shown in Table 8. For further details on interfacing to development tools and
device programmers, see the MSP430 Hardware Tools User's Guide, literature number SLAU278.
Table 8. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
DIRECTION
FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input/output
VCC
Power supply
VSS
Ground supply
Flash Memory
The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the
flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually. Segments A to D are also called information memory.
• Segment A can be locked separately.
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RAM Memory
The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage,
however all data is lost. Features of the RAM memory include:
• RAM memory has n sectors. The size of a sector can be found in the Memory Organization section.
• Each sector 0 to n can be complete disabled, however data retention is lost.
• Each sector 0 to n automatically enters low power retention mode when possible.
• For Devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.
Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x5xx Family User's Guide, literature number
SLAU208.
Digital I/O
There are up to eight 8-bit I/O ports implemented: For 80 pin options, P1, P2, P3, P4, P5, P6, and P7 are
complete. P8 is reduced to 3-bit I/O. For 64 pin options, P3 and P5 are reduced to 5-bit I/O and 6-bit I/O,
respectively. P7 and P8 are completely removed. Port PJ contains four individual I/O ports, common to all
devices.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Pullup or pulldown on all ports is programmable.
• Drive strength on all ports is programmable.
• Edge-selectable interrupt and LPM4.5 wakeup input capability is available for all bits of ports P1 and P2.
• Read/write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise (P1 through P8) or word-wise in pairs (PA through PD).
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Port Mapping Controller
The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P4.
Table 9. Port Mapping, Mnemonics, and Functions
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION
0
PM_NONE
None
DVSS
PM_CBOUT0
-
Comparator_B output
PM_TB0CLK
TB0 clock input
1
PM_ADC12CLK
-
PM_DMAE0
DMAE0 input
PM_SVMOUT
-
PM_TB0OUTH
TB0 high impedance input
TB0OUTH
4
PM_TB0CCR0A
TB0 CCR0 capture input CCI0A
TB0 CCR0 compare output Out0
5
PM_TB0CCR1A
TB0 CCR1 capture input CCI1A
TB0 CCR1 compare output Out1
6
PM_TB0CCR2A
TB0 CCR2 capture input CCI2A
TB0 CCR2 compare output Out2
7
PM_TB0CCR3A
TB0 CCR3 capture input CCI3A
TB0 CCR3 compare output Out3
8
PM_TB0CCR4A
TB0 CCR4 capture input CCI4A
TB0 CCR4 compare output Out4
9
PM_TB0CCR5A
TB0 CCR5 capture input CCI5A
TB0 CCR5 compare output Out5
10
PM_TB0CCR6A
TB0 CCR6 capture input CCI6A
TB0 CCR6 compare output Out6
2
3
11
12
13
14
15
16
SVM output
USCI_A1 UART RXD (Direction controlled by USCI - input)
PM_UCA1SOMI
USCI_A1 SPI slave out master in (direction controlled by USCI)
PM_UCA1TXD
USCI_A1 UART TXD (Direction controlled by USCI - output)
PM_UCA1SIMO
USCI_A1 SPI slave in master out (direction controlled by USCI)
PM_UCA1CLK
USCI_A1 clock input/output (direction controlled by USCI)
PM_UCB1STE
USCI_B1 SPI slave transmit enable (direction controlled by USCI)
PM_UCB1SOMI
USCI_B1 SPI slave out master in (direction controlled by USCI)
PM_UCB1SCL
USCI_B1 I2C clock (open drain and direction controlled by USCI)
PM_UCB1SIMO
USCI_B1 SPI slave in master out (direction controlled by USCI)
PM_UCB1SDA
USCI_B1 I2C data (open drain and direction controlled by USCI)
PM_UCB1CLK
USCI_B1 clock input/output (direction controlled by USCI)
PM_UCA1STE
USCI_A1 SPI slave transmit enable (direction controlled by USCI)
17
PM_CBOUT1
None
Comparator_B output
18
PM_MCLK
None
MCLK
None
DVSS
31 (0FFh)
24
ADC12CLK
PM_UCA1RXD
19 - 30
(1)
OUTPUT PIN FUNCTION
Reserved
(1)
PM_ANALOG
Disables the output driver as well as the input Schmitt-trigger to prevent
parasitic cross currents when applying analog signals.
The value of the PMPAP_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are
ignored resulting in a read out value of 31.
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Table 10. Default Mapping
PIN
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
P4.0/P4MAP0
PM_UCB1STE/PM_UCA1CLK
USCI_B1 SPI slave transmit enable (direction controlled by USCI)
USCI_A1 clock input/output (direction controlled by USCI)
P4.1/P4MAP1
PM_UCB1SIMO/PM_UCB1SDA
USCI_B1 SPI slave in master out (direction controlled by USCI)
USCI_B1 I2C data (open drain and direction controlled by USCI)
P4.2/P4MAP2
PM_UCB1SOMI/PM_UCB1SCL
USCI_B1 SPI slave out master in (direction controlled by USCI)
USCI_B1 I2C clock (open drain and direction controlled by USCI)
P4.3/P4MAP3
PM_UCB1CLK/PM_UCA1STE
USCI_A1 SPI slave transmit enable (direction controlled by USCI)
USCI_B1 clock input/output (direction controlled by USCI)
P4.4/P4MAP4
PM_UCA1TXD/PM_UCA1SIMO
USCI_A1 UART TXD (Direction controlled by USCI - output)
USCI_A1 SPI slave in master out (direction controlled by USCI)
P4.5/P4MAP5
PM_UCA1RXD/PM_UCA1SOMI
USCI_A1 UART RXD (Direction controlled by USCI - input)
USCI_A1 SPI slave out master in (direction controlled by USCI)
P4.6/P4MAP6
PM_NONE
None
DVSS
P4.7/P4MAP7
PM_NONE
None
DVSS
Oscillator and System Clock
The clock system in the MSP430F552x and MSP430F551x family of devices is supported by the Unified Clock
System (UCS) module that includes support for a 32 kHz watch crystal oscillator (XT1 LF mode - XT1 HF mode
not supported), an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency
oscillator (REFO), an integrated internal digitally-controlled oscillator (DCO), and a high-frequency crystal
oscillator XT2. The UCS module is designed to meet the requirements of both low system cost and low-power
consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in conjunction with a
digital modulator, stabilizes the DCO frequency to a programmable multiple of the selected FLL reference
frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 5 µs. The UCS
module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32 kHz watch crystal (XT1), a high-frequency crystal (XT2), the
internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal
digitally-controlled oscillator DCO.
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by
same sources made available to ACLK.
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
Power Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains
programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor
(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is
implemented to provide the proper internal reset signal to the device during power-on and power-off. The
SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply
voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not
automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.
Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs operations with
32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations.
Real-Time Clock (RTC_A)
The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated
real-time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers
that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Calendar
mode integrates an internal calendar which compensates for months with less than 31 days and includes leap
year correction. The RTC_A also supports flexible alarm functions and offset-calibration hardware.
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Watchdog Timer (WDT_A)
The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
System Module (SYS)
The SYS module handles many of the system functions within the device. These include power on reset and
power up clear handling, NMI source selection and management, reset interrupt vector generators, boot strap
loader entry mechanisms, as well as, configuration management (device descriptors). It also includes a data
exchange mechanism via JTAG called a JTAG mailbox that can be used in the application.
Table 11. System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTER
ADDRESS
INTERRUPT EVENT
VALUE
019Eh
No interrupt pending
00h
Brownout (BOR)
02h
RST/NMI (POR)
04h
PMMSWBOR (BOR)
06h
Wakeup from LPMx.5
08h
SYSRSTIV , System Reset
019Ch
SYSSNIV , System NMI
019Ah
SYSUNIV, User NMI
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Security violation (BOR)
0Ah
SVSL (POR)
0Ch
SVSH (POR)
0Eh
SVML_OVP (POR)
10h
SVMH_OVP (POR)
12h
PMMSWPOR (POR)
14h
WDT timeout (PUC)
16h
WDT password violation (PUC)
18h
KEYV flash password violation (PUC)
1Ah
FLL unlock (PUC)
1Ch
Peripheral area fetch (PUC)
1Eh
PMM password violation (PUC)
20h
Reserved
22h to 3Eh
No interrupt pending
00h
SVMLIFG
02h
SVMHIFG
04h
SVSMLDLYIFG
06h
SVSMHDLYIFG
08h
VMAIFG
0Ah
JMBINIFG
0Ch
JMBOUTIFG
0Eh
SVMLVLRIFG
10h
SVMHVLRIFG
12h
Reserved
14h to 1Eh
No interrupt pending
00h
NMIFG
02h
OFIFG
04h
ACCVIFG
06h
BUSIFG
08h
Reserved
0Ah to 1Eh
PRIORITY
Highest
Lowest
Highest
Lowest
Highest
Lowest
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DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU intervention. For
example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or
from a peripheral.
The USB timestamp generator also utilizes the DMA trigger assignments described in Table 12.
Table 12. DMA Trigger Assignments (1)
CHANNEL
TRIGGER
(1)
(2)
0
1
2
0
DMAREQ
DMAREQ
DMAREQ
1
TA0CCR0 CCIFG
TA0CCR0 CCIFG
TA0CCR0 CCIFG
2
TA0CCR2 CCIFG
TA0CCR2 CCIFG
TA0CCR2 CCIFG
3
TA1CCR0 CCIFG
TA1CCR0 CCIFG
TA1CCR0 CCIFG
4
TA1CCR2 CCIFG
TA1CCR2 CCIFG
TA1CCR2 CCIFG
5
TA2CCR0 CCIFG
TA2CCR0 CCIFG
TA2CCR0 CCIFG
6
TA2CCR2 CCIFG
TA2CCR2 CCIFG
TA2CCR2 CCIFG
7
TB0CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR0 CCIFG
8
TB0CCR2 CCIFG
TB0CCR2 CCIFG
TB0CCR2 CCIFG
9
Reserved
Reserved
Reserved
10
Reserved
Reserved
Reserved
11
Reserved
Reserved
Reserved
12
Reserved
Reserved
Reserved
13
Reserved
Reserved
Reserved
14
Reserved
Reserved
Reserved
15
Reserved
Reserved
Reserved
16
UCA0RXIFG
UCA0RXIFG
UCA0RXIFG
17
UCA0TXIFG
UCA0TXIFG
UCA0TXIFG
18
UCB0RXIFG
UCB0RXIFG
UCB0RXIFG
19
UCB0TXIFG
UCB0TXIFG
UCB0TXIFG
20
UCA1RXIFG
UCA1RXIFG
UCA1RXIFG
21
UCA1TXIFG
UCA1TXIFG
UCA1TXIFG
22
UCB1RXIFG
UCB1RXIFG
UCB1RXIFG
23
UCB1TXIFG
UCB1TXIFG
UCB1TXIFG
(2)
ADC12IFGx
(2)
ADC12IFGx (2)
24
ADC12IFGx
25
Reserved
Reserved
Reserved
26
Reserved
Reserved
Reserved
27
USB FNRXD
USB FNRXD
USB FNRXD
28
USB ready
USB ready
USB ready
29
MPY ready
MPY ready
MPY ready
30
DMA2IFG
DMA0IFG
DMA1IFG
31
DMAE0
DMAE0
DMAE0
If a reserved trigger source is selected, no Trigger1 is generated.
Only on devices with ADC. Reserved on devices without ADC.
Universal Serial Communication Interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as
UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module contains two portions,
A and B.
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The USCI_An module provides support for SPI (3 pin or 4 pin), UART, enhanced UART, or IrDA.
The USCI_Bn module provides support for SPI (3 pin or 4 pin) or I2C.
The MSP430F55xx series includes two complete USCI modules (n = 0, 1).
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TA0
TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. It can support multiple
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may
be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 13. TA0 Signal Connections
INPUT PIN NUMBER
RGC/ZQE
PN
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
18/H2-P1.0
21-P1.0
TA0CLK
TACLK
ACLK
(internal)
ACLK
SMCLK
(internal)
SMCLK
18/H2-P1.0
21-P1.0
TA0CLK
TACLK
19/H3-P1.1
22-P1.1
TA0.0
CCI0A
DVSS
CCI0B
DVSS
GND
20/J3-P1.2
21/G4-P1.3
22/H4-P1.4
23/J4-P1.5
(1)
23-P1.2
24-P1.3
25-P1.4
26-P1.5
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
NA
NA
CCR0
TA0
OUTPUT PIN NUMBER
RGC/ZQE
PN
19/H3-P1.1
22-P1.1
TA0.0
DVCC
VCC
TA0.1
CCI1A
20/J3-P1.2
23-P1.2
CBOUT
(internal)
CCI1B
ADC12
(internal) (1)
ADC12SHSx =
{1}
ADC12
(internal) (1)
ADC12SHSx =
{1}
DVSS
GND
21/G4-P1.3
24-P1.3
22/H4-P1.4
25-P1.4
23/J4-P1.5
26-P1.5
DVCC
VCC
TA0.2
CCI2A
ACLK
(internal)
CCI2B
DVSS
GND
DVCC
VCC
TA0.3
CCI3A
DVSS
CCI3B
DVSS
GND
DVCC
VCC
TA0.4
CCI4A
DVSS
CCI4B
DVSS
GND
DVCC
VCC
CCR1
CCR2
CCR3
CCR4
TA1
TA2
TA3
TA4
TA0.1
TA0.2
TA0.3
TA0.4
Only on devices with ADC.
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TA1
TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It can support multiple
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may
be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 14. TA1 Signal Connections
INPUT PIN NUMBER
RGC/ZQE
PN
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
24/G5-P1.6
27-P1.6
TA1CLK
TACLK
ACLK
(internal)
ACLK
SMCLK
(internal)
SMCLK
24/G5-P1.6
27-P1.6
TA1CLK
TACLK
25/H5-P1.7
28-P1.7
TA1.0
CCI0A
DVSS
CCI0B
DVSS
GND
26/J5-P2.0
27/G6-P2.1
30
29-P2.0
30-P2.1
DVCC
VCC
TA1.1
CCI1A
CBOUT
(internal)
CCI1B
DVSS
GND
DVCC
VCC
TA1.2
CCI2A
ACLK
(internal)
CCI2B
DVSS
GND
DVCC
VCC
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MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
NA
NA
CCR0
CCR1
CCR2
TA0
TA1
TA2
OUTPUT PIN NUMBER
RGC/ZQE
PN
25/H5-P1.7
28-P1.7
26/J5-P2.0
29-P2.0
27/G6-P2.1
30-P2.1
TA1.0
TA1.1
TA1.2
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TA2
TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It can support multiple
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may
be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 15. TA2 Signal Connections
INPUT PIN NUMBER
RGC/ZQE
PN
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
28/J6-P2.2
31-P2.2
TA2CLK
TACLK
ACLK
(internal)
ACLK
SMCLK
(internal)
SMCLK
28/J6-P2.2
31-P2.2
TA2CLK
TACLK
29/H6-P2.3
32-P2.3
TA2.0
CCI0A
DVSS
CCI0B
DVSS
GND
30/J7-P2.4
31/J8-P2.5
33-P2.4
34-P2.5
DVCC
VCC
TA2.1
CCI1A
CBOUT
(internal)
CCI1B
DVSS
GND
DVCC
VCC
TA2.2
CCI2A
ACLK
(internal)
CCI2B
DVSS
GND
DVCC
VCC
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MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
NA
NA
CCR0
CCR1
CCR2
TA0
TA1
TA2
OUTPUT PIN NUMBER
RGC/ZQE
PN
29/H6-P2.3
32-P2.3
30/J7-P2.4
33-P2.4
31/J8-P2.5
34-P2.5
TA2.0
TA2.1
TA2.2
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TB0
TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. It can support multiple
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may
be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 16. TB0 Signal Connections
INPUT PIN NUMBER
RGC/ZQE
(1)
PN
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
60-P7.7
TB0CLK
TBCLK
ACLK
(internal)
ACLK
SMCLK
(internal)
SMCLK
60-P7.7
TB0CLK
TBCLK
55-P5.6
TB0.0
CCI0A
55-P5.6
56-P5.7
32
CCI0B
DVSS
GND
DVCC
VCC
TB0.1
CCI1A
CBOUT
(internal)
CCI1B
DVSS
GND
DVCC
VCC
57-P7.4
TB0.2
CCI2A
57-P7.4
TB0.2
CCI2B
DVSS
GND
DVCC
VCC
58-P7.5
TB0.3
CCI3A
58-P7.5
TB0.3
CCI3B
DVSS
GND
DVCC
VCC
59-P7.6
TB0.4
CCI4A
59-P7.6
TB0.4
CCI4B
DVSS
GND
DVCC
VCC
42-P3.5
TB0.5
CCI5A
42-P3.5
TB0.5
CCI5B
DVSS
GND
43-P3.6
(1)
(2)
TB0.0
DVCC
VCC
TB0.6
CCI6A
ACLK
(internal)
CCI6B
DVSS
GND
DVCC
VCC
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
NA
NA
OUTPUT PIN NUMBER
RGC/ZQE (1)
PN
55-P5.6
CCR0
TB0
TB0.0
ADC12
(internal) (2)
ADC12SHSx =
{2}
ADC12
(internal) (2)
ADC12SHSx =
{2}
ADC12 (internal)
ADC12SHSx =
{3}
ADC12 (internal)
ADC12SHSx =
{3}
56-P5.7
CCR1
TB1
TB0.1
57-P7.4
CCR2
TB2
TB0.2
58-P7.5
CCR3
TB3
TB0.3
59-P7.6
CCR4
TB4
TB0.4
42-P3.5
CCR5
TB5
TB0.5
43-P3.6
CCR6
TB6
TB0.6
Timer functions selectable via the port mapping controller.
Only on devices with ADC.
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Comparator_B
The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions,
battery voltage supervision, and monitoring of external analog signals.
ADC12_A
The ADC12_A module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator and a 16 word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any
CPU intervention.
CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used for data
checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
REF Voltage Reference
The reference module (REF) is responsible for generation of all critical reference voltages that can be used by
the various analog peripherals in the device.
USB Universal Serial Bus
The USB module is a fully integrated USB interface that is compliant with the USB 2.0 specification. The module
supports full-speed operation of control, interrupt, and bulk transfers. The module includes an integrated LDO,
PHY, and PLL. The PLL is highly-flexible and can support a wide range of input clock frequencies. USB RAM,
when not used for USB communication, can be used by the system.
Embedded Emulation Module (EEM)
The Embedded Emulation Module (EEM) supports real-time in-system debugging. The L version of the EEM
implemented on all devices has the following features:
• Eight hardware triggers/breakpoints on memory access
• Two hardware trigger/breakpoint on CPU register write access
• Up to ten hardware triggers can be combined to form complex triggers/breakpoints
• Two cycle counters
• Sequencer
• State storage
• Clock control on module level
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Peripheral File Map
Table 17. Peripherals
34
MODULE NAME
BASE ADDRESS
OFFSET ADDRESS
RANGE
Special Functions (refer to Table 18)
0100h
000h - 01Fh
PMM (refer to Table 19)
0120h
000h - 010h
Flash Control (refer to Table 20)
0140h
000h - 00Fh
CRC16 (refer to Table 21)
0150h
000h - 007h
RAM Control (refer to Table 22)
0158h
000h - 001h
Watchdog (refer to Table 23)
015Ch
000h - 001h
UCS (refer to Table 24)
0160h
000h - 01Fh
SYS (refer to Table 25)
0180h
000h - 01Fh
Shared Reference (refer to Table 26)
01B0h
000h - 001h
Port Mapping Control (refer to Table 27)
01C0h
000h - 002h
Port Mapping Port P4 (refer to Table 27)
01E0h
000h - 007h
Port P1/P2 (refer to Table 28)
0200h
000h - 01Fh
Port P3/P4 (refer to Table 29)
0220h
000h - 00Bh
Port P5/P6 (refer to Table 30)
0240h
000h - 00Bh
Port P7/P8 (refer to Table 31)
0260h
000h - 00Bh
Port PJ (refer to Table 32)
0320h
000h - 01Fh
TA0 (refer to Table 33)
0340h
000h - 02Eh
TA1 (refer to Table 34)
0380h
000h - 02Eh
TB0 (refer to Table 35)
03C0h
000h - 02Eh
TA2 (refer to Table 36)
0400h
000h - 02Eh
Real Timer Clock (RTC_A) (refer to Table 37)
04A0h
000h - 01Bh
32-bit Hardware Multiplier (refer to Table 38)
04C0h
000h - 02Fh
DMA General Control (refer to Table 39)
0500h
000h - 00Fh
DMA Channel 0 (refer to Table 39)
0510h
000h - 00Ah
DMA Channel 1 (refer to Table 39)
0520h
000h - 00Ah
DMA Channel 2 (refer to Table 39)
0530h
000h - 00Ah
USCI_A0 (refer to Table 40)
05C0h
000h - 01Fh
USCI_B0 (refer to Table 41)
05E0h
000h - 01Fh
USCI_A1 (refer to Table 42)
0600h
000h - 01Fh
USCI_B1 (refer to Table 43)
0620h
000h - 01Fh
ADC12_A (refer to Table 44)
0700h
000h - 03Eh
Comparator_B (refer to Table 45)
08C0h
000h - 00Fh
USB configuration (refer to Table 46)
0900h
000h - 014h
USB control (refer to Table 47)
0920h
000h - 01Fh
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Table 18. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SFR interrupt enable
SFRIE1
00h
SFR interrupt flag
SFRIFG1
02h
SFR reset pin control
SFRRPCR
04h
Table 19. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
OFFSET
PMM Control 0
PMMCTL0
00h
PMM control 1
PMMCTL1
02h
SVS high side control
SVSMHCTL
04h
SVS low side control
SVSMLCTL
06h
PMM interrupt flags
PMMIFG
0Ch
PMM interrupt enable
PMMIE
0Eh
PMM power mode 5 control
PM5CTL0
10h
Table 20. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Flash control 1
FCTL1
00h
Flash control 3
FCTL3
04h
Flash control 4
FCTL4
06h
Table 21. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
OFFSET
CRC data input
CRC16DI
00h
CRC data input reverse byte
CRCDIRB
02h
CRC initialization and result
CRCINIRES
04h
CRC result reverse byte
CRCRESR
06h
Table 22. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
RAM control 0
REGISTER
RCCTL0
OFFSET
00h
Table 23. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
Watchdog timer control
REGISTER
WDTCTL
OFFSET
00h
Table 24. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
OFFSET
UCS control 0
UCSCTL0
00h
UCS control 1
UCSCTL1
02h
UCS control 2
UCSCTL2
04h
UCS control 3
UCSCTL3
06h
UCS control 4
UCSCTL4
08h
UCS control 5
UCSCTL5
0Ah
UCS control 6
UCSCTL6
0Ch
UCS control 7
UCSCTL7
0Eh
UCS control 8
UCSCTL8
10h
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Table 25. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
System control
SYSCTL
00h
Bootstrap loader configuration area
SYSBSLC
02h
JTAG mailbox control
SYSJMBC
06h
JTAG mailbox input 0
SYSJMBI0
08h
JTAG mailbox input 1
SYSJMBI1
0Ah
JTAG mailbox output 0
SYSJMBO0
0Ch
JTAG mailbox output 1
SYSJMBO1
0Eh
Bus Error vector generator
SYSBERRIV
18h
User NMI vector generator
SYSUNIV
1Ah
System NMI vector generator
SYSSNIV
1Ch
Reset vector generator
SYSRSTIV
1Eh
Table 26. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
Shared reference control
REGISTER
REFCTL
OFFSET
00h
Table 27. Port Mapping Registers
(Base Address of Port Mapping Control: 01C0h, Port P4: 01E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port mapping key/ID register
PMAPKEYID
00h
Port mapping control register
PMAPCTL
02h
Port P4.0 mapping register
P4MAP0
00h
Port P4.1 mapping register
P4MAP1
01h
Port P4.2 mapping register
P4MAP2
02h
Port P4.3 mapping register
P4MAP3
03h
Port P4.4 mapping register
P4MAP4
04h
Port P4.5 mapping register
P4MAP5
05h
Port P4.6 mapping register
P4MAP6
06h
Port P4.7 mapping register
P4MAP7
07h
36
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Table 28. Port P1/P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1 input
P1IN
00h
Port P1 output
P1OUT
02h
Port P1 direction
P1DIR
04h
Port P1 pullup/pulldown enable
P1REN
06h
Port P1 drive strength
P1DS
08h
Port P1 selection
P1SEL
0Ah
Port P1 interrupt vector word
P1IV
0Eh
Port P1 interrupt edge select
P1IES
18h
Port P1 interrupt enable
P1IE
1Ah
Port P1 interrupt flag
P1IFG
1Ch
Port P2 input
P2IN
01h
Port P2 output
P2OUT
03h
Port P2 direction
P2DIR
05h
Port P2 pullup/pulldown enable
P2REN
07h
Port P2 drive strength
P2DS
09h
Port P2 selection
P2SEL
0Bh
Port P2 interrupt vector word
P2IV
1Eh
Port P2 interrupt edge select
P2IES
19h
Port P2 interrupt enable
P2IE
1Bh
Port P2 interrupt flag
P2IFG
1Dh
Table 29. Port P3/P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
Port P3 output
P3OUT
02h
Port P3 direction
P3DIR
04h
Port P3 pullup/pulldown enable
P3REN
06h
Port P3 drive strength
P3DS
08h
Port P3 selection
P3SEL
0Ah
Port P4 input
P4IN
01h
Port P4 output
P4OUT
03h
Port P4 direction
P4DIR
05h
Port P4 pullup/pulldown enable
P4REN
07h
Port P4 drive strength
P4DS
09h
Port P4 selection
P4SEL
0Bh
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Table 30. Port P5/P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P5 input
P5IN
00h
Port P5 output
P5OUT
02h
Port P5 direction
P5DIR
04h
Port P5 pullup/pulldown enable
P5REN
06h
Port P5 drive strength
P5DS
08h
Port P5 selection
P5SEL
0Ah
Port P6 input
P6IN
01h
Port P6 output
P6OUT
03h
Port P6 direction
P6DIR
05h
Port P6 pullup/pulldown enable
P6REN
07h
Port P6 drive strength
P6DS
09h
Port P6 selection
P6SEL
0Bh
Table 31. Port P7/P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P7 input
P7IN
00h
Port P7 output
P7OUT
02h
Port P7 direction
P7DIR
04h
Port P7 pullup/pulldown enable
P7REN
06h
Port P7 drive strength
P7DS
08h
Port P7 selection
P7SEL
0Ah
Port P8 input
P8IN
01h
Port P8 output
P8OUT
03h
Port P8 direction
P8DIR
05h
Port P8 pullup/pulldown enable
P8REN
07h
Port P8 drive strength
P8DS
09h
Port P8 selection
P8SEL
0Bh
Table 32. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port PJ input
PJIN
00h
Port PJ output
PJOUT
02h
Port PJ direction
PJDIR
04h
Port PJ pullup/pulldown enable
PJREN
06h
Port PJ drive strength
PJDS
08h
38
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Table 33. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA0 control
TA0CTL
00h
Capture/compare control 0
TA0CCTL0
02h
Capture/compare control 1
TA0CCTL1
04h
Capture/compare control 2
TA0CCTL2
06h
Capture/compare control 3
TA0CCTL3
08h
Capture/compare control 4
TA0CCTL4
0Ah
TA0 counter register
TA0R
10h
Capture/compare register 0
TA0CCR0
12h
Capture/compare register 1
TA0CCR1
14h
Capture/compare register 2
TA0CCR2
16h
Capture/compare register 3
TA0CCR3
18h
Capture/compare register 4
TA0CCR4
1Ah
TA0 expansion register 0
TA0EX0
20h
TA0 interrupt vector
TA0IV
2Eh
Table 34. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA1 control
TA1CTL
00h
Capture/compare control 0
TA1CCTL0
02h
Capture/compare control 1
TA1CCTL1
04h
Capture/compare control 2
TA1CCTL2
06h
TA1 counter register
TA1R
10h
Capture/compare register 0
TA1CCR0
12h
Capture/compare register 1
TA1CCR1
14h
Capture/compare register 2
TA1CCR2
16h
TA1 expansion register 0
TA1EX0
20h
TA1 interrupt vector
TA1IV
2Eh
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Table 35. TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TB0 control
TB0CTL
00h
Capture/compare control 0
TB0CCTL0
02h
Capture/compare control 1
TB0CCTL1
04h
Capture/compare control 2
TB0CCTL2
06h
Capture/compare control 3
TB0CCTL3
08h
Capture/compare control 4
TB0CCTL4
0Ah
Capture/compare control 5
TB0CCTL5
0Ch
Capture/compare control 6
TB0CCTL6
0Eh
TB0 register
TB0R
10h
Capture/compare register 0
TB0CCR0
12h
Capture/compare register 1
TB0CCR1
14h
Capture/compare register 2
TB0CCR2
16h
Capture/compare register 3
TB0CCR3
18h
Capture/compare register 4
TB0CCR4
1Ah
Capture/compare register 5
TB0CCR5
1Ch
Capture/compare register 6
TB0CCR6
1Eh
TB0 expansion register 0
TB0EX0
20h
TB0 interrupt vector
TB0IV
2Eh
Table 36. TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA2 control
TA2CTL
00h
Capture/compare control 0
TA2CCTL0
02h
Capture/compare control 1
TA2CCTL1
04h
Capture/compare control 2
TA2CCTL2
06h
TA2 counter register
TA2R
10h
Capture/compare register 0
TA2CCR0
12h
Capture/compare register 1
TA2CCR1
14h
Capture/compare register 2
TA2CCR2
16h
TA2 expansion register 0
TA2EX0
20h
TA2 interrupt vector
TA2IV
2Eh
40
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Table 37. Real Time Clock Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
RTC control 0
RTCCTL0
00h
RTC control 1
RTCCTL1
01h
RTC control 2
RTCCTL2
02h
RTC control 3
RTCCTL3
03h
RTC prescaler 0 control
RTCPS0CTL
08h
RTC prescaler 1 control
RTCPS1CTL
0Ah
RTC prescaler 0
RTCPS0
0Ch
RTC prescaler 1
RTCPS1
0Dh
RTC interrupt vector word
RTCIV
0Eh
RTC seconds/counter register 1
RTCSEC/RTCNT1
10h
RTC minutes/counter register 2
RTCMIN/RTCNT2
11h
RTC hours/counter register 3
RTCHOUR/RTCNT3
12h
RTC day of week/counter register 4
RTCDOW/RTCNT4
13h
RTC days
RTCDAY
14h
RTC month
RTCMON
15h
RTC year low
RTCYEARL
16h
RTC year high
RTCYEARH
17h
RTC alarm minutes
RTCAMIN
18h
RTC alarm hours
RTCAHOUR
19h
RTC alarm day of week
RTCADOW
1Ah
RTC alarm days
RTCADAY
1Bh
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Table 38. 32-bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
16-bit operand 1 – signed multiply
MPYS
02h
16-bit operand 1 – multiply accumulate
MAC
04h
16-bit operand 1 – signed multiply accumulate
MACS
06h
16-bit operand 2
OP2
08h
16 × 16 result low word
RESLO
0Ah
16 × 16 result high word
RESHI
0Ch
16 × 16 sum extension register
SUMEXT
0Eh
32-bit operand 1 – multiply low word
MPY32L
10h
32-bit operand 1 – multiply high word
MPY32H
12h
32-bit operand 1 – signed multiply low word
MPYS32L
14h
32-bit operand 1 – signed multiply high word
MPYS32H
16h
32-bit operand 1 – multiply accumulate low word
MAC32L
18h
32-bit operand 1 – multiply accumulate high word
MAC32H
1Ah
32-bit operand 1 – signed multiply accumulate low word
MACS32L
1Ch
32-bit operand 1 – signed multiply accumulate high word
MACS32H
1Eh
32-bit operand 2 – low word
OP2L
20h
32-bit operand 2 – high word
OP2H
22h
32 × 32 result 0 – least significant word
RES0
24h
32 × 32 result 1
RES1
26h
32 × 32 result 2
RES2
28h
32 × 32 result 3 – most significant word
RES3
2Ah
MPY32 control register 0
MPY32CTL0
2Ch
42
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Table 39. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 0 control
DMA0CTL
00h
DMA channel 0 source address low
DMA0SAL
02h
DMA channel 0 source address high
DMA0SAH
04h
DMA channel 0 destination address low
DMA0DAL
06h
DMA channel 0 destination address high
DMA0DAH
08h
DMA channel 0 transfer size
DMA0SZ
0Ah
DMA channel 1 control
DMA1CTL
00h
DMA channel 1 source address low
DMA1SAL
02h
DMA channel 1 source address high
DMA1SAH
04h
DMA channel 1 destination address low
DMA1DAL
06h
DMA channel 1 destination address high
DMA1DAH
08h
DMA channel 1 transfer size
DMA1SZ
0Ah
DMA channel 2 control
DMA2CTL
00h
DMA channel 2 source address low
DMA2SAL
02h
DMA channel 2 source address high
DMA2SAH
04h
DMA channel 2 destination address low
DMA2DAL
06h
DMA channel 2 destination address high
DMA2DAH
08h
DMA channel 2 transfer size
DMA2SZ
0Ah
DMA module control 0
DMACTL0
00h
DMA module control 1
DMACTL1
02h
DMA module control 2
DMACTL2
04h
DMA module control 3
DMACTL3
06h
DMA module control 4
DMACTL4
08h
DMA interrupt vector
DMAIV
0Eh
Table 40. USCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 1
UCA0CTL1
00h
USCI control 0
UCA0CTL0
01h
USCI baud rate 0
UCA0BR0
06h
USCI baud rate 1
UCA0BR1
07h
USCI modulation control
UCA0MCTL
08h
USCI status
UCA0STAT
0Ah
USCI receive buffer
UCA0RXBUF
0Ch
USCI transmit buffer
UCA0TXBUF
0Eh
USCI LIN control
UCA0ABCTL
10h
USCI IrDA transmit control
UCA0IRTCTL
12h
USCI IrDA receive control
UCA0IRRCTL
13h
USCI interrupt enable
UCA0IE
1Ch
USCI interrupt flags
UCA0IFG
1Dh
USCI interrupt vector word
UCA0IV
1Eh
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Table 41. USCI_B0 Registers (Base Address: 05E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 1
UCB0CTL1
00h
USCI synchronous control 0
UCB0CTL0
01h
USCI synchronous bit rate 0
UCB0BR0
06h
USCI synchronous bit rate 1
UCB0BR1
07h
USCI synchronous status
UCB0STAT
0Ah
USCI synchronous receive buffer
UCB0RXBUF
0Ch
USCI synchronous transmit buffer
UCB0TXBUF
0Eh
USCI I2C own address
UCB0I2COA
10h
USCI I2C slave address
UCB0I2CSA
12h
USCI interrupt enable
UCB0IE
1Ch
USCI interrupt flags
UCB0IFG
1Dh
USCI interrupt vector word
UCB0IV
1Eh
Table 42. USCI_A1 Registers (Base Address: 0600h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 1
UCA1CTL1
00h
USCI control 0
UCA1CTL0
01h
USCI baud rate 0
UCA1BR0
06h
USCI baud rate 1
UCA1BR1
07h
USCI modulation control
UCA1MCTL
08h
USCI status
UCA1STAT
0Ah
USCI receive buffer
UCA1RXBUF
0Ch
USCI transmit buffer
UCA1TXBUF
0Eh
USCI LIN control
UCA1ABCTL
10h
USCI IrDA transmit control
UCA1IRTCTL
12h
USCI IrDA receive control
UCA1IRRCTL
13h
USCI interrupt enable
UCA1IE
1Ch
USCI interrupt flags
UCA1IFG
1Dh
USCI interrupt vector word
UCA1IV
1Eh
44
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Table 43. USCI_B1 Registers (Base Address: 0620h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 1
UCB1CTL1
00h
USCI synchronous control 0
UCB1CTL0
01h
USCI synchronous bit rate 0
UCB1BR0
06h
USCI synchronous bit rate 1
UCB1BR1
07h
USCI synchronous status
UCB1STAT
0Ah
USCI synchronous receive buffer
UCB1RXBUF
0Ch
USCI synchronous transmit buffer
UCB1TXBUF
0Eh
USCI I2C own address
UCB1I2COA
10h
USCI I2C slave address
UCB1I2CSA
12h
USCI interrupt enable
UCB1IE
1Ch
USCI interrupt flags
UCB1IFG
1Dh
USCI interrupt vector word
UCB1IV
1Eh
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Table 44. ADC12_A Registers (Base Address: 0700h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Control register 0
ADC12CTL0
00h
Control register 1
ADC12CTL1
02h
Control register 2
ADC12CTL2
04h
Interrupt-flag register
ADC12IFG
0Ah
Interrupt-enable register
ADC12IE
0Ch
Interrupt-vector-word register
ADC12IV
0Eh
ADC memory-control register 0
ADC12MCTL0
10h
ADC memory-control register 1
ADC12MCTL1
11h
ADC memory-control register 2
ADC12MCTL2
12h
ADC memory-control register 3
ADC12MCTL3
13h
ADC memory-control register 4
ADC12MCTL4
14h
ADC memory-control register 5
ADC12MCTL5
15h
ADC memory-control register 6
ADC12MCTL6
16h
ADC memory-control register 7
ADC12MCTL7
17h
ADC memory-control register 8
ADC12MCTL8
18h
ADC memory-control register 9
ADC12MCTL9
19h
ADC memory-control register 10
ADC12MCTL10
1Ah
ADC memory-control register 11
ADC12MCTL11
1Bh
ADC memory-control register 12
ADC12MCTL12
1Ch
ADC memory-control register 13
ADC12MCTL13
1Dh
ADC memory-control register 14
ADC12MCTL14
1Eh
ADC memory-control register 15
ADC12MCTL15
1Fh
Conversion memory 0
ADC12MEM0
20h
Conversion memory 1
ADC12MEM1
22h
Conversion memory 2
ADC12MEM2
24h
Conversion memory 3
ADC12MEM3
26h
Conversion memory 4
ADC12MEM4
28h
Conversion memory 5
ADC12MEM5
2Ah
Conversion memory 6
ADC12MEM6
2Ch
Conversion memory 7
ADC12MEM7
2Eh
Conversion memory 8
ADC12MEM8
30h
Conversion memory 9
ADC12MEM9
32h
Conversion memory 10
ADC12MEM10
34h
Conversion memory 11
ADC12MEM11
36h
Conversion memory 12
ADC12MEM12
38h
Conversion memory 13
ADC12MEM13
3Ah
Conversion memory 14
ADC12MEM14
3Ch
Conversion memory 15
ADC12MEM15
3Eh
46
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Table 45. Comparator_B Registers (Base Address: 08C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Comp_B control register 0
CBCTL0
00h
Comp_B control register 1
CBCTL1
02h
Comp_B control register 2
CBCTL2
04h
Comp_B control register 3
CBCTL3
06h
Comp_B interrupt register
CBINT
0Ch
Comp_B interrupt vector word
CBIV
0Eh
Table 46. USB Configuration Registers (Base Address: 0900h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USB key/ID
USBKEYID
00h
USB module configuration
USBCNF
02h
USB PHY control
USBPHYCTL
04h
USB power control
USBPWRCTL
08h
USB PLL control
USBPLLCTL
10h
USB PLL divider
USBPLLDIV
12h
USB PLL interrupts
USBPLLIR
14h
Table 47. USB Control Registers (Base Address: 0920h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Input endpoint#0 configuration
IEPCNF_0
00h
Input endpoint #0 byte count
IEPCNT_0
01h
Output endpoint#0 configuration
OEPCNF_0
02h
Output endpoint #0 byte count
OEPCNT_0
03h
Input endpoint interrupt enables
IEPIE
0Eh
Output endpoint interrupt enables
OEPIE
0Fh
Input endpoint interrupt flags
IEPIFG
10h
Output endpoint interrupt flags
OEPIFG
11h
USB interrupt vector
USBIV
12h
USB maintenance
MAINT
16h
Time stamp
TSREG
18h
USB frame number
USBFN
1Ah
USB control
USBCTL
1Ch
USB interrupt enables
USBIE
1Dh
USB interrupt flags
USBIFG
1Eh
Function address
FUNADR
1Fh
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Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
Voltage applied at VCC to VSS
–0.3 V to 4.1 V
Voltage applied to any pin (excluding VCORE, VBUS, V18)
(2)
–0.3 V to VCC + 0.3 V
Diode current at any device pin
Storage temperature range, Tstg
±2 mA
(3)
–55°C to 105°C
Maximum junction temperature, TJ
(1)
(2)
(3)
95°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. VCORE is for internal device usage only. No external DC loading or voltage should be applied.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Thermal Packaging Characteristics
PARAMETER
Low-K board (JESD51-3)
qJA
Junction-to-ambient thermal resistance, still air
High-K board (JESD51-7)
qJC
qJB
48
Junction-to-case thermal resistance
Junction-to-board thermal resistance
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VALUE
QFP (PN)
70
QFN (RGC)
55
BGA (ZQE)
84
QFP (PN)
45
QFN (RGC)
25
BGA (ZQE)
46
QFP (PN)
12
QFN (RGC)
12
BGA (ZQE)
30
QFP (PN)
22
QFN (RGC)
6
BGA (ZQE)
20
UNIT
°C/W
°C/W
°C/W
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Recommended Operating Conditions
MIN
Supply voltage during program execution and flash
programming(AVCC = DVCC1/2 = DVCC) (1)
VCC
Supply voltage during USB operation, USB PLL disabled
USB_EN = 1, UPLLEN = 0
VCC, USB
Supply voltage during USB operation, USB PLL enabled
USB_EN = 1, UPLLEN = 1
(2)
NOM
MAX
UNIT
PMMCOREVx = 0
1.8
3.6
V
PMMCOREVx = 0, 1
2.0
3.6
V
PMMCOREVx = 0, 1, 2
2.2
3.6
V
PMMCOREVx = 0, 1, 2, 3
2.4
3.6
V
PMMCOREVx = 0
1.8
3.6
V
PMMCOREVx = 0, 1
2.0
3.6
V
PMMCOREVx = 0, 1, 2
2.2
3.6
V
PMMCOREVx = 0, 1, 2, 3
2.4
3.6
V
PMMCOREVx = 2
2.2
3.6
V
PMMCOREVx = 2, 3
2.4
3.6
V
VSS
Supply voltage (AVSS = DVSS1/2 = DVSS)
TA
Operating free-air temperature
I version
–40
85
°C
TJ
Operating junction temperature
I version
–40
85
°C
CVCORE
Capacitor at VCORE
CDVCC/
CVCORE
Capacitor ratio of DVCC to VCORE
fSYSTEM
0
470
Processor frequency (maximum MCLK frequency) (3)
(see Figure 1)
Minimum processor frequency for USB operation
USB_wait
Wait state cycles during USB operation
(2)
(3)
nF
10
fSYSTEM_USB
(1)
V
PMMCOREVx = 0
1.8 V ≤ VCC ≤ 3.6 V
(default condition)
0
8.0
PMMCOREVx = 1
2.0 V ≤ VCC ≤ 3.6 V
0
12.0
PMMCOREVx = 2
2.2 V ≤ VCC ≤ 3.6 V
0
20.0
PMMCOREVx = 3
2.4 V ≤ VCC ≤ 3.6 V
0
25.0
1.5
MHz
MHz
16
cycles
It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
USB operation with USB PLL enabled requires PMMCOREVx ≥ 2 for proper operation.
Modules may have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet.
25
System Frequency - MHz
3
20
2
2, 3
1
1, 2
1, 2, 3
0, 1
0, 1, 2
0, 1, 2, 3
12
8
0
0
1.8
2.0
2.2
2.4
3.6
Supply Voltage - V
The numbers within the fields denote the supported PMMCOREVx settings.
Figure 1. Maximum System Frequency
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Electrical Characteristics
Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted) (1)
(2) (3)
FREQUENCY (fDCO = fMCLK = fSMCLK)
PARAMETER
IAM,
IAM,
(1)
(2)
(3)
50
Flash
RAM
EXECUTION
MEMORY
Flash
RAM
VCC
3.0 V
3.0 V
PMMCOREVx
1 MHz
8 MHz
12 MHz
TYP
MAX
2.65
4.0
4.4
2.90
20 MHz
TYP
MAX
TYP
MAX
0
0.36
0.47
2.32
2.60
1
0.40
2
0.44
3
0.46
0
0.20
1
0.22
1.35
2.0
2
0.24
1.50
2.2
3.7
3
0.26
1.60
2.4
3.9
3.10
0.24
1.20
TYP
MAX
4.3
7.1
7.7
4.6
7.6
25 MHz
TYP
UNIT
MAX
mA
10.1
11.0
1.30
2.2
mA
4.2
5.3
6.2
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
Characterized with program executing typical data processing. USB disabled (VUSBEN = 0, SLDOEN = 0).
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.
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Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
ILPM0,1MHz
Low-power mode 0 (3) (4)
ILPM2
Low-power mode 2 (5) (4)
ILPM4
0
73
77
85
80
85
97
3.0 V
3
79
83
92
88
95
105
2.2 V
0
6.5
6.5
12
10
11
17
3.0 V
3
7.0
7.0
13
11
12
18
0
1.60
1.90
2.6
4.4
1
1.65
2.00
2.7
4.6
2
1.75
2.15
2.9
4.9
0
1.8
2.1
2.8
4.6
1
1.9
2.3
2.9
4.8
2
2.0
2.4
3.0
5.0
3
2.0
2.5
3.9
3.1
5.1
9.0
0
1.1
1.4
2.7
1.9
3.8
6.5
1
1.1
1.4
2.0
4.0
2
1.2
1.5
2.1
4.1
3
1.3
1.6
3.0
2.2
4.2
8.5
0
0.9
1.1
1.5
1.8
4.0
6.0
1
1.1
1.2
2.0
4.2
2
1.2
1.2
2.1
4.3
3
1.3
1.3
1.6
2.2
4.4
8.0
ILPM4.5
0.15
0.18
0.35
0.26
0.5
1.0
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
3.0 V
Low-power mode 4 (8) (4)
Low-power mode 4.5
(9)
85°C
2.2 V
Low-power mode 3,
crystal mode (6) (4)
Low-power mode 3,
VLO mode (7) (4)
60°C
PMMCOREVx
3.0 V
ILPM3,VLO
25°C
VCC
2.2 V
ILPM3,XT1LF
-40°C
(2)
3.0 V
3.0 V
TYP
MAX
TYP
MAX
2.9
TYP
MAX
TYP
MAX
7.0
UNIT
µA
µA
µA
µA
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
USB disabled (VUSBEN = 0, SLDOEN = 0).
Current for brownout, high side supervisor (SVSH) normal mode included. Low side supervisor and monitors disabled (SVSL, SVML).
High side monitor disabled (SVMH). RAM retention enabled.
Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz; DCO setting = 1
MHz operation, DCO bias generator enabled.
USB disabled (VUSBEN = 0, SLDOEN = 0)
Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
USB disabled (VUSBEN = 0, SLDOEN = 0)
Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz
USB disabled (VUSBEN = 0, SLDOEN = 0)
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
USB disabled (VUSBEN = 0, SLDOEN = 0)
Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
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Schmitt-Trigger Inputs – General Purpose I/O (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup/pulldown resistor
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
(1)
VCC
MIN
TYP
1.8 V
0.80
1.40
3V
1.50
2.10
1.8 V
0.45
1.00
3V
0.75
1.65
1.8 V
0.3
0.85
3V
0.4
1.0
20
35
MAX
50
5
UNIT
V
V
V
kΩ
pF
Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
Inputs – Ports P1 and P2 (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
t(int)
(1)
(2)
External interrupt timing
(2)
TEST CONDITIONS
VCC
Port P1, P2: P1.x to P2.x, External trigger pulse width to
set interrupt flag
2.2 V/3 V
MIN
MAX
20
UNIT
ns
Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set by trigger signals shorter
than t(int).
Leakage Current – General Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.x)
(1)
(2)
TEST CONDITIONS
VCC
(1) (2)
High-impedance leakage current
MIN
1.8 V/3 V
MAX
UNIT
±50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
Outputs – General Purpose I/O (Full Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –3 mA
VOH
High-level output voltage
I(OHmax) = –10 mA (2)
I(OHmax) = –5 mA (1)
I(OHmax) = –15 mA (2)
I(OLmax) = 3 mA
VOL
Low-level output voltage
(2)
52
1.8 V
3V
(1)
I(OLmax) = 10 mA (2)
I(OLmax) = 5 mA (1)
I(OLmax) = 15 mA (2)
(1)
VCC
(1)
1.8 V
3V
MIN
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
UNIT
V
VSS VSS + 0.25
VSS VSS + 0.60
VSS VSS + 0.25
V
VSS VSS + 0.60
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
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Outputs – General Purpose I/O (Reduced Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA
VOH
1.8 V
I(OHmax) = –3 mA (3)
High-level output voltage
I(OHmax) = –2 mA (2)
3.0 V
I(OHmax) = –6 mA (3)
I(OLmax) = 1 mA
VOL
(3)
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
1.8 V
I(OLmax) = 2 mA (2)
3.0 V
I(OLmax) = 6 mA (3)
(1)
(2)
MIN
(2)
I(OLmax) = 3 mA (3)
Low-level output voltage
VCC
(2)
UNIT
V
VSS VSS + 0.25
VSS VSS + 0.60
VSS VSS + 0.25
V
VSS VSS + 0.60
Selecting reduced drive strength may reduce EMI.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
Output Frequency – General Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
(1) (2)
Port output frequency
(with load)
fPx.y
fPort_CLK
(1)
(2)
Clock output frequency
ACLK
SMCLK
MCLK
CL = 20 pF (2)
VCC = 1.8 V
PMMCOREVx = 0
16
VCC = 3 V
PMMCOREVx = 3
25
VCC = 1.8 V
PMMCOREVx = 0
16
VCC = 3 V
PMMCOREVx = 3
25
MHz
MHz
A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
8.0
VCC = 3.0 V
Px.y
IOL – Typical Low-Level Output Current – mA
IOL – Typical Low-Level Output Current – mA
25.0
TA = 25°C
20.0
TA = 85°C
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
7.0
TA = 85°C
6.0
5.0
4.0
3.0
2.0
1.0
0.0
0.0
3.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
2.0
0.0
VCC = 3.0 V
Px.y
IOH – Typical High-Level Output Current – mA
IOH – Typical High-Level Output Current – mA
1.5
Figure 3.
-5.0
-10.0
TA = 85°C
TA = 25°C
VCC = 1.8 V
Px.y
-1.0
-2.0
-3.0
-4.0
TA = 85°C
-5.0
-6.0
TA = 25°C
-7.0
-8.0
-25.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOH – High-Level Output Voltage – V
Figure 4.
54
1.0
Figure 2.
0.0
-20.0
0.5
VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
-15.0
TA = 25°C
VCC = 1.8 V
Px.y
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0.0
0.5
1.0
1.5
VOH – High-Level Output Voltage – V
2.0
Figure 5.
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SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TA = 25°C
VCC = 3.0 V
Px.y
55.0
50.0
IOL – Typical Low-Level Output Current – mA
IOL – Typical Low-Level Output Current – mA
60.0
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TA = 85°C
45.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
24
VCC = 1.8 V
Px.y
TA = 85°C
16
12
8
4
0
0.0
3.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
IOH – Typical High-Level Output Current – mA
IOH – Typical High-Level Output Current – mA
2.0
0
-10.0
-15.0
-20.0
-25.0
-30.0
-35.0
-40.0
-45.0
TA = 85°C
-55.0
TA = 25°C
0.0
1.5
Figure 7.
VCC = 3.0 V
Px.y
-60.0
1.0
Figure 6.
0.0
-50.0
0.5
VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
-5.0
TA = 25°C
20
0.5
VCC = 1.8 V
Px.y
-4
-8
-12
TA = 85°C
-16
TA = 25°C
-20
1.0
1.5
2.0
2.5
3.0
VOH – High-Level Output Voltage – V
Figure 8.
Copyright © 2009–2010, Texas Instruments Incorporated
3.5
0.0
0.5
1.0
1.5
2.0
VOH – High-Level Output Voltage – V
Figure 9.
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Crystal Oscillator, XT1, Low-Frequency Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ΔIDVCC.LF
Differential XT1 oscillator
crystal current consumption
from lowest drive setting, LF
mode
TEST CONDITIONS
VCC
MIN
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 1, TA = 25°C
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 2, TA = 25°C
3.0 V
0.170
0.290
XTS = 0, XT1BYPASS = 0
32768
XT1 oscillator crystal
frequency, LF mode
fXT1,LF,SW
XT1 oscillator logic-level
square-wave input frequency, XTS = 0, XT1BYPASS = 1 (2)
LF mode
OALF
Oscillation allowance for
LF crystals (4)
(3)
10
210
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF
300
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
12.0
LF mode
fFault,LF
Oscillator fault frequency,
LF mode (7)
XTS = 0 (8)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
56
Startup time, LF mode
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 0, TA = 25°C, CL,eff = 6 pF
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 3, TA = 25°C, CL,eff = 12 pF
µA
Hz
50
kHz
2
5.5
Duty cycle
UNIT
kΩ
XTS = 0, XCAPx = 1
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
tSTART,LF
32.768
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF
XTS = 0, XCAPx = 0 (6)
CL,eff
MAX
0.075
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 3, TA = 25°C
fXT1,LF0
Integrated effective load
capacitance, LF mode (5)
TYP
pF
30
70
%
10
10000
Hz
1000
3.0 V
ms
500
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this datasheet.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
(a) For XT1DRIVEx = 0, CL,ef f ≤ 6 pF.
(b) For XT1DRIVEx = 1, 6 pF ≤ CL,ef f ≤ 9 pF.
(c) For XT1DRIVEx = 2, 6 pF ≤ CL,ef f ≤ 10 pF.
(d) For XT1DRIVEx = 3, CL,ef f ≥ 6 pF.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
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Crystal Oscillator, XT2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
MIN
fOSC = 4 MHz, XT2OFF = 0, XT2BYPASS = 0,
XT2DRIVEx = 0, TA = 25°C
IDVCC.XT2
XT2 oscillator crystal
current consumption
fOSC = 12 MHz, XT2OFF = 0, XT2BYPASS = 0,
XT2DRIVEx = 1, TA = 25°C
fOSC = 20 MHz, XT2OFF = 0, XT2BYPASS = 0,
XT2DRIVEx = 2, TA = 25°C
(2)
TYP
MAX
UNIT
200
260
3.0 V
µA
325
fOSC = 32 MHz, XT2OFF = 0, XT2BYPASS = 0,
XT2DRIVEx = 3, TA = 25°C
450
fXT2,HF0
XT2 oscillator crystal
frequency, mode 0
XT2DRIVEx = 0, XT2BYPASS = 0 (3)
4
8
MHz
fXT2,HF1
XT2 oscillator crystal
frequency, mode 1
XT2DRIVEx = 1, XT2BYPASS = 0 (3)
8
16
MHz
fXT2,HF2
XT2 oscillator crystal
frequency, mode 2
XT2DRIVEx = 2, XT2BYPASS = 0 (3)
16
24
MHz
fXT2,HF3
XT2 oscillator crystal
frequency, mode 3
XT2DRIVEx = 3, XT2BYPASS = 0 (3)
24
32
MHz
fXT2,HF,SW
XT2 oscillator logic-level
square-wave input
frequency, bypass mode
XT2BYPASS = 1 (4)
1.5
32
MHz
OAHF
tSTART,HF
CL,eff
Oscillation allowance for
HF crystals (5)
Startup time
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
XT2DRIVEx = 0, XT2BYPASS = 0,
fXT2,HF0 = 6 MHz, CL,eff = 15 pF
450
XT2DRIVEx = 1, XT2BYPASS = 0,
fXT2,HF1 = 12 MHz, CL,eff = 15 pF
320
XT2DRIVEx = 2, XT2BYPASS = 0,
fXT2,HF2 = 20 MHz, CL,eff = 15 pF
200
XT2DRIVEx = 3, XT2BYPASS = 0,
fXT2,HF3 = 32 MHz, CL,eff = 15 pF
200
fOSC = 6 MHz, XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C, CL,eff = 15 pF
fOSC = 20 MHz, XT2BYPASS = 0, XT2DRIVEx = 2,
TA = 25°C, CL,eff = 15 pF
Ω
0.5
3.0 V
ms
0.3
Integrated effective load
capacitance,
HF mode (6) (7)
Duty cycle
fFault,HF
(3)
1
Measured at ACLK, fXT2,HF2 = 20 MHz
Oscillator fault
frequency (8)
XT2BYPASS = 1
(9)
40
30
50
pF
60
%
300
kHz
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
To improve EMI on the XT2 oscillator the following guidelines should be observed.
(a) Keep the traces between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
(d) Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device
operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.
When XT2BYPASS is set, the XT2 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined
in the Schmitt-trigger Inputs section of this datasheet.
Oscillation allowance is based on a safety factor of 5 for recommended crystals.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
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Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fVLO
VLO frequency
Measured at ACLK
1.8 V to 3.6 V
dfVLO/dT
VLO frequency temperature drift
Measured at ACLK (1)
1.8 V to 3.6 V
Measured at ACLK (2)
1.8 V to 3.6 V
Measured at ACLK
1.8 V to 3.6 V
dfVLO/dVCC VLO frequency supply voltage drift
Duty cycle
(1)
(2)
MIN
TYP
MAX
6
9.4
14
0.5
kHz
%/°C
4
40
UNIT
%/V
50
60
TYP
MAX
%
Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)
Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IREFO
fREFO
TEST CONDITIONS
VCC
MIN
REFO oscillator current consumption TA = 25°C
1.8 V to 3.6 V
3
REFO frequency calibrated
Measured at ACLK
1.8 V to 3.6 V
32768
Full temperature range
1.8 V to 3.6 V
REFO absolute tolerance calibrated
TA = 25°C
µA
Hz
±3.5
3V
UNIT
±1.5
%
%
dfREFO/dT
REFO frequency temperature drift
Measured at ACLK (1)
1.8 V to 3.6 V
0.01
%/°C
dfREFO/dVCC
REFO frequency supply voltage drift
Measured at ACLK (2)
1.8 V to 3.6 V
1.0
%/V
Measured at ACLK
1.8 V to 3.6 V
40%/60% duty cycle
1.8 V to 3.6 V
Duty cycle
tSTART
(1)
(2)
58
REFO startup time
40
50
25
60
%
µs
Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)
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DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fDCO(0,0)
DCO frequency (0, 0)
DCORSELx = 0, DCOx = 0, MODx = 0
0.07
0.20
MHz
fDCO(0,31)
DCO frequency (0, 31)
DCORSELx = 0, DCOx = 31, MODx = 0
0.70
1.70
MHz
fDCO(1,0)
DCO frequency (1, 0)
DCORSELx = 1, DCOx = 0, MODx = 0
0.15
0.36
MHz
fDCO(1,31)
DCO frequency (1, 31)
DCORSELx = 1, DCOx = 31, MODx = 0
1.47
3.45
MHz
fDCO(2,0)
DCO frequency (2, 0)
DCORSELx = 2, DCOx = 0, MODx = 0
0.32
0.75
MHz
fDCO(2,31)
DCO frequency (2, 31)
DCORSELx = 2, DCOx = 31, MODx = 0
3.17
7.38
MHz
fDCO(3,0)
DCO frequency (3, 0)
DCORSELx = 3, DCOx = 0, MODx = 0
0.64
1.51
MHz
fDCO(3,31)
DCO frequency (3, 31)
DCORSELx = 3, DCOx = 31, MODx = 0
6.07
14.0
MHz
fDCO(4,0)
DCO frequency (4, 0)
DCORSELx = 4, DCOx = 0, MODx = 0
1.3
3.2
MHz
fDCO(4,31)
DCO frequency (4, 31)
DCORSELx = 4, DCOx = 31, MODx = 0
12.3
28.2
MHz
fDCO(5,0)
DCO frequency (5, 0)
DCORSELx = 5, DCOx = 0, MODx = 0
2.5
6.0
MHz
fDCO(5,31)
DCO frequency (5, 31)
DCORSELx = 5, DCOx = 31, MODx = 0
23.7
54.1
MHz
fDCO(6,0)
DCO frequency (6, 0)
DCORSELx = 6, DCOx = 0, MODx = 0
4.6
10.7
MHz
fDCO(6,31)
DCO frequency (6, 31)
DCORSELx = 6, DCOx = 31, MODx = 0
39.0
88.0
MHz
fDCO(7,0)
DCO frequency (7, 0)
DCORSELx = 7, DCOx = 0, MODx = 0
8.5
19.6
MHz
fDCO(7,31)
DCO frequency (7, 31)
DCORSELx = 7, DCOx = 31, MODx = 0
60
135
MHz
SDCORSEL
Frequency step between range
DCORSEL and DCORSEL + 1
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)
1.2
2.3
ratio
SDCO
Frequency step between tap
DCO and DCO + 1
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)
1.02
1.12
ratio
Duty cycle
Measured at SMCLK
40
50
60
%
dfDCO/dT
DCO frequency temperature drift
fDCO = 1 MHz,
0.1
%/°C
dfDCO/dVCC
DCO frequency voltage drift
fDCO = 1 MHz
1.9
%/V
Typical DCO Frequency, VCC = 3.0 V, TA = 25°C
100
fDCO – MHz
10
DCOx = 31
1
0.1
DCOx = 0
0
1
2
3
4
5
6
7
DCORSEL
Figure 10. Typical DCO frequency
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PMM, Brown-Out Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V(DVCC_BOR_IT–)
BORH on voltage,
DVCC falling level
| dDVCC/dt | < 3 V/s
V(DVCC_BOR_IT+)
BORH off voltage,
DVCC rising level
| dDVCC/dt | < 3 V/s
V(DVCC_BOR_hys)
BORH hysteresis
tRESET
Pulse length required at
RST/NMI pin to accept a
reset
MIN
0.80
TYP
1.30
60
MAX
UNIT
1.45
V
1.50
V
250
mV
2
µs
PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCORE3(AM)
Core voltage, active mode,
PMMCOREV = 3
2.4 V ≤ DVCC ≤ 3.6 V
1.90
V
VCORE2(AM)
Core voltage, active mode,
PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V
1.80
V
VCORE1(AM)
Core voltage, active mode,
PMMCOREV = 1
2.0 V ≤ DVCC ≤ 3.6 V
1.60
V
VCORE0(AM)
Core voltage, active mode,
PMMCOREV = 0
1.8 V ≤ DVCC ≤ 3.6 V
1.40
V
VCORE3(LPM)
Core voltage, low-current mode,
PMMCOREV = 3
2.4 V ≤ DVCC ≤ 3.6 V
1.94
V
VCORE2(LPM)
Core voltage, low-current mode,
PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V
1.84
V
VCORE1(LPM)
Core voltage, low-current mode,
PMMCOREV = 1
2.0 V ≤ DVCC ≤ 3.6 V
1.64
V
VCORE0(LPM)
Core voltage, low-current mode,
PMMCOREV = 0
1.8 V ≤ DVCC ≤ 3.6 V
1.44
V
60
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PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVSHE = 0, DVCC = 3.6 V
I(SVSH)
V(SVSH_IT–)
V(SVSH_IT+)
tpd(SVSH)
t(SVSH)
dVDVCC/dt
(1)
SVS current consumption
SVSH on voltage level (1)
SVSH off voltage level (1)
SVSH propagation delay
SVSH on/off delay time
TYP
MAX
0
UNIT
nA
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0
200
nA
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1
1.5
µA
SVSHE = 1, SVSHRVL = 0
1.57
1.68
1.78
SVSHE = 1, SVSHRVL = 1
1.79
1.88
1.98
SVSHE = 1, SVSHRVL = 2
1.98
2.08
2.21
SVSHE = 1, SVSHRVL = 3
2.10
2.18
2.31
SVSHE = 1, SVSMHRRL = 0
1.62
1.74
1.85
SVSHE = 1, SVSMHRRL = 1
1.88
1.94
2.07
SVSHE = 1, SVSMHRRL = 2
2.07
2.14
2.28
SVSHE = 1, SVSMHRRL = 3
2.20
2.30
2.42
SVSHE = 1, SVSMHRRL = 4
2.32
2.40
2.55
SVSHE = 1, SVSMHRRL = 5
2.52
2.70
2.88
SVSHE = 1, SVSMHRRL = 6
2.90
3.10
3.23
SVSHE = 1, SVSMHRRL = 7
2.90
3.10
3.23
SVSHE = 1, dVDVCC/dt = 10 mV/µs,
SVSHFP = 1
2.5
SVSHE = 1, dVDVCC/dt = 1 mV/µs,
SVSHFP = 0
20
V
µs
SVSHE = 0 → 1
SVSHFP = 1
12.5
SVSHE = 0 → 1
SVSHFP = 0
100
DVCC rise time
V
µs
0
1000
V/s
The SVSH settings available depend on the VCORE (PMMCOREVx) setting. Please refer to the Power Management Module and Supply
Voltage Supervisor chapter in the MSP430x5xx Family User's Guide (SLAU208) on recommended settings and usage.
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PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
SVMHE = 0, DVCC = 3.6 V
I(SVMH)
SVMH current consumption
V(SVMH)
SVMH on/off voltage level
(1)
0
t(SVMH)
(1)
SVMH propagation delay
SVMH on/off delay time
UNIT
nA
SVMHE= 1, DVCC = 3.6 V, SVMHFP = 0
200
nA
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1
1.5
µA
SVMHE = 1, SVSMHRRL = 0
1.62
1.74
1.85
SVMHE = 1, SVSMHRRL = 1
1.88
1.94
2.07
SVMHE = 1, SVSMHRRL = 2
2.07
2.14
2.28
SVMHE = 1, SVSMHRRL = 3
2.20
2.30
2.42
SVMHE = 1, SVSMHRRL = 4
2.32
2.40
2.55
SVMHE = 1, SVSMHRRL = 5
2.52
2.70
2.88
SVMHE = 1, SVSMHRRL = 6
2.90
3.10
3.23
SVMHE = 1, SVSMHRRL = 7
2.90
3.10
3.23
SVMHE = 1, SVMHOVPE = 1
tpd(SVMH)
MAX
V
3.75
SVMHE = 1, dVDVCC/dt = 10 mV/µs,
SVMHFP = 1
2.5
SVMHE = 1, dVDVCC/dt = 1 mV/µs,
SVMHFP = 0
20
µs
SVMHE = 0 → 1
SVMHFP = 1
12.5
SVMHE = 0 → 1
SVMHFP = 0
100
µs
The SVMH settings available depend on the VCORE (PMMCOREVx) setting. Please refer to the Power Management Module and
Supply Voltage Supervisor chapter in the MSP430x5xx Family User's Guide (SLAU208) on recommended settings and usage.
PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVSLE = 0, PMMCOREV = 2
I(SVSL)
SVSL current consumption
tpd(SVSL)
t(SVSL)
62
SVSL propagation delay
SVSL on/off delay time
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TYP
0
MAX
UNIT
nA
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
200
nA
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
1.5
µA
SVSLE = 1, dVCORE/dt = 10 mV/µs,
SVSLFP = 1
2.5
SVSLE = 1, dVCORE/dt = 1 mV/µs,
SVSLFP = 0
20
µs
SVSLE = 0 → 1
SVSLFP = 1
12.5
SVSLE = 0 → 1
SVSLFP = 0
100
µs
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PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
SVMLE = 0, PMMCOREV = 2
I(SVML)
tpd(SVML)
t(SVML)
SVML current consumption
SVML propagation delay
SVML on/off delay time
MAX
0
UNIT
nA
SVMLE= 1, PMMCOREV = 2, SVMLFP = 0
200
nA
SVMLE= 1, PMMCOREV = 2, SVMLFP = 1
1.5
µA
SVMLE = 1, dVCORE/dt = 10 mV/µs,
SVMLFP = 1
2.5
SVMLE = 1, dVCORE/dt = 1 mV/µs,
SVMLFP = 0
20
µs
SVMLE = 0 → 1
SVMLFP = 1
12.5
SVMLE = 0 → 1
SVMLFP = 0
100
µs
Wake-up from Low Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
fMCLK < 4.0 MHz
6
tWAKE-UP-FAST
tWAKE-UP-SLOW
Wake-up time from LPM2,
LPM3 or LPM4 to active
mode (2)
PMMCOREV = SVSMLRRL = n, where n = 0, 1, 2,
or 3
SVSLFP = 0
tWAKE-UP-LPM5
tWAKE-UP-RESET
(2)
(3)
MAX
5
PMMCOREV = SVSMLRRL = n,
where n = 0, 1, 2, or 3
SVSLFP = 1
(1)
TYP
fMCLK ≥ 4.0 MHz
Wake-up time from LPM2,
LPM3, or LPM4 to active
mode (1)
UNIT
µs
150
165
µs
Wake-up time from LPM4.5 to
active mode (3)
2
3
ms
Wake-up time from RST or
BOR event to active mode (3)
2
3
ms
This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVSL) and low side monitor (SVML). Fastest wakeup times are possible with SVSLand SVML in full
performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while
operating in LPM2, LPM3, and LPM4. Please refer to the Power Management Module and Supply Voltage Supervisor chapter in the
MSP430x5xx Family User's Guide (SLAU208).
This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVSL) and low side monitor (SVML). In this case, the SVSLand SVML are in normal mode (low current)
mode when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while operating in LPM2, LPM3, and
LPM4. Please refer to the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx Family User's Guide
(SLAU208).
This value represents the time from the wakeup event to the reset vector execution.
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Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fTA
Timer_A input clock frequency
Internal: SMCLK, ACLK
External: TACLK
Duty cycle = 50% ± 10%
1.8 V/
3.0 V
tTA,cap
Timer_A capture timing
All capture inputs.
Minimum pulse width required for
capture.
1.8 V/
3.0 V
MIN
TYP
MAX
UNIT
25
MHz
20
ns
Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fTB
Timer_B input clock frequency
Internal: SMCLK, ACLK
External: TBCLK
Duty cycle = 50% ± 10%
1.8 V/
3.0 V
tTB,cap
Timer_B capture timing
All capture inputs.
Minimum pulse width required for
capture.
1.8 V/
3.0 V
MIN
TYP
MAX
UNIT
25
MHz
20
ns
USCI (UART Mode) - recommended operating conditions
PARAMETER
fUSCI
USCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
MAX
UNIT
fSYSTEM
MHz
1
MHz
MAX
UNIT
USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tt
(1)
64
UART receive deglitch time (1)
TEST CONDITIONS
VCC
MIN
2.2 V
50
TYP
600
3V
50
600
ns
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
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USCI (SPI Master Mode) - recommended operating conditions
PARAMETER
fUSCI
CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
Duty cycle = 50% ± 10%
USCI input clock frequency
MAX
UNIT
fSYSTEM
MHz
MAX
UNIT
fSYSTEM
MHz
USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note (1), Figure 11 and Figure 12)
PARAMETER
fUSCI
TEST CONDITIONS
VCC
SMCLK, ACLK
Duty cycle = 50% ± 10%
USCI input clock frequency
PMMCOREV = 0
tSU,MI
SOMI input data setup time
PMMCOREV = 3
PMMCOREV = 0
tHD,MI
SOMI input data hold time
PMMCOREV = 3
tVALID,MO
tHD,MO
(1)
(2)
(3)
SIMO output data valid time
MIN
(2)
SIMO output data hold time (3)
1.8 V
55
3.0 V
38
2.4 V
30
3.0 V
25
1.8 V
0
3.0 V
0
2.4 V
0
3.0 V
0
TYP
ns
ns
ns
ns
UCLK edge to SIMO valid,
CL = 20 pF
PMMCOREV = 0
1.8 V
20
3.0 V
18
UCLK edge to SIMO valid,
CL = 20 pF
PMMCOREV = 3
2.4 V
16
3.0 V
15
CL = 20 pF
PMMCOREV = 0
1.8 V
-10
3.0 V
-8
CL = 20 pF
PMMCOREV = 3
2.4 V
-10
3.0 V
-8
ns
ns
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) refer to the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 11 and Figure 12.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams in
Figure 11 and Figure 12.
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 11. SPI Master Mode, CKPH = 0
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1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tHD,MI
tSU,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 12. SPI Master Mode, CKPH = 1
66
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USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note (1), Figure 13 and Figure 14)
PARAMETER
TEST CONDITIONS
PMMCOREV = 0
tSTE,LEAD
STE lead time, STE low to clock
PMMCOREV = 3
PMMCOREV = 0
tSTE,LAG
STE lag time, Last clock to STE high
PMMCOREV = 3
PMMCOREV = 0
tSTE,ACC
STE access time, STE low to SOMI data out
PMMCOREV = 3
PMMCOREV = 0
tSTE,DIS
STE disable time, STE high to SOMI high
impedance
PMMCOREV = 3
PMMCOREV = 0
tSU,SI
SIMO input data setup time
PMMCOREV = 3
PMMCOREV = 0
tHD,SI
SIMO input data hold time
PMMCOREV = 3
tVALID,SO
tHD,SO
(1)
(2)
(3)
SOMI output data valid time
(2)
SOMI output data hold time (3)
VCC
MIN
1.8 V
11
3.0 V
8
2.4 V
7
3.0 V
6
1.8 V
3
3.0 V
3
2.4 V
3
3.0 V
3
TYP
MAX
ns
ns
ns
ns
1.8 V
66
3.0 V
50
2.4 V
36
3.0 V
30
1.8 V
30
3.0 V
23
2.4 V
16
3.0 V
13
1.8 V
5
3.0 V
5
2.4 V
2
3.0 V
2
1.8 V
5
3.0 V
5
2.4 V
5
3.0 V
5
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
UCLK edge to SOMI valid,
CL = 20 pF
PMMCOREV = 0
1.8 V
76
3.0 V
60
UCLK edge to SOMI valid,
CL = 20 pF
PMMCOREV = 3
2.4 V
44
3.0 V
40
CL = 20 pF
PMMCOREV = 0
1.8 V
18
3.0 V
12
CL = 20 pF
PMMCOREV = 3
2.4 V
10
3.0 V
8
ns
ns
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).
For the master's parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 11 and Figure 12.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams in
Figure 11 and Figure 12.
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tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tSU,SI
tLO/HI
tHD,SI
SIMO
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
SOMI
Figure 13. SPI Slave Mode, CKPH = 0
tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tHD,SI
tSU,SI
SIMO
tSTE,ACC
tHD,MO
tVALID,SO
tSTE,DIS
SOMI
Figure 14. SPI Slave Mode, CKPH = 1
68
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USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 15)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
MAX
UNIT
fSYSTEM
MHz
400
kHz
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2.2 V/3 V
0
ns
tSU,DAT
Data setup time
2.2 V/3 V
250
ns
2.2 V/3 V
fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
tSU,STO
Setup time for STOP
tSP
Pulse width of spikes suppressed by input filter
fSCL > 100 kHz
tSU,STA
tHD,STA
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
0
4.0
µs
0.6
4.7
µs
0.6
4.0
µs
0.6
2.2 V
50
600
3V
50
600
tHD,STA
ns
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 15. I2C Mode Timing
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12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
AVCC
Analog supply voltage
Full performance
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
V(Ax)
Analog input voltage range (2)
All ADC12 analog input pins Ax
IADC12_A
Operating supply current into
AVCC terminal (3)
fADC12CLK = 5.0 MHz, ADC12ON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADC12DIV = 0
CI
Input capacitance
Only one terminal Ax can be selected at one
time
RI
Input MUX ON resistance
0 V ≤ VAx ≤ AVCC
(1)
(2)
(3)
VCC
MIN
TYP
MAX
UNIT
2.2
3.6
V
0
AVCC
V
2.2 V
125
155
3V
150
220
2.2 V
20
25
pF
200
1900
Ω
10
µA
The leakage current is specified by the digital I/O input leakage.
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. If the
reference voltage is supplied by an external source or if the internal reference voltage is used and REFOUT = 1, then decoupling
capacitors are required. See REF, External Reference andREF, Built-In Reference.
The internal reference supply current is not included in current consumption parameter IADC12_A.
12-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fADC12CLK
fADC12OSC
tCONVERT
tSample
(1)
(2)
(3)
Internal ADC12
oscillator (1)
Conversion time
Sampling time
VCC
MIN
TYP
MAX
UNIT
For specified performance of ADC12 linearity
parameters
TEST CONDITIONS
2.2 V/3 V
0.45
4.8
5.4
MHz
ADC12DIV = 0, fADC12CLK = fADC12OSC
2.2 V/3 V
4.2
4.8
5.4
MHz
REFON = 0, Internal oscillator,
fADC12OSC = 4.2 MHz to 5.4 MHz
2.2 V/3 V
2.4
µs
External fADC12CLK from ACLK, MCLK or SMCLK,
ADC12SSEL ≠ 0
RS = 400 Ω, RI = 1000 Ω, CI = 20 pF,
t = [RS + RI] × CI (3)
3.1
(2)
2.2 V/3 V
1000
ns
The ADC12OSC is sourced directly from MODOSC inside the UCS.
13 × ADC12DIV × 1/fADC12CLK
Approximately ten Tau (t) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) x (RS + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance
12-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
EI
Integral
linearity error (INL)
1.4 V ≤ (VeREF+ – VREF–/VeREF–)min ≤ 1.6 V
ED
Differential
linearity error (DNL)
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ = 20 pF
2.2 V/3 V
EO
Offset error
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
Internal impedance of source RS < 100 Ω, CVREF+ = 20 pF
2.2 V/3 V
EG
Gain error
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ = 20 pF
ET
Total unadjusted
error
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ = 20 pF
70
1.6 V < (VeREF+ – VREF–/VeREF–)min ≤ VAVCC
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MIN
TYP
MAX
±2
2.2 V/3 V
±1.7
UNIT
LSB
±1.0
LSB
±1.0
±2.0
LSB
2.2 V/3 V
±1.0
±2.0
LSB
2.2 V/3 V
±1.4
±3.5
LSB
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12-Bit ADC, Temperature Sensor and Built-In VMID
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VSENSOR
See
TEST CONDITIONS
ADC12ON = 1, INCH = 0Ah,
TA = 0°C
(2)
TCSENSOR
tSENSOR(sample)
ADC12ON = 1, INCH = 0Ah
Sample time required if
channel 10 is selected (3)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
AVCC divider at channel 11,
VAVCC factor
ADC12ON = 1, INCH = 0Bh
AVCC divider at channel 11
ADC12ON = 1, INCH = 0Bh
Sample time required if
channel 11 is selected (4)
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
VMID
tVMID(sample)
(1)
(2)
(3)
(4)
VCC
MIN
TYP
2.2 V
680
3V
680
2.2 V
2.25
3V
2.25
2.2 V
30
3V
30
MAX
UNIT
mV
mV/°C
µs
0.48
0.5
0.52 VAVCC
2.2 V
1.06
1.1
1.14
3V
1.44
1.5
1.56
2.2 V/3 V
1000
V
ns
The temperature sensor is provided by the REF module. Please refer to the REF module parametric, IREF+, regarding the current
consumption of the temperature sensor.
The temperature sensor offset can be as much as ±20°C. A single-point calibration is recommended in order to minimize the offset error
of the built-in temperature sensor. The TLV structure contains calibration values for 30°C ± 3°C and 85°C ± 3°C for each of the available
reference voltage levels. The sensor voltage can be computed as VSENSE = TCSENSOR * (Temperature,°C) + VSENSOR, where TCSENSOR
and VSENSOR can be computed from the calibration values for higher accuracy. See also the MSP430x5xx Family User's Guide
(SLAU208).
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
Typical Temperature Sensor Voltage - mV
1000
950
900
850
800
750
700
650
600
550
500
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
Ambient Temperature - ˚C
Figure 16. Typical Temperature Sensor Voltage
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REF, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VeREF+
Positive external reference
voltage input
VeREF+ > VREF–/VeREF–
(2)
1.4
AVCC
V
VREF–/VeREF–
Negative external reference
voltage input
VeREF+ > VREF–/VeREF–
(3)
0
1.2
V
(VeREF+ –
VREF–/VeREF–)
Differential external reference
voltage input
VeREF+ > VREF–/VeREF–
(4)
1.4
AVCC
V
±26
µA
±1
µA
IVeREF+,
IVREF–/VeREF–
CVREF+/(1)
(2)
(3)
(4)
(5)
Static input current
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0
V, fADC12CLK = 5 MHz,
ADC12SHTx = 1h,
Conversion rate 200ksps
2.2 V/3 V
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0
V, fADC12CLK = 5 MHz,
ADC12SHTx = 8h,
Conversion rate 20ksps
2.2 V/3 V
±8.5
(5)
Capacitance at VREF+/- terminal
10
µF
The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
Two decoupling capacitors, 10µF and 100nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC12_A. See also the MSP430x5xx Family User's Guide (SLAU208).
REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
Positive built-in reference
voltage output
VREF+
AVCC(min)
IREF+
(1)
(2)
(3)
72
AVCC minimum voltage,
Positive built-in reference
active
Operating supply current into
AVCC terminal (2) (3)
TEST CONDITIONS
TYP
MAX
3V
2.50
±1.5%
REFVSEL = {1} for 2.0 V
REFON = REFOUT = 1
IVREF+= 0 A
3V
1.98
±1.5%
REFVSEL = {0} for 1.5 V
REFON = REFOUT = 1
IVREF+= 0 A
2.2 V/ 3 V
1.49
±1.5%
REFVSEL = {2} for 2.5 V
REFON = REFOUT = 1
IVREF+= 0 A
VCC
MIN
REFVSEL = {0} for 1.5 V, reduced
performance
1.8
REFVSEL = {0} for 1.5 V
2.2
REFVSEL = {1} for 2.0 V
2.3
REFVSEL = {2} for 2.5 V
2.8
UNIT
V
V
REFON = 1, REFOUT = 0, REFBURST = 0
3V
100
140
µA
REFON = 1, REFOUT = 1, REFBURST = 0
3V
0.9
1.5
mA
The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers, one
smaller and one larger for driving the VREF+ terminal. When REFOUT = 1, the reference is available at the VREF+ terminal, as well as,
used as the reference for the conversion and utilizes the larger buffer. When REFOUT = 0, the reference is only used as the reference
for the conversion and utilizes the smaller buffer.
The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. REFOUT = 0 represents the current contribution of the smaller buffer. REFOUT = 1 represents the current
contribution of the larger buffer without external load.
The temperature sensor is provided by the REF module. Its current is supplied via terminal AVCC and is equivalent to IREF+ with REFON
=1 and REFOUT = 0.
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REF, Built-In Reference (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
IL(VREF+)
Load-current regulation,
VREF+ terminal (4)
REFVSEL = (0, 1, 2}
IVREF+ = +10 µA/–1000 µA
AVCC = AVCC (min) for each reference level.
REFVSEL = (0, 1, 2}, REFON = REFOUT = 1
CVREF+/-
Capacitance at VREF+/terminals
REFON = REFOUT = 1 (5)
TCREF+
Temperature coefficient of
built-in reference (6)
IVREF+ = 0 A
REFVSEL = (0, 1, 2}, REFON = 1,
REFOUT = 0 or 1
PSRR_DC
Power supply rejection ratio
(DC)
PSRR_AC
Power supply rejection ratio
(AC)
tSETTLE
(4)
(5)
(6)
(7)
Settling time of reference
voltage (7)
VCC
MIN
TYP
MAX
UNIT
2500 µV/mA
20
100
pF
30
50
ppm/°
C
AVCC = AVCC (min) - AVCC(max)
TA = 25°C
REFVSEL = (0, 1, 2}, REFON = 1,
REFOUT = 0 or 1
120
300
µV/V
AVCC = AVCC (min) - AVCC(max)
TA = 25°C
f = 1 kHz, ΔVpp = 100 mV
REFVSEL = (0, 1, 2}, REFON = 1,
REFOUT = 0 or 1
6.4
AVCC = AVCC (min) - AVCC(max)
REFVSEL = (0, 1, 2}, REFOUT = 0,
REFON = 0 → 1
75
AVCC = AVCC (min) - AVCC(max)
CVREF = CVREF(max)
REFVSEL = (0, 1, 2}, REFOUT = 1,
REFON = 0 → 1
75
mV/V
µs
Contribution only due to the reference and buffer including package. This does not include resistance due to PCB trace, etc.
Two decoupling capacitors, 10µF and 100nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC12_A. See also the MSP430x5xx Family User's Guide (SLAU208).
Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C)/(85°C – (–40°C)).
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load when REFOUT = 1.
Comparator B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
TEST CONDITIONS
VCC
Supply voltage
MIN
TYP
1.8
3.6
1.8 V
IAVCC_COMP
Comparator operating supply
current into AVCC. Excludes
reference resistor ladder.
IAVCC_REF
Quiescent current of local
reference voltage amplifier into
AVCC.
VIC
Common mode input range
VOFFSET
Input offset voltage
CIN
Input capacitance
CBPWRMD = 00
MAX
UNIT
V
40
2.2 V
30
50
3.0 V
40
65
CBPWRMD = 01
2.2/3.0 V
10
30
CBPWRMD = 10
2.2/3.0 V
0.1
0.5
CBREFACC = 1, CBREFLx = 01
22
0
VCC-1
µA
µA
V
CBPWRMD = 00
±20
mV
CBPWRMD = 01, 10
±10
mV
4
kΩ
5
ON - switch closed
3
pF
RSIN
Series input resistance
CBPWRMD = 00, CBF = 0
450
tPD
Propagation delay, response time CBPWRMD = 01, CBF = 0
600
ns
CBPWRMD = 10, CBF = 0
50
µs
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OFF - switch opened
30
MΩ
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Comparator B (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Propagation delay with filter
active
tPD,filter
VCC
MIN
TYP
MAX
UNIT
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 00
0.35
0.6
1.0
µs
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 01
0.6
1.0
1.8
µs
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 10
1.0
1.8
3.4
µs
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 11
1.8
3.4
6.5
µs
tEN_CMP
Comparator enable time, settling
time
CBON = 0 to CBON = 1
CBPWRMD = 00, 01, 10
1
2
µs
tEN_REF
Resistor reference enable time
CBON = 0 to CBON = 1
0.3
1.5
µs
VCB_REF
Reference voltage for a given tap
VIN = reference into resistor ladder.
n = 0 to 31
VIN*(n
+1)
/32
V
Ports PU.0 and PU.1
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
VUSB = 3.3 V ± 10%, IOH = -25 mA
VOL
Low-level output voltage
VUSB = 3.3 V ± 10%, IOL = 25 mA
VIH
High-level input voltage
VUSB = 3.3 V ± 10%
VIL
Low-level input voltage
VUSB = 3.3 V ± 10%
VCC
MIN
TYP
MAX
2.4
UNIT
V
0.4
2.0
V
V
0.8
V
MAX
UNIT
USB-Output Ports DP and DM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
VOH
D+, D- single ended
USB 2.0 load conditions
2.8
3.6
VOL
D+, D- single ended
USB 2.0 load conditions
0
0.3
V
V
Z(DRV)
D+, D- impedance
Including external series resistor of 27 Ω
28
44
Ω
tRISE
Rise time
Full speed, differential, CL = 50 pF,
10%/90%, Rpu on D+
4
20
ns
tFALL
Fall time
Full speed, differential, CL = 50 pF,
10%/90%, Rpu on D+
4
20
ns
USB-Input Ports DP and DM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
Differential input common mode range
0.8
Z(IN)
Input impedance
300
VCRS
Crossover voltage
1.3
VIL
Static SE input logic low level
0.8
VIH
Static SE input logic high level
2.0
V
VDI
Differential input voltage
0.2
V
74
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2.5
UNIT
V(CM)
V
kΩ
2.0
V
V
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USB-PWR (USB Power System)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
VLAUNCH
VBUS detection threshold
VBUS
USB bus voltage
VUSB
USB LDO output voltage
3.3
V18
Internal USB voltage (1)
1.8
IUSB_EXT
Maximum external current from VUSB
terminal (2)
Normal operation
3.76
USB LDO is on
(3)
UNIT
3.75
V
5.5
V
±9%
V
V
12
mA
100
mA
250
µA
IDET
USB LDO current overload detection
ISUSPEND
Operating supply current into VBUS terminal. (4)
CBUS
VBUS terminal recommended capacitance
4.7
µF
CUSB
VUSB terminal recommended capacitance
220
nF
C18
V18 terminal recommended capacitance
220
nF
tENABLE
Settling time VUSB and V18
RPUR
Pullup resistance of PUR terminal
(1)
(2)
(3)
(4)
60
MAX
USB LDO is on,
USB PLL disabled
Within 2%,
recommended capacitances
70
110
2
ms
150
Ω
This voltage is for internal usages only. No external DC loading should be applied.
This represents additional current that can be supplied to the application from the VUSB terminal beyond the needs of the USB
operation.
A current overload will be detected when the total current supplied from the USB LDO, including IUSB_EXT, exceeds this value.
Does not include current contribution of Rpu and Rpd as outlined in the USB specification.
USB-PLL (USB Phase Locked Loop)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IPLL
Operating supply current
fPLL
PLL frequency
fUPD
PLL reference frequency
tLOCK
PLL lock time
tJitter
PLL jitter
Copyright © 2009–2010, Texas Instruments Incorporated
TEST CONDITIONS
VCC
MIN
TYP
MAX
7
48
1.5
UNIT
mA
MHz
3
MHz
2
ms
1000
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Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
DVCC(PGM/ERASE) Program and erase supply voltage
IPGM
Average supply current from DVCC during program
IERASE
Average supply current from DVCC during erase
IMERASE, IBANK
Average supply current from DVCC during mass erase or bank erase
tCPT
Cumulative program time
MIN
TYP
1.8
3.6
3
See
(1)
UNIT
V
5
mA
2
mA
2
mA
16
104
Program/erase endurance
MAX
105
ms
cycles
tRetention
Data retention duration
TJ = 25°C
tWord
Word or byte program time
See
(2)
64
85
µs
tBlock,
0
Block program time for first byte or word
See
(2)
49
65
µs
1–(N–1)
Block program time for each additional byte or word, except for last
byte or word
See
(2)
37
49
µs
Block program time for last byte or word
See
(2)
55
73
µs
tErase
Erase time for segment, mass erase, and bank erase when
available.
See
(2)
23
32
ms
fMCLK,MGR
MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)
0
1
MHz
tBlock,
tBlock,
(1)
(2)
N
100
years
The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
These values are hardwired into the flash controller's state machine.
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V/3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse length
2.2 V/3 V
0.025
15
µs
tSBW,
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
edge) (1)
2.2 V/3 V
1
µs
En
tSBW,Rst
Spy-Bi-Wire return to normal operation time
fTCK
TCK input frequency - 4-wire JTAG (2)
Rinternal
Internal pulldown resistance on TEST
(1)
(2)
76
2.2 V
15
100
0
5
MHz
10
MHz
80
kΩ
3V
0
2.2 V/3 V
45
60
µs
Tools accessing the Spy-Bi-Wire interface need to wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
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SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
INPUT/OUTPUT SCHEMATICS
Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
Pad Logic
P1REN.x
P1DIR.x
0
From module
1
P1OUT.x
0
From module
1
0
DVCC
1
1
Direction
0: Input
1: Output
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
EN
To module
DVSS
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/TA1CLK/CBOUT
P1.7/TA1.0
D
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
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Table 48. Port P1 (P1.0 to P1.7) Pin Functions
PIN NAME (P1.x)
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
x
0
1
2
3
4
FUNCTION
P1DIR.x
P1SEL.x
P1.0 (I/O)
I: 0; O: 1
0
TA0CLK
0
1
ACLK
1
1
I: 0; O: 1
0
TA0.CCI0A
0
1
TA0.0
1
1
I: 0; O: 1
0
TA0.CCI1A
0
1
TA0.1
1
1
I: 0; O: 1
0
TA0.CCI2A
0
1
TA0.2
1
1
I: 0; O: 1
0
0
1
P1.1 (I/O)
P1.2 (I/O)
P1.3 (I/O)
P1.4 (I/O)
TA0.CCI3A
TA0.3
P1.5/TA0.4
5
P1.5 (I/O)
TA0.CCI4A
TA0.4
P1.6/TA1CLK/CBOUT
6
78
7
1
1
I: 0; O: 1
0
0
1
1
1
P1.6 (I/O)
I: 0; O: 1
0
TA1CLK
0
1
CBOUT comparator B
P1.7/TA1.0
CONTROL BITS/SIGNALS
1
1
I: 0; O: 1
0
TA1.CCI0A
0
1
TA1.0
1
1
P1.7 (I/O)
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SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
Pad Logic
P2REN.x
P2DIR.x
0
From module
1
P2OUT.x
0
From module
1
0
DVCC
1
1
Direction
0: Input
1: Output
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
EN
To module
DVSS
P2.0/TA1.1
P2.1/TA1.2
P2.2/TA2CLK/SMCLK
P2.3/TA2.0
P2.4/TA2.1
P2.5/TA2.2
P2.6/RTCCLK/DMAE0
P2.7/UB0STE/UCA0CLK
D
P2IE.x
EN
To module
Q
P2IFG.x
P2SEL.x
P2IES.x
Set
Interrupt
Edge
Select
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Table 49. Port P2 (P2.0 to P2.7) Pin Functions
PIN NAME (P2.x)
P2.0/TA1.1
P2.1/TA1.2
P2.2/TA2CLK/SMCLK
P2.3/TA2.0
P2.4/TA2.1
x
0
1
2
3
4
FUNCTION
P2.0 (I/O)
0
0
1
TA1.1
1
1
I: 0; O: 1
0
TA1.CCI2A
0
1
TA1.2
1
1
P2.2 (I/O)
I: 0; O: 1
0
TA2CLK
0
1
SMCLK
1
1
I: 0; O: 1
0
TA2.CCI0A
0
1
TA2.0
1
1
I: 0; O: 1
0
0
1
P2.1 (I/O)
P2.3 (I/O)
P2.4 (I/O)
P2.5 (I/O)
TA2.CCI2A
TA2.2
P2.6/RTCCLK/DMAE0
6
7
80
1
0
0
1
1
1
0
0
1
RTCCLK
1
1
P2.7 (I/O)
I: 0; O: 1
0
X
1
UCB0STE/UCA0CLK (2)
(1)
(2)
(3)
1
I: 0; O: 1
I: 0; O: 1
P2.6 (I/O)
DMAE0
P2.7/UCB0STE/UCA0CLK
P2SEL.x
I: 0; O: 1
TA2.1
5
P2DIR.x
TA1.CCI1A
TA2.CCI1A
P2.5/TA2.2
CONTROL BITS/SIGNALS (1)
(3)
X = Don't care
The pin direction is controlled by the USCI module.
UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI A0/B0 is forced
to 3-wire SPI mode if 4-wire SPI mode is selected.
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SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
Pad Logic
P3REN.x
P3DIR.x
0
From module
1
P3OUT.x
0
From module
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P3.0/UCB0SIMO/UCB0SDA
P3.1/UCB0SOMI/UCB0SCL
P3.2/UCB0CLK/UCA0STE
P3.3/UCA0TXD/UCA0SIMO
P3.4/UCA0RXD/UCA0SOMI
P3.5/TB0.5
P3.6/TB0.6
P3.7/TB0OUTH/SVMOUT
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
EN
To module
D
Table 50. Port P3 (P3.0 to P3.7) Pin Functions
PIN NAME (P3.x)
x
P3.0/UCB0SIMO/UCB0SDA
0
FUNCTION
P3.0 (I/O)
UCB0SIMO/UCB0SDA
P3.1/UCB0SOMI/UCB0SCL
1
(2) (3)
P3.1 (I/O)
UCB0SOMI/UCB0SCL (2)
P3.2/UCB0CLK/UCA0STE
2
P3.2 (I/O)
UCB0CLK/UCA0STE
P3.3/UCA0TXD/UCA0SIMO
3
(2) (4)
4
P3.6/TB0.6 (5)
5
6
(1)
(2)
(3)
(4)
(5)
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
TB0.CCI5A
0
1
TB0.5
1
1
I: 0; O: 1
0
0
1
P3.4 (I/O)
P3.5 (I/O)
P3.6 (I/O)
TB0.6
7
0
1
TB0.CCI6A
P3.7/TB0OUTH/SVMOUT (5)
P3SEL.x
X
UCA0RXD/UCA0SOMI (2)
P3.5/TB0.5 (5)
P3DIR.x
I: 0; O: 1
I: 0; O: 1
P3.3 (I/O)
UCA0TXD/UCA0SIMO (2)
P3.4/UCA0RXD/UCA0SOMI
(3)
CONTROL BITS/SIGNALS (1)
1
1
P3.7 (I/O)
I: 0; O: 1
0
TB0OUTH
0
1
SVMOUT
1
1
X = Don't care
The pin direction is controlled by the USCI module.
If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI A0/B0 is forced
to 3-wire SPI mode if 4-wire SPI mode is selected.
'F5529, 'F5527, 'F5525, 'F5521, 'F5519, 'F5517, 'F5515 devices only.
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Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
Pad Logic
P4REN.x
P4DIR.x
0
from Port Mapping Control
1
P4OUT.x
0
from Port Mapping Control
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P4.0/P4MAP0
P4.1/P4MAP1
P4.2/P4MAP2
P4.3/P4MAP3
P4.4/P4MAP4
P4.5/P4MAP5
P4.6/P4MAP6
P4.7/P4MAP7
P4DS.x
0: Low drive
1: High drive
P4SEL.x
P4IN.x
EN
D
to Port Mapping Control
Table 51. Port P4 (P4.0 to P4.7) Pin Functions
PIN NAME (P4.x)
P4.0/P4MAP0
x
0
FUNCTION
P4.0 (I/O)
Mapped secondary digital function
P4.1/P4MAP1
1
P4.2/P4MAP2
2
P4.1 (I/O)
Mapped secondary digital function
P4.2 (I/O)
Mapped secondary digital function
P4.3/P4MAP3
3
P4.3 (I/O)
Mapped secondary digital function
P4.4/P4MAP4
4
P4.5/P4MAP5
5
P4.4 (I/O)
Mapped secondary digital function
P4.5 (I/O)
Mapped secondary digital function
P4.6/P4MAP6
6
P4.7/P4MAP7
7
P4.6 (I/O)
Mapped secondary digital function
P4.7 (I/O)
Mapped secondary digital function
(1)
82
CONTROL BITS/SIGNALS
P4DIR.x (1)
P4SEL.x
I: 0; O: 1
0
X
X
1
≤ 30
I: 0; O: 1
0
X
≤ 30
P4MAPx
X
1
I: 0; O: 1
0
X
X
1
≤ 30
I: 0; O: 1
0
X
X
1
≤ 30
I: 0; O: 1
0
X
≤ 30
X
1
I: 0; O: 1
0
X
X
1
≤ 30
I: 0; O: 1
0
X
≤ 30
X
1
I: 0; O: 1
0
X
X
1
≤ 30
The direction of some mapped secondary functions are controlled directly by the module. Please refer to Table 9 for specific direction
control information of mapped secondary functions.
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SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
Pad Logic
to/from Reference
(n/a MSP430F551x)
(n/a MSPF430F551x)
to ADC12
(n/a MSPF430F551x)
INCHx = x
P5REN.x
P5DIR.x
DVSS
0
DVCC
1
1
0
1
P5OUT.x
0
From module
1
P5.0/(A8/VREF+/VeREF+)
P5.1/(A9/VREF–/VeREF–)
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5IN.x
Bus
Keeper
EN
To module
D
Table 52. Port P5 (P5.0 and P5.1) Pin Functions
PIN NAME (P5.x)
P5.0/A8/VREF+/VeREF+ (2)
x
0
FUNCTION
P5.0 (I/O) (3)
A8/VeREF+ (4)
A8/VREF+
P5.1/A9/VREF–/VeREF– (6)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
1
(5)
CONTROL BITS/SIGNALS (1)
P5DIR.x
P5SEL.x
REFOUT
I: 0; O: 1
0
X
X
1
0
X
1
1
I: 0; O: 1
0
X
A9/VeREF– (7)
X
1
0
A9/VREF– (8)
X
1
1
P5.1 (I/O) (3)
X = Don't care
VREF+/VeREF+ available on MSP430F552x devices only.
Default condition
Setting the P5SEL.0 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC12_A when available. Channel A8,
when selected with the INCHx bits, is connected to the VREF+/VeREF+ pin.
Setting the P5SEL.0 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. The VREF+ reference is available at the pin. Channel A8, when selected with the INCHx bits, is connected to the
VREF+/VeREF+ pin.
VREF-/VeREF- available on MSP430F552x devices only.
Setting the P5SEL.1 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. An external voltage can be applied to VeREF- and used as the reference for the ADC12_A when available. Channel A9,
when selected with the INCHx bits, is connected to the VREF-/VeREF- pin.
Setting the P5SEL.1 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. The VREF– reference is available at the pin. Channel A9, when selected with the INCHx bits, is connected to the
VREF-/VeREF- pin.
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Port P5, P5.2, Input/Output With Schmitt Trigger
Pad Logic
To XT2
P5REN.2
P5DIR.2
DVSS
0
DVCC
1
1
0
1
P5OUT.2
0
Module X OUT
1
P5DS.2
0: Low drive
1: High drive
P5SEL.2
P5.2/XT2IN
P5IN.2
EN
Module X IN
84
Bus
Keeper
D
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SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
Port P5, P5.3, Input/Output With Schmitt Trigger
Pad Logic
To XT2
P5REN.3
P5DIR.3
DVSS
0
DVCC
1
1
0
1
P5OUT.3
0
Module X OUT
1
P5.3/XT2OUT
P5DS.3
0: Low drive
1: High drive
P5SEL.3
P5IN.3
Bus
Keeper
EN
Module X IN
D
Table 53. Port P5 (P5.2, P5.3) Pin Functions
PIN NAME (P5.x)
P5.2/XT2IN
P5.3/XT2OUT
(1)
(2)
(3)
x
2
3
FUNCTION
P5.2 (I/O)
CONTROL BITS/SIGNALS (1)
P5DIR.x
P5SEL.2
P5SEL.3
XT2BYPASS
I: 0; O: 1
0
X
X
XT2IN crystal mode (2)
X
1
X
0
XT2IN bypass mode (2)
X
1
X
1
I: 0; O: 1
0
X
X
XT2OUT crystal mode (3)
X
1
X
0
P5.3 (I/O) (3)
X
1
X
1
P5.3 (I/O)
X = Don't care
Setting P5SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P5.2 is configured for crystal
mode or bypass mode.
Setting P5SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.3 can be used as
general-purpose I/O.
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Port P5, P5.4 and P5.5 Input/Output With Schmitt Trigger
Pad Logic
to XT1
P5REN.4
P5DIR.4
DVSS
0
DVCC
1
1
0
1
P5OUT.4
0
Module X OUT
1
P5DS.4
0: Low drive
1: High drive
P5SEL.4
P5.4/XIN
P5IN.4
EN
Module X IN
86
Bus
Keeper
D
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Pad Logic
to XT1
P5REN.5
P5DIR.5
DVSS
0
DVCC
1
1
0
1
P5OUT.5
0
Module X OUT
1
P5.5/XOUT
P5DS.5
0: Low drive
1: High drive
P5SEL.5
XT1BYPASS
P5IN.5
Bus
Keeper
EN
Module X IN
D
Table 54. Port P5 (P5.4 and P5.5) Pin Functions
PIN NAME (P7.x)
P5.4/XIN
x
4
FUNCTION
P5DIR.x
P5SEL.4
P5SEL.5
XT1BYPASS
I: 0; O: 1
0
X
X
X
1
X
0
X
1
X
1
I: 0; O: 1
0
X
X
XOUT crystal mode (3)
X
1
X
0
P5.5 (I/O) (3)
X
1
X
1
P5.4 (I/O)
XIN crystal mode
(2)
XIN bypass mode (2)
P5.5/XOUT
(1)
(2)
(3)
5
CONTROL BITS/SIGNALS (1)
P5.5 (I/O)
X = Don't care
Setting P5SEL.4 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P5.4 is configured for crystal
mode or bypass mode.
Setting P5SEL.4 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.5 can be used as
general-purpose I/O.
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Port P5, P5.6 to P5.7, Input/Output With Schmitt Trigger
Pad Logic
P5REN.x
P5DIR.x
0
From Module
1
P5OUT.x
0
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
1
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5.6/TB0.0
P5.7/TB0.1
P5IN.x
EN
D
To module
Table 55. Port P5 (P5.6 to P5.7) Pin Functions
PIN NAME (P5.x)
P5.6/TB0.0
P5.7/TB0.1
(1)
88
(1)
(1)
x
6
7
FUNCTION
P5.6 (I/O)
CONTROL BITS/SIGNALS
P5DIR.x
P5SEL.x
I: 0; O: 1
0
TB0.CCI0A
0
1
TB0.0
1
1
TB0.CCI1A
0
1
TB0.1
1
1
'F5529, 'F5527, 'F5525, 'F5521, 'F5519, 'F5517, 'F5515 devices only.
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SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
Pad Logic
to ADC12
(n/a MSPF430F551x)
INCHx = x
(n/a MSPF430F551x)
to Comparator_B
from Comparator_B
CBPD.x
P6REN.x
P6DIR.x
0
0
From module
1
0
DVCC
1
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
EN
To module
1
Direction
0: Input
1: Output
1
P6OUT.x
DVSS
D
Copyright © 2009–2010, Texas Instruments Incorporated
Bus
Keeper
P6.0/CB0/(A0)
P6.1/CB1/(A1)
P6.2/CB2/(A2)
P6.3/CB3/(A3)
P6.4/CB4/(A4)
P6.5/CB5/(A5)
P6.6/CB6/(A6)
P6.7/CB7/(A7)
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Table 56. Port P6 (P6.0 to P6.7) Pin Functions
PIN NAME (P6.x)
P6.0/CB0/(A0)
x
0
FUNCTION
P6.0 (I/O)
A0 (only MSP430F552x)
CB0 (1)
P6.1/CB1/(A1)
P6.2/CB2/(A2)
P6.3/CB3/(A3)
P6.4/CB4/(A4)
1
2
3
4
P6.1 (I/O)
(1)
90
X
X
X
1
I: 0; O: 1
0
0
1
X
1
I: 0; O: 1
0
0
P6.2 (I/O)
A2 (only MSP430F552x)
X
1
X
CB2 (1)
X
X
1
I: 0; O: 1
0
0
P6.3 (I/O)
A3 (only MSP430F552x)
X
1
X
CB3 (1)
X
X
1
I: 0; O: 1
0
0
X
1
X
1
P6.4 (I/O)
P6.5 (I/O)
P6.6 (I/O)
CB6 (1)
7
0
1
X
A6 (only MSP430F552x)
P6.7/CB7/(A7)
0
X
X
CB5 (1)
6
I: 0; O: 1
X
A5 (only MSP430F552x)
P6.6/CB6/(A6)
CBPD
CB1 (1)
CB4 (1)
5
P6SEL.x
A1 (only MSP430F552x)
A4 (only MSP430F552x)
P6.5/CB5/(A5)
CONTROL BITS/SIGNALS
P6DIR.x
X
X
I: 0; O: 1
0
0
X
1
X
1
X
X
I: 0; O: 1
0
0
X
1
X
1
X
X
I: 0; O: 1
0
0
A7 (only MSP430F552x)
X
1
X
CB7 (1)
X
X
1
P6.7 (I/O)
Setting the CBPD.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. Selecting the CBx input pin to the comparator multiplexer with the CBx bits automatically disables output driver and input
buffer for that pin, regardless of the state of the associated CBPD.x bit.
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SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
Port P7, P7.0 to P7.3, Input/Output With Schmitt Trigger
Pad Logic
to ADC12
(n/a MSPF430F551x)
INCHx = x
(n/a MSPF430F551x)
to Comparator_B
from Comparator_B
CBPD.x
P7REN.x
P7DIR.x
0
0
From module
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P7OUT.x
DVSS
P7DS.x
0: Low drive
1: High drive
P7SEL.x
P7.0/CB8/(A12)
P7.1/CB9/(A13)
P7.2/CB10/(A14)
P7.3/CB11/(A15)
P7IN.x
EN
To module
Bus
Keeper
D
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Table 57. Port P7 (P7.0 to P7.3) Pin Functions
PIN NAME (P7.x)
P7.0/CB8/(A12)
x
0
FUNCTION
P7.0 (I/O)
A12
(2)
CB8 (3)
P7.1/CB9/(A13)
1
X
1
0
(2)
X
1
X
X
X
1
I: 0; O: 1
0
0
X
1
X
X
X
1
I: 0; O: 1
0
0
X
1
X
X
X
1
(1)
P7.2 (I/O) (1)
(2)
(1)
P7.3 (I/O) (1)
(2)
CB11 (3)
92
0
1
0
A15
(1)
(2)
(3)
0
X
X
CB10 (3)
3
I: 0; O: 1
X
A14
P7.3/CB11/(A15)
CBPD
I: 0; O: 1
CB9 (3)
2
(1)
P7SEL.x
P7.1 (I/O) (1)
A13
P7.2/CB10/(A14)
(1)
CONTROL BITS/SIGNALS
P7DIR.x
(1)
'F5529, 'F5527, 'F5525, 'F5521, 'F5519, 'F5517, 'F5515 devices only.
'F5529, 'F5527, 'F5525, 'F5521 devices only.
Setting the CBPD.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. Selecting the CBx input pin to the comparator multiplexer with the CBx bits automatically disables output driver and input
buffer for that pin, regardless of the state of the associated CBPD.x bit.
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Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
Pad Logic
P7REN.x
P7DIR.x
0
From module
1
P7OUT.x
0
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
1
P7DS.x
0: Low drive
1: High drive
P7SEL.x
P7.4/TB0.2
P7.5/TB0.3
P7.6/TB0.4
P7.7/TB0CLK/MCLK
P7IN.x
EN
To module
D
Table 58. Port P7 (P7.4 to P7.7) Pin Functions
PIN NAME (P7.x)
P7.4/TB0.2
P7.5/TB0.3
(1)
(1)
P7.6/TB0.4 (1)
P7.7/TB0CLK/MCLK (1)
(1)
x
4
5
6
7
FUNCTION
P7.4 (I/O)
CONTROL BITS/SIGNALS
P7DIR.x
P7SEL.x
I: 0; O: 1
0
TB0.CCI2A
0
1
TB0.2
1
1
P7.5 (I/O)
I: 0; O: 1
0
TB0.CCI3A
0
1
TB0.3
1
1
I: 0; O: 1
0
TB0.CCI4A
0
1
TB0.4
1
1
P7.7 (I/O)
I: 0; O: 1
0
TB0CLK
0
1
MCLK
1
1
P7.6 (I/O)
'F5529, 'F5527, 'F5525, 'F5521, 'F5519, 'F5517, 'F5515 devices only.
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Port P8, P8.0 to P8.2, Input/Output With Schmitt Trigger
Pad Logic
P8REN.x
P8DIR.x
0
from Port Mapping Control
1
P8OUT.x
0
from Port Mapping Control
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P8.0
P8.1
P8.2
P8DS.x
0: Low drive
1: High drive
P8SEL.x
P8IN.x
EN
D
to Port Mapping Control
Table 59. Port P8 (P8.0 to P8.2) Pin Functions
PIN NAME (P8.x)
x
FUNCTION
CONTROL BITS/SIGNALS
P8DIR.x
P8SEL.x
P8.0 (1)
0
P8.0(I/O)
I: 0; O: 1
0
P8.1 (1)
1
P8.1(I/O)
I: 0; O: 1
0
P8.2 (1)
2
P8.2(I/O)
I: 0; O: 1
0
(1)
94
'F5529, 'F5527, 'F5525, 'F5521, 'F5519, 'F5517, 'F5515 devices only.
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SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
Port PU.0/DP, PU.1/DM, PUR USB Ports
PUSEL
PUDIR
0
USB output enable
1
PUOUT0
USB DP output
VUSB
VSSU
Pad Logic
0
PU.0/
DP
1
PUIN0
USB DP input
.
PUIN1
USB DM input
PUOUT0
0
USB DM output
1
PU.1/
DM
VUSB
VSSU
Pad Logic
PUREN
“1”
PUR
PUSEL
PURIN
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Table 60. Port PU.0/DP, PU.1/DM Output Functions
CONTROL BITS
PIN NAME
FUNCTION
PUSEL
PUDIR
PUOUT1
PUOUT0
PU.1/DM
PU.0/DP
0
0
X
X
Hi-Z
Hi-Z
Outputs off
0
1
0
0
0
0
Outputs enabled
0
1
0
1
0
1
Outputs enabled
0
1
1
0
1
0
Outputs enabled
0
1
1
1
1
1
Outputs enabled
1
X
X
X
DM
DP
Direction set by
USB module
Table 61. Port PUR Input Functions
CONTROL BITS
96
FUNCTION
PUSEL
PUREN
0
0
Input disabled
Pull up disabled
0
1
Input disabled
Pull up enabled
1
0
Input enabled
Pull up disabled
1
1
Input enabled
Pull up enabled
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SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output
Pad Logic
PJREN.0
PJDIR.0
0
DVCC
1
PJOUT.0
0
From JTAG
1
DVSS
0
DVCC
1
1
PJ.0/TDO
PJDS.0
0: Low drive
1: High drive
From JTAG
PJIN.0
EN
D
Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
Pad Logic
PJREN.x
PJDIR.x
0
DVSS
1
PJOUT.x
0
From JTAG
1
DVSS
0
DVCC
1
1
PJDS.x
0: Low drive
1: High drive
From JTAG
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
PJIN.x
EN
To JTAG
D
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Table 62. Port PJ (PJ.0 to PJ.3) Pin Functions
PIN NAME (PJ.x)
x
CONTROL BITS/
SIGNALS (1)
FUNCTION
PJDIR.x
PJ.0/TDO
0
(2)
I: 0; O: 1
PJ.1 (I/O) (2)
I: 0; O: 1
PJ.0 (I/O)
TDO (3)
PJ.1/TDI/TCLK
1
X
TDI/TCLK (3)
PJ.2/TMS
2
PJ.2 (I/O)
TMS (3)
PJ.3/TCK
3
(1)
(2)
(3)
(4)
98
X
I: 0; O: 1
(4)
PJ.3 (I/O)
TCK (3)
(4)
(2)
X
(2)
I: 0; O: 1
(4)
X
X = Don't care
Default condition
The pin direction is controlled by the JTAG module.
In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.
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SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
DEVICE DESCRIPTORS (TLV)
Table 63 and Table 64 list the complete contents of the device descriptor tag-length-value (TLV) structure for
each device type.
Table 63. 'F552x Device Descriptor Table (1)
Info Block
Die Record
ADC12
Calibration
REF
Calibration
Peripheral
Descriptor
(1)
Description
Address
Size
bytes
'F5529
'F5528
'F5527
'F5526
'F5525
'F5524
'F5522
'F5521
Value
Value
Value
Value
Value
Value
Value
Value
Info length
01A00h
1
06h
06h
06h
06h
06h
06h
06h
06h
CRC length
01A01h
1
06h
06h
06h
06h
06h
06h
06h
06h
CRC value
01A02h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Device ID
01A04h
1
55h
55h
55h
55h
55h
55h
55h
55h
Device ID
01A05h
1
29h
28h
27h
26h
25h
24h
22h
21h
Hardware revision
01A06h
1
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Firmware revision
01A07h
1
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Die Record Tag
01A08h
1
08h
08h
08h
08h
08h
08h
08h
08h
Die Record length
01A09h
1
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
Lot/Wafer ID
01A0Ah
4
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Die X position
01A0Eh
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Die Y position
01A10h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Test results
01A12h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC12 Calibration Tag
01A14h
1
11h
11h
11h
11h
11h
11h
11h
11h
ADC12 Calibration length
01A15h
1
10h
10h
10h
10h
10h
10h
10h
10h
ADC Gain Factor
01A16h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC Offset
01A18h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC 1.5-V Reference
Temp. Sensor 30°C
01A1Ah
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC 1.5-V Reference
Temp. Sensor 85°C
01A1Ch
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.0-V Reference
Temp. Sensor 30°C
01A1Eh
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.0-V Reference
Temp. Sensor 85°C
01A20h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.5-V Reference
Temp. Sensor 30°C
01A22h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.5-V Reference
Temp. Sensor 85°C
01A24h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
REF Calibration Tag
01A26h
1
12h
12h
12h
12h
12h
12h
12h
12h
REF Calibration length
01A27h
1
06h
06h
06h
06h
06h
06h
06h
06h
REF 1.5-V Reference
Factor
01A28h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
REF 2.0-V Reference
Factor
01A2Ah
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
REF 2.5-V Reference
Factor
01A2Ch
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Peripheral Descriptor Tag
01A2Eh
1
02h
02h
02h
02h
02h
02h
02h
02h
Peripheral Descriptor
Length
01A2Fh
1
63h
61h
65h
63h
63h
61h
61h
64h
Memory 1
2
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
Memory 2
2
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
Memory 3
2
0Eh
2Ah
0Eh
2Ah
0Eh
2Ah
0Eh
2Ah
0Eh
2Ah
0Eh
2Ah
0Eh
2Ah
0Eh
2Ah
NA = Not applicable, blank = unused and reads FFh.
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Table 63. 'F552x Device Descriptor Table(1) (continued)
Description
100
Address
Size
bytes
'F5529
'F5528
'F5527
'F5526
'F5525
'F5524
'F5522
'F5521
Value
Value
Value
Value
Value
Value
Value
Value
12h
2Eh
12h
2Dh
12h
2Dh
12h
2Ch
12h
2Ch
12h
2Eh
12h
2Dh
Memory 4
2
12h
2Eh
Memory 5
2
22h
96h
22h
96h
2Ah
22h
2Ah
22h
22h
94h
22h
94h
40h
92h
2Ah
40h
Memory 6
1/2
N/A
N/A
95h
92h
95h
92h
N/A
N/A
N/A
92h
delimiter
1
00h
00h
00h
00h
00h
00h
00h
00h
Peripheral count
1
21h
20h
21h
20h
21h
20h
20h
21h
MSP430CPUXV2
2
00h
23h
00h
23h
00h
23h
00h
23h
00h
23h
00h
23h
00h
23h
00h
23h
JTAG
2
00h
09h
00h
09h
00h
09h
00h
09h
00h
09h
00h
09h
00h
09h
00h
09h
SBW
2
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
EEM-L
2
00h
05h
00h
05h
00h
05h
00h
05h
00h
05h
00h
05h
00h
05h
00h
05h
TI BSL
2
00h
FCh
00h
FCh
00h
FCh
00h
FCh
00h
FCh
00h
FCh
00h
FCh
00h
FCh
SFR
2
10h
41h
10h
41h
10h
41h
10h
41h
10h
41h
10h
41h
10h
41h
10h
41h
PMM
2
02h
30h
02h
30h
02h
30h
02h
30h
02h
30h
02h
30h
02h
30h
02h
30h
FCTL
2
02h
38h
02h
38h
02h
38h
02h
38h
02h
38h
02h
38h
02h
38h
02h
38h
CRC16
2
01h
3Ch
01h
3Ch
01h
3Ch
01h
3Ch
01h
3Ch
01h
3Ch
01h
3Ch
01h
3Ch
CRC16_RB
2
00h
3Dh
00h
3Dh
00h
3Dh
00h
3Dh
00h
3Dh
00h
3Dh
00h
3Dh
00h
3Dh
RAMCTL
2
00h
44h
00h
44h
00h
44h
00h
44h
00h
44h
00h
44h
00h
44h
00h
44h
WDT_A
2
00h
40h
00h
40h
00h
40h
00h
40h
00h
40h
00h
40h
00h
40h
00h
40h
UCS
2
01h
48h
01h
48h
01h
48h
01h
48h
01h
48h
01h
48h
01h
48h
01h
48h
SYS
2
02h
42h
02h
42h
02h
42h
02h
42h
02h
42h
02h
42h
02h
42h
02h
42h
REF
2
03h
A0h
03h
A0h
03h
A0h
03h
A0h
03h
A0h
03h
A0h
03h
A0h
03h
A0h
Port Mapping
2
01h
10h
01h
10h
01h
10h
01h
10h
01h
10h
01h
10h
01h
10h
01h
10h
Port 1/2
2
04h
51h
04h
51h
04h
51h
04h
51h
04h
51h
04h
51h
04h
51h
04h
51h
Port 3/4
2
02h
52h
02h
52h
02h
52h
02h
52h
02h
52h
02h
52h
02h
52h
02h
52h
Port 5/6
2
02h
53h
02h
53h
02h
53h
02h
53h
02h
53h
02h
53h
02h
53h
02h
53h
Port 7/8
2
02h
54h
N/A
02h
54h
N/A
02h
54h
N/A
N/A
02h
54h
JTAG
2
0Ch
5Fh
0Eh
5Fh
0Ch
5Fh
0Eh
5Fh
0Ch
5Fh
0Eh
5Fh
0Eh
5Fh
0Ch
5Fh
TA0
2
02h
62h
02h
62h
02h
62h
02h
62h
02h
62h
02h
62h
02h
62h
02h
62h
TA1
2
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
TB0
2
04h
67h
04h
67h
04h
67h
04h
67h
04h
67h
04h
67h
04h
67h
04h
67h
TA2
2
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
RTC
2
0Ah
68h
0Ah
68h
0Ah
68h
0Ah
68h
0Ah
68h
0Ah
68h
0Ah
68h
0Ah
68h
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Table 63. 'F552x Device Descriptor Table(1) (continued)
Description
Interrupts
Address
Size
bytes
'F5529
'F5528
'F5527
'F5526
'F5525
'F5524
'F5522
'F5521
Value
Value
Value
Value
Value
Value
Value
Value
02h
85h
02h
85h
02h
85h
02h
85h
02h
85h
02h
85h
02h
85h
MPY32
2
02h
85h
DMA-3
2
04h
47h
04h
47h
04h
47h
04h
47h
04h
47h
04h
47h
04h
47h
04h
47h
USCI_A/B
2
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
USCI_A/B
2
04h
90h
04h
90h
04h
90h
04h
90h
04h
90h
04h
90h
04h
90h
04h
90h
ADC12_A
2
10h
D1h
10h
D1h
10h
D1h
10h
D1h
10h
D1h
10h
D1h
10h
D1h
10h
D1h
COMP_B
2
1Ch
A8h
1Ch
A8h
1Ch
A8h
1Ch
A8h
1Ch
A8h
1Ch
A8h
1Ch
A8h
1Ch
A8h
USB
2
04h
98h
04h
98h
04h
98h
04h
98h
04h
98h
04h
98h
04h
98h
04h
98h
COMP_B
1
A8h
A8h
A8h
A8h
A8h
A8h
A8h
A8h
TB0.CCIFG0
1
64h
64h
64h
64h
64h
64h
64h
64h
TB0.CCIFG1..6
1
65h
65h
65h
65h
65h
65h
65h
65h
WDTIFG
1
40h
40h
40h
40h
40h
40h
40h
40h
USCI_A0
1
90h
90h
90h
90h
90h
90h
90h
90h
USCI_B0
1
91h
91h
91h
91h
91h
91h
91h
91h
ADC12_A
1
D0h
D0h
D0h
D0h
D0h
D0h
D0h
D0h
TA0.CCIFG0
1
60h
60h
60h
60h
60h
60h
60h
60h
TA0.CCIFG1..4
1
61h
61h
61h
61h
61h
61h
61h
61h
USB
1
98h
98h
98h
98h
98h
98h
98h
98h
DMA
1
46h
46h
46h
46h
46h
46h
46h
46h
TA1.CCIFG0
1
62h
62h
62h
62h
62h
62h
62h
62h
TA1.CCIFG1..2
1
63h
63h
63h
63h
63h
63h
63h
63h
P1
1
50h
50h
50h
50h
50h
50h
50h
50h
USCI_A1
1
92h
92h
92h
92h
92h
92h
92h
92h
USCI_B1
1
93h
93h
93h
93h
93h
93h
93h
93h
TA1.CCIFG0
1
66h
66h
66h
66h
66h
66h
66h
66h
TA1.CCIFG1..2
1
67h
67h
67h
67h
67h
67h
67h
67h
P2
1
51h
51h
51h
51h
51h
51h
51h
51h
RTC_A
1
68h
68h
68h
68h
68h
68h
68h
68h
delimiter
1
00h
00h
00h
00h
00h
00h
00h
00h
Table 64. 'F551x Device Descriptor Table (1)
Info Block
Die Record
(1)
Description
Address
Size
bytes
'F5519
'F5517
'F5515
'F5514
'F5513
Value
Value
Value
Value
Value
Info length
01A00h
1
55h
55h
55h
55h
55h
CRC length
01A01h
1
19h
17h
15h
14h
13h
CRC value
01A02h
2
per unit
per unit
per unit
per unit
per unit
Device ID
01A04h
1
22h
21h
55h
55h
20h
Device ID
01A05h
1
80h
80h
15h
14h
80h
Hardware revision
01A06h
1
per unit
per unit
per unit
per unit
per unit
Firmware revision
01A07h
1
per unit
per unit
per unit
per unit
per unit
Die Record Tag
01A08h
1
08h
08h
08h
08h
08h
Die Record length
01A09h
1
0Ah
0Ah
0Ah
0Ah
0Ah
Lot/Wafer ID
01A0Ah
4
per unit
per unit
per unit
per unit
per unit
Die X position
01A0Eh
2
per unit
per unit
per unit
per unit
per unit
NA = Not applicable, blank = unused and reads FFh.
Copyright © 2009–2010, Texas Instruments Incorporated
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SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
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Table 64. 'F551x Device Descriptor Table(1) (continued)
ADC12
Calibration
REF
Calibration
Peripheral
Descriptor
102
Description
Address
Size
bytes
'F5519
'F5517
'F5515
'F5514
'F5513
Value
Value
Value
Value
Value
Die Y position
01A10h
2
per unit
per unit
per unit
per unit
per unit
Test results
01A12h
2
per unit
per unit
per unit
per unit
per unit
ADC12 Calibration
Tag
01A14h
1
05h
05h
11h
11h
05h
ADC12 Calibration
length
01A15h
1
10h
10h
10h
10h
10h
ADC Gain Factor
01A16h
2
blank
blank
blank
blank
blank
ADC Offset
01A18h
2
blank
blank
blank
blank
blank
ADC 1.5-V
Reference
Temp. Sensor
30°C
01A1Ah
2
blank
blank
blank
blank
blank
ADC 1.5-V
Reference
Temp. Sensor
85°C
01A1Ch
2
blank
blank
blank
blank
blank
ADC 2.0-V
Reference
Temp. Sensor
30°C
01A1Eh
2
blank
blank
blank
blank
blank
ADC 2.0-V
Reference
Temp. Sensor
85°C
01A20h
2
blank
blank
blank
blank
blank
ADC 2.5-V
Reference
Temp. Sensor
30°C
01A22h
2
blank
blank
blank
blank
blank
ADC 2.5-V
Reference
Temp. Sensor
85°C
01A24h
2
blank
blank
blank
blank
blank
REF Calibration
Tag
01A26h
1
12h
12h
12h
12h
12h
REF Calibration
length
01A27h
1
06h
06h
06h
06h
06h
REF 1.5-V
Reference Factor
01A28h
2
per unit
per unit
per unit
per unit
per unit
REF 2.0-V
Reference Factor
01A2Ah
2
per unit
per unit
per unit
per unit
per unit
REF 2.5-V
Reference Factor
01A2Ch
2
per unit
per unit
per unit
per unit
per unit
Peripheral
Descriptor Tag
01A2Eh
1
02h
02h
02h
02h
02h
Peripheral
Descriptor Length
01A2Fh
1
61h
63h
61h
5Fh
5Fh
Memory 1
2
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
Memory 2
2
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
Memory 3
2
0Eh
2Ah
0Eh
2Ah
0Eh
2Ah
0Eh
2Ah
0Eh
2Ah
Memory 4
2
12h
2Eh
12h
2Dh
12h
2Ch
12h
2Ch
12h
2Ch
Memory 5
2
22h
96h
2Ah
22h
22h
94h
22h
94h
40h
92h
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Copyright © 2009–2010, Texas Instruments Incorporated
MSP430F551x
MSP430F552x
www.ti.com
SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
Table 64. 'F551x Device Descriptor Table(1) (continued)
Size
bytes
'F5519
'F5517
'F5515
'F5514
'F5513
Value
Value
Value
Value
Value
Memory 6
1/2
N/A
95h
92h
N/A
N/A
N/A
delimiter
1
00h
00h
00h
00h
00h
Peripheral count
1
20h
20h
20h
1Fh
1Fh
MSP430CPUXV2
2
00h
23h
00h
23h
00h
23h
00h
23h
00h
23h
JTAG
2
00h
09h
00h
09h
00h
09h
00h
09h
00h
09h
SBW
2
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
EEM-L
2
00h
05h
00h
05h
00h
05h
00h
05h
00h
05h
TI BSL
2
00h
FCh
00h
FCh
00h
FCh
00h
FCh
00h
FCh
SFR
2
10h
41h
10h
41h
10h
41h
10h
41h
10h
41h
PMM
2
02h
30h
02h
30h
02h
30h
02h
30h
02h
30h
FCTL
2
02h
38h
02h
38h
02h
38h
02h
38h
02h
38h
CRC16
2
01h
3Ch
01h
3Ch
01h
3Ch
01h
3Ch
01h
3Ch
CRC16_RB
2
00h
3Dh
00h
3Dh
00h
3Dh
00h
3Dh
00h
3Dh
RAMCTL
2
00h
44h
00h
44h
00h
44h
00h
44h
00h
44h
WDT_A
2
00h
40h
00h
40h
00h
40h
00h
40h
00h
40h
UCS
2
01h
48h
01h
48h
01h
48h
01h
48h
01h
48h
SYS
2
02h
42h
02h
42h
02h
42h
02h
42h
02h
42h
REF
2
03h
A0h
03h
A0h
03h
A0h
03h
A0h
03h
A0h
Port Mapping
2
01h
10h
01h
10h
01h
10h
01h
10h
01h
10h
Port 1/2
2
04h
51h
04h
51h
04h
51h
04h
51h
04h
51h
Port 3/4
2
02h
52h
02h
52h
02h
52h
02h
52h
02h
52h
Port 5/6
2
02h
53h
02h
53h
02h
53h
02h
53h
02h
53h
Port 7/8
2
02h
54h
02h
54h
02h
54h
N/A
N/A
JTAG
2
0Ch
5Fh
0Ch
5Fh
0Ch
5Fh
0Eh
5Fh
0Eh
5Fh
TA0
2
02h
62h
02h
62h
02h
62h
02h
62h
02h
62h
TA1
2
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
TB0
2
04h
67h
04h
67h
04h
67h
04h
67h
04h
67h
TA2
2
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
Description
Address
Copyright © 2009–2010, Texas Instruments Incorporated
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MSP430F551x
MSP430F552x
SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
www.ti.com
Table 64. 'F551x Device Descriptor Table(1) (continued)
Description
Interrupts
104
Address
Size
bytes
'F5519
'F5517
'F5515
'F5514
'F5513
Value
Value
Value
Value
Value
RTC
2
0Ah
68h
0Ah
68h
0Ah
68h
0Ah
68h
0Ah
68h
MPY32
2
02h
85h
02h
85h
02h
85h
02h
85h
02h
85h
DMA-3
2
04h
47h
04h
47h
04h
47h
04h
47h
04h
47h
USCI_A/B
2
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
USCI_A/B
2
04h
90h
04h
90h
04h
90h
04h
90h
04h
90h
ADC12_A
2
N/A
N/A
N/A
N/A
N/A
COMP_B
2
2Ch
A8h
2Ch
A8h
2Ch
A8h
2Ch
A8h
2Ch
A8h
USB
2
04h
98h
04h
98h
04h
98h
04h
98h
04h
98h
COMP_B
1
A8h
A8h
A8h
A8h
A8h
TB0.CCIFG0
1
64h
64h
64h
64h
64h
TB0.CCIFG1..6
1
65h
65h
65h
65h
65h
WDTIFG
1
40h
40h
40h
40h
40h
USCI_A0
1
90h
90h
90h
90h
90h
USCI_B0
1
91h
91h
91h
91h
91h
ADC12_A
1
01h
01h
01h
01h
01h
TA0.CCIFG0
1
60h
60h
60h
60h
60h
TA0.CCIFG1..4
1
61h
61h
61h
61h
61h
USB
1
98h
98h
98h
98h
98h
DMA
1
46h
46h
46h
46h
46h
TA1.CCIFG0
1
62h
62h
62h
62h
62h
TA1.CCIFG1..2
1
63h
63h
63h
63h
63h
P1
1
50h
50h
50h
50h
50h
USCI_A1
1
92h
92h
92h
92h
92h
USCI_B1
1
93h
93h
93h
93h
93h
TA1.CCIFG0
1
66h
66h
66h
66h
66h
TA1.CCIFG1..2
1
67h
67h
67h
67h
67h
P2
1
51h
51h
51h
51h
51h
RTC_A
1
68h
68h
68h
68h
68h
delimiter
1
00h
00h
00h
00h
00h
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Copyright © 2009–2010, Texas Instruments Incorporated
MSP430F551x
MSP430F552x
www.ti.com
SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
REVISION HISTORY
REVISION
SLAS590
DESCRIPTION
Limited product preview release
SLAS590A
Changes throughout for XMS430F5529 sampling
SLAS590B
Changes throughout for updated preview
SLAS590C
Changes throughout for updated preview
SLAS590D
Production data release
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
105
PACKAGE OPTION ADDENDUM
www.ti.com
18-Aug-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
MSP430F5513IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
MSP430F5513IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
MSP430F5513IZQE
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
360
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Purchase Samples
MSP430F5513IZQER
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Request Free Samples
MSP430F5514IRGCR
PREVIEW
VQFN
RGC
64
2000
TBD
Call TI
Call TI
Samples Not Available
MSP430F5514IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Request Free Samples
MSP430F5514IZQE
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
360
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Purchase Samples
MSP430F5514IZQER
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Request Free Samples
MSP430F5515IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Contact TI Distributor
or Sales Office
MSP430F5515IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Request Free Samples
MSP430F5517IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
MSP430F5517IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Request Free Samples
MSP430F5519IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Contact TI Distributor
or Sales Office
MSP430F5519IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Request Free Samples
MSP430F5521IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
18-Aug-2010
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
MSP430F5521IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Request Free Samples
MSP430F5522IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Request Free Samples
MSP430F5522IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Contact TI Distributor
or Sales Office
MSP430F5522IZQE
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
360
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Contact TI Distributor
or Sales Office
MSP430F5522IZQER
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Request Free Samples
MSP430F5524IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
MSP430F5524IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Request Free Samples
MSP430F5524IZQE
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
360
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Contact TI Distributor
or Sales Office
MSP430F5524IZQER
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Request Free Samples
MSP430F5525IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
MSP430F5525IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Request Free Samples
MSP430F5526IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
MSP430F5526IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Request Free Samples
MSP430F5526IZQE
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
360
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Purchase Samples
MSP430F5526IZQER
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Request Free Samples
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
18-Aug-2010
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
MSP430F5527IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
MSP430F5527IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Request Free Samples
MSP430F5528IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
MSP430F5528IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Request Free Samples
MSP430F5528IZQE
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
360
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Contact TI Distributor
or Sales Office
MSP430F5528IZQER
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Request Free Samples
MSP430F5529CY
PREVIEW
DIESALE
Y
0
1
TBD
Call TI
Samples Not Available
MSP430F5529IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Call TI
Contact TI Distributor
or Sales Office
MSP430F5529IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Request Free Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
18-Aug-2010
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
41
60
61
40
80
21
0,13 NOM
1
20
Gage Plane
9,50 TYP
12,20
SQ
11,80
14,20
SQ
13,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 / B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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