USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C346 128-Macrocell MAX® EPLD Features The 128 macrocells in the CY7C346 are divided into eight LABs, 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB. • 128 macrocells in eight logic array blocks (LABs) • 20 dedicated inputs, up to 64 bidirectional I/O pins Each LAB is interconnected through the programmable interconnect array, allowing all signals to be routed throughout the chip. • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology • Available in 84-pin CLCC, PLCC, and 100-pin PGA, PQFP Functional Description The CY7C346 is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within the device. The MAX® architecture is 100% user-configurable, allowing the device to accommodate a variety of independent logic functions. The speed and density of the CY7C346 allow it to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 25 times the functionality of 20-pin PLDs, the CY7C346 allows the replacement of over 50 TTL devices. By replacing large amounts of logic, the CY7C346 reduces board space, part count, and increases system reliability. Logic Block Diagram .. 1 . 78 . 79 80 . 83 . 84 .. 2 .. 5 .. 6 .. 7 (C7) [16] (A10) [9] (B9) [10] (A9) [11] (A8) [14] (B7) [15] (A7) [17] (C6) [20] (A5) [21] (B5) [22] INPUT [59] INPUT [60] INPUT [61] INPUT [64] INPUT [65] INPUT [66] INPUT [67] INPUT [70] INPUT [71] INPUT [72] . INPUT/CLK ..... INPUT ..... INPUT ..... INPUT ..... INPUT ..... INPUT ..... INPUT ..... INPUT ..... INPUT ..... INPUT (N4) (M5) (N5) (N6) (M7) (L7) (N7) (L8) (N9) (M9) . . . . . . . . . . 36 37 38 41 42 43 44 47 48 49 SYSTEM CLOCK 8 (B13) [1] 9 (C12) [2] 10 (A13) [3] 11 (B12) [4] 12 (A12) [5] 13 (11) [6] NC (A11) [7] NC (B10) [8] LAB A MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL LAB H MACROCELL 120 MACROCELL 119 MACROCELL 118 MACROCELL 117 MACROCELL 116 MACROCELL 115 MACROCELL 114 MACROCELL 113 1 2 3 4 5 6 7 8 MACROCELL 121–128 MACROCELL 9–16 14 (A4) 15 (B4) 16 (A3) 17 (A2) 18 (B3) 21 (A1) NC (B2) NC (B1) [23] [24] [25] [26] [27] [28] [29] [30] LAB B MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL LAB G MACROCELL 104 MACROCELL 103 MACROCELL 102 MACROCELL 101 MACROCELL 100 MACROCELL 99 MACROCELL 98 MACROCELL 97 17 18 19 20 21 22 23 24 MACROCELL 25–32 22 (C2) [31] 25 (C1) [32] 26 (D2) [33] 27 (D1) [34] 28 (E2) [35] 29 (E1) [36] NC (F1) [39] NC (G2) [40] LAB C MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL LAB F MACROCELL 88 MACROCELL 87 MACROCELL 86 MACROCELL 85 MACROCELL 84 MACROCELL 83 MACROCELL 82 MACROCELL 81 MACROCELL 86–96 33 34 35 36 37 38 39 40 LAB D (G12) NC (H13) NC (J13) 71 (J12) 70 (K13) 69 (K12) 68 (L13) 67 (L12) 64 [80] [79] [78] [77] [76] [75] [74] [73] (M13) (M12) (N13) (M11) (N12) (N11) (M10) (N10) [58] [57] [56] [55] [54] [53] [52] [51] (M4) NC (N3) NC (M3) 55 (N2) 54 (M2) 53 (N1) 52 (L2) 51 (M1) 50 NC NC 63 60 59 58 57 56 LAB E MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL 49 50 51 52 53 54 55 56 MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL [18, 19, 43, 44, 68, 69, 93, 94] VCC 16, 33, 50, 67 (B8,C8,F2,F3,H11,H12,L6,M6) [12, 13, 37, 38, 62, 63, 87, 88] GND • 72 71 70 69 68 67 66 65 MACROCELL 73– 80 MACROCELL 57– 64 3, 20, 37, 54 (A6,B6,F12,F13,H1,H2,M8,N8) Cypress Semiconductor Corporation Document #: 38-03005 Rev. *B [90] [89] [86] [85] [84] [83] [82] [81] MACROCELL 105–112 P I A MACROCELL 41–48 30 (G3) [41] 31 (G1) [42] 32 (H3) [45] 33 (J1) [46] 34 (J2) [47] 35 (K1) [48] NC (K2) [49] NC (L1) [50] [100] (C13) NC [99] (D12) NC [98] (D13) 77 [97] (E12) 76 [96] (E13) 75 [95] (F11) 74 [92] (G13) 73 [91] (G11) 72 3901 North First Street () – PERTAIN TO 100-PIN PGA PACKAGE [ ] –PERTAIN TO 100-PIN PQFP PACKAGE • San Jose, CA 95134 • 408-943-2600 Revised April 19, 2004 USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C346 Selection Guide 7C346-25 7C346-30 7C346-35 Unit 25 30 35 ns Commercial 250 250 250 mA Military 325 320 320 Industrial 320 320 320 Commercial 225 225 225 Military 275 275 275 Industrial 275 275 275 Maximum Access Time Maximum Operating Current Maximum Standby Current mA Pin Configurations 11 10 9 8 7 6 I/O I/O I/O I/O INPUT INPUT INPUT GND GND PGA Bottom View INPUT INPUT INPUT/CLK INPUT INPUT V CC V CC INPUT INPUT I/O I/O I/O I/O PLCC/CLCC Top View 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 I/O I/O 12 13 73 I/O I/O I/O 14 15 72 I/O I/O I/O 16 I/O I/O GND 17 18 19 69 GND 20 21 66 65 22 I/O I/O VCC 23 VCC I/O 24 25 26 I/O 71 70 68 67 CY7C346 I/O INP GND INP VCC INP I/O I/O I/O I/O L I/O I/O I/O I/O K I/O I/O I/O I/O J I/O I/O I/O I/O H VCC VCC GND INP D I/O I/O I/O I/O I/O INP I/O I/O I/O I/O 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 I/O I/O I/O I/O 32 INPUT I/O I/O I/O INPUT I/O E 56 INPUT V CC V CC INPUT M GND I/O 55 INPUT I/O 61 31 INPUT I/O I/O GND GND 30 INPUT I/O F 29 INPUT GND GND I/O I/O GND I/O I/O INPUT INP INP INP VCC INP 63 62 I/O I/O INP I/O 58 57 INPUT I/O G 27 I/O I/O I/O VCC I/O 64 I/O I/O Document #: 38-03005 Rev. *B I/O I/O I/O VCC I/O 60 59 28 I/O N GND GND CY7C346 I/O I/O I/O I/O I/O I/O VCC VCC I/O I/O I/O I/O I/O I/O I/O C I/O I/O I/O I/O B I/O I/O I/O I/O INP VCC INP GND INP A I/O I/O I/O I/O INP VCC INP 1 2 3 4 INP 5 6 INP GND /CLK 7 I/O I/O I/O I/O INP INP INP I/O I/O I/O 9 11 12 13 8 10 Page 2 of 21 USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C346 Pin Configurations (continued) 87 86 85 84 83 I/O I/O I/O I/O I/O I/O GND 100 99 98 97 96 95 94 93 92 91 90 89 88 GND I/O I/O I/O CC I/O V I/O VCC I/O I/O I/O I/O I/O PQFP Top View 82 81 I/O I/O 1 I/O 2 80 79 I/O I/O 3 78 I/O I/O 4 I/O I/O 5 77 76 I/O 6 75 I/O I/O 7 74 I/O I/O 8 73 I/O INPUT 9 72 INPUT 10 71 INPUT INPUT 11 70 GND 12 INPUT VCC GND 13 69 68 14 67 INPUT INPUT 15 66 INPUT INPUT/CLK 16 65 INPUT INPUT 17 64 INPUT VCC 18 63 GND VCC 19 62 INPUT 20 GND INPUT INPUT INPUT INPUT CY7C346 I/O VCC 21 61 60 INPUT 22 59 INPUT I/O 23 58 I/O I/O 24 57 I/O I/O 25 56 I/O I/O 26 55 I/O I/O 27 54 I/O I/O 28 I/O 29 I/O 30 53 INPUT I/O 52 I/O 51 I/O Document #: 38-03005 Rev. *B I/O I/O I/O I/O I/O I/O VCC VCC I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O I/O 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Page 3 of 21 USE ULTRA37000TM FOR ALL NEW DESIGNS Logic Array Blocks that may be individually configured for input, output, or bidirectional data flow. There are eight logic array blocks in the CY7C346. Each LAB consists of a macrocell array containing 16 macrocells, an expander product term array containing 32 expanders, and an I/O block. The LAB is fed by the programmable interconnect array and the dedicated input bus. All macrocell feedbacks go to the macrocell array, the expander array, and the programmable interconnect array. Expanders feed themselves and the macrocell array. All I/O feedbacks go to the programmable interconnect array so that they may be accessed by macrocells in other LABs as well as the macrocells in the LAB in which they are situated. Programmable Interconnect Array The Programmable Interconnect Array (PIA) solves interconnect limitations by routing only the signals needed by each logic array block. The inputs to the PIA are the outputs of every macrocell within the device and the I/O pin feedback of every pin on the device. Timing Delays Timing delays within the CY7C346 may be easily determined using Warp®, Warp Professional™, or Warp Enterprise™ software. The CY7C346 has fixed internal delays, allowing the user to determine the worst case timing delays for any design. Externally, the CY7C346 provides 20 dedicated inputs, one of which may be used as a system clock. There are 64 I/O pins EXPANDER DELAY tEXP REGISTER LOGIC ARRAY CONTROL DELAY tCLR tLAC tPRE INPUT INPUT DELAY tIN CY7C346 LOGIC ARRAY DELAY tLAD tRSU tRH OUTPUT DELAY OUTPUT tRD tCOMB tLATCH tOD tXZ tZX SYSTEM CLOCK DELAY tICS PIA DELAY tPIA CLOCK DELAY tIC FEEDBACK DELAY tFD I/O DELAY tIO Figure 1. CY7C346 Internal Timing Model Design Recommendations Operation of the devices described herein with conditions above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. The CY7C346 contains circuitry to protect device pins from high static voltages or electric fields, but normal precautions should be taken to avoid application of any voltage higher than the maximum rated voltages. For proper operation, input and output pins must be constrained to the range GND ≤ (VIN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic level Document #: 38-03005 Rev. *B (either VCC or GND). Each set of VCC and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at least 0.2 µF must be connected between VCC and GND. For the most effective decoupling, each VCC pin should be separately decoupled to GND directly at the device. Decoupling capacitors should have good frequency response, such as monolithic ceramic types have. Design Security The CY7C346 contains a programmable design security feature that controls the access to the data programmed into the device. If this programmable feature is used, a proprietary design implemented in the device cannot be copied or retrieved. This enables a high level of design control to be Page 4 of 21 USE ULTRA37000TM FOR ALL NEW DESIGNS obtained since programmed data within EPROM cells is invisible. The bit that controls this function, along with all other program data, may be reset simply by erasing the entire device. The CY7C346 is fully functionally tested and guaranteed through complete testing of each programmable EPROM bit and all internal logic elements thus ensuring 100% programming yield. The erasable nature of these devices allows test programs to be used and erased during early stages of the production flow. The devices also contain on-board logic test circuitry to allow verification of function and AC specification once encapsulated in non-windowed packages. Typical ICC vs. fMAX ICC ACTIVE (mA) Typ. 400 Timing Considerations Unless otherwise stated, propagation delays do not include expanders. When using expanders, add the maximum expander delay tEXP to the overall delay. Similarly, there is an additional tPIA delay for an input from an I/O pin when compared to a signal from straight input pin. When calculating synchronous frequencies, use tS1 if all inputs are on dedicated input pins. The parameter tS2 should be used if data is applied at an I/O pin. If tS2 is greater than tCO1, 1/tS2 becomes the limiting frequency in the data path mode unless 1/(tWH + tWL) is less than 1/tS2. When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tS1. Determine which of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tS1) is the lowest frequency. The lowest of these frequencies is the maximum data path frequency for the synchronous configuration. When calculating external asynchronous frequencies, use tAS1 if all inputs are on the dedicated input pins. If any data is applied to an I/O pin, tAS2 must be used as the required set-up time. If (tAS2 + tAH) is greater than tACO1, 1/(tAS2 + tAH) becomes the limiting frequency in the data path mode unless 1/(tAWH + tAWL) is less than 1/(tAS2 + tAH). 300 VCC = 5.0V Room Temp. 200 When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tAS1. Determine which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the lowest frequency. The lowest of these frequencies is the maximum data path frequency for the asynchronous configuration. 100 0 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 50 MHz MAXIMUM FREQUENCY Output Drive Current IO OUTPUT CURRENT (mA) TYPICAL CY7C346 The parameter tAOH indicates the system compatibility of this device when driving subsequent registered logic with a positive hold time and using the same asynchronous clock as the CY7C346. 100 IOL In general, if tAOH is greater than the minimum required input hold time of the subsequent logic (synchronous or asynchronous) then the devices are guaranteed to function properly under worst-case environmental and supply voltage conditions, provided the clock signal source is the same. This also applies if expander logic is used in the clock signal path of the driving device, but not for the driven device. This is due to the expander logic in the second device’s clock signal path adding an additional delay (tEXP) causing the output data from the preceding device to change prior to the arrival of the clock signal at the following device’s register. 80 VCC = 5.0V Room Temp. 60 40 IOH 20 0 0.45 1 2 The parameter tOH indicates the system compatibility of this device when driving other synchronous logic with positive input hold times, which is controlled by the same synchronous clock. If tOH is greater than the minimum required input hold time of the subsequent synchronous logic, then the devices are guaranteed to function properly with a common synchronous clock under worst-case environmental and supply voltage conditions. 3 4 5 VO OUTPUT VOLTAGE (V) Document #: 38-03005 Rev. *B Page 5 of 21 USE ULTRA37000TM FOR ALL NEW DESIGNS Maximum Ratings CY7C346 DC Output Current per Pin ...................... –25 mA to +25 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to+150°C Ambient Temperature with Power Applied............................................. –55°C to+125°C Maximum Junction Temperature (under bias).................................................................. 150°C DC Input Voltage[1] .........................................–3.0V to +7.0V DC Program Voltage..................................................... 13.0V Static Discharge Voltage........................................... > 1100V (per MIL-STD-883, Method 3015) Operating Range Range Supply Voltage to Ground Potential ............... –2.0V to +7.0V Commercial Maximum Power Dissipation...................................2500 mW Industrial DC VCC or GND Current ............................................500 mA Military Ambient Temperature VCC 0°C to +70°C 5V ± 5% –40°C to +85°C 5V ± 10% –55°C to +125°C (Case) 5V ± 10% Electrical Characteristics Over the Operating Range[2] Parameter Description VOH Output HIGH Voltage Test Conditions VCC = Min., IOH = –4.0 mA VOL VIH VIL IIX IOZ IOS ICC1 Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Current Output Leakage Current Output Short Circuit Current Power Supply Current (Standby) VCC = Min., IOL = 8.0 mA ICC2 Power Supply Current[5] tR tF Recommended Input Rise Time Recommended Input Fall Time Min. 2.4 2.2 –0.3 –10 –40 –30 GND < VIN < VCC VO = VCC or GND VCC = Max., VOUT = 0.5V[3, 4] VI = GND (No Load) Commercial Military/Industrial VI = VCC or GND (No Load) Commercial f = 1.0 MHz[4] Military/Industrial Max. Unit V 0.45 VCC + 0.3 0.8 +10 +40 –90 225 275 250 320 100 100 V V V µA µA mA mA mA ns ns Capacitance[6] Parameter Description Test Conditions Max. Unit CIN Input Capacitance VIN = 2V, f = 1.0 MHz 10 pF COUT Output Capacitance VOUT = 2V, f = 1.0 MHz 20 pF AC Test Loads and Waveforms[6] R1 464Ω 5V R1 464Ω 5V OUTPUT ALL INPUT PULSES OUTPUT 50 pF R2 250Ω 3.0V 5 pF R2 250Ω INCLUDING JIG AND SCOPE (a) (b) THÉVENIN EQUIVALENT (Commercial/Military) 163Ω OUTPUT 1.75V INCLUDING JIG AND SCOPE Equivalent to: 10% GND ≤ 6 ns 90% 90% 10% ≤ 6 ns Notes: 1. Minimum DC input is –0.3V. During transitions, the inputs may undershoot to –3.0V for periods less than 20 ns. 2. Typical values are for TA = 25°C and VCC = 5V. 3. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 4. Guaranteed by design but not 100% tested. 5. This parameter is measured with device programmed as a 16-bit counter in each LAB. 6. Part (a) in AC Test Load and Waveforms is used for all parameters except tER and tXZ, which is used for part (b) in AC Test Load and Waveforms. All external timing parameters are measured referenced to external pins of the device. Document #: 38-03005 Rev. *B Page 6 of 21 USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C346 Commercial and Industrial External Synchronous Switching Characteristics[6] Over Operating Range Parameter Description tPD1 Dedicated Input to Combinatorial Output Delay[7] tPD2 I/O Input to Combinatorial Output Delay[10] tPD3 Dedicated Input to Combinatorial Output Delay with Expander Delay[11] tPD4 I/O Input to Combinatorial Output Delay with Expander Delay[4, 12] tEA Input to Output Enable Delay[4, 7] tER Input to Output Disable Delay[4, 7] tCO1 Synchronous Clock Input to Output Delay tCO2 Synchronous Clock to Local Feedback to Combinatorial Output[4, 13] tS1 Dedicated Input or Feedback Set-Up Time to Synchronous Clock Input[7, 14] tS2 I/O Input Set-Up Time to Synchronous Clock Input[7] tH Input Hold Time from Synchronous Clock Input[7] tWH Synchronous Clock Input HIGH Time tWL Synchronous Clock Input LOW Time tRW Asynchronous Clear Width[4, 7] tRR Asynchronous Clear Recovery Time[4, 7] tRO Asynchronous Clear to Registered Output Delay[7] tPW Asynchronous Preset Width[4, 7] tPR Asynchronous Preset Recovery Time[4, 7] tPO Asynchronous Preset to Registered Output Delay[7] tCF Synchronous Clock to Local Feedback Input[4, 15] tP External Synchronous Clock Period (1/(fMAX3)[4] fMAX1 External Feedback Maximum Frequency (1/(tCO1 + tS1))[4, 16] fMAX2 Internal Local Feedback Maximum Frequency, lesser of (1/(tS1 + tCF)) or (1/tCO1)[4, 17] fMAX3 Data Path Maximum Frequency, lesser of (1/(tWL + tWH)), (1/(tS1 + tH)) or (1/tCO1)[4, 18] fMAX4 Maximum Register Toggle Frequency (1/(tWL + tWH)[4, 19] tOH Output Data Stable Time from Synchronous Clock Input[4, 20] 7C346-25 Min. Max. 25 40 37 7C346-30 Min. Max. 30 45 44 7C346-35 Min. Max. 35 55 55 Unit ns ns ns 52 59 75 ns 25 25 14 30 30 30 16 35 35 35 20 42 ns ns ns ns 15 20 25 ns 30 0 8 8 25 25 36 0 10 10 30 30 45 0 12.5 12.5 35 35 16 34.5 55.5 20 27.7 43.4 25 22.2 32.2 ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz 62.5 50 40 MHz 62.5 3 50 3 40 3 MHz ns 25 25 25 30 30 30 25 3 35 35 35 30 3 35 6 Notes: 7. This specification is a measure of the delay from input signal applied to a dedicated input (68-pin PLCC input pin 1, 2, 32, 34, 35, 66, or 68) to combinatorial output on any output pin. This delay assumes no expander terms are used to form the logic function. 8. When this note is applied to any parameter specification it indicates that the signal (data, asynchronous clock, asynchronous clear, and/or asynchronous preset) is applied to a dedicated input only and no signal path (either clock or data) employs expander logic. 9. If an input signal is applied to an I/O pin an additional delay equal to tPIA should be added to the comparable delay for a dedicated input. If expanders are used, add the maximum expander delay tEXP to the overall delay for the comparable delay without expanders. 10. This specification is a measure of the delay from input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to form the logic function. 11. This specification is a measure of the delay from an input signal applied to a dedicated input (68-pin PLCC input pin 1, 2, 32, 34, 35, 36, 66, or 68) to combinatorial output on any output pin. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. 12. This specification is a measure of the delay from an input signal applied to an I/O macrocell pin to any output. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by sampling production material. 13. This specification is a measure of the delay from synchronous register clock to internal feedback of the register output signal to the input of the LAB logic array and then to a combinatorial output. This delay assumes no expanders are used, register is synchronously clocked and all feedback is within the same LAB. This parameter is tested periodically by sampling production material. 14. If data is applied to an I/O input for capture by a macrocell register, the I/O pin input set-up time minimums should be observed. These parameters are tS2 for synchronous operation and tAS2 for asynchronous operation. 15. This specification is a measure of the delay associated with the internal register feedback path. This is the delay from synchronous clock to LAB logic array input. This delay plus the register set-up time, tS1, is the minimum internal period for an internal synchronous state machine configuration. This delay is for feedback within the same LAB. This parameter is tested periodically by sampling production material. 16. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which a state machine configuration with external feedback can operate. It is assumed that all data inputs and external feedback signals are applied to dedicated inputs. 17. This specification indicates the guaranteed maximum frequency at which a state machine with internal-only feedback can operate. If register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/tCO1. All feedback is assumed to be local originating within the same LAB. 18. This frequency indicates the maximum frequency at which the device may operate in data path mode (dedicated input pin to output pin). This assumes data input signals are applied to dedicated input pins and no expander logic is used. If any of the data inputs are I/O pins, tS2 is the appropriate tS for calculation. 19. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or buried register can be cycled by a clock signal applied to the dedicated clock input pin. 20. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register output signal to the input of the LAB logic array and then to a combinatorial output. This delay assumes no expanders are used in the logic of combinatorial output or the asynchronous clock input. The clock signal is applied to the dedicated clock input pin and all feedback is within a single LAB. This parameter is tested periodically by sampling production material. Document #: 38-03005 Rev. *B Page 7 of 21 USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C346 Commercial and Industrial External Asynchronous Switching Characteristics[6] Over Operating Range 7C346-25 Parameter Max. Unit Asynchronous Clock Input to Output Delay[7] 25 30 35 ns tACO2 Asynchronous Clock Input to Local Feedback to Combinatorial Output[20] 39 46 55 ns tAS1 Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input[7] 5 6 8 ns tAS2 I/O Input Set-Up Time to Asynchronous Clock Input[7] 19 22 28 ns tAH Input Hold Time from Asynchronous Clock Input[7] 6 8 10 ns 11 14 16 ns 9 11 14 ns tAWL Min. [7] Asynchronous Clock Input HIGH Time Asynchronous Clock Input LOW Time[7, 21] Input[4, 22] tACF Asynchronous Clock to Local Feedback tAP External Asynchronous Clock Period (1/(fMAXA4))[4] fMAXA1 External Feedback Maximum Frequency in Asynchronous Mode (1/(tACO1 + tAS1))[4, 23] fMAXA2 Maximum Internal Asynchronous Frequency[4, 24] Max. Min. 15 Max. 7C346-35 tACO1 tAWH Description 7C346-30 Min. 18 22 ns 20 25 30 ns 33.3 27.7 23.2 MHz 50 40 33.3 MHz fMAXA3 Data Path Maximum Frequency in Asynchronous Mode[4, 25] 40 33.3 28.5 MHz fMAXA4 Maximum Asynchronous Register Toggle Frequency 1/(tAWH + tAWL)[4, 26] 50 40 33.3 MHz tAOH Output Data Stable Time from Asynchronous Clock Input[4, 27] 15 15 15 ns Notes: 21. This parameter is measured with a positive-edge triggered clock at the register. For negative edge triggering, the tAWH and tAWL parameters must be swapped. If a given input is used to clock multiple registers with both positive and negative polarity, tAWH should be used for both tAWH and tAWL. 22. This specification is a measure of the delay associated with the internal register feedback path for an asynchronous clock to LAB logic array input. This delay plus the asynchronous register set-up time, tAS1, is the minimum internal period for an internal asynchronously clocked state machine configuration. This delay is for feedback within the same LAB, assumes no expander logic in the clock path, and assumes that the clock input signal is applied to a dedicated input pin. This parameter is tested periodically by sampling production material. 23. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can operate. It is assumed that all data inputs, clock inputs, and feedback signals are applied to dedicated inputs and that no expander logic is employed in the clock signal path or data path. 24. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal-only feedback can operate. This parameter is determined by the lesser of (1/(tACF + tAS1)) or (1/(tAWH + tAWL)). If register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/tACO1. This specification assumes no expander logic is utilized, all data inputs and clock inputs are applied to dedicated inputs, and all state feedback is within a single LAB. This parameter is tested periodically by sampling production material. 25. This frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path mode. This specification is determined by the lesser of 1/(tAWH + tAWL), 1/(tAS1 + tAH) or 1/tACO1. It assumes data and clock input signals are applied to dedicated input pins and no expander logic is used. 26. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode by a clock signal applied to an external dedicated input pin. 27. This parameter indicates the minimum time that the previous register output data is maintained on the output after an asynchronous register clock input applied to an external dedicated input pin. Document #: 38-03005 Rev. *B Page 8 of 21 USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C346 Commercial and Industrial Internal Switching Characteristics Over Operating Range 7C346-25 Parameter Description Min. Max. 7C346-30 Min. Max. 7C346-35 Min. Max. Unit tIN Dedicated Input Pad and Buffer Delay 5 7 9 ns tIO I/O Input Pad and Buffer Delay 6 6 9 ns tEXP Expander Array Delay 12 14 20 ns tLAD Logic Array Data Delay 12 14 16 ns tLAC Logic Array Control Delay 10 12 13 ns tOD Output Buffer and Pad Delay 5 5 6 ns 10 11 13 ns 10 11 13 ns [28] tZX Output Buffer Enable Delay tXZ Output Buffer Disable Delay tRSU Register Set-Up Time Relative to Clock Signal at Register 6 8 10 ns tRH Register Hold Time Relative to Clock Signal at Register 6 8 10 ns tLATCH Flow Through Latch Delay 3 4 4 ns tRD Register Delay 1 2 2 ns 3 4 4 ns Delay[29] tCOMB Transparent Mode tCH Clock HIGH Time 8 tCL Clock LOW Time 8 tIC Asynchronous Clock Logic Delay 14 16 18 ns tICS Synchronous Clock Delay 1 1 1 ns tFD Feedback Delay 1 1 2 ns tPRE Asynchronous Register Preset Time 5 6 7 ns tCLR Asynchronous Register Clear Time 5 6 7 ns tPCW Asynchronous Preset and Clear Pulse Width 5 6 7 ns tPCR Asynchronous Preset and Clear Recovery Time 5 6 7 ns tPIA Programmable Interconnect Array Delay Time 10 12.5 10 14 ns 12.5 16 ns 20 ns Notes: 28. Sample tested only for an output change of 500 mV. 29. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial operation. Document #: 38-03005 Rev. *B Page 9 of 21 USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C346 Military External Synchronous Switching Characteristics[6] Over Operating Range 7C346-30 Parameter Description Min. [7] Max. 7C346-35 Min. Max. Unit tPD1 Dedicated Input to Combinatorial Output Delay 30 35 ns tPD2 I/O Input to Combinatorial Output Delay[10] 45 55 ns tPD3 Dedicated Input to Combinatorial Output Delay with Expander Delay[11] 44 55 ns tPD4 I/O Input to Combinatorial Output Delay with Expander Delay[4, 12] 59 75 ns tEA Input to Output Enable Delay[4, 7] 30 35 ns tER Input to Output Disable Delay[4, 7] 30 35 ns tCO1 Synchronous Clock Input to Output Delay 16 20 ns tCO2 Synchronous Clock to Local Feedback to Combinatorial Output[4, 13] 35 42 ns tS1 Dedicated Input or Feedback Set-Up Time to Synchronous Clock Input[7, 14] 20 25 ns tS2 I/O Input Set-Up Time to Synchronous Clock Input[7] 36 45 ns tH Input Hold Time from Synchronous Clock Input[7] 0 0 ns tWH Synchronous Clock Input HIGH Time 10 12.5 ns tWL Synchronous Clock Input LOW Time 10 12.5 ns 30 35 ns tRW Asynchronous Clear Width[4, 7] Time[4, 7] tRR Asynchronous Clear Recovery tRO Asynchronous Clear to Registered Output Delay[7] tPW Asynchronous Preset 30 Width[4, 7] Time[4, 7 ] 35 30 ns 35 ns 30 35 ns 30 35 ns tPR Asynchronous Preset Recovery tPO Asynchronous Preset to Registered Output Delay[7] 30 35 ns tCF Synchronous Clock to Local Feedback Input[4, 15] 3 6 ns tP External Synchronous Clock Period (1/(fMAX3 fMAX1 ))[4] 20 25 ns External Feedback Maximum Frequency (1/(tCO1 + tS1))[4, 16] 27.7 22.2 MHz fMAX2 Internal Local Feedback Maximum Frequency, lesser of (1/(tS1 + tCF)) or (1/tCO1)[4, 17] 43.4 32.2 MHz fMAX3 Data Path Maximum Frequency, lesser of (1/(tWL + tWH)), (1/(tS1 + tH)) or (1/tCO1)[4, 18] 50 40 MHz fMAX4 Maximum Register Toggle Frequency (1/(tWL + tWH))[4, 19] 50 40 MHz tOH Output Data Stable Time from Synchronous Clock Input[4, 20] 3 3 ns Document #: 38-03005 Rev. *B Page 10 of 21 USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C346 Military External Asynchronous Switching Characteristics[6] Over Operating Range 7C346-30 Parameter Description Min. [7] Max. 7C346-35 Min. Max. Unit tACO1 Asynchronous Clock Input to Output Delay 30 35 ns tACO2 Asynchronous Clock Input to Local Feedback to Combinatorial Output[20] 46 55 ns tAS1 Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input[7] 6 8 ns tAS2 I/O Input Set-Up Time to Asynchronous Clock Input[7] 22 28 ns tAH Input Hold Time from Asynchronous Clock Input[7] 8 10 ns tAWH Asynchronous Clock Input HIGH Time[7] 14 16 ns 11 14 ns tAWL tACF Asynchronous Clock Input LOW Time[7, 21] Asynchronous Clock to Local Feedback Input[4, 22] tAP External Asynchronous Clock Period (1/(fMAXA4 fMAXA1 External Feedback Maximum Frequency in Asynchronous Mode (1/(tACO1 + tAS1))[4, 23] fMAXA2 ))[4] 18 22 ns 25 30 ns 27.7 23.2 MHz Maximum Internal Asynchronous Frequency[4, 24] 40 33.3 MHz fMAXA3 Data Path Maximum Frequency in Asynchronous Mode[4, 25 ] 33.3 28.5 MHz fMAXA4 Maximum Asynchronous Register Toggle Frequency 1/(tAWH + tAWL)[4, 26] 40 33.3 MHz tAOH Output Data Stable Time from Asynchronous Clock Input[4, 27] 15 15 ns Document #: 38-03005 Rev. *B Page 11 of 21 USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C346 Military Typical Internal Switching Characteristics Over Operating Range 7C346-30 Parameter Description Min. Max. 7C346-35 Min. Max. Unit tIN Dedicated Input Pad and Buffer Delay 7 9 ns tIO I/O Input Pad and Buffer Delay 6 9 ns tEXP Expander Array Delay 14 20 ns tLAD Logic Array Data Delay 14 16 ns tLAC Logic Array Control Delay 12 13 ns tOD Output Buffer and Pad Delay 5 6 ns [28] tZX Output Buffer Enable Delay 11 13 ns tXZ Output Buffer Disable Delay 11 13 ns tRSU Register Set-Up Time Relative to Clock Signal at Register 8 10 ns tRH Register Hold Time Relative to Clock Signal at Register 8 10 ns tLATCH Flow Through Latch Delay 4 4 ns tRD Register Delay 2 2 ns 4 4 ns Delay[29] tCOMB Transparent Mode tCH Clock HIGH Time 10 tCL Clock LOW Time 10 tIC Asynchronous Clock Logic Delay 16 18 ns tICS Synchronous Clock Delay 2 3 ns tFD Feedback Delay 1 2 ns tPRE Asynchronous Register Preset Time 6 7 ns tCLR Asynchronous Register Clear Time 6 7 ns tPCW Asynchronous Preset and Clear Pulse Width 6 7 ns tPCR Asynchronous Preset and Clear Recovery Time 6 7 ns tPIA Programmable Interconnect Array Delay Time Document #: 38-03005 Rev. *B 12.5 ns 12.5 16 ns 20 ns Page 12 of 21 USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C346 Switching Waveforms External Combinatorial DEDICATED INPUT/ I/O INPUT [7] tPD1 /tPD2 [10] COMBINATORIAL OUTPUT tER[7] HIGH-IMPEDANCE THREE-STATE COMBINATORIAL OR REGISTERED OUTPUT tEA [7] HIGH-IMPEDANCE THREE-STATE VALID OUTPUT External Synchronous DEDICATED INPUTS OR REGISTERED FEEDBACK [7] tS1 tH tWH tWL SYNCHRONOUS CLOCK tCO1 ASYNCHRONOUS CLEAR/PRESET[7] tRW/tPW tRR/tPR tOH tRO/tPO REGISTERED OUTPUTS tCO2 COMBINATORIAL OUTPUT FROM REGISTERED FEEDBACK [7] External Asynchronous DEDICATED INPUTS OR REGISTERED FEEDBACK tAS1 ASYNCHRONOUS CLOCK INPUT ASYNCHRONOUS CLEAR/PRESET tAH tACO1 tAWH tRW/tPW tAWL tRR/tPR tAOH tRO/tPO ASYNCHRONOUS REGISTERED OUTPUTS tACO2 COMBINATORIAL OUTPUT FROM ASYNCHRONOUS REGISTERED FEEDBACK Document #: 38-03005 Rev. *B Page 13 of 21 USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C346 Switching Waveforms (continued) Internal Combinatorial tIN INPUT PIN tPIA tIO I/O PIN tEXP EXPANDER ARRAY DELAY tLAC, tLAD LOGIC ARRAY INPUT LOGIC ARRAY OUTPUT Internal Asynchronous tAWH tIOtR tAWL tF CLOCK PIN tIN CLOCK INTO LOGIC ARRAY tIC CLOCK FROM LOGIC ARRAY tRSU tRH DATA FROM LOGIC ARRAY tRD,tLATCH tFD tCLR,tPRE tFD REGISTER OUTPUT TO LOCAL LAB LOGIC ARRAY tPIA REGISTER OUTPUT TO ANOTHER LAB Internal Synchronous tCH tCL SYSTEM CLOCK PIN tIN tICS tRSU tRH SYSTEM CLOCK AT REGISTER DATA FROM LOGIC ARRAY Document #: 38-03005 Rev. *B Page 14 of 21 USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C346 Switching Waveforms (continued) Internal Synchronous CLOCK FROM LOGIC ARRAY tRD tOD DATA FROM LOGIC ARRAY tXZ OUTPUT PIN Document #: 38-03005 Rev. *B tZX HIGH IMPEDANCE STATE Page 15 of 21 USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C346 MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Subgroups VOH 1, 2, 3 VOL 1, 2, 3 VIH 1, 2, 3 VIL 1, 2, 3 IIX 1, 2, 3 IOZ 1, 2, 3 ICC1 1, 2, 3 Switching Characteristics Parameter Subgroups tPD1 7, 8, 9, 10, 11 tPD2 7, 8, 9, 10, 11 tPD3 7, 8, 9, 10, 11 tCO1 7, 8, 9, 10, 11 tS1 7, 8, 9, 10, 11 tS2 7, 8, 9, 10, 11 tH 7, 8, 9, 10, 11 tWH 7, 8, 9, 10, 11 tWL 7, 8, 9, 10, 11 tRO 7, 8, 9, 10, 11 tPO 7, 8, 9, 10, 11 tACO1 7, 8, 9, 10, 11 tACO2 7, 8, 9, 10, 11 tAS1 7, 8, 9, 10, 11 tAH 7, 8, 9, 10, 11 tAWH 7, 8, 9, 10, 11 tAWL 7, 8, 9, 10, 11 Ordering Information Speed (ns) 25 30 Ordering Code CY7C346-25HC/HI CY7C346-25JC/JI CY7C346-25NC/NI CY7C346-25RC/RI CY7C346-30HC/HI CY7C346-30JC/JI CY7C346-30NC/NI CY7C346-30HMB CY7C346-30RMB Document #: 38-03005 Rev. *B Package Name H84 J83 N100 R100 H84 J83 N100 Package Type 84-pin Windowed Leaded Chip Carrier 84-lead Plastic Leaded Chip Carrier 100-lead Plastic Quad Flatpack 100-pin Windowed Ceramic Pin Grid Array 84-pin Windowed Leaded Chip Carrier 84-lead Plastic Leaded Chip Carrier 100-lead Plastic Quad Flatpack Operating Range Commercial/Industrial H84 R100 84-pin Windowed Leaded Chip Carrier 100-pin Windowed Ceramic Pin Grid Array Military Commercial/Industrial Page 16 of 21 USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C346 Ordering Information (continued) Speed (ns) 35 Ordering Code CY7C346-35JC/JI CY7C346-35NC/NI CY7C346-35RC/RI CY7C346-35HMB CY7C346-35RMB Package Name J83 N100 R100 H84 R100 Package Type 84-lead Plastic Leaded Chip Carrier 100-lead Plastic Quad Flatpack 100-pin Windowed Ceramic Pin Grid Array 84-pin Windowed Leaded Chip Carrier 100-pin Windowed Ceramic Pin Grid Array Operating Range Commercial/Industrial Military Package Diagrams 84-Leaded Windowed Leaded Chip Carrier H84 51-80081-** Document #: 38-03005 Rev. *B Page 17 of 21 USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C346 Package Diagrams (continued) 84-Lead Plastic Leaded Chip Carrier J83 51-85006-*A Document #: 38-03005 Rev. *B Page 18 of 21 USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C346 Package Diagrams (continued) 100-Lead Plastic Quad Flatpack N100 51-85052-*A Document #: 38-03005 Rev. *B Page 19 of 21 USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C346 Package Diagrams (continued) 100-Pin Windowed Ceramic Pin Grid Array R100 51-80010-*C MAX and Warp are registered trademarks and Ultra37000, Warp Professional and Warp Enterprise are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-03005 Rev. *B Page 20 of 21 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C346 Document History Page Document Title: CY7C346 128-Macrocell MAX® EPLD Document Number: 38-03005 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 106270 04/23/01 SZV Change from Spec number 38-00244 to 38-03005 *A 113614 04/11/02 OOR PGA package diagram dimensions updated *B 213375 See ECN FSG Added note to title page: “Use Ultra37000 For All New Designs” Document #: 38-03005 Rev. *B Page 21 of 21