Dallas DS1747-70 Y2k-compliant, nonvolatile timekeeping ram Datasheet

DS1747/DS1747P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
www.maxim-ic.com
FEATURES
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PIN CONFIGURATIONS
Integrated NV SRAM, Real-Time Clock
(RTC), Crystal, Power-Fail Control Circuit,
and Lithium Energy Source
Clock Registers are Accessed Identically to
the Static RAM. These Registers are Resident
in the Eight Top RAM Locations.
Century Byte Register (Y2K Compliant)
Totally Nonvolatile with Over 10 Years of
Operation in the Absence of Power
BCD-Coded Century, Year, Month, Date,
Day, Hours, Minutes, and Seconds with
Automatic Leap-Year Compensation Valid
Up to the Year 2100
Battery Voltage-Level Indicator Flag
Power-Fail Write Protection Allows for ±10%
VCC Power-Supply Tolerance
Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until
Power is Applied for the First Time
DIP Module Only:
Standard JEDEC Byte-Wide 512k x 8 Static
RAM Pinout
PowerCapÒ Module Board Only:
Surface-Mountable Package for Direct
Connection to PowerCap Containing
Battery and Crystal
Replaceable Battery (PowerCap)
Power-On Reset Output
Pin-for-Pin Compatible with Other Densities
of DS174xP Timekeeping RAM
Also Available in Industrial Temperature
Range: -40°C to +85°C
TOP VIEW
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
1
32
Dallas
31
2
Semiconductor
30
3
DS1747
29
4
28
5
27
6
26
7
25
8
24
9
23
10
22
11
21
12
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ0
13
20
DQ6
DQ1
DQ2
14
19
DQ5
15
18
DQ4
GND
16
17
DQ3
A0
DQ7
Encapsulated DIP
(512k x 8)
N.C.
A15
A16
RST
VCC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Dallas
Semiconductor
DS1747P
X1
GND
VBAT
X2
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A18
A17
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
PowerCap Module Board
(Uses DS9034PCX PowerCap)
PowerCap is a registered trademark of Dallas Semiconductor.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
1 of 18
REV: 011204
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
PIN DESCRIPTION
A0–A18
CE
OE
WE
VCC
GND
DQ0–DQ7
N.C.
RST
X1, X2
VBAT
– Address Input
– Chip Enable
– Output Enable
– Write Enable
– Power-Supply Input
– Ground
– Data Input/Output
– No Connection
– Power-On Reset Output (PowerCap Module board only)
– Crystal Connection
– Battery Connection
ORDERING INFORMATION
PART
TEMP RANGE
PIN-PACKAGE
DS1747-70
DS1747-70IND
DS1747P-70
DS1747P-70IND
DS1747W-120
DS1747W-120IND
DS1747WP-120
DS1747WP-120IND
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
32 EDIP (0.740a)
32 EDIP (0.740a)
34 PowerCap
34 PowerCap
32 EDIP (0.740a)
32 EDIP (0.740a)
34 PowerCap
34 PowerCap
TOP MARK
DS1747-70
DS1747-70 IND
DS1747P-70
DS1747P-70 IND
DS1747W-120
DS1747W-120 IND
DS1747WP-120
DS1747WP-120 IND
DESCRIPTION
The DS1747 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and
512k x 8 nonvolatile static RAM. User access to all registers within the DS1747 is accomplished with a
byte-wide interface as shown in Figure 1. The RTC information and control bits reside in the eight
uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes,
and seconds data in 24-hour BCD format. Corrections for the date of each month and leap year are made
automatically. The RTC clock registers are double buffered to avoid access of incorrect data that can
occur during clock update cycles. The double-buffered system also prevents time loss as the
timekeeping countdown continues unabated by access to time register data. The DS1747 also contains
its own power-fail circuitry that deselects the device when the VCC supply is in an out-of-tolerance
condition. This feature prevents loss of data from unpredictable system operation brought on by low VCC
as errant access and update cycles are avoided.
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DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Figure 1. Block Diagram
Dallas
Semiconductor
DS1747
PACKAGES
The DS1747 is available in two packages (32-pin DIP and 34-pin PowerCap module). The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap
(DS9034PCX) that contains the crystal and battery. This design allows the Power-Cap to be mounted on
top of the DS1747P after the completion of the surface mount process. Mounting the PowerCap after the
surface mount process prevents damage to the crystal and battery due to the high temperatures required
for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board
and PowerCap are ordered separately and shipped in separate containers. The part number for the
PowerCap is DS9034PCX.
CLOCK OPERATIONS—READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal
updates to the DS1747 clock registers should be halted before clock data is read to prevent reading of
data in transition. However, halting the internal clock register updating process does not affect clock
accuracy. Updating is halted when a one is written into the read bit, bit 6 of the century register, see
Table 2. As long as a one remains in that position, updating is halted. After a halt is issued, the registers
reflect the count, that is day, date, and time that was current at the moment the halt command was
issued. However, the internal clock registers of the double-buffered system continue to update so that
the clock accuracy is not affected by the access of data. All the DS1747 registers are updated
simultaneously after the internal clock register updating process has been re-enabled. Updating is within
a second after the read bit is written to zero. The READ bit must be set to a zero for a minimum of
500 ms to ensure the external registers will be updated.
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DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Table 1. Truth Table
CE
OE
WE
VSO<VCC<VPF
VIH
VIL
VIL
VIL
X
X
X
VIL
VIH
X
VCC<VSO<VPF
X
X
VCC
VCC>VPF
X
VIL
VIH
VIH
X
MODE
Deselect
Write
Read
Read
Deselect
DQ
High-Z
Data In
Data Out
High-Z
High-Z
X
Deselect
High-Z
POWER
Standby
Active
Active
Active
CMOS Standby
Data-Retention
Mode
SETTING THE CLOCK
As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a one, like the
read bit, halts updates to the DS1747 registers. The user can then load them with the correct day, date
and time data in 24 hour BCD format. Resetting the write bit to a zero then transfers those values to the
actual clock counters and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned
off to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers,
see Table 2. Setting it to a one stops the oscillator.
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic “1” and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the
seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for
access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and
stable).
CLOCK ACCURACY (DIP MODULE)
The DS1747 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not
require additional calibration. For this reason, methods of field clock calibration are not available and
not necessary. The electrical environment also affects the clock accuracy, and caution should be taken to
place the RTC in the lowest-level EMI section of the PC board layout. For additional information, please
refer to Application Note 58.
CLOCK ACCURACY (PowerCap MODULE)
The DS1747 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module typically keeps time accuracy to within ±1.53 minutes per month (35 ppm) at 25°C. Clock
accuracy is also affected by the electrical environment and caution should be taken to place the RTC in
the lowest-level EMI section of the PC board layout. For additional information, please refer to
Application Note 58.
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DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Table 2. Register Map
ADDRESS
7FFFF
7FFFE
7FFFD
7FFFC
7FFFB
7FFFA
7FFF9
7FFF8
DATA
B7
B6
X
X
BF
X
X
OSC
W
X
X
FT
X
B5
B4
B3
10 Year
R
B2
B1
Year
Month
Date
X
10 Month
10 Date
X
X
10 Hour
10 Minutes
10 Seconds
10 Century
X
Day
Hour
Minutes
Seconds
Century
OSC = Stop Bit
R = Read Bit
FT = Frequency Test
W = Write Bit
X = See Note
BF = Battery Flag
B0
FUNCTION
RANGE
Year
Month
Date
Day
Hour
Minutes
Seconds
Century
00-99
01-12
01-31
01-07
00-23
00-59
00-59
00-39
NOTE: All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1747 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE
(chip enable) is low. The device architecture allows ripple-through access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is
stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times and
states are not met, valid data will be available at the latter of chip-enable access (tCEA) or at output enable
access time (tOEA). The state of the data input/output pins (DQ) is controlled by CE and OE. If the
outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the address
inputs are changed while CE and OE remain valid, output data will remain valid for output data hold
time (tOH) but will then go indeterminate until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1747 is in the write mode whenever WE, and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE. The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or
write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low
the data bus can become active with read data defined by the address inputs. A low transition on WE
will then disable the output tWEZ after WE goes active.
5 of 18
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
DATA-RETENTION MODE
The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF.
However, when VCC is below the power failing point, VPF, (point at which write protection occurs) the
internal clock registers and SRAM are blocked from any access. At this time the power fail reset output
signal (RST) is driven active and will remain active until VCC returns to nominal levels. When VCC falls
below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to
the backup battery. RTC operation and SRAM data are maintained from the battery until VCC is returned
to nominal levels. The 3.3V device is fully accessible and data can be written or read only when VCC is
greater than VPF. When VCC falls below the power fail point, VPF, access to the device is inhibited. At
this time the power fail reset output signal (RST) is driven active and will remain active until VCC returns
to nominal levels. If VPF is less than VSO, the device power is switched from VCC to the backup supply
(VBAT) when VCC drops below VPF. If VPF is greater than Vso, the device power is switched from VCC to
the backup supply (VBAT) when VCC drops below VSO. RTC operation and SRAM data are maintained
from the battery until VCC is returned to nominal levels. The RST signal is an open drain output and
requires a pull up. Except for the RST, all control, data, and address signals must be powered down
when VCC is powered down.
BATTERY LONGEVITY
The DS1747 has a lithium power source that is designed to provide energy for clock activity, and clock
and RAM data retention when the VCC supply is not present. The capability of this internal power supply
is sufficient to power the DS1747 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at +25°C with the internal clock oscillator running
in the absence of VCC power. Each DS1747 is shipped from Dallas Semiconductor with its lithium
energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level
greater than VPF, the lithium energy source is enabled for battery backup operation. Actual life
expectancy of the DS1747 will be much longer than 10 years since no lithium battery energy is
consumed when VCC is present.
BATTERY MONITOR
The DS1747 constantly monitors the battery voltage of the internal battery. The Battery Flag bit (bit 7)
of the day register is used to indicate the voltage level range of the battery. This bit is not writable and
should always be a one when read. If a zero is ever present, an exhausted lithium energy source is
indicated and both the contents of the RTC and RAM are questionable.
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DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground……………………………………………………………..-0.3V to +6.0V
Storage Temperature Range………………………………………………………………………………...-40°C to +85°C
Soldering Temperature………………………….See IPC/JEDEC Standard J-STD-020A for Surface-Mount Devices.
See Note 7 for Through-Hole Mounted Devices.
This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the
operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of
time may affect reliability.
OPERATING RANGE
RANGE
Commercial
Industrial
TEMP RANGE
0°C to +70°C
-40°C to +85°C
VCC
3.3V ±10% or 5V ±10%
3.3V ±10% or 5V ±10%
RECOMMENDED DC OPERATING CONDITIONS
(TA = Over the Operating Range)
PARAMETER
Logic 1 Voltage All Inputs
VCC = 5V±10%
VCC = 3.3V±10%
Logic 0 Voltage All Inputs
VCC = 5V±10%
VCC = 3.3V±10%
SYMBOL
MIN
VIH
2.2
VIH
2.0
VIL
-0.3
VIL
-0.3
TYP
MAX
UNITS
NOTES
V
1
V
1
+0.8
V
1
+0.6
V
1
VCC +
0.3V
VCC +
0.3V
DC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V ± 10%, TA = Over the Operating Range.)
PARAMETER
Active Supply Current
TTL Standby Current
( CE = VIH)
CMOS Standby Current
( CE ³ VCC - 0.2V)
Input Leakage Current
(Any Input)
Output Leakage Current
(Any Output)
Output Logic 1 Voltage
(IOUT = -1.0 mA)
Output Logic 0 Voltage
(IOUT = +2.1 mA)
Write Protection Voltage
Battery Switchover Voltage
SYMBOL
Icc
MIN
TYP
MAX
85
UNITS
mA
NOTES
2, 3
Icc1
6
mA
2, 3
Icc2
4
mA
2, 3
IIL
-1
+1
mA
IOL
-1
+1
mA
VOH
2.4
1
0.4
VOL
VPF
4.25
VSO
4.50
VBAT
7 of 18
1
V
1
1, 4
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V ±10%, TA = Over the Operating Range.)
PARAMETER
Active Supply Current
TTL Standby Current
( CE = VIH)
CMOS Standby Current
( CE ³ VCC - 0.2V)
Input Leakage Current
(Any Input)
Output Leakage Current
(Any Output)
Output Logic 1 Voltage
(IOUT = -1.0 mA)
Output Logic 0 Voltage
(IOUT = +2.1 mA)
Write Protection Voltage
Battery Switchover Voltage
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Icc
30
mA
2, 3
Icc1
2
mA
2, 3
Icc2
2
mA
2, 3
IIL
-1
+1
mA
IOL
-1
+1
mA
VOH
2.4
1
0.4
VOL
VPF
2.80
2.97
VBAT
or
VPF
VSO
1
V
1
V
1, 4
UNITS
NOTES
AC CHARACTERISTICS—READ CYCLE (5V)
(VCC = 5.0V ±10%, TA = Over the Operating Range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
Read Cycle Time
tRC
70
Address Access Time
tAA
CE to DQ Low-Z
tCEL
CE E Access Time
tCEA
70
ns
CE Data Off Time
tCEZ
25
ns
OE to DQ Low-Z
tOEL
OE Access Time
tOEA
35
ns
OE Data Off Time
tOEZ
25
ns
Output Hold from Address
tOH
ns
70
5
ns
5
5
8 of 18
ns
ns
ns
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
AC CHARACTERISTICS—READ CYCLE (3.3V)
(VCC = 3.3V ±10%, TA = Over the Operating Range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
Read Cycle Time
tRC
120
Address Access Time
tAA
CE to DQ Low-Z
tCEL
CE E Access Time
tCEA
120
ns
CE Data Off Time
tCEZ
40
ns
OE to DQ Low-Z
tOEL
OE Access Time
tOEA
100
ns
OE Data Off Time
tOEZ
35
ns
Output Hold from Address
tOH
ns
120
5
READ CYCLE TIMING DIAGRAM
9 of 18
ns
ns
5
5
UNITS
ns
ns
NOTES
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
AC CHARACTERISTICS—WRITE CYCLE (5V)
(VCC = 5.0V ±10%, TA = Over the Operating Range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
Write Cycle Time
tWC
70
ns
Address Setup Time
tAS
0
ns
WE Pulse Width
tWEW
50
ns
CE Pulse Width
tCEW
60
ns
Data Setup Time
tDS
30
ns
Data Hold Time
tDH1
0
ns
8
Data Hold Time
tDH2
0
ns
9
Address Hold Time
tAH1
5
ns
8
Address Hold Time
tAH2
5
ns
9
WE Data Off Time
tWEZ
Write Recovery Time
tWR
25
5
UNITS
NOTES
ns
ns
AC CHARACTERISTICS—WRITE CYCLE (3.3V)
(VCC = 3.3V ±10%, TA = Over the Operating Range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
Write Cycle Time
tWC
120
Address Setup Time
tAS
0
WE Pulse Width
tWEW
100
ns
CE Pulse Width
tCEW
110
ns
CE and CE2 Pulse Width
tCEW
110
ns
Data Setup Time
tDS
80
ns
Data Hold Time
tDH1
0
ns
8
Data Hold Time
tDH2
0
ns
9
Address Hold Time
tAH1
0
ns
8
Address Hold Time
tAH2
10
ns
9
WE Data Off Time
tWEZ
Write Recovery Time
tWR
10 of 18
NOTES
ns
120
40
10
UNITS
ns
ns
ns
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
WRITE CYCLE TIMING DIAGRAM, WRITE-ENABLE CONTROLLED
WRITE CYCLE TIMING DIAGRAM, CHIP-ENABLE CONTROLLED
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DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
POWER-UP/DOWN AC CHARACTERISTICS (5V)
(VCC = 5.0V ±10%, TA = Over the Operating Range.)
PARAMETER
SYMBOL
MIN
CE or WE at VH
Before Power-Down
VCC Fall Time: VPF(MAX) to
VPF(MIN)
tPD
0
ms
tF
300
ms
VCC Fall Time: VPF(MIN) to VSO
tFB
10
ms
tR
0
ms
VCC Rise Time: VPF(MIN) to
VPF(MAX)
Power-Up Recover Time
Expected Data-Retention Time
(Oscillator ON)
tREC
tDR
TYP
MAX
35
10
POWER-UP/DOWN TIMING (5V DEVICE)
12 of 18
UNITS
NOTES
ms
years
5, 6
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
POWER-UP/DOWN CHARACTERISTICS (3.3V)
(VCC = 3.3V ±10%, TA = Over the Operating Range.)
PARAMETER
SYMBOL
MIN
CE or WE at VH, Before
Power-Down
VCC Fall Time: VPF(MAX) to
VPF(MIN)
VCC Rise Time: VPF(MIN) to
VPF(MAX)
tPD
0
ms
tF
300
ms
tR
0
ms
VPF to RST High
Expected Data-Retention Time
(Oscillator ON)
tREC
tDR
TYP
MAX
35
10
UNITS
NOTES
ms
years
5, 6
UNITS
pF
pF
NOTES
POWER-UP/DOWN WAVEFORM TIMING (3.3V DEVICE)
CAPACITANCE
(TA = +25°C)
PARAMETER
Capacitance on All Input Pins
Capacitance on All Output Pins
SYMBOL
CIN
CO
MIN
13 of 18
TYP
MAX
14
10
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
AC TEST CONDITIONS
Output Load: 50 pF + 1TTL Gate
Input Pulse Levels: 0 to 3.0V
Timing Measurement Reference Levels:
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5 ns
NOTES:
1) Voltages are referenced to ground.
2) Typical values are at +25°C and nominal supplies.
3) Outputs are open.
4) Battery switchover occurs at the lower of either the battery terminal voltage or VPF.
5) Data-retention time is at +25°C.
6) Each DS1747 has a built-in switch that disconnects the lithium source until the user first applies VCC.
The expected tDR is defined for DIP modules and assembled PowerCap modules as accumulative time
in the absence of VCC starting from the time power is first applied by the user.
7) RTC Modules (DIP) can be successfully processed through conventional wave-soldering techniques
as long as temperatures as long as temperature exposure to the lithium energy source contained
within does not exceed +85°C. Post-solder cleaning with water-washing techniques is acceptable,
provided that ultra-sonic vibration is not used.
In addition, for the PowerCap:
a) Dallas Semiconductor recommends that PowerCap Module bases experience one pass through
solder reflow oriented with the label side up (“live-bug”).
b) Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than
3 seconds. To solder, apply flux to the pad, heat the lead frame pad, and apply solder. To remove
the part, apply flux, heat the lead frame pad until the solder reflows, and use a solder wick to
remove solder.
8) tAH1, tDH1 are measured from WE going high.
9) tAH2, tDH2 are measured from CE going high.
14 of 18
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package
outline information, go to www.maxim-ic.com/DallasPackInfo.)
PKG
A
B
C
D
E
F
G
H
J
K
15 of 18
DIM
IN
MM
IN
MM
IN
MM
IN
MM
IN
MM
IN
MM
IN
MM
IN
MM
IN
MM
IN
MM
32-PIN
MIN
MAX
1.680
1.740
42.67
44.20
0.715
0.740
18.16
18.80
0.335
0.365
8.51
9.27
0.075
0.105
1.91
2.67
0.015
0.030
0.38
0.76
0.140
0.180
3.56
4.57
0.090
0.110
2.29
2.79
0.590
0.630
14.99
16.00
0.010
0.018
0.25
0.46
0.015
0.025
0.38
0.64
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
PACKAGE INFORMATION (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package
outline information, go to www.maxim-ic.com/DallasPackInfo.)
PKG
DIM
A
B
C
D
E
F
G
IN
IN
IN
IN
IN
IN
IN
34-PIN PowerCap
MODULE
MIN
NOM
MAX
0.920 0.925 0.930
0.980 0.985 0.990
—
—
0.080
0.052 0.055 0.058
0.048 0.050 0.052
0.015 0.020 0.025
0.025 0.027 0.030
NOTE: DALLAS SEMICONDUCTOR RECOMMENDS THAT POWERCAP MODULE
BASES EXPERIENCE ONE PASS THROUGH SOLDER REFLOW ORIENTED WITH THE
LABEL SIDE UP (“LIVE-BUG”).
NOTE: HAND SOLDERING AND TOUCH-UP: DO NOT TOUCH OR APPLY THE
SOLDERING IRON TO LEADS FOR MORE THAN 3 SECONDS. TO SOLDER, APPLY FLUX
TO THE PAD, HEAT THE LEAD FRAME PAD, AND APPLY SOLDER. TO REMOVE THE
PART, APPLY FLUX, HEAT THE LEAD FRAME PAD UNTIL THE SOLDER REFLOWS, AND
USE A SOLDER WICK TO REMOVE SOLDER.
COMPONENTS AND PLACEMENT MAY VARY FROM EACH DEVICE TYPE.
16 of 18
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
PACKAGE INFORMATION (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package
outline information, go to www.maxim-ic.com/DallasPackInfo.)
DS1747P WITH DS9034PCX ATTACHED
PKG
DIM
A
B
C
D
E
F
G
MIN
0.920
0.955
0.240
0.052
0.048
0.015
0.020
INCHES
NOM
0.925
0.960
0.245
0.055
0.050
0.020
0.025
MAX
0.930
0.965
0.250
0.058
0.052
0.025
0.030
COMPONENTS AND PLACEMENT MAY VARY FROM EACH DEVICE TYPE.
17 of 18
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
PACKAGE INFORMATION (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package
outline information, go to www.maxim-ic.com/DallasPackInfo.)
RECOMMENDED POWERCAP MODULE LAND PATTERN
PKG
DIM
A
B
C
D
E
MIN
—
—
—
—
—
INCHES
NOM
MAX
1.050
—
0.826
—
0.050
—
0.030
—
0.112
—
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products · Printed USA
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