Anpec APL5610CI-TRG Low dropout linear regulator controller Datasheet

APL5610/A
Low Dropout Linear Regulator Controller
Features
General Description
•
Wide Supply Voltage Range from 4.5 to 13.5V
•
High Output Accuracy Over Operating Temperature
The APL5610/A is a low dropout linear regulator controller.
The APL5610/A could drive an external N-Channel
MOSFET and provides an adjustable output by using an
external resistive divider.
and Loading Ranges
•
Fast Transient Response
•
Power-On-Reset Monitoring on VCC
•
Internal Soft-Start Function
•
Low Shutdown Current: < 5µA
•
Enable Control Function
•
Under-Voltage Protection
•
Power-OK Output with a Delay Time
•
Two Versions of IC Available:
The APL5610/A integrates various functions. For example,
a Power-On-Reset (POR) circuit monitors VCC supply
voltage to prevent wrong operations; the function of Under-Voltage Protection (UVP) protects the device from short
circuit condition. A POK indicates that the output status
with time delay which is set internally. It can control other
converter for power sequence. Moreover, the APL5610/A
can be enabled by other power system; namely, holding
- APL5610A: UVP Activated after VCC is Supplied
the EN above 1.6V enables output and pulling the EN
under 0.4 disables output.
•
SOT-23-6 Package
The APL5610/A is available in SOT-23-6 package.
•
Lead Free and Green Devices Available
- APL5610: UVP Activated after VOUT is Ready
Simplified Application Circuit
(RoHS Compliant)
Applications
VCC
•
Note Book PC Applications
•
Motherboard Applications
VIN
ON
EN
EN
VCC
DRV
OFF
APL5610
APL5610A
Pin Configuration
POK
POK
VOUT
FB
GND
-
APL5610/A
EN 1
GND 2
FB 3
6 VCC
5 DRV
4 POK
SOT-23-6
(Top View)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
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APL5610/A
Ordering and Marking Information
Package Code
C : SOT-23-6
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APL5610
APL5610A
Assembly Material
Handling Code
Temperature Range
Package Code
APL5610 C:
L10X
X - Date Code
APL5610A C:
LA0X
X - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings (Note 1 )
Symbol
VCC
VFB
VDRV
TJ
Parameter
Rating
Unit
VCC Input Voltage (VCC to GND)
-0.3 to 15
V
EN, POK, to GND Voltage
-0.3 to 7
V
FB to GND Voltage
-0.3 to 7
V
DRV to GND Voltage
-0.3 to VCC+0.3
Maximum Junction Temperature
TSTG
Storage Temperature
TSDR
Maximum Lead Soldering Temperature, 10 Seconds
V
150
o
-65 to 150
o
260
o
C
C
C
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristic
Symbol
θJA
Parameter
Junction-to-Ambient Resistance in Free Air
Typical Value
Unit
(Note 2)
SOT-23-6
o
250
C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Recommended Operating Conditions (Note 3)
Symbol
Parameter
VCC
VCC Input Voltage (VCC to GND)
VEN
EN to GND Voltage
VOUT
VOUT Output Voltage (Note4)
TA
TJ
Range
Unit
4.5 to 13.5
V
0 to 5.5
V
0.8 ~ VIN - VDROP
Ambient Temperature
Junction Temperature
V
-40 to 85
o
-40 to 125
o
C
C
Note 3: Refer to the typical application circuit.
Note 4: VDROP defined as the VIN -VOUT voltage at VOUT = 98% normal VOUT. The linear regulator must provide the output MOSFET with
sufficient Gate-to-Source voltage (VGS = VCC - VOUT) to regulate the output voltage.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
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APL5610/A
Electrical Characteristics
Unless otherwise specified, these specifications apply over VCC = 5/12V, TA = -40 to 85 oC. Typical values are at TA =25oC.
Symbol
Parameter
APL5610/A
Test Conditions
Min.
Typ.
Unit
Max.
SUPPLY CURRENT
ICC
VCC Supply Current
ISD
VCC Shutdown Current
VCC = 12V
-
0.8
1.0
VCC = 5V
-
0.8
1.0
VCC = 12V, EN=GND
-
-
5
VCC = 5V, EN=GND
-
-
5
3.8
4.0
4.2
V
-
0.4
-
V
mA
µA
POWER-ON-RESET (POR)
VCC POR Threshold
VCC rising
VCC POR Hysteresis
REFERENCE VOLTAGE
VREF
Reference Voltage
VCC = 12V, TA = 25 oC
-
0.8
-
V
Reference Voltage Accuracy
VCC = 12V, TA = 25 oC
-0.5
-
0.5
%
Line Regulation
VCC = 4.5V to 13.2V
FB Input Current
-1.5
-
1.5
%
-100
-
100
nA
-
2
-
MHz
ERROR AMPLIFIER
PSRR
Unity Gain Bandwidth
VCC = 5/12V
Open Loop DC Gain
VCC =12V, No Load
60
80
-
dB
Power Supply Rejection Ratio
VCC =12V, 100Hz, No Load
50
-
-
dB
VCC =12V, IDRV (SOURCE) = 5mA, VFB = 0.6V
11.2
11.5
-
VCC =5V, IDRV (SOURCE) = 5mA, VFB = 0.6V
-
4.7
-
VCC =12V, IDRV (SINK) = 5mA, VFB = 1V
-
0.5
1
VCC =5V, IDRV (SINK) = 5mA, VFB = 1V
-
0.8
-
VCC =12V, VDRV =6V, VFB = 0.6V
-
50
-
VCC =5V, VDRV =2.5V, VFB = 0.6V
-
10
-
VCC =12V, VDRV =6V, VFB = 1V
-
40
-
VCC =5V, VDRV =2.5V, VFB = 1V
-
10
-
VEN rising
-
0.8
-
V
-
50
-
mV
-
2
-
µs
100
200
300
µs
68
75
82
%
-
5
-
µs
VDRV (high) DRV High Voltage
VDRV (low) DRV Low Voltage
IDRV (source) DRV Source Current
IDRV (sink)
DRV Sink Current
V
V
mA
mA
ENABLE
VEN (TH)
EN Logic High Threshold Voltage
EN Hysteresis
EN Shutdown Debounce
VEN falling
SOFT-START
TSS
Soft-Start Interval
UNDER-VOLTAGE PROTECTION (UVP)
VUV (TH)
Under-Voltage Threshold
VEN =5V, VFB falling
UVP Debounce Interval
POWER-OK AND DELAY
VCC =12V, VFB rising
-
90
-
%
POK Threshold Hysteresis
VCC =12V
-
15
-
%
POK Pull-Low Voltage
VCC =12V, POK sinks 4mA
-
0.2
0.4
V
POK Debounce Interval
VFB<falling POK voltage threshold
-
5
-
µs
VPOK (TH) Rising POK Threshold Voltage
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
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APL5610/A
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VCC = 5/12V, TA = -40 to 85 oC. Typical values are at TA =25oC.
Symbol
Parameter
APL5610/A
Test Conditions
Min.
Typ.
Unit
Max.
POWER-OK AND DELAY (CONT.)
POK Delay Time
From VFB =VTHPOK to rising edge of the VPOK
1
2
4
ms
POK Leakage Current
VPOK =5V
-
-
1.0
µA
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APL5610/A
Typical Operating Characteristics
Feedback Voltage vs. Junction
Temperature
Supply Current vs. Supply Voltage
0.50
0.900
0.45
Feedback Voltage (V)
Supply Current (mA)
0.875
IC Enabled
0.40
0.35
0.30
0.25
0.20
0.15
IC Disabled
0.10
0.850
0.825
0.800
0.775
0.750
0.725
0.05
0.700
-50
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0
25
50
75
Junction Temperature
Supply Voltage (V)
100
125
(oC)
DRV Source Current vs. DRV Voltage
DRV Sink Current vs. DRV Voltage
70
45
40
60
35
DRV Sink Current (µA)
DRV Sink Current (µA)
-25
30
25
20
15
10
VIN = 12V, VFB=1V,
TA=25oC
5
50
40
30
20
10
VIN = 12V, VFB=0.75V,
TA=25oC
0
0
0
2
4
6
8
10
0
12
DRV Voltage (V)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
2
4
6
8
10
12
DRV Voltage (V)
5
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APL5610/A
Operating Waveforms
The test condition TA= 25oC unless otherwise specified.
Turn On Response
Turn Off Response
V CC
VCC
VDRV
1
1
VDRV
V OUT
2
2
VOUT
3
3
VPOK
VPOK
4
4
VCC=5V, VIN =5V, VOUT =1.5V, CIN =33µF/
Electrolytic,COUT =1µF/Electrolytic,
CH1: VCC, 2V/Div, DC
CH2: VDRV, 2V/Div, DC
CH3: VOUT, 1V/Div, DC
CH4: VPOK, 5V/Div, DC
TIME: 2ms/Div
VCC=5V, VIN =5V, VOUT =1.5V, CIN =33µF/
Electrolytic,COUT =1µF/Electrolytic,
CH1: VCC, 2V/Div, DC
CH2: VDRV, 2V/Div, DC
CH3: VOUT, 1V/Div, DC
CH4: VPOK, 5V/Div, DC
TIME: 0.1s/Div
Load Transient Response-1
Load Transient Response-2
V OUT
VOUT
1
1
I LOA D
ILOA D
2
2
VCC=5V, VIN =5V, VOUT=1.2V,
ILOAD =0-5-0A(rising/falling edge=1A/µs ),
CIN =22µF/MLCC, C OUT =100µF/Electrolytic,
VCC=5V, VIN =5V, VOUT=1.5V,
ILOAD =0-5-0A(rising/falling edge=1A/µs ),
CIN =22µF/MLCC, C OUT =22µF/MLCC,
CH1: VOUT, 50mV/Div, AC
CH2: IOUT, 2A/Div, DC
CH1: VOUT, 50mV/Div, AC
CH2: IOUT, 2A/Div, DC
TIME:100µs/Div
TIME:20µs/Div
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APL5610/A
Operating Waveforms (Cont.)
The test condition TA= 25oC unless otherwise specified.
Short Circuit Response
(Short-Circuit after Power-up)
Load Transient Response-3
VOUT
1
1
2
3
IOUT
IOUT
VDRV
VOUT
VPOK
2
4
VCC=5V, VIN =5V, VOUT=1.5V,
ILOAD =0-0.2-0A(rising/falling edge=1A/µs ),
CIN =22µF/MLCC, C OUT =22µF/MLCC,
VCC=5V, VIN =5V, VOUT =1.5V,
CIN =22µF/MLCC,COUT =22µF/MLCC,
CH1: IOUT, 20A/Div, DC
CH2: VDRV, 2V/Div, DC
CH3: VOUT (Short to GND after power-up),1V/Div, DC
CH4: VPOK, 5V/Div, DC
TIME: 20µs/Div
CH1: VOUT, 20mV/Div, AC
CH2: IOUT, 100mA/Div, DC
TIME:100µs/Div
Short Circuit Response
(Short-Circuit before Power-up)
(APL5610A)
VOCB
VCC
VOUT
1
2
3
IOUT
VOUT
IOUT
VPOK
4
VCC=5V, VIN =5V, VOUT =1.5V,
CIN =22µF/MLCC,COUT =22µF/MLCC,
CH1: VCC, 2V/Div, DC
CH2: IOUT, 20A/Div, DC
CH3: VOUT (Short to GND before power-up),1V/Div, DC
CH4: VPOK, 5V/Div, DC
TIME: 20µs/Div
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APL5610/A
Pin Description
PIN
FUNCTION
NO.
NAME
1
EN
2
GND
3
FB
4
POK
5
DRV
Voltage Feedback Pin. Connecting this pin to an external resistor divider receives the feedback voltage
of the regulator.
Power-OK signal output pin. This pin is an open-drain output used to indicate the status of output
voltage by sensing FB voltage. This pin is pulled low when output voltage is not within the Power-OK
voltage window.
This pin drives the gate of an external N-channel MOSFET for linear regulator.
6
VCC
Power input pin of the device. The voltage at this pin is monitored for Power-On-Reset purpose.
Enable control pin. Pulling the EN high (VEN>1.6) enables the VOUT; forcing the EN low (VEN<0.4V)
disables the VOUT. When re-enabled, the IC undergoes a new soft-start process.
Ground pin of the circuitry. All voltage levels are measured with respect to this pin.
Block Diagram
Power-On
Reset
VCC
Internal
Regulator
Enable_EA
POR
SoftStart
DRV
VREF
0.8V
Error
Amplifier
UVP
Comparator
EN
Enable
FB
Control Logic
UV
75%VREF
0.8V
POK
Power-OK
Comparator
Enable_EA
PWOK
Delay
GND
90%VREF
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APL5610/A
Typical Application Circuit
VCC
CCC
5V or 12V
1µF
VIN
1.5V
ON
EN
VCC
EN
CIN
100µF
DRV
OFF
APM4354KP
VOUT
APL5610
APL5610A
R1
10kΩ
POK
GND
R2
20kΩ
100kΩ
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
100µF
FB
POK
R3
1.2V
COUT
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APL5610/A
Function Description
Power-On-Reset (POR)
Power-OK and Delay
The APL5610/A monitors the VCC pin voltage (VCC) for
power-on-reset function to prevent wrong operation. The
The APL5610/A indicates the status of the output voltage
by monitoring the feedback voltage (VFB) on FB pin. As the
VFB rises and reaches the rising Power-OK voltage thresh-
built-in POR circuit keeps the output shutting off until internal circuit is operating properly. Typical POR threshold
old (VPOKTH), an internal delay function starts to work. At
the end of the delay time, the IC turns off the internal
is 4.0V with 0.4V hysteresis.
NMOS of the POK to indicate that the output is ok. As the
V FB falls and reaches the falling Power-OK voltage
Soft-Start
The APL5610/A provides an internal soft-start circuitry to
threshold, the IC turns on the NMOS of the POK (after a
debounce time of 5µs typical).
control rise rate of the output voltage and limit the current
surge during start-up. Typical soft-start interval is about
0.3ms.
Output Voltage Regulation
Under-Voltage Protection (UVP)
The APL5610/A is a linear regulator controller. An external
N-channel MOSFET should be connected to DRV as the
The APL5610/A monitors the voltage on FB. When the
voltage on FB falls below the under-voltage threshold,
pass element. The output voltage set by the resistor divider is determined by:
the UVP circuit shuts off the output voltage immediately
by pulling down DRV to 0V and latches APL5610/A off,
R1 

VOUT = 0.8 ⋅  1 +

R
2

requiring either a VCC POR or EN re-enable again to restart.
The UVP activation timing is different in these 2 variants
Where R1 is connected from VOUT to FB and R2 is connected from FB to GND.
of IC, APL5610 and APL5610A. The APL5610 UVP is activated after VOUT voltage has reached 90% POK threshold
while the APL5610A UVP is activated after VCC has been
applied to VCC pin. In order to avoid erroneous UVP latchoff in APL5610A, please make sure the power sequence
is a proper one when you use the APL5610A. For the
suggested power sequence of APL5610A, you can refer
to the Power Sequencing in Application Information.
Enable Control
The APL5610/A has a dedicated enable pin (EN). A logic
low signal applied to this pin shuts down the output. Following a shutdown, a logic high signal re-enables the
output through initiation of a new soft-start cycle. It’s not
necessary to use an external transistor to save cost.
Copyright  ANPEC Electronics Corp.
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APL5610/A
Application Information
2. RDS(on) : Select the MOSFET RDS(on) to ensure that the
output voltage will never enter dropout:
Input Capacitor
The APL5610/A requires proper input capacitor of VIN
RDS(on )(max) < (VIN(min) –VOUT(max))/ IOUT(max)
(connected to the external MOSFET’s drain) to supply
surge current during stepping load transients to prevent
(Note: RDS(on)(max) must be met at all temperatures and at the minimum VGS
condition)
the input rail from dropping. Because the parasitic inductor from the voltage sources or other bulk capacitors to
3. Continuous IDS(max): Select the IDS(max) that can support
the output current:
the VIN limits the slew rate of the surge current, it is necessary to place the input capacitor near the MOSFET’s
Continuous IDS(max) > IOUT(max)
4. Package Thermal Resistance θ(JA): Select a package
of MOSFET that can dissipate the heat, θ(JA) < (TJ –TA)/PD,
drain as close as possible. If the MOSFET is located
near the bulk capacitor for upstream voltage regulator,
where TJ is the maximum allowable Junction temperature of MOSFET, TA is the ambient temperature, PD is the
this input capacitor may not be required. The Input capacitor for VIN should be larger than 1µF. Higher capaci-
maximum power dissipation on MOSFET, calculated as
below:
tance of this VIN input capacitor is needed if the stepping
load transients are large and fast.
PD =(VIN(max) –VOUT(min)) x IOUT(max)
Another input capacitor for VCC is recommended. Placing
the input capacitor of VCC as close to VCC pin as possible
Power Sequencing (Only for APL5610A)
prevents outside noise from entering APL5610/A’s control circuitry. The recommended capacitance of VCC input
At start-up, it is necessary to ensure that the VIN (the volt-
capacitor is 1µF.
age supplied to MOSFET drain), VCC and V EN are sequenced correctly to avoid erroneous latch-off. To avoid
Output Capacitor
The APL5610/A needs a proper output capacitor to main-
UVP latch-off happened at start-up due to sequencing
issues, the key method is the VIN should be larger than
tain circuit stability and to improve transient response
over temperature and current. In order to insure the cir-
the output under-voltage threshold plus the drop through
the pass MOSFET when that output is enabled.
cuit stability, the proper output capacitor value should be
larger than 10µF. With X5R and X7R dielectrics, 22µF is
Figure 1 and 2 show the two types of power on sequence.
Figure 1 shows the VCC comes up before the VIN, and then
sufficient at all operating temperatures.
the output would be enabled when the VEN is applied.
Figure 2 shows the VIN comes up before the VCC, and then
POK Pull High
the output can either be enabled with the VCC or VEN. Recommended power on sequence is shown in Figure1 and
The POK is an open-drain output that needs to be pulled
high to a proper voltage (not greater than 5.5V) via a pull-
2.
up resistor. The pull-up resistor can be 20kΩ~100kΩ.
VCC
MOSFET Selection
APL5610/A requires an N-channel MOSFET as a pass
VIN
element. There are some parameters must be considered in selecting a MOFSET, including: Threshold Volt-
VEN
age VTH, RDS(on ), Continuous IDS current and Package Thermal Resistance. The MOSFET selection guidelines are
VUV(TH)
VEN(TH)
VOUT
listed as below:
1. Threshold Voltage VTH: Select the MOSFET VTH rating to
VEN(TH) occurs after
VUV(TH) is reached
meet the following equation:
VTH < VCC(min) –VOUT(max)
Figure 1. APL5610A supply comes up before MOSFET
drain supply
Copyright  ANPEC Electronics Corp.
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APL5610/A
Application Information (Cont.)
VCC
Power Sequencing (Only for APL5610A) (Cont.)
VIN
VCC
CVCC
VIN
CVIN
VUV(TH)
VEN
VCC
VEN(TH)
DRV
VOUT
APL5610
APL5610A
VEN(TH) occurs after
VUV(TH) is reached
R1
FB
Figure 2. MOSFET drain supply comes up before
GND
R2
COUT
Load
APL5610A supply
Short Circuit Concerns (Only for APL5610)
Figure 3
Since the APL5610 UVP function is activated after the
VOUT reaches 90% level, any combinations of sequence
among VIN, VCC, and VEN are allowable. However, please
note that the advantage of none-power-sequencing
brings a drawback. If and only if a short circuit condition of
output voltage occurs before VIN supply, the UVP won’t be
activated. Thus, the short circuit current persists to flow
and could impair the MOSFET. If in your application the
short circuit is most likely to be encountered before VIN
supply, we suggest you use the APL5610A instead of the
APL5610, who can provide this short circuit protection.
Nevertheless, if the V IN supply can provide the OCP
protection, this short circuit won’t be an issue in APL5610.
Layout Consideration
Figure 3 illustrates the layout. Below is a checklist for
your layout:
1. Please place the input capacitor CVCC close to the VCC
pin.
2. Please place the CVIN close to the MOSFET’s drain.
3. Layout a copper plane for N-channel MOSFET’s drain
to improve the heat dissipation.
4. Output capacitor COUT for load must be placed near the
load as close as possible.
5. Large current paths, the bold lines in figure 3, must
have wide tracks.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
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APL5610/A
Package Information
SOT-23-6
D
e
E
E1
SEE
VIEW A
b
c
0.25
A
L
0
GAUGE PLANE
SEATING PLANE
A1
A2
e1
VIEW A
S
Y
M
B
O
L
SOT-23-6
INCHES
MILLIMETERS
MAX.
MIN.
A
MIN.
MAX.
1.45
0.057
0.00
0.15
0.000
0.006
A2
0.90
1.30
0.035
0.051
b
0.30
0.50
0.012
0.020
A1
c
0.08
0.22
0.003
0.009
D
2.70
3.10
0.106
0.122
E
2.60
3.00
0.102
0.118
E1
1.40
1.80
0.055
e
0.95 BSC
e1
L
0
0.071
0.037 BSC
0.075 BSC
1.90 BSC
0.30
0.60
0°
8°
0.012
0°
0.024
8°
Note : 1. Follow JEDEC TO-178 AB.
2. Dimension D and E1 do not include mold flash, protrusions or
gate burrs. Mold flash, protrusion or gate burrs shall not exceed
10 mil per side.
Copyright  ANPEC Electronics Corp.
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APL5610/A
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
SOT-23-6
A
H
T1
C
d
D
W
E1
F
178.0±2.00
50 MIN.
8.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
8.0±0.30
1.75±0.10
3.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
4.0±0.10
4.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.0 MIN.
0.6+0.00
-0.40
3.20±0.20
3.10±0.20
1.50±0.20
(mm)
Devices Per Unit
Package Type
Unit
Quantity
SOT-23-6
Tape & Reel
3000
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
14
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APL5610/A
Taping Direction Information
SOT-23-6
USER DIRECTION OF FEED
AAAX
AAAX
AAAX
AAAX
AAAX
AAAX
AAAX
Classification Profile
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
15
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APL5610/A
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
16
Description
5 Sec, 245°C
1000 Hrs, Bias @ 125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
www.anpec.com.tw
APL5610/A
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
17
www.anpec.com.tw
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