LINER LTC1669 10-bit rail-to-rail micropower dac with i2c interface Datasheet

LTC1669
10-Bit Rail-to-Rail
Micropower DAC with I2C Interface
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DESCRIPTIO
FEATURES
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Micropower 10-Bit DAC in SOT-23
Low Operating Current: 60µA
Ultralow Power Shutdown Mode: 12µA
2-Wire Serial Interface Compatible
with I2CTM
Selectable Internal Reference or Ratiometric to VCC
Maximum DNL Error: 0.75LSB
8 User Selectable Addresses (MSOP Package)
Single 2.7V to 5.5V Operation
Buffered True Rail-to-Rail Voltage Output
Power-On Reset
1.5V VIL and 2.1V VIH for SDA and SCL
Small 5-Lead SOT-23 and 8-Lead MSOP Packages
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APPLICATIO S
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The part features a simple 2-wire serial interface compatible with I2C that allows communication between many
devices. The internal data registers are double buffered to
allow for simultaneous update of several devices at once.
The DAC can be put in low current power-down mode for
use in power conscious systems.
Power-on reset ensures the DAC output is at 0V when
power is initially applied, and all internal registers are
cleared. The LTC1669 is pin-for-pin compatible with the
LTC1663.
Digital Calibration
Offset/Gain Adjustment
Industrial Process Control
Automatic Test Equipment
Arbitrary Function Generators
Battery-Powered Data Conversion Products
, LTC and LT are registered trademarks of Linear Technology Corporation.
I2C is a trademark of Philips Electronics N.V.
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The LTC®1669 is a 10-bit voltage output DAC with true
buffered rail-to-rail output voltage capability. It operates
from a single supply with a range of 2.7V to 5.5V. The
reference for the DAC is selectable between the supply
voltage or an internal bandgap reference. Selecting the
internal bandgap reference will set the full-scale output
voltage range to 2.5V. Selecting the supply as the reference sets the output voltage range to the supply voltage.
BLOCK DIAGRA
4 (5)
VCC
1.25V
BANDGAP
REFERENCE
Differential Nonlinearity (DNL)
1.0
VREF = VCC = 5V
TA = 25°C
0.8
REFERENCE
SELECT
0.6
10-BIT
DAC LATCH
10-BIT BUFFERED VOUT DAC
COMMAND
LATCH
MSOP
PACKAGE
ONLY
VOUT 3 (8)
(3) AD2
0.2
0
– 0.2
– 0.4
– 0.6
INPUT
LATCH
– 0.8
–1.0
(6) AD0
(2) AD1
ERROR (LSB)
0.4
0
2-WIRE INTERFACE
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156 384 512 640 768 896 1024
CODE
1669 G02
SDA
SCL
GND
1 (1)
5 (4)
2 (7)
1669 BD
NOTE: PIN NUMBERS IN PARENTHESES REFER TO THE MSOP PACKAGE
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LTC1669
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ABSOLUTE
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RATI GS
(Note 1)
VCC to GND .............................................. – 0.3V to 7.5V
SDA, SCL ..................................................– 0.3V to 7.5V
AD0, AD1, AD2 (MSOP Only) ...... – 0.3V to (VCC + 0.3V)
VOUT ............................................ – 0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC1669C .............................................. 0°C to 70°C
LTC1669I ........................................... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
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PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
TOP VIEW
TOP VIEW
SDA
AD1
AD2
SCL
8
7
6
5
1
2
3
4
ORDER PART
NUMBER
VOUT
GND
AD0
VCC
LTC1669CMS8
LTC1669IMS8
SDA 1
5 SCL
GND 2
VOUT 3
MS8 PART MARKING
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 150°C/W
LTC1669-8CMS8
LTC1669-8IMS8
LTAHV
LTAHX
LTAHT
LTAHU
LTC1669CS5
LTC1669-1CS5
4 VCC
S5 PACKAGE
5-LEAD PLASTIC SOT-23
S5 PART MARKING
LTAHW
LTAHR
TJMAX = 125°C, θJA = 250°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VCC set as reference, VOUT unloaded,
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DAC
Resolution
●
10
Bits
Monotonicity
(Note 2)
●
10
Bits
DNL
Differential Nonlinearity
Guaranteed Monotonic (Note 2)
●
±0.2
±0.75
LSB
INL
Integral Nonlinearity
(Note 2)
●
±0.5
±2.5
LSB
VOS
Offset Error
Measured at Code 20
●
±10
±30
VOSTC
Offset Error Temperature Coefficient
FSE
Full-Scale Error
Reference Set to VCC
Reference Set to Internal Bandgap
VOUT
DAC Output Span
Reference Set to VCC
Reference Set to Internal Bandgap
0 to VCC
0 to 2.5
VFSTC
Full-Scale Voltage Temperature Coefficient
Reference Set to VCC
Reference Set to Internal Bandgap
±30
±50
µV/°C
µV/°C
PSRR
Power Supply Rejection Ratio
Reference Set to Internal Bandgap,
Code = 1023
±0.4
LSB/V
±15
±3
±3
●
●
mV
µV/°C
±15
±15
LSB
LSB
V
V
Power Supply
VCC
Positive Supply Voltage
5.5
V
ICC
Supply Current
VCC = 3V (Note 3)
VCC = 5V (Note 3)
●
●
60
75
100
125
µA
µA
ISD
Supply Current in Shutdown Mode
(Note 3)
●
12
24
µA
Short-Circuit Current (Sourcing)
VOUT Shorted to GND, Input Code = 1023
●
25
100
mA
Short-Circuit Current (Sinking)
VOUT Shorted to VCC, Input Code = 0
●
30
120
●
2.7
Op Amp DC Performance
mA
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LTC1669
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VCC set as reference, VOUT unloaded,
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
Output Impedance to GND
Input Code = 0, VCC = 5V
Input Code = 0, VCC = 3V
In Shutdown Mode
MIN
TYP
65
150
500
MAX
UNITS
Ω
Ω
kΩ
Output Impedance to VCC
Input Code = 1023, VCC = 5V
Input Code = 1023, VCC = 3V
80
120
Ω
Ω
Voltage Output Slew Rate
Rising (Notes 4, 5)
Falling (Notes 4, 5)
0.75
0.25
V/µs
V/µs
Voltage Output Settling Time
To ±0.5LSB (Notes 4, 5)
AC Performance
Digital-to-Analog Glitch Impulse
µs
30
Digital Feedthrough
1LSB Change Around Major Carry
0.75
nV • s
70
nV • s
Digital Inputs SCL, SDA
VIH
High Level Input Voltage
●
2.1
V
VIL
Low Level Input Voltage
●
VLTH
Logic Threshold Voltage
ILEAK
Digital Input Leakage
VCC = 5.5V and 0V, VIN = GND to VCC
●
±1
µA
CIN
Digital Input Capacitance
(Note 7)
●
10
pF
IPULLUP = 3mA
●
0.4
V
VIN = 0V
●
1.5
µA
1.5
V
1.8
V
Digital Output SDA
VOL
Digital Output Low Voltage
Address Inputs AD0, AD1, AD2 (MSOP Only)
IUP
Address Pin Pull-Up Current
0.5
VIH
High Level Input Voltage
● VCC – 0.3
VIL
Low Level Input Voltage
●
V
0.8
V
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TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VCC set as reference, VOUT unloaded, unless otherwise noted.
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
100
kHz
Timing Characteristics (Notes 6, 7)
fSCL
Clock Operating Frequency
●
tBUF
Bus Free Time Between Stop and Start Condition
●
tHD, STA
Hold Time After (Repeated) Start Condition
tSU, STA
Repeated Start Condition Setup Time
tSU, STO
4.7
µs
●
4
µs
●
4.7
µs
Stop Condition Setup Time
●
4
µs
tHD, DAT (IN)
Data Hold Time (Input)
●
0
tHD, DAT (OUT)
Data Hold Time (Output)
●
225
tSU, DAT
Data Setup Time
●
250
tLOW
Clock Low Period
●
4.7
µs
tHIGH
Clock High Period
●
4
µs
tf
Clock, Data Fall Time
●
20
300
ns
tr
Clock, Data Rise Time
●
20
1000
ns
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: Nonlinearity and monotonicity are defined from code 20 to code
1003 (full scale). See Applications Information.
Note 3: Digital inputs at 0V or VCC.
ns
500
3450
ns
ns
Note 4: Load is 10kΩ in parallel with 100pF.
Note 5: VCC = VREF = 5V. DAC switched between 0.1VFS and 0.9VFS,
i.e., codes k = 102 and k = 922.
Note 6: All values are referenced to VIH and VIL levels.
Note 7: Guaranteed by design and not subject to test.
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LTC1669
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TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity (INL)
1.0
1.0
VREF = VCC = 5V
TA = 25°C
5.0
VREF = VCC = 5V
TA = 25°C
0.8
0.6
0.4
0.4
ERROR (LSB)
0.6
0.2
0
– 0.2
0.2
0
– 0.2
3.5
3.0
2.5
2.0
– 0.4
– 0.6
– 0.6
1.0
– 0.8
– 0.8
0.5
1.5
–1.0
0
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CODE
DAC CODE = 1023
4.0
– 0.4
–1.0
TA = 25°C
4.5
OUTPUT VOLTAGE (V)
0.8
ERROR (LSB)
Source and Sink Current
Capability with VCC = 5V
Differential Nonlinearity (DNL)
0
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156 384 512 640 768 896 1024
CODE
1669 G01
DAC CODE = 0
1 2 3 4 5 6 7 8 9 10
OUTPUT CURRENT SOURCE/SINK (mA)
0
1669 G02
Large-Signal Step Response
1669 G03
Midscale Glitch
Load Regulation vs Output Current
1.0
5
SDA
(VOLTS) 0
0.8
5V
SDA
0V
5
0.6
0.4
CODE = 512 TO 511
∆VOUT (LSB)
CODE = 990
4
VCC = 5V
RL = 4.7k
CL = 100pF
TA = 25°C
3
VOUT
(VOLTS) 2
VOUT
10mV/DIV
0
SOURCE
– 0.4
VCC = 5V
RL = 4.7k
CL = 100pF
TA = 25°C
CODE = 32
0
2µs/DIV
1669 G04
0.2
– 0.2
1
5µs/DIV
VCC = VREF = 5V
VOUT = 2.5V
CODE = 512
TA = 25°C
SINK
– 0.6
– 0.8
–1.0
–4
1669 G05
–3
–2
–1 0
1
IOUT (mA)
3
2
4
1669 G06
Offset Error Voltage vs
Temperature
Load Regulation vs Output Current
0.6
OFFSET ERROR VOLTAGE (mV)
0.8
VCC = VREF = 3V
VOUT = 1.5V
CODE = 512
TA = 25°C
∆VOUT (LSB)
0.4
0.2
0
– 0.2
– 0.4
SOURCE
SINK
– 0.6
5
2.510
4
2.508
3
2.506
OUTPUT VOLTAGE (V)
1.0
Full-Scale Output Voltage vs
Temperature
2
1
0
–1
–2
2.504
2.502
2.500
2.498
2.496
–3
2.494
– 0.8
–4
2.492
–1.0
–1.0 – 0.8– 0.6– 0.4– 0.2 0 0.2 0.4 0.6 0.8 1.0
IOUT (mA)
–5
–60 –40 –20 0 20 40 60
TEMPERATURE (°C)
1669 G07
80
100
1669 G08
REFERENCE SET TO
INTERNAL BANDGAP
2.490
–60 –40 –20 0 20 40 60
TEMPERATURE (°C)
80
100
1669 G09
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LTC1669
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PIN FUNCTIONS
SDA (Pin 1, Pin 1 on SOT-23): Serial Data Bidirectional
Pin. Data is shifted into the SDA pin and acknowledged by
the SDA pin. High impedance pin while data is shifted in.
Open-drain N-channel output during acknowledgment.
Requires a pull-up resistor or current source to VCC.
AD1 (Pin 2): Slave Address Select Bit 1. Tie this pin to
either VCC or GND to modify the corresponding bit of the
LTC1669’s slave address.
AD2 (Pin 3): Slave Address Select Bit 2. Tie this pin to
either VCC or GND to modify the corresponding bit of the
LTC1669’s slave address.
VCC (Pin 5, Pin 4 on SOT-23): Power Supply. 2.7V ≤ VCC
≤ 5.5V. Also used as the reference voltage input when the
part is programmed to use VCC as the reference.
AD0 (Pin 6): Slave Address Select Bit 0. Tie this pin to
either VCC or GND to modify the corresponding bit of the
LTC1669’s slave address.
GND (Pin 7, Pin 2 on SOT-23): System Ground.
VOUT (Pin 8, Pin 3 on SOT-23): Voltage Output. Buffered
rail-to-rail DAC output.
SCL (Pin 4, Pin 5 on SOT-23): Serial Clock Input Pin. Data
is shifted into the SDA pin at the rising edges of the clock.
This high impedance pin requires a pull-up resistor or
current source to VCC.
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DEFINITIONS
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL = (∆VOUT – LSB)/LSB
Where ∆VOUT is the measured voltage difference between
two adjacent codes.
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
(nV)(sec).
Full-Scale Error (FSE): The deviation of the actual fullscale voltage from ideal. FSE includes the effects of offset
and gain errors (see Applications Information).
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (Endpoint INL). Because the output cannot go below
zero, the linearity is measured between full scale and the
lowest code that guarantees the output will be greater than
zero. The INL error at a given input code is calculated as
follows:
INL = [VOUT – VOS – (VFS – VOS)(code/1023)]/LSB
Where VOUT is the output voltage of the DAC measured at
the given input code.
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
LSB = VREF/1024
Resolution (n): Defines the number of DAC output states
(2n) that divide the full-scale range. Resolution does not
imply linearity.
Voltage Offset Error (VOS): Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
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6
3
0
0
NOTE: X = DON’T CARE
2
1
SCL
VOUT
1
0
1
SDA
START
0
4
0
0
5
1
AD2
ADDRESS
6
1
AD1
AD0
7
1
tLOW
tr
tHIGH
tf
tSU, DAT
tHD, DAT
REPEATED START
CONDITION
tSU, STA
tHD, STA
STOP
CONDITION
tBUF
tSU, STO
8
0
WR
9
ACK
1
X
X
2
X
X
3
X
X
4
X
X
5
X
X
COMMAND
6
0
BG
7
0
SD
8
0
SY
9
ACK
1
1
D7
2
1
D6
3
1
D5
4
1
5
1
D3
LS DATA
D4
6
1
D2
7
1
D1
8
1
D0
9
ACK
1
X
X
2
X
X
3
X
X
4
X
5
X
X
MS DATA
X
1663 TD
6
X
X
START
CONDITION
Typical LTC1669 Input Waveform—Programming DAC Output for Full Scale (AD2 to AD0 Set High)
START
CONDITION
tHD, STA
SCL
SDA
7
1
D9
8
1
D8
9
ACK
STOP
1669 TA02
ZERO-SCALE
VOLTAGE
FULL-SCALE
VOLTAGE
LTC1669
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TI I G DIAGRA
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LTC1669
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APPLICATIONS INFORMATION
Write Word Protocol Used by the LTC1669
1
7
1
1
8
1
8
1
8
1
1
S
Slave Address
Wr
A
Command Byte
A
LSData Byte
A
MSData Byte
A
P
1669 TA03
S = Start Condition, Wr = Write Bit = 0, A = Acknowledge, P = Stop Condition
Serial Digital Interface
Write Word Protocol
The LTC1669 communicates with a host (master) using
the standard 2-wire interface. The Timing Diagram shows
the timing relationship of the signals on the bus. The two
bus lines, SDA and SCL, must be high when the bus is not
in use. External pull-up resistors or current sources, such
as the LTC1694 SMBus/I2C Accelerator, are required on
these lines.
The master initiates communication with the LTC1669
with a START condition and a 7-bit address followed by the
Write Bit (Wr) = 0. The LTC1669 acknowledges and the
master delivers the command byte. The LTC1669 acknowledges and latches the command byte into the command byte input register. The master then delivers the
least significant data byte. Again the LTC1669 acknowledges and the data is latched into the least significant data
byte input register. The master then delivers the most
significant data byte. The LTC1669 acknowledges once
more and latches the data into the most significant data
byte input register. Lastly, the master terminates the
communication with a STOP condition. On the reception
of the STOP condition, the LTC1669 transfers the input
register information to output registers and the DAC
output is updated.
The LTC1669 is a receive-only (slave) device. The master
can communicate with the LTC1669 using the Quick
Command, Send Byte or Write Word protocols as explained later.
The START and STOP Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communication to a slave device by transmitting a START condition.
A START condition is generated by transitioning SDA
from high to low while SCL is high.
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while SCL
is high. The bus is then free for communication with
another SMBus device.
Slave Address (MSOP Package Only)
The LTC1669 can respond to one of eight 7-bit addresses.
The first 4 bits (MSBs) have been factory programmed to
0100. The first 4 bits of the LTC1669-8 have been factory
programmed to 0011. The three address bits, AD2, AD1
and AD0 are programmed by the user and determine the
LSBs of the slave address, as shown in the table below:
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the latest
byte of information was received. The Acknowledge related clock pulse is generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge
clock pulse. The slave-receiver must pull down the SDA
line during the Acknowledge clock pulse so that it remains
a stable LOW during the HIGH period of this clock pulse.
LTC1669
LTC-1669-8
AD2
AD1
AD0
0100 xxx
0011 xxx
L
L
L
0100 000
0011 000
L
L
H
0100 001
0011 001
L
H
L
0100 010
0011 010
L
H
H
0100 011
0011 011
H
L
L
0100 100
0011 100
H
L
H
0100 101
0011 101
H
H
L
0100 110
0011 110
H
H
H
0100 111
0011 111
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LTC1669
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APPLICATIONS INFORMATION
Slave Address (SOT-23 Package)
The slave address for the SOT-23 package has been
factory programmed to be “0100 000” (LTC1669) and
“0100 001” (LTC1669-1). If another address is required,
please consult the factory.
Command Byte
The Bandgap (BG) bit when set to “0” selects the DAC
supply voltage as its voltage reference. The full-scale
output of the DAC with this setting is equal to the supply
voltage. When the BG bit is set to “1,” the internal bandgap
reference (≈1.25V) is selected as the DAC’s reference. The
full-scale output voltage for this setting is 2.5V.
Data Bytes
7
6
5
4
3
2
1
0
X
X
X
X
X
BG
SD
SY
SY
1
0
Allows update on Acknowledge of SYNC Address only
Update on Stop condition only (Power-On Default)
SD
1
0
Puts the device in power-down mode
Puts the device in standard operating mode
(Power-On Default)
BG
1
0
Selects the internal bandgap reference
Selects the supply as the reference (Power-On Default)
X
X
Don’t Care
The stop condition normally initiates the update of the
DAC’s output latches. Simultaneous update of more than
one DAC or other devices on the bus can be achieved by
reissuing new start bit, address, command and data bytes
before issuing a final stop condition (which will update all
the devices). An alternate way to achieve simultaneous
LTC1669 updates is to override the stop condition update
by setting the “SY” bit of the command byte. Setting this
bit sets the device to update the DAC output latches only
at the reception of a SYNC address quick command. The
actual update occurs on the rising edge of SCL during the
Acknowledge. In this way, all devices can update on the
reception of the SYNC address quick command instead of
the STOP condition.
A Shutdown (SD) bit = HIGH will put the device in a low
power state but retain all data latch information. Shutdown
will occur at the reception of a STOP condition. This way
shutdown could be synchronized to other devices. The
output impedance of the DAC will go to a high impedance
state (≈ 500kΩ to GND).
Least Significant Data Byte
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Most Significant Data Byte
7
6
5
4
3
2
1
0
X
X
X
X
X
X
D9
D8
X = Don’t care
Send Byte Protocol
The Send Byte protocol used on the LTC1669 is actually a
subset of the Write Word protocol described previously.
The Send Byte protocol can only be used to send the
command byte information to the LTC1669.
1
7
1
1
8
1
1
S
Slave Address
Wr
A
Command Byte
A
P
S = Start Condition, Wr = Write Bit, A = Acknowledge, P = Stop Condition
1669 TA04
The Send Byte protocol is also used whenever the Write
Word protocol is interrupted for any reason. Reception of
a START or STOP condition after the Acknowledge of the
command byte, but before the Acknowledge of the last
data byte, will cause both data bytes to be ignored and the
command byte to be accepted.
Reception of a START or STOP condition before the
Acknowledge of the command byte will cause the interrupted command byte to be ignored.
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LTC1669
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APPLICATIONS INFORMATION
SYNC Address/Quick Command
Rail-to-Rail Output Considerations
In addition to the slave address, the LTC1669 has an
address that can be shared by other devices so that they
may be updated synchronously. The address is called to
the SYNC address and uses the quick command protocol.
As in any rail-to-rail device, the output is limited to
voltages within the supply range.
The SYNC Address is 1111 110
Similarly, limiting can occur near full scale when VCC is
used as the reference. If VREF = VCC and the DAC full-scale
error (FSE) is positive, the output for the highest codes
limits at VCC as shown in Figure 1c. No full-scale limiting
can occur if the internal reference is used.
1
7
1
1
1
Start
1111 110
SY/CLR
Ack
Stop
SYNC Address
SY/CLR
1
0
1669 TA05
Update output latches on rising edge of SCL during
Acknowledge of SYNC Address
Clear all internal latches on rising edge of SCL during
Acknowledge of SYNC Address
The SY/CLR bit set high only has meaning when the “SY”
bit of the command byte was previously set HIGH. On the
otherhand, the SY/CLR bit set LOW will always clear the
part, independent of the state of the “SY” bit in the
command byte.
Voltage Output
The output amplifier contained in the LTC1669 can source
or sink up to 5mA. The output stage swings to within a few
millivolts of either supply rail when unloaded and has an
equivalent output resistance of 85Ω when driving a load to
the rails. The output amplifier is stable driving capacitive
loads up to 1000pF.
A small resistor placed in series with the output can be
used to achieve stability for any load capacitance greater
than 1000pF. For example, a 0.1µF load can be driven by
the LTC1669 if a 110Ω series resistance is used. The phase
margin of the resulting circuit is 45° and increases monotonically from this point if larger values of resistance, capacitance or both are substituted for the values given.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 1b.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
Internal Reference
In applications where a predictable output is required that
is independent of supply voltage, the LTC1669 has a userselectable internal reference. Selecting the internal reference will set the full-scale output voltage to 2.5V. This can
be useful in applications where the supply voltage is
poorly regulated.
Using the LT®1460 Micropower Series Reference as a
Power Supply for the LTC1669
In applications where the advantages of using the internal
reference are required but the full-scale range needs to be
greater than 2.5V, an external series reference can be
used. The LT1460 is ideal for use as a power supply for the
LTC1669 and can provide 3V, 3.3V and 5V full-scale
output voltage ranges. The LT1460 provides accuracy,
noise immunity and extended supply range to the LTC1669
when the LTC1669 is operated ratiometric to VCC. Since
both parts are available in SOT-23 packages, the PC board
space for this application is extremely small. See Figure 2.
1669f
9
LTC1669
U
W
U
U
APPLICATIONS INFORMATION
POSITIVE
FSE
VREF = VCC
OUTPUT
VOLTAGE
INPUT CODE
(c)
VREF = VCC
OUTPUT
VOLTAGE
0
512
INPUT CODE
1023
(a)
OUTPUT
VOLTAGE
0V
NEGATIVE
OFFSET
INPUT CODE
(b)
1669 F01
Figure 1. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
1
3.9V TO 20V
0.1µF
IN
LT1460S3-3
2
OUT
+
GND
3V
0.01µF
3
4 (5)
VCC
5 (4)
TO
µP
1 (1)
SCL
LTC1669
OUT
3 (8)
0V ≤ VOUT ≤ 3V
SDA
GND
LTC1669 PIN NUMBERS IN PARENTHESES
REFER TO MSOP PACKAGE
2 (7)
1669 F02
Figure 2. LT1460 As Power Supply for the LTC1669
1669f
10
LTC1669
U
PACKAGE DESCRIPTION
S5 Package
5-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1635)
0.62
MAX
0.95
REF
2.90 BSC
(NOTE 4)
1.22 REF
2.80 BSC
1.4 MIN
3.85 MAX 2.62 REF
1.50 – 1.75
(NOTE 4)
PIN ONE
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45 TYP
5 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
0.01 – 0.10
1.00 MAX
DATUM ‘A’
0.30 – 0.50 REF
0.09 – 0.20
(NOTE 3)
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
1.90 BSC
S5 TSOT-23 0302
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
0.42 ± 0.038
(.0165 ± .0015)
TYP
3.20 – 3.45
(.126 – .136)
0.65
(.0256)
BSC
0.254
(.010)
8
7 6 5
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.52
(.0205)
REF
0° – 6° TYP
GAUGE PLANE
0.53 ± 0.152
(.021 ± .006)
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
1
2 3
1.10
(.043)
MAX
4
0.86
(.034)
REF
0.18
(.007)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.65
(.0256)
BSC
0.127 ± 0.076
(.005 ± .003)
MSOP (MS8) 0603
1669f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LTC1669
U
TYPICAL APPLICATION
Program Up to 16 Control Outputs Per BUS and Place Them Where They Are Needed
VCC = 2.7V TO 5.5V
5
4
1
VCC
SMBus 1
LTC1694
+
0.1µF
SMBus 2
GND
2
+
5
4
VCC
SCL
1
SDA
8
LTC1669CMS8
6
VOUT
AD0
2
AD1
3
GND
AD2
SCL
µP
SDA
0.1µF
CONTROL
OUTPUT 0
0V ≤ VOUT0 < VCC
7
+
5
4
VCC
SCL
1
SDA
8
LTC1669CMS8
6
VOUT
AD0
2
AD1
3
AD2
GND
0.1µF
CONTROL
OUTPUT 1
0V ≤ VOUT1 < VCC
7
+
5
4
VCC
SCL
1
SDA
8
LTC1669-8CMS8
6
VOUT
AD0
2
AD1
3
AD2
GND
2
TO OTHER I C
DEVICES
0.1µF
CONTROL
OUTPUT 15
0V ≤ VOUT15 < VCC
7
1669 TA06
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1694
SMBus/I2C Accelerator
Dual SMBus Accelerator with Active AC and DC Pull-Up Current Sources
LTC1694-1
SMBus/I2C Accelerator
Dual SMBus Accelerator with Active AC Pull-Up Current Only
LTC1659
Single Rail-to-Rail 12-Bit VOUT DAC in
8-Lead MSOP Package. VCC = 2.7V to 5.5V
Low Power Multiplying VOUT DAC. Output Swings from
GND to REF. REF Input Can Be Tied to VCC. 3-Wire Interface.
LTC1660/LTC1664
LTC1661
Octal/Quad 10-Bit VOUT DACs in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V Micropower Rail-to-Rail Output. 3-Wire Interface.
Dual 10-Bit VOUT in 8-Lead MSOP Package
VCC = 2.7V to 5.5V Micropower Rail-to-Rail Output. 3-Wire Interface.
LTC1663
10-Bit VOUT in SOT-23, SMBUS Interface
Pin-for-Pin Compatible with LTC1669
LTC1285/LTC1288
8-Pin SO, 3V Micropower ADCs
1- or 2-Channel, Autoshutdown
LTC1286/LTC1298
8-Pin SO, 5V Micropower ADCs
1- or 2-Channel, Autoshutdown
DACs
ADCs
1669f
12
Linear Technology Corporation
LT/TP 1103 1K • PRINTED IN THE USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2003